uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / .gitignore

diff --git a/.gitignore b/.gitignore
index b150b26e1f7d02ef7570c2cbb3e9d8ca09f56810..34721068c010f3c28fd6a439735a6bb452f8c4b3 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -7,14 +7,14 @@ spec/*.backup
 spec/*.out
 spec/*.pdf
 spec/*.png
 spec/*.out
 spec/*.pdf
 spec/*.png

-spec/sm/*.pdf

 *.swp
 *~
 
 *.ppk
 
 #sim
 *.swp
 *~
 
 *.ppk
 
 #sim

-sim/
+sim/post
+sim/beh

 
 #modelsim
 src/transcript
 
 #modelsim
 src/transcript


@@ -24,3 +24,9 @@ quartus/calc/
 src/quartus*.tmp
 quartus/project_web.tcl
 quartus/project_tilab.tcl
 src/quartus*.tmp
 quartus/project_web.tcl
 quartus/project_tilab.tcl

+
+#stuff
+tags
+
+#abgabe
+abgabe_g20_*.zip