uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / .gitignore

diff --git a/.gitignore b/.gitignore
index ad19137fe648ad35ae17c530af235e99859d8fda..34721068c010f3c28fd6a439735a6bb452f8c4b3 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -6,7 +6,27 @@ spec/*.toc
 spec/*.backup
 spec/*.out
 spec/*.pdf
+spec/*.png
 *.swp
 *~
 
-*.ppk
\ No newline at end of file
+*.ppk
+
+#sim
+sim/post
+sim/beh
+
+#modelsim
+src/transcript
+
+#quartus
+quartus/calc/
+src/quartus*.tmp
+quartus/project_web.tcl
+quartus/project_tilab.tcl
+
+#stuff
+tags
+
+#abgabe
+abgabe_g20_*.zip