uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / .gitignore

diff --git a/.gitignore b/.gitignore
index 9dc857a91105fd08bfcfb6c3e5b1e88f770a0087..34721068c010f3c28fd6a439735a6bb452f8c4b3 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -7,14 +7,14 @@ spec/*.backup
 spec/*.out
 spec/*.pdf
 spec/*.png
-spec/sm/*.pdf
 *.swp
 *~
 
 *.ppk
 
 #sim
-sim/
+sim/post
+sim/beh
 
 #modelsim
 src/transcript
@@ -22,3 +22,11 @@ src/transcript
 #quartus
 quartus/calc/
 src/quartus*.tmp
+quartus/project_web.tcl
+quartus/project_tilab.tcl
+
+#stuff
+tags
+
+#abgabe
+abgabe_g20_*.zip