library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.gen_pkg.all;

--package int_types is
--	type STATE_UART_TX is (IDLE, STARTBITS, PAYLOAD, PARITY, STOP, DONE);
--	type PARITY_TYPE is (ODD, EVEN, NONE);
--end package int_types;

entity uart_tx is
port(
	sys_clk : in std_logic;
	sys_res : in std_logic;
	--txd : out std_logic;
	--tx_data : in std_logic;
	tx_new : in std_logic;
	tx_done : out std_logic
);
end entity uart_tx;

architecture beh of uart_tx is
	signal timer : integer range 0 to 65535;
	signal timer_next : integer range 0 to 65535;
	constant timer_max : integer := 35;
	signal counter : integer;
	signal counter_next : integer;
begin
	process (sys_clk, sys_res)
	begin
		if sys_res = '0' then
			counter <= 0;
			timer <= 0;
		elsif rising_edge(sys_clk) then
			counter <= counter_next;
			timer <= timer_next;
		end if;
	end process;


	process (timer, counter)
	begin
		if (timer = timer_max) then
			timer_next <= 0;
			counter_next <= counter + 1;
		else
			timer_next <= timer + 1;
			counter_next <= counter;
		end if;
	end process;

	tx_done <= '0';

end architecture beh;