library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;

entity post_alu_tb is
end entity post_alu_tb;

architecture sim of post_alu_tb is
	component alu is
		port
		(
			sys_clk : in std_logic;
			sys_res_n : in std_logic;
			\opcode.NOP\ : in std_logic;
			\opcode.SUB\ : in std_logic;
			\opcode.ADD\ : in std_logic;
			\opcode.MUL\ : in std_logic;
			\opcode.DIV\ : in std_logic;
			\opcode.DONE\ : in std_logic;
			op1 : in std_logic_vector(31 downto 0);
			op2 : in std_logic_vector(31 downto 0);
			op3 : out std_logic_vector(31 downto 0);
			do_calc : in std_logic;
			calc_done : out std_logic
		);
	end component alu;

	signal sys_clk, sys_res_n, do_calc, calc_done : std_logic;
	signal opcode : alu_ops;
	signal \opcode.NOP\ : std_logic;
	signal \opcode.SUB\ : std_logic;
	signal \opcode.ADD\ : std_logic;
	signal \opcode.MUL\ : std_logic;
	signal \opcode.DIV\ : std_logic;
	signal \opcode.DONE\ : std_logic;
	signal op1, op2, op3 : std_logic_vector(31 downto 0);
	signal stop : boolean := false;
begin
	inst : alu
	port map
	(
		sys_clk => sys_clk,
		sys_res_n => sys_res_n,
		do_calc => do_calc,
		calc_done => calc_done,
		op1 => op1,
		op2 => op2,
		op3 => op3,
		\opcode.NOP\ => \opcode.NOP\,
		\opcode.SUB\ => \opcode.SUB\,
		\opcode.ADD\ => \opcode.ADD\,
		\opcode.MUL\ => \opcode.MUL\,
		\opcode.DIV\ => \opcode.DIV\,
		\opcode.DONE\ => \opcode.DONE\
	);

	process
	begin
		sys_clk <= '0';
		wait for 15 ns;
		sys_clk <= '1';
		wait for 15 ns;
		if stop = true then
			wait;
		end if;
	end process;

	process
		type alu_testv is record
			o1 : cinteger;
			o : alu_ops;
			o2 : cinteger;
			expected : cinteger;
		end record alu_testv;

		-- ggf. groesse des arrays erhoehen
		type alu_testv_array is array (natural range 0 to 20) of alu_testv;

		variable testmatrix : alu_testv_array :=
			( 0 => (-5, DIV, 3, -1),
			  1 => (7, ADD, 3, 10),
			  2 => (7, SUB, 1, 6),
			  3 => (7, DIV, 1, 7),
			  4 => (7, DIV, 3, 2),
			  5 => (7, ADD, 1, 8),
			  6 => (7, MUL, 3, 21),
			  7 => (-7, MUL, 3, -21),
			  8 => (268435456, MUL, -2, -536870912),
			  9 => (268435456, MUL, 2**5, 0), -- um fuenf nach links shiften
			  10 => (268435456 + 5, MUL, 2**5, 160), -- = 5 * (2^5)
			  11 => (100, DIV, 10, 10),
			  12 => (100, DIV, 51, 1),
			  13 => (100, DIV, 49, 2),
			  14 => (153156, DIV, 3543, 43),
			  15 => (-153156, DIV, 3543, -43),
			  16 => (153156, DIV, -3543, -43),
			  17 => (-153156, DIV, -3543, 43),
			  others => (0, ADD, 0, 0)
			);

	begin
		sys_res_n <= '0';
		wait for 50 ns;
		sys_res_n <= '1';

		for i in testmatrix'range loop
			wait for 100 ns;
			\opcode.NOP\ <= '0';
			\opcode.SUB\ <= '0';
			\opcode.ADD\ <= '0';
			\opcode.MUL\ <= '0';
			\opcode.DIV\ <= '0';
			\opcode.DONE\ <= '0';
			op1 <= std_logic_vector(to_signed(testmatrix(i).o1,CBITS));
			case testmatrix(i).o is
				when NOP => \opcode.NOP\ <= '1';
				when SUB => \opcode.SUB\ <= '1';
				when ADD => \opcode.ADD\ <= '1';
				when MUL => \opcode.MUL\ <= '1';
				when DIV => \opcode.DIV\ <= '1';
				when DONE => \opcode.DONE\ <= '1';
			end case;
			op2 <= std_logic_vector(to_signed(testmatrix(i).o2,CBITS));

			-- berechnung kann los gehen
			do_calc <= '1';

			-- warten auf die alu einheit
			wait on calc_done;

			assert op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))
				report "" & cinteger'image(testmatrix(i).o1) & 
				" " & alu_ops'image(opcode) &
				" " & cinteger'image(testmatrix(i).o2) &
				"/= " & integer'image(to_integer(signed(op3))) &
				" -- erwartet: " & cinteger'image(testmatrix(i).expected);

			wait for 5 ns;
			-- ack it!
			do_calc <= '0';
		end loop;

		assert false
			report "alle testfaelle der ALU waren erfolgreich!";
		stop <= true;
		wait;
	end process;
end architecture sim;