library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;

entity pc_communication is
	port (
		sys_clk : in std_logic;
		sys_res_n : in std_logic;
		--button
		btn_a : in std_logic;
		--uart_tx
		tx_data : out std_logic_vector(7 downto 0);
		tx_new : out std_logic;
		tx_done : in std_logic;
		--uart_rx
		rx_data : in std_logic_vector(7 downto 0);
		rx_new : in std_logic;
		-- History
		pc_zeile : out hzeile;
		pc_spalte : out hspalte;
		pc_get :  out std_logic;
		pc_done : in std_logic;
		pc_char : in hbyte
	);
end entity pc_communication;

architecture beh of pc_communication is
	signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
	signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
	signal get, get_next : std_logic;
	signal new_i, new_i_next : std_logic;
	signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);

	type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT,
		NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
		PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
		PRINT_NO5_WAIT, PRINT_NO6);
	signal state, state_next : STATE_PC ;
begin
	pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
	pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
	pc_get <= get;
	tx_new <= new_i;
	tx_data <= tx_data_i;

	sync: process (sys_clk, sys_res_n)
	begin
		if sys_res_n = '0' then
			state <= IDLE;
			spalte <= 1;
			zeile <= 0;
			get <= '0';
			new_i <= '0';
			tx_data_i <= x"00";
		elsif rising_edge(sys_clk) then
			spalte <= spalte_next;
			zeile <= zeile_next;
			state <= state_next;
			get <= get_next;
			new_i <= new_i_next;
			tx_data_i <= tx_data_i_next;
		end if;
	end process sync;

	process (state, zeile, spalte, tx_data_i, tx_done, pc_char, rx_new, btn_a,
			pc_done, rx_data)
		variable tmp : std_logic_vector(6 downto 0);
	begin
		get_next <= '0';
		new_i_next <= '0';
		spalte_next <= spalte;
		zeile_next <= zeile;
		tx_data_i_next <= tx_data_i;

		state_next <= state;
		case state is
			when IDLE =>
				zeile_next <= 0;
				spalte_next <= 1;
				if ((rx_new = '1' and rx_data = x"41") or btn_a = '0') and tx_done = '0' then
					state_next <= PRINT_NO1;
				end if;

			when PRINT_NO1 =>
				tx_data_i_next <= x"28"; -- '('
				new_i_next <= '1';
				if tx_done = '1' then
					state_next <= PRINT_NO1_WAIT;
				end if;
			when PRINT_NO1_WAIT =>
				if tx_done = '0' then
					state_next <= PRINT_NO2;
				end if;
			when PRINT_NO2 =>
				tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
				new_i_next <= '1';
				if tx_done = '1' then
					state_next <= PRINT_NO2_WAIT;
				end if;
			when PRINT_NO2_WAIT =>
				if tx_done = '0' then
					state_next <= PRINT_NO3;
				end if;
			when PRINT_NO3 =>
				tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
				new_i_next <= '1';
				if tx_done = '1' then
					state_next <= PRINT_NO3_WAIT;
				end if;
			when PRINT_NO3_WAIT =>
				if tx_done = '0' then
					state_next <= PRINT_NO4;
				end if;
			when PRINT_NO4 =>
				tx_data_i_next <= x"29"; -- ')'
				new_i_next <= '1';
				if tx_done = '1' then
					state_next <= PRINT_NO4_WAIT;
				end if;
			when PRINT_NO4_WAIT =>
				if tx_done = '0' then
					state_next <= PRINT_NO5;
				end if;
			when PRINT_NO5 =>
				tx_data_i_next <= x"24"; -- '$'
				new_i_next <= '1';
				if tx_done = '1' then
					state_next <= PRINT_NO5_WAIT;
				end if;
			when PRINT_NO5_WAIT =>
				if tx_done = '0' then
					state_next <= PRINT_NO6;
				end if;
			when PRINT_NO6 =>
				tx_data_i_next <= x"20"; -- ' '
				new_i_next <= '1';
				if tx_done = '1' then
					state_next <= FETCH;
				end if;

			when FETCH =>
				get_next <= '1';
				if pc_done = '1' and tx_done = '0' then
					state_next <= FORWARD;
					if pc_char = x"00" then
						state_next <= UART_DONE;
					end if;
				end if;
			when FORWARD =>
				tx_data_i_next <= pc_char;
				new_i_next <= '1';
				-- halte pc_get weiterhin high sodass pc_char garantiert
				-- gleicht bleibt (blockiert history!)
				get_next <= '1';
				if tx_done = '1' then
					state_next <= UART_DONE;
				end if;
			when UART_DONE =>
				if tx_done = '0' then
					state_next <= FETCH;
					spalte_next <= spalte + 1;
					if spalte = HSPALTE_MAX + 1 then
						state_next <= NL;
						spalte_next <= 1;
						zeile_next <= zeile + 1;
					end if;
				end if;
			when NL =>
				tx_data_i_next <= x"0a";
				new_i_next <= '1';
				if tx_done = '1' then
					state_next <= NL_WAIT;
				end if;
			when NL_WAIT =>
				if tx_done = '0' then
					state_next <= CR;
				end if;
			when CR =>
				tx_data_i_next <= x"0d";
				new_i_next <= '1';
				if tx_done = '1' then
					state_next <= CR_WAIT;
				end if;
			when CR_WAIT =>
				if tx_done = '0' then
					tmp := std_logic_vector(to_unsigned(zeile,7));
					if tmp(0) = '0' then
						-- es handelt sich um eingabe im naechsten schritt
						-- => print zeilennummer
						state_next <= PRINT_NO1;
					else
						state_next <= FETCH;
					end if;
				end if;
				if zeile = HZEILE_MAX then
					state_next <= IDLE;
				end if;
		end case;
	end process;
end architecture beh;