library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;

entity history is
	port (
		sys_clk : in std_logic;
		sys_res_n : in std_logic;
		-- PC-komm
		-- TODO: pins
		-- Scanner
		s_char : in hbyte;
		s_take : in std_logic;
		s_done : out std_logic;
		s_backspace : in std_logic;
		-- Display
		d_new_eingabe : out std_logic;
		d_new_result : out std_logic;
		d_zeile : in hzeile;
		d_spalte : in hspalte;
		d_get : in std_logic;
		d_done : out std_logic;
		d_char : out hbyte
		-- Parser
		-- TODO: pins
	);
end entity history;

architecture beh of history is
	type HISTORY_STATE is (SIDLE);
	signal state_int, state_next : HISTORY_STATE;
	signal s_done_int, s_done_next : std_logic;
	signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
	signal d_new_result_int, d_new_result_next : std_logic;
	signal d_done_int, d_done_next : std_logic;
	signal d_char_int, d_char_next : hbyte;
begin
	s_done <= s_done_int;
	d_new_eingabe <= d_new_eingabe_int;
	d_new_result <= d_new_result_int;
	d_done <= d_done_int;
	d_char <= d_char_int;

	process(sys_clk, sys_res_n)
	begin
		if sys_res_n = '0' then
			-- internal
			state_int <= SIDLE;
			-- out
			s_done_int <= '0';
			d_new_result_int <= '0';
			d_new_eingabe_int <= '0';
			d_done_int <= '0';
			d_char_int <= (others => '0');
		elsif rising_edge(sys_clk) then
			-- internal
			state_int <= state_next;
			-- out
			s_done_int <= s_done_next;
			d_new_result_int <= d_new_result_next;
			d_new_eingabe_int <= d_new_eingabe_next;
			d_done_int <= d_done_next;
			d_char_int <= d_char_next;
		end if;
	end process;

	-- next state
	process(state_int)
	begin
		state_next <= state_int;

		case state_int is
			when SIDLE =>
				null;
		end case;
	end process;

	-- out
	process(state_int)
	begin
		case state_int is
			when SIDLE =>
				null;
		end case;
	end process;
end architecture beh;