library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_pkg.all;

package gen_pkg is
	subtype alu_ops is std_logic_vector(2 downto 0);
	constant ALU_NOP : alu_ops := "000";
	constant ALU_SUB : alu_ops := "001";
	constant ALU_ADD : alu_ops := "010";
	constant ALU_MUL : alu_ops := "011";
	constant ALU_DIV : alu_ops := "100";
	constant ALU_DONE : alu_ops := "101";

	constant CBITS : integer := 32;
	subtype csigned is signed((CBITS-1) downto 0);
	subtype divinteger is integer range -33 to 33;
	-- integer ist 32bit (31bit + sign)
	subtype cinteger is integer;

	-- vorerst: 2 * 71
	-- constant H_RAM_SIZE : integer := 142;
	-- danach: 50 * 71 * 2 = 7100
	constant H_RAM_SIZE : integer := 7100;
	constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
	subtype hspalte is std_logic_vector(6 downto 0);
	subtype hzeile is std_logic_vector(4 downto 0);
	subtype hbyte is std_logic_vector(7 downto 0);
	subtype hstring is string(1 to 71);
	subtype hstr_int is integer range 0 to 72;

	function find_msb(a : csigned) return divinteger;
	procedure icwait(signal clk_i : IN std_logic; cycles: natural);
end package gen_pkg;

package body gen_pkg is
	function find_msb(a : csigned) return divinteger is
		variable r : divinteger := 0;
	begin
		for i in (CBITS-1) downto 0 loop
			exit when a(i) = '1';
			r := r+1;
		end loop;
		return (CBITS - r);
	end function find_msb;

	procedure icwait(signal clk_i : IN std_logic; cycles: Natural) is
	begin
		for i in 1 to cycles loop
			wait until clk_i= '0' and clk_i'event;
		end loop;
	end;
end package body gen_pkg;