library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;
use work.textmode_vga_component_pkg.all;
use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;

entity display is
	port (
		sys_clk : in std_logic;
		sys_res_n : in std_logic;
		-- History
		d_new_eingabe : in std_logic;
		d_new_result : in std_logic;
		d_new_bs : in std_logic;
		d_zeile : out hzeile;
		d_spalte : out hspalte;
		d_get : out std_logic;
		d_done : in std_logic;
		d_char : in hbyte;
		-- VGA
		command : out std_logic_vector(7 downto 0);
		command_data : out std_logic_vector(31 downto 0);
		free : in std_logic
	);
end entity display;

architecture beh of display is
	type DISPLAY_STATE is (SIDLE, S_NEW_BS, S_BACK, S_BLANK, S_NEW_RESULT,
		S_ZEILEUP, S_NEW_INPUT, S_COUNTUP, S_GETCH, S_CR1, S_NL1, S_PUTCH1,
		S_PUTCH2, S_WAIT, S_NOP1, S_READ_RESULT);
	signal state_int, state_next : DISPLAY_STATE;
	signal d_zeile_int, d_zeile_next : hzeile;
	signal d_spalte_int, d_spalte_next : hspalte;
	signal d_get_int, d_get_next : std_logic;
	signal command_int, command_next : std_logic_vector(7 downto 0);
	signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
	signal istate_next, istate_int : signed(2 downto 0);
begin
	d_zeile <= d_zeile_int;
	d_spalte <= d_spalte_int;
	d_get <= d_get_int;
	command <= command_int;
	command_data <= command_data_int;

	process(sys_clk, sys_res_n)
	begin
		if sys_res_n = '0' then
			-- internal
			state_int <= SIDLE;
			istate_int <= (others => '0');
			-- out
			d_zeile_int <= (others => '0');
			d_spalte_int <= (others => '0');
			d_get_int <= '0';
			command_int <= COMMAND_NOP;
			command_data_int <= (others => '0');
		elsif rising_edge(sys_clk) then
			-- internal
			state_int <= state_next;
			istate_int <= istate_next;
			-- out
			d_zeile_int <= d_zeile_next;
			d_spalte_int <= d_spalte_next;
			d_get_int <= d_get_next;
			command_int <= command_next;
			command_data_int <= command_data_next;
		end if;
	end process;

	-- next state
	process(state_int, d_new_result, d_new_eingabe, d_new_bs, d_done, free,
		d_spalte_int, d_char, istate_int)
	begin
		state_next <= state_int;
		istate_next <= istate_int;

		case state_int is
			when SIDLE =>
				istate_next <= b"111"; -- default: immer wieder ins SIDLE;
				if d_new_bs = '1' then
					state_next <= S_NEW_BS;
				elsif d_new_eingabe = '1' then
					state_next <= S_NEW_INPUT;
				end if;
				if d_new_result = '1' then
					state_next <= S_NEW_RESULT;
				end if;

			when S_NEW_RESULT =>
				state_next <= S_ZEILEUP;
			when S_NEW_INPUT =>
				state_next <= S_COUNTUP;

			when S_NEW_BS =>
				state_next <= S_BACK;
			when S_BACK =>
				if free = '0' then
					state_next <= S_WAIT;
					case istate_int is
						when b"111" => istate_next <= b"001"; -- => danach S_BLANK und wieder hierher
						when others => istate_next <= b"111"; -- => danach SIDLE
					end case;
				end if;
			when S_BLANK =>
				if free = '0' then
					state_next <= S_WAIT;
					istate_next <= b"010"; -- => danach S_BACK
				end if;

			when S_ZEILEUP =>
				case istate_int is
					when b"011" =>
						state_next <= S_WAIT;
						istate_next <= b"111";
					when others => state_next <= S_CR1;
				end case;

			when S_CR1 =>
				if free = '0' then
					state_next <= S_WAIT;
					case istate_int is
						when b"110" => istate_next <= b"101"; -- => danach S_NL1 und SIDLe
						when others => istate_next <= b"000"; -- => danach S_NL1 und S_COUNTUP
					end case;
				end if;
			when S_NL1 =>
				if free = '0' then
					state_next <= S_WAIT;
					case istate_int is
						when b"101" => istate_next <= b"011"; -- => danach S_ZEILEUP
						when others => istate_next <= b"100"; -- => danach S_READ_RESULT
					end case;
				end if;
			when S_READ_RESULT =>
				if unsigned(d_spalte_int) /= 70 then
					state_next <= S_COUNTUP;
					istate_next <= b"100"; -- => wieder nach S_READ_RESULT
				else
					state_next <= S_WAIT;
					istate_next <= b"110"; -- => danach S_CR1 und d_spalte_next clearen und d_zeile_next inkrementieren
				end if;

			when S_COUNTUP =>
				state_next <= S_GETCH;
			when S_GETCH =>
				if free = '1' and d_done = '1' and d_new_result = '0' and d_new_eingabe = '0' then
					state_next <= S_PUTCH1;
				end if;
			when S_PUTCH1 =>
				state_next <= S_PUTCH2;
			when S_PUTCH2 =>
				if free = '0' or (free = '1' and d_char = x"00") then
					state_next <= S_WAIT;
				end if;
			when S_WAIT =>
				if free = '1' and d_done = '0' then
					state_next <= S_NOP1;
				end if;
			when S_NOP1 =>
				if free = '1' then
					case istate_int is
						when b"000" => state_next <= S_NL1;
						when b"001" => state_next <= S_BLANK;
						when b"010" => state_next <= S_BACK;
						when b"011" => state_next <= S_ZEILEUP;
						when b"100" => state_next <= S_READ_RESULT;
						when b"110" => state_next <= S_CR1;
						when b"101" => state_next <= S_NL1;
						when others => state_next <= SIDLE;
					end case;
				end if;
		end case;
	end process;

	-- out
	process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
		command_data_int, d_char, istate_int)
	begin
		d_zeile_next <= d_zeile_int;
		d_spalte_next <= d_spalte_int;
		d_get_next <= '0';
		command_next <= command_int;
		command_data_next <= command_data_int;

		case state_int is
			when SIDLE =>
				null;
			when S_NEW_RESULT =>
			when S_NEW_INPUT =>
				null;

			when S_NEW_BS =>
				-- underflow check schon im history modul
				d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) - 1);
			when S_BACK =>
				-- einen schritt zurueck
				command_next <= COMMAND_SET_CURSOR_COLUMN;
				command_data_next <= x"ffffff" & '0' & std_logic_vector(unsigned(d_spalte_int));
			when S_BLANK =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"ffffff" & x"20"; -- white space

			when S_ZEILEUP =>
				d_spalte_next <= (others => '0');
				case d_zeile_int is
					when "1111111" => d_zeile_next <= (others => '0');
					when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
				end case;

			when S_CR1 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"ffffff" & x"0d"; -- carrige return
			when S_NL1 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"ffffff" & x"0a"; -- newline
			when S_READ_RESULT => null;

			when S_COUNTUP =>
				d_get_next <= '1';
				d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1);
			when S_GETCH =>
				d_get_next <= '1';
			when S_PUTCH1 =>
				if d_char /= x"00" then
					command_next <= COMMAND_SET_CHAR;
					command_data_next <= x"ffffff" & std_logic_vector(d_char);
				end if;
			when S_PUTCH2 => null;
			when S_WAIT | S_NOP1 =>
				command_next <= COMMAND_NOP;
				command_data_next <= x"00000000";
		end case;
	end process;
end architecture beh;