library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clk_vga_s3e is
	port (
		clk50 : in std_logic;
		clk25 : out std_logic
	);
end clk_vga_s3e;

architecture beh of clk_vga_s3e is
	signal clk25_int : std_logic;
begin
	clk25 <= clk25_int;
	process (clk50)
	begin
		if clk50'event and clk50='1' then
			clk25_int <= not clk25_int;
		end if;
	end process;
end architecture beh;