-- TODO: dient im moment nur als "fake top entity"
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;

entity calc is
	port
	(
		sys_clk : in std_logic;
		sys_res_n : in std_logic
	);
end entity calc;

architecture top of calc is
	component alu is
		port
		(
			sys_clk : in std_logic;
			sys_res_n : in std_logic;
			opcode : in alu_ops;
			op1 : in csigned;
			op2 : in csigned;
			op3 : out csigned;
			do_calc : in std_logic;
			calc_done : out std_logic
		);
	end component alu;

	signal do_calc, calc_done : std_logic;
	signal opcode : alu_ops;
	signal op1, op2, op3 : csigned;
begin
	aluc : alu
	port map
	(
		sys_clk => sys_clk,
		sys_res_n => sys_res_n,
		do_calc => do_calc,
		calc_done => calc_done,
		op1 => op1,
		op2 => op2,
		op3 => op3,
		opcode => opcode
	);

	process
	begin
		op1 <= op3;
		opcode <= DIV;
		op2 <= to_signed(2,CBITS);

		do_calc <= calc_done;
		wait until sys_clk = '1';
	end process;
end architecture top;