library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;

entity beh_history_tb is
end entity beh_history_tb;

architecture sim of beh_history_tb is
	-- system
	signal sys_clk, sys_res_n : std_logic;
	-- history/display
	signal d_new_eingabe, d_new_result : std_logic;
	signal d_zeile : hzeile;
	signal d_spalte : hspalte;
	signal d_get, d_done : std_logic;
	signal d_char : hbyte;
	-- history/scanner
	signal s_char : hbyte;
	signal s_take, s_done, s_backspace : std_logic;

	-- tmp: history<>scanner
	signal do_it, finished : std_logic;

	signal stop : boolean := false;
begin
	-- history
	inst : entity work.history(beh)
	port map (
		sys_clk => sys_clk,
		sys_res_n => sys_res_n,
		-- scanner
		s_char => s_char,
		s_take => s_take,
		s_done => s_done,
		s_backspace => s_backspace,
		-- display
		d_new_eingabe => d_new_eingabe,
		d_new_result => d_new_result,
		d_zeile => d_zeile,
		d_spalte => d_spalte,
		d_get => d_get,
		d_done => d_done,
		d_char => d_char,
		-- TODO: tmp only!
		do_it => do_it,
		finished => finished
	);

	process
	begin
		sys_clk <= '0';
		wait for 15 ns;
		sys_clk <= '1';
		wait for 15 ns;
		if stop = true then
			wait;
		end if;
	end process;

	process
		variable input : hstring := "12345678                                                                ";
		variable ctmp : character;

		variable checkall : boolean := true;
		variable i : integer := 1;
		variable j : integer;
	begin
		-- init & reset
		sys_res_n <= '0';
		s_char <= x"00";
		s_take <= '0';
		s_backspace <= '0';
		d_zeile <= (others => '0');
		d_spalte <= (others => '0');
		d_get <= '0';
		do_it <= '0';

		icwait(sys_clk, 5);
		sys_res_n <= '1';

		while i <= 10 loop
			s_take <= '1';
			ctmp := input(i);
			s_char <= hbyte(to_unsigned(character'pos(ctmp),8));
			wait on s_done;
			s_take <= '0';
			icwait(sys_clk, 2);
			j := 1;
			while j <= i loop
				d_spalte <= std_logic_vector(to_unsigned(j,7));
				d_zeile <= (others => '0');
				d_get <= '1';
				wait on d_done;
				icwait(sys_clk, 1);
				if d_char /= hbyte(to_unsigned(character'pos(input(j)),8)) then
					assert(false) report "passt nicht? d_char: "
					& character'val(to_integer(unsigned(d_char))) & ", solte sein: "
					& input(j);
					checkall := false;
				end if;
				d_get <= '0';
				icwait(sys_clk, 2);
				j := j + 1;
			end loop;
			i := i + 1;
		end loop;

		do_it <= '1';
		wait on finished;
		icwait(sys_clk, 2);
		do_it <= '0';


		if checkall then
			report "alle testfaelle der History waren erfolgreich!";
		else
			report "einige testfaelle schlugen fehl";
		end if;
		icwait(sys_clk, 10);
		stop <= true;
		wait;
	end process;
end architecture sim;