library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;
use work.textmode_vga_component_pkg.all;
use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;

entity beh_display_tb is
end entity beh_display_tb;

architecture sim of beh_display_tb is
	-- system
	signal sys_clk, sys_res_n : std_logic;
	-- vga/display
	signal free : std_logic;
	signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
	signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
	-- history/display
	signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
	signal d_zeile : hzeile;
	signal d_spalte : hspalte;
	signal d_get, d_done : std_logic;
	signal d_char : hbyte;
	-- history/scanner
	signal s_char : hbyte;
	signal s_take, s_done, s_backspace : std_logic;

	signal stop : boolean := false;
begin
	-- display
	inst : display
	port map (
		sys_clk => sys_clk,
		sys_res_n => sys_res_n,
		-- history
		d_new_eingabe => d_new_eingabe,
		d_new_result => d_new_result,
		d_new_bs => d_new_bs,
		d_zeile => d_zeile,
		d_spalte => d_spalte,
		d_get => d_get,
		d_done => d_done,
		d_char => d_char,
		-- vga
		command => command,
		command_data => command_data,
		free => free
	);

	process
	begin
		sys_clk <= '0';
		wait for 15 ns;
		sys_clk <= '1';
		wait for 15 ns;
		if stop = true then
			wait;
		end if;
	end process;

	process
	begin
		free <= '0';
		wait for 15 ns;
		free <= '1';
		wait for 30 ns;
		if stop = true then
			wait;
		end if;
	end process;

	process
		variable input : hstring := "123513                                                                  ";
		variable ctmp : character;

		variable checkall : boolean := true;
		variable i : integer := 1;
	begin
		-- init & reset
		sys_res_n <= '0';
		d_new_eingabe <= '0';
		d_new_result <= '0';
		d_new_bs <= '0';
		d_done <= '0';
		d_char <= x"00";

		icwait(sys_clk, 5);
		sys_res_n <= '1';

		while i <= 5 loop
			icwait(sys_clk, 10);
			d_new_eingabe <= '1';
			wait on d_get; -- = '1';
			icwait(sys_clk, 1);
			d_new_eingabe <= '0';

			ctmp := input(to_integer(unsigned(d_spalte)));
			d_char <= hbyte(to_unsigned(character'pos(ctmp),8));

			d_done <= '1';
			wait on d_get; -- = '0';
			icwait(sys_clk, 1);
			d_done <= '0';

			i := i + 1;
		end loop;

		icwait(sys_clk, 2);
		d_new_result <= '1';
		icwait(sys_clk, 2);
		d_new_result <= '0';

		if checkall then
			report "alle testfaelle des Displays waren erfolgreich!";
		else
			report "nicht alle testfaelle des Displays waren erfolgreich!";
		end if;
		icwait(sys_clk, 10);
		stop <= true;
		wait;
	end process;
end architecture sim;