library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;

entity alu is
	port
	(
		sys_clk : in std_ulogic;
		sys_res_n : in std_ulogic;
		opcode : in alu_ops;
		op1 : in signed(31 downto 0);
		op2 : in signed(31 downto 0);
		op3 : out signed(31 downto 0);
		do_calc : in std_ulogic;
		calc_done : out std_ulogic
	);
end entity alu;

architecture beh of alu is
	-- signal cnt_int, cnt_next : integer range 0 to CNT_MAX;
	signal op3_next : signed (31 downto 0);
begin
	process(sys_clk, sys_res_n)
	begin
		if sys_res_n = '0' then
			op3 <= (others => '0');
		elsif rising_edge(sys_clk) then
			op3 <= op3_next;
		end if;
	end process;

	process(do_calc, opcode, op1, op2)
	begin
		case opcode is
			when ADD => op3_next <= op1 + op2;
			when SUB => op3_next <= op1 - op2;
			when MUL => op3_next <= op1 * op2;
			when DIV => op3_next <= op1 / op2;
			when others => op3_next <= (others => '0');
		end case;
		--	calc_done <= '1';
		--else
		--	calc_done <= '0';
		--end if;
	end process;
end architecture beh;