library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.demo_pkg.all; entity demo is port ( clk : in std_logic; reset : in std_logic; leds : out std_logic_vector(7 downto 0)); end demo; architecture behav of demo is function GetShiftDelay return time is begin if SIMULATION then return 1 us; else return 100 ms; end if; end; signal knightlight, knightlight_next : std_logic_vector (7 downto 0); type LEDSTATE_T is (LEFT_S, RIGHT_S); signal ledstate, ledstate_next : LEDSTATE_T; subtype counter_t is integer range 0 to (GetShiftDelay / PERIOD); signal counter : counter_t; signal syncreset : std_logic; begin -- behav process(clk) begin if rising_edge(clk) then syncreset <= reset; end if; end process; sync: process(clk, reset) begin if rising_edge(clk) then if syncreset = RESETVALUE then knightlight <= (others => LED_OFF); knightlight(2 downto 0) <= (others => LED_ON); ledstate <= LEFT_S; else knightlight <= knightlight_next; ledstate <= ledstate_next; end if; end if; end process; next_state_logic: process(ledstate, knightlight, counter) variable knightlight_tmp : bit_vector (7 downto 0); begin -- process -- default assignments ledstate_next <= ledstate; knightlight_tmp := TO_BITVECTOR(knightlight); case ledstate is when LEFT_S => if counter = counter_t'high - 1 then knightlight_tmp := knightlight_tmp sll 1; end if; if knightlight_tmp = "11100000" then ledstate_next <= RIGHT_S; end if; when RIGHT_S => if counter = counter_t'high - 1 then knightlight_tmp := knightlight_tmp srl 1; end if; if knightlight_tmp = "00000111" then ledstate_next <= LEFT_S; end if; when others => null; end case; knightlight_next <= TO_STDLOGICVECTOR(knightlight_tmp); end process; counterProcess: process(clk, reset) begin -- process if rising_edge(clk) then if syncreset = RESETVALUE then counter <= 0; elsif counter < counter_t'high then counter <= counter + 1; else counter <= 0; end if; end if; end process; leds <= not knightlight; end behav;