# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		demo_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C35F484C6
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY demo_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:09:40  MARCH 24, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id eda_simulation
set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT ../sim/demo_tb_rtl.do -section_id eda_simulation
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VHDL_FILE ../src/demo_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/demo.vhd
set_global_assignment -name VHDL_FILE ../src/pll.vhd
set_global_assignment -name BDF_FILE ../src/demo_top.bdf
set_location_assignment PIN_M1 -to CLK
set_location_assignment PIN_B3 -to RESET
set_location_assignment PIN_W5 -to LEDS[0]
set_location_assignment PIN_W4 -to LEDS[1]
set_location_assignment PIN_W3 -to LEDS[2]
set_location_assignment PIN_W2 -to LEDS[3]
set_location_assignment PIN_W1 -to LEDS[4]
set_location_assignment PIN_V2 -to LEDS[5]
set_location_assignment PIN_V1 -to LEDS[6]
set_location_assignment PIN_U1 -to LEDS[7]