# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 222 10/21/2009 SJ Full Version
# Date created = 10:23:26  March 26, 2010
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		mjl_stratix_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY Stratix
set_global_assignment -name DEVICE EP1S25F672C6
set_global_assignment -name TOP_LEVEL_ENTITY debounce_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:23:26  MARCH 26, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION 9.1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MISC_FILE mjl_stratix.dpf
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name VHDL_FILE ../src/counter.vhd
set_global_assignment -name VHDL_FILE ../src/counter_beh.vhd
set_global_assignment -name VHDL_FILE ../src/debounce.vhd
set_global_assignment -name VHDL_FILE ../src/debounce_fsm.vhd
set_global_assignment -name VHDL_FILE ../src/debounce_fsm_beh.vhd
set_global_assignment -name VHDL_FILE ../src/debounce_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/debounce_struct.vhd
set_global_assignment -name VHDL_FILE ../src/debounce_tb.vhd
set_global_assignment -name VHDL_FILE ../src/debounce_top.vhd
set_global_assignment -name VHDL_FILE ../src/debounce_top_struct.vhd
set_global_assignment -name VHDL_FILE ../src/event_counter.vhd
set_global_assignment -name VHDL_FILE ../src/event_counter_beh.vhd
set_global_assignment -name VHDL_FILE ../src/event_counter_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/math_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/sync.vhd
set_global_assignment -name VHDL_FILE ../src/sync_beh.vhd
set_global_assignment -name VHDL_FILE ../src/sync_pkg.vhd
set_location_assignment PIN_T2 -to seg_b[6]
set_location_assignment PIN_AA11 -to seg_b[5]
set_location_assignment PIN_R6 -to seg_b[4]
set_location_assignment PIN_R4 -to seg_b[3]
set_location_assignment PIN_N8 -to seg_b[2]
set_location_assignment PIN_Y11 -to seg_b[0]
set_location_assignment PIN_N7 -to seg_b[1]
set_location_assignment PIN_R23 -to seg_a[6]
set_location_assignment PIN_R22 -to seg_a[5]
set_location_assignment PIN_R21 -to seg_a[4]
set_location_assignment PIN_R20 -to seg_a[3]
set_location_assignment PIN_R19 -to seg_a[2]
set_location_assignment PIN_R9 -to seg_a[1]
set_location_assignment PIN_R8 -to seg_a[0]
set_location_assignment PIN_N3 -to sys_clk
set_location_assignment PIN_AF17 -to sys_res_n
set_location_assignment PIN_A3 -to btn_a
set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top