src/history.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity history is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10                 -- PC-komm
  11                 pc_get :  in std_logic;
  12                 pc_spalte : in hspalte;
  13                 pc_zeile : in hzeile;
  14                 pc_char : out hbyte;
  15                 pc_done : out std_logic;
  16                 -- Scanner
  17                 s_char : in hbyte;
  18                 s_take : in std_logic;
  19                 s_done : out std_logic;
  20                 s_backspace : in std_logic;
  21                 -- Display
  22                 d_new_eingabe : out std_logic;
  23                 d_new_result : out std_logic;
  24                 d_new_bs : out std_logic;
  25                 d_zeile : in hzeile;
  26                 d_spalte : in hspalte;
  27                 d_get : in std_logic;
  28                 d_done : out std_logic;
  29                 d_char : out hbyte;
  30                 -- Parser
  31                 p_rget : in std_logic;
  32                 p_rdone : out std_logic;
  33                 p_read : out hbyte;
  34                 p_wtake : in std_logic;
  35                 p_wdone : out std_logic;
  36                 p_write : in hbyte;
  37                 p_finished : in std_logic
  38         );
  39 end entity history;
  40
  41 architecture beh of history is
  42         type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
  43                 S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
  44                 S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ);
  45         signal state_int, state_next : HISTORY_STATE;
  46         signal was_bs_int, was_bs_next : std_logic;
  47         signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  48         signal s_done_int, s_done_next : std_logic;
  49         signal s_cnt_int, s_cnt_next : hspalte;
  50         signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
  51         signal d_new_result_int, d_new_result_next : std_logic;
  52         signal d_new_bs_int, d_new_bs_next: std_logic;
  53         signal d_done_int, d_done_next : std_logic;
  54         signal d_char_int, d_char_next : hbyte;
  55         signal p_rdone_int, p_rdone_next : std_logic;
  56         signal p_wdone_int, p_wdone_next : std_logic;
  57         signal p_read_int, p_read_next : hbyte;
  58         signal p_sp_read_int, p_sp_read_next : hspalte;
  59         signal p_sp_write_int, p_sp_write_next : hspalte;
  60         signal pc_char_next ,pc_char_int : hbyte;
  61         signal pc_done_next, pc_done_int : std_logic;
  62
  63         -- ram
  64         signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  65         signal data_out, data_in_next, data_in_int : hbyte;
  66         signal wr_next, wr_int : std_logic;
  67 begin
  68         s_done <= s_done_int;
  69         d_new_eingabe <= d_new_eingabe_int;
  70         d_new_result <= d_new_result_int;
  71         d_new_bs <= d_new_bs_int;
  72         d_done <= d_done_int;
  73         d_char <= d_char_int;
  74         p_rdone <= p_rdone_int;
  75         p_wdone <= p_wdone_int;
  76         p_read <= p_read_int;
  77         pc_done <= pc_done_int;
  78         pc_char <= pc_char_int;
  79
  80         process(sys_clk, sys_res_n)
  81         begin
  82                 if sys_res_n = '0' then
  83                         -- internal
  84                         state_int <= S_INIT;
  85                         was_bs_int <= '0';
  86                         pos_int <= (others => '0');
  87                         -- out
  88                         s_done_int <= '0';
  89                         s_cnt_int <= (0 => '1', others => '0');
  90                         d_new_result_int <= '0';
  91                         d_new_eingabe_int <= '0';
  92                         d_new_bs_int <= '0';
  93                         d_done_int <= '0';
  94                         d_char_int <= (others => '0');
  95                         p_rdone_int <= '0';
  96                         p_wdone_int <= '0';
  97                         p_read_int <= (others => '0');
  98                         p_sp_read_int <= (others => '0');
  99                         p_sp_write_int <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_int'length));
 100
 101                         pc_char_int  <= (others => '0');
 102                         pc_done_int  <= '0';
 103
 104                         address_int <= (0 => '1', others => '0');
 105                         data_in_int <= x"00";
 106                         wr_int <= '0';
 107                 elsif rising_edge(sys_clk) then
 108                         -- internal
 109                         state_int <= state_next;
 110                         was_bs_int <= was_bs_next;
 111                         pos_int <= pos_next;
 112                         -- out
 113                         s_done_int <= s_done_next;
 114                         s_cnt_int <= s_cnt_next;
 115                         d_new_result_int <= d_new_result_next;
 116                         d_new_eingabe_int <= d_new_eingabe_next;
 117                         d_new_bs_int <= d_new_bs_next;
 118                         d_done_int <= d_done_next;
 119                         d_char_int <= d_char_next;
 120                         p_rdone_int <= p_rdone_next;
 121                         p_wdone_int <= p_wdone_next;
 122                         p_read_int <= p_read_next;
 123                         p_sp_read_int <= p_sp_read_next;
 124                         p_sp_write_int <= p_sp_write_next;
 125
 126                         pc_char_int <= pc_char_next;
 127                         pc_done_int <= pc_done_next;
 128
 129                         address_int <= address_next;
 130                         data_in_int <= data_in_next;
 131                         wr_int <= wr_next;
 132                 end if;
 133         end process;
 134
 135         -- next state
 136         process(state_int, d_get, pc_get, p_finished, s_take, s_backspace, was_bs_int,
 137                 p_rget, p_wtake, pos_int, s_cnt_int)
 138         begin
 139                 state_next <= state_int;
 140
 141                 case state_int is
 142                         when S_INIT =>
 143                                 -- ganzen speicher clearen: fuer ausgabe am vga nicht umbedingt
 144                                 -- noetig, aber spaetestens fuers dumpen per rs232
 145                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
 146                                         state_next <= SIDLE;
 147                                 end if;
 148                         when SIDLE =>
 149                                 -- S_S_FIN: tmp..
 150                                 if s_take = '1' then
 151                                         state_next <= S_S_INIT;
 152                                 elsif p_rget = '1' then
 153                                         state_next <= S_P_READ;
 154                                 elsif p_wtake = '1' then
 155                                         state_next <= S_P_WRITE;
 156                                 elsif p_finished = '1' then
 157                                         state_next <= S_S_FIN;
 158                                 elsif d_get = '1' then
 159                                         state_next <= S_D_INIT;
 160                                 elsif pc_get = '1' then
 161                                         state_next <= S_PC_INIT;
 162                                 end if;
 163                         when S_S_INIT =>
 164                                 if s_backspace = '1' then
 165                                         state_next <= S_S_BS;
 166                                 else
 167                                         state_next <= S_S_WRITE;
 168                                 end if;
 169                         when S_S_WRITE =>
 170                                 state_next <= S_S_DONE;
 171                         when S_S_BS =>
 172                                 state_next <= S_S_DONE;
 173                         when S_S_FIN =>
 174                                 if p_finished = '0' then
 175                                         state_next <= S_S_FIN_POSUP;
 176                                 end if;
 177                         when S_S_FIN_POSUP =>
 178                                 state_next <= S_S_CLEAR_NEXT0;
 179                         when S_S_CLEAR_NEXT0 =>
 180                                 if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
 181                                         state_next <= S_S_CLEAR_NEXT1;
 182                                 end if;
 183                         when S_S_CLEAR_NEXT1 =>
 184                                 if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
 185                                         state_next <= SIDLE;
 186                                 end if;
 187                         when S_S_DONE =>
 188                                 if s_take = '0' then
 189                                         state_next <= SIDLE;
 190                                 end if;
 191
 192                         when S_D_INIT =>
 193                                 state_next <= S_D_READ;
 194                         when S_D_READ =>
 195                                 if d_get = '0' then
 196                                         state_next <= SIDLE;
 197                                 end if;
 198                         when S_PC_INIT =>
 199                                 state_next <= S_PC_READ;
 200                         when S_PC_READ =>
 201                                 if pc_get = '0' then
 202                                         state_next <= SIDLE;
 203                                 end if;
 204                         when S_P_READ =>
 205                                 state_next <= S_P_READ_DONE;
 206                         when S_P_READ_DONE =>
 207                                 if p_rget = '0' then
 208                                         state_next <= S_P_DONE;
 209                                 end if;
 210                         when S_P_WRITE =>
 211                                 state_next <= S_P_WRITE_DONE;
 212                         when S_P_WRITE_DONE =>
 213                                 if p_wtake = '0' then
 214                                         state_next <= S_P_DONE;
 215                                 end if;
 216                         when S_P_DONE =>
 217                                 state_next <= SIDLE;
 218                 end case;
 219         end process;
 220
 221         -- out
 222         process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
 223                         data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
 224                         was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
 225                         p_write, p_sp_read_int, p_sp_write_int, pc_char_int, pc_zeile, pc_spalte)
 226                 variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
 227                 variable spalte_tmp : hspalte;
 228                 variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
 229         begin
 230                 s_done_next <= '0';
 231                 s_cnt_next <= s_cnt_int;
 232                 was_bs_next <= was_bs_int;
 233                 pos_next <= pos_int;
 234                 d_new_result_next <= d_new_result_int;
 235                 d_new_eingabe_next <= d_new_eingabe_int;
 236                 d_new_bs_next <= '0';
 237                 d_done_next <= '0';
 238                 d_char_next <= (others => '0');
 239                 wr_next <= '0';
 240                 address_next <= address_int;
 241                 data_in_next <= data_in_int;
 242                 pc_done_next <= '0';
 243                 pc_char_next <= pc_char_int;
 244                 p_rdone_next <= p_rdone_int;
 245                 p_wdone_next <= p_wdone_int;
 246                 p_read_next <= p_read_int;
 247                 p_sp_read_next <= p_sp_read_int;
 248                 p_sp_write_next <= p_sp_write_int;
 249
 250                 case state_int is
 251                         when S_INIT =>
 252                                 wr_next <= '1';
 253                                 address_next <= pos_int;
 254                                 data_in_next <= (others => '0');
 255                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
 256                                         pos_next <= (others => '0');
 257                                 else
 258                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(1,H_RAM_WIDTH));
 259                                 end if;
 260                         when SIDLE =>
 261                                 d_new_result_next <= '0';
 262                         when S_S_INIT =>
 263                                 null;
 264                         when S_S_WRITE =>
 265                                 -- nur bei < HSPALTE_MAX weiter machen
 266                                 -- Hint: '/=' billiger als '<'
 267                                 if unsigned(s_cnt_int) /= HSPALTE_MAX then
 268                                         wr_next <= '1';
 269                                         address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
 270                                         data_in_next <= s_char;
 271                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 272                                 else
 273                                         -- was_bs hier missbrauchen, um ein d_new_eingabe zu verhindern
 274                                         was_bs_next <= '1';
 275                                 end if;
 276                         when S_S_BS =>
 277                                 -- ab 1 darf nicht mehr dekrementiert werden
 278                                 addr_tmp := (others => '0');
 279                                 if unsigned(s_cnt_int) /= 1 then
 280                                         addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1);
 281                                         d_new_bs_next <= '1';
 282                                 else
 283                                         addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int;
 284                                 end if;
 285                                 s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0);
 286                                 wr_next <= '1';
 287                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp));
 288                                 data_in_next <= (others => '0');
 289                                 was_bs_next <= '1';
 290                         when S_S_FIN =>
 291                                 s_cnt_next <= (0 => '1', others => '0');
 292                                 d_new_result_next <= '1';
 293                                 -- resetten der parser counter
 294                                 p_sp_read_next <= (others => '0');
 295                                 p_sp_write_next <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_next'length));
 296                         when S_S_FIN_POSUP =>
 297                                 -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen
 298                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then
 299                                         pos_next <= (others => '0');
 300                                 else
 301                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
 302                                 end if;
 303                         when S_S_CLEAR_NEXT0 =>
 304                                 -- die naechsten 142 bytes im speicher resetten
 305                                 wr_next <= '1';
 306                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
 307                                 data_in_next <= (others => '0');
 308                                 if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
 309                                         s_cnt_next <= (0 => '1', others => '0');
 310                                 else
 311                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 312                                 end if;
 313                         when S_S_CLEAR_NEXT1 =>
 314                                 -- die naechsten 142 bytes im speicher resetten
 315                                 wr_next <= '1';
 316                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(s_cnt_int));
 317                                 data_in_next <= (others => '0');
 318                                 if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
 319                                         s_cnt_next <= (0 => '1', others => '0');
 320                                 else
 321                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 322                                 end if;
 323                         when S_S_DONE =>
 324                                 s_done_next <= '1';
 325                                 if was_bs_int = '0' then
 326                                         d_new_eingabe_next <= '1';
 327                                 end if;
 328                                 if s_take = '0' then
 329                                         was_bs_next <= '0';
 330                                 end if;
 331
 332                         when S_D_INIT =>
 333                                 addr_tmp := (others => '0');
 334                                 addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
 335                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH));
 336                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
 337                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
 338                                 address_next <= addr_tmp;
 339                                 d_new_eingabe_next <= '0';
 340                                 d_new_result_next <= '0';
 341                         when S_D_READ =>
 342                                 d_char_next <= data_out;
 343                                 d_done_next <= '1';
 344
 345                         when S_PC_INIT =>
 346                                 addr_tmp := (others => '0');
 347                                 addr_tmp(hzeile'length - 1 downto 0) := pc_zeile;
 348                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH));
 349                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
 350                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
 351                                 address_next <= addr_tmp;
 352                         when S_PC_READ =>
 353                                 pc_done_next <= '1';
 354                                 pc_char_next <= data_out;
 355
 356                         when S_P_READ =>
 357                                 wr_next <= '0';
 358                                 spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
 359                                 p_sp_read_next <= spalte_tmp;
 360                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp));
 361                         when S_P_READ_DONE =>
 362                                 p_rdone_next <= '1';
 363                                 p_read_next <= data_out;
 364
 365                         when S_P_WRITE =>
 366                                 wr_next <= '1';
 367                                 data_in_next <= p_write;
 368                                 spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
 369                                 p_sp_write_next <= spalte_tmp;
 370                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(spalte_tmp));
 371                         when S_P_WRITE_DONE =>
 372                                 p_wdone_next <= '1';
 373                         when S_P_DONE =>
 374                                 p_rdone_next <= '0';
 375                                 p_wdone_next <= '0';
 376                 end case;
 377         end process;
 378
 379         sp_ram_inst : sp_ram
 380         generic map (
 381                 ADDR_WIDTH => H_RAM_WIDTH
 382         )
 383         port map (
 384                 sys_clk => sys_clk,
 385                 address => address_int,
 386                 data_out => data_out,
 387                 wr => wr_int,
 388                 data_in => data_in_int
 389         );
 390 end architecture beh;