2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 subtype alu_ops is std_logic_vector(2 downto 0);
8 constant ALU_NOP : alu_ops := "000";
9 constant ALU_SUB : alu_ops := "001";
10 constant ALU_ADD : alu_ops := "010";
11 constant ALU_MUL : alu_ops := "011";
12 constant ALU_DIV : alu_ops := "100";
13 constant ALU_DONE : alu_ops := "101";
15 constant CBITS : integer := 32;
16 subtype csigned is signed((CBITS-1) downto 0);
17 subtype divinteger is unsigned(4 downto 0);
18 -- integer ist 32bit (31bit + sign)
19 subtype cinteger is integer;
22 constant HSPALTE_MAX : integer := 71;
23 subtype hspalte is std_logic_vector(6 downto 0);
25 constant HZEILE_MAX : integer := 100;
26 subtype hzeile is std_logic_vector(6 downto 0);
28 -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes
29 constant H_RAM_SIZE : integer := HZEILE_MAX * HSPALTE_MAX;
30 constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
32 subtype hbyte is std_logic_vector(7 downto 0);
33 subtype hstring is string(1 to HSPALTE_MAX+1);
34 subtype hstr_int is integer range 0 to HSPALTE_MAX+1;
36 procedure icwait(signal clk_i : IN std_logic; cycles: natural);
38 function ascii2sc (x : hbyte) return hbyte;
39 function valid_char (x : hbyte) return boolean;
40 function zeile2char(i : std_logic_vector; stelle : natural) return hbyte;
42 -- http://www.marjorie.de/ps2/scancode-set2.htm
43 constant SC_KP_0 : hbyte := x"70";
44 constant SC_KP_1 : hbyte := x"69";
45 constant SC_KP_2 : hbyte := x"72";
46 constant SC_KP_3 : hbyte := x"7a";
47 constant SC_KP_4 : hbyte := x"6b";
48 constant SC_KP_5 : hbyte := x"73";
49 constant SC_KP_6 : hbyte := x"74";
50 constant SC_KP_7 : hbyte := x"6c";
51 constant SC_KP_8 : hbyte := x"75";
52 constant SC_KP_9 : hbyte := x"7d";
54 constant SC_0 : hbyte := x"45";
55 constant SC_1 : hbyte := x"16";
56 constant SC_2 : hbyte := x"1e";
57 constant SC_3 : hbyte := x"26";
58 constant SC_4 : hbyte := x"25";
59 constant SC_5 : hbyte := x"2e";
60 constant SC_6 : hbyte := x"36";
61 constant SC_7 : hbyte := x"3d";
62 constant SC_8 : hbyte := x"3e";
63 constant SC_9 : hbyte := x"46";
65 constant SC_KP_PLUS : hbyte := x"79";
66 constant SC_KP_MINUS : hbyte := x"7b";
67 constant SC_KP_MUL : hbyte := x"7c";
68 constant SC_KP_DIV : hbyte := x"4a"; -- inkl. 0xe0!
70 -- fuer deutsches layout, alle anderen zeichen sind unguenstig belegt
71 constant SC_PLUS : hbyte := x"5b";
73 constant SC_ENTER : hbyte := x"5a";
74 constant SC_BKSP : hbyte := x"66";
75 constant SC_SPACE : hbyte := x"29";
80 sys_clk : in std_logic;
81 sys_res_n : in std_logic;
87 do_calc : in std_logic;
88 calc_done : out std_logic;
89 calc_error : out std_logic
95 sys_clk : in std_logic;
96 sys_res_n : in std_logic;
98 p_rget : out std_logic;
99 p_rdone : in std_logic;
101 p_wtake : out std_logic;
102 p_wdone : in std_logic;
104 p_finished : out std_logic;
106 do_it : in std_logic;
107 finished : out std_logic
109 end component parser;
113 sys_clk : in std_logic;
114 sys_res_n : in std_logic;
116 new_data : in std_logic;
117 data : in std_logic_vector(7 downto 0);
120 s_take : out std_logic;
121 s_done : in std_logic;
122 s_backspace : out std_logic;
124 do_it : out std_logic;
125 finished : in std_logic
127 end component scanner;
131 sys_clk : in std_logic;
132 sys_res_n : in std_logic;
134 pc_get : in std_logic;
135 pc_spalte : in hspalte;
136 pc_zeile : in hzeile;
138 pc_done : out std_logic;
141 s_take : in std_logic;
142 s_done : out std_logic;
143 s_backspace : in std_logic;
145 d_new_eingabe : out std_logic;
146 d_new_result : out std_logic;
147 d_new_bs : out std_logic;
149 d_spalte : in hspalte;
150 d_get : in std_logic;
151 d_done : out std_logic;
154 p_rget : in std_logic;
155 p_rdone : out std_logic;
157 p_wtake : in std_logic;
158 p_wdone : out std_logic;
160 p_finished : in std_logic
162 end component history;
166 sys_clk : in std_logic;
167 sys_res_n : in std_logic;
169 d_new_eingabe : in std_logic;
170 d_new_result : in std_logic;
171 d_new_bs : in std_logic;
172 d_zeile : out hzeile;
173 d_spalte : out hspalte;
174 d_get : out std_logic;
175 d_done : in std_logic;
178 command : out std_logic_vector(7 downto 0);
179 command_data : out std_logic_vector(31 downto 0);
182 end component display;
184 component pc_communication is
186 sys_clk : in std_logic;
187 sys_res_n : in std_logic;
189 btn_a : in std_logic;
191 tx_data : out std_logic_vector(7 downto 0);
192 tx_new : out std_logic;
193 tx_done : in std_logic;
195 rx_data : in std_logic_vector(7 downto 0);
196 rx_new : in std_logic;
198 pc_zeile : out hzeile;
199 pc_spalte : out hspalte;
200 pc_get : out std_logic;
201 pc_done : in std_logic;
204 end component pc_communication;
208 CLK_FREQ : integer := 33000000;
209 BAUDRATE : integer := 115200
212 sys_clk : in std_logic;
213 sys_res_n : in std_logic;
215 rx_data : out std_logic_vector(7 downto 0);
216 rx_new : out std_logic
218 end component uart_rx;
222 CLK_FREQ : integer := 33000000;
223 BAUDRATE : integer := 115200
226 sys_clk : in std_logic;
227 sys_res_n : in std_logic;
229 tx_data : in std_logic_vector(7 downto 0);
230 tx_new : in std_logic;
231 tx_done : out std_logic
233 end component uart_tx;
237 inclk0 : in std_logic := '0';
242 component clk_vga_s3e is
244 clk50 : in std_logic;
245 clk25 : out std_logic
247 end component clk_vga_s3e;
251 ADDR_WIDTH : integer range 1 to integer'high
254 sys_clk : in std_logic;
255 address : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
256 data_out : out hbyte;
260 end component sp_ram;
263 package body gen_pkg is
264 procedure icwait(signal clk_i : IN std_logic; cycles: Natural) is
266 for i in 1 to cycles loop
267 wait until clk_i= '0' and clk_i'event;
271 function ascii2sc (x : hbyte) return hbyte is
275 when x"30" => y := SC_KP_0;
276 when x"31" => y := SC_KP_1;
277 when x"32" => y := SC_KP_2;
278 when x"33" => y := SC_KP_3;
279 when x"34" => y := SC_KP_4;
280 when x"35" => y := SC_KP_5;
281 when x"36" => y := SC_KP_6;
282 when x"37" => y := SC_KP_7;
283 when x"38" => y := SC_KP_8;
284 when x"39" => y := SC_KP_9;
285 when x"2b" => y := SC_KP_PLUS;
286 when x"2d" => y := SC_KP_MINUS;
287 when x"2a" => y := SC_KP_MUL;
288 when x"2f" => y := SC_KP_DIV;
289 when x"20" => y := SC_SPACE;
290 when x"1c" => y := SC_ENTER;
291 when x"0e" => y := SC_BKSP;
292 when others => y := x"41";
297 function valid_char (x : hbyte) return boolean is
298 variable y : boolean;
301 when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
302 SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
303 SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
304 SC_KP_MINUS | SC_KP_MUL |
305 SC_KP_DIV | SC_SPACE |
306 SC_BKSP | SC_ENTER =>
308 when others => y := false;
313 function zeile2char(i : std_logic_vector; stelle : natural) return hbyte is
314 subtype zeilnum is string(1 to 2);
315 type zeilnum_arr is array (natural range 0 to 49) of zeilnum;
316 constant zn : zeilnum_arr := (
317 0 => "00", 1 => "01", 2 => "02", 3 => "03", 4 => "04",
318 5 => "05", 6 => "06", 7 => "07", 8 => "08", 9 => "09",
319 10 => "10", 11 => "11", 12 => "12", 13 => "13", 14 => "14",
320 15 => "15", 16 => "16", 17 => "17", 18 => "18", 19 => "19",
321 20 => "20", 21 => "21", 22 => "22", 23 => "23", 24 => "24",
322 25 => "25", 26 => "26", 27 => "27", 28 => "28", 29 => "29",
323 30 => "30", 31 => "31", 32 => "32", 33 => "33", 34 => "34",
324 35 => "35", 36 => "36", 37 => "37", 38 => "38", 39 => "39",
325 40 => "40", 41 => "41", 42 => "42", 43 => "43", 44 => "44",
326 45 => "45", 46 => "46", 47 => "47", 48 => "48", 49 => "49",
328 variable t : signed(hzeile'length downto 0);
330 t := signed('0' & i);
332 return hbyte(to_unsigned(character'pos(zn(to_integer(t))(stelle)),8));
334 end package body gen_pkg;