uart_rx: ein prozessmodell. spart weitere 3 logic elements :P
[hwmod.git] / src / display.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use work.gen_pkg.all;
5 use work.textmode_vga_component_pkg.all;
6 use work.textmode_vga_pkg.all;
7 use work.textmode_vga_platform_dependent_pkg.all;
8
9 entity display is
10         port (
11                 sys_clk : in std_logic;
12                 sys_res_n : in std_logic;
13                 -- History
14                 d_new_eingabe : in std_logic;
15                 d_new_result : in std_logic;
16                 d_new_bs : in std_logic;
17                 d_zeile : out hzeile;
18                 d_spalte : out hspalte;
19                 d_get : out std_logic;
20                 d_done : in std_logic;
21                 d_char : in hbyte;
22                 -- VGA
23                 command : out std_logic_vector(7 downto 0);
24                 command_data : out std_logic_vector(31 downto 0);
25                 free : in std_logic
26         );
27 end entity display;
28
29 architecture beh of display is
30         type DISPLAY_STATE is (S_INIT, SIDLE, S_NEW_BS, S_BACK, S_BLANK, S_NEW_RESULT,
31                 S_ZEILEUP, S_NEW_INPUT, S_COUNTUP, S_GETCH, S_CR1, S_NL1, S_PUTCH1,
32                 S_PUTCH2, S_WAIT, S_NOP1, S_READ_RESULT_0, S_READ_RESULT_1,
33                 S_READ_RESULT_2, S_PS1_0, S_PS1_1, S_PS1_2, S_PS1_3, S_PS1_4,
34                 S_PS1_5);
35         type DISPLAY_ISTATE is (IS_BACK_2_BLANK, IS_BLANK_2_BACK,
36                 IS_NL1_2_ZEILEUP, IS_RESULT2_2_CR1, IS_CR1_2_NL1, IS_NL1_2_RESULT0,
37                 IS_RESULT0_2_RESULT1, IS_RESULT1_2_RESULT2, IS_ZEILEUP_2_PS10,
38                 IS_PS10_2_PS11, IS_PS11_2_PS12, IS_PS12_2_PS13, IS_PS13_2_PS14,
39                 IS_PS14_2_PS15, IS_RANDOM_2_IDLE, IS_OTHER_2_NL1);
40
41         signal state_int, state_next : DISPLAY_STATE;
42         signal istate_next, istate_int : DISPLAY_ISTATE;
43         signal d_zeile_int, d_zeile_next : hzeile;
44         signal d_spalte_int, d_spalte_next : hspalte;
45         signal d_get_int, d_get_next : std_logic;
46         signal command_int, command_next : std_logic_vector(7 downto 0);
47         signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
48 begin
49         d_zeile <= d_zeile_int;
50         d_spalte <= d_spalte_int;
51         d_get <= d_get_int;
52         command <= command_int;
53         command_data <= command_data_int;
54
55         process(sys_clk, sys_res_n)
56         begin
57                 if sys_res_n = '0' then
58                         -- internal
59                         state_int <= S_INIT;
60                         istate_int <= IS_RANDOM_2_IDLE;
61                         -- out
62                         d_zeile_int <= (others => '0');
63                         d_spalte_int <= (others => '0');
64                         d_get_int <= '0';
65                         command_int <= COMMAND_NOP;
66                         command_data_int <= (others => '0');
67                 elsif rising_edge(sys_clk) then
68                         -- internal
69                         state_int <= state_next;
70                         istate_int <= istate_next;
71                         -- out
72                         d_zeile_int <= d_zeile_next;
73                         d_spalte_int <= d_spalte_next;
74                         d_get_int <= d_get_next;
75                         command_int <= command_next;
76                         command_data_int <= command_data_next;
77                 end if;
78         end process;
79
80         -- next state
81         process(state_int, d_new_result, d_new_eingabe, d_new_bs, d_done, free,
82                 d_spalte_int, d_char, istate_int)
83         begin
84                 state_next <= state_int;
85                 istate_next <= istate_int;
86
87                 case state_int is
88                         when S_INIT =>
89                                 state_next <= S_PS1_0;
90
91                         when S_PS1_0 =>
92                                 istate_next <= IS_PS10_2_PS11;
93                                 state_next <= S_WAIT;
94                         when S_PS1_1 =>
95                                 istate_next <= IS_PS11_2_PS12;
96                                 state_next <= S_WAIT;
97                         when S_PS1_2 =>
98                                 istate_next <= IS_PS12_2_PS13;
99                                 state_next <= S_WAIT;
100                         when S_PS1_3 =>
101                                 istate_next <= IS_PS13_2_PS14;
102                                 state_next <= S_WAIT;
103                         when S_PS1_4 =>
104                                 istate_next <= IS_PS14_2_PS15;
105                                 state_next <= S_WAIT;
106                         when S_PS1_5 =>
107                                 istate_next <= IS_RANDOM_2_IDLE;
108                                 state_next <= S_WAIT;
109
110                         when SIDLE =>
111                                 istate_next <= IS_RANDOM_2_IDLE;
112                                 if d_new_bs = '1' then
113                                         state_next <= S_NEW_BS;
114                                 elsif d_new_eingabe = '1' then
115                                         state_next <= S_NEW_INPUT;
116                                 end if;
117                                 if d_new_result = '1' then
118                                         state_next <= S_NEW_RESULT;
119                                 end if;
120
121                         when S_NEW_RESULT =>
122                                 state_next <= S_ZEILEUP;
123                         when S_NEW_INPUT =>
124                                 state_next <= S_COUNTUP;
125
126                         when S_NEW_BS =>
127                                 state_next <= S_BACK;
128                         when S_BACK =>
129                                 if free = '0' then
130                                         state_next <= S_WAIT;
131                                         case istate_int is
132                                                 when IS_RANDOM_2_IDLE => istate_next <= IS_BACK_2_BLANK;
133                                                 when others => istate_next <= IS_RANDOM_2_IDLE;
134                                         end case;
135                                 end if;
136                         when S_BLANK =>
137                                 if free = '0' then
138                                         state_next <= S_WAIT;
139                                         istate_next <= IS_BLANK_2_BACK;
140                                 end if;
141
142                         when S_ZEILEUP =>
143                                 case istate_int is
144                                         when IS_NL1_2_ZEILEUP =>
145                                                 state_next <= S_WAIT;
146                                                 istate_next <= IS_ZEILEUP_2_PS10;
147                                         when others => state_next <= S_CR1;
148                                 end case;
149
150                         when S_CR1 =>
151                                 if free = '0' then
152                                         state_next <= S_WAIT;
153                                         case istate_int is
154                                                 when IS_RESULT2_2_CR1 => istate_next <= IS_OTHER_2_NL1;
155                                                 when others => istate_next <= IS_CR1_2_NL1;
156                                         end case;
157                                 end if;
158                         when S_NL1 =>
159                                 if free = '0' then
160                                         state_next <= S_WAIT;
161                                         case istate_int is
162                                                 when IS_OTHER_2_NL1 => istate_next <= IS_NL1_2_ZEILEUP;
163                                                 when others => istate_next <= IS_NL1_2_RESULT0;
164                                         end case;
165                                 end if;
166
167                         when S_READ_RESULT_0 =>
168                                 istate_next <= IS_RESULT0_2_RESULT1;
169                                 state_next <= S_WAIT;
170                         when S_READ_RESULT_1 =>
171                                 istate_next <= IS_RESULT1_2_RESULT2;
172                                 state_next <= S_WAIT;
173                         when S_READ_RESULT_2 =>
174                                 if unsigned(d_spalte_int) /= HSPALTE_MAX-1 then
175                                         state_next <= S_COUNTUP;
176                                         istate_next <= IS_RESULT1_2_RESULT2;
177                                 else
178                                         state_next <= S_WAIT;
179                                         istate_next <= IS_RESULT2_2_CR1;
180                                 end if;
181
182                         when S_COUNTUP =>
183                                 state_next <= S_GETCH;
184                         when S_GETCH =>
185                                 if free = '1' and d_done = '1' and d_new_result = '0' and d_new_eingabe = '0' then
186                                         state_next <= S_PUTCH1;
187                                 end if;
188                         when S_PUTCH1 =>
189                                 state_next <= S_PUTCH2;
190                         when S_PUTCH2 =>
191                                 if free = '0' then
192                                         state_next <= S_WAIT;
193                                 end if;
194                         when S_WAIT =>
195                                 if free = '1' and d_done = '0' then
196                                         state_next <= S_NOP1;
197                                 end if;
198                         when S_NOP1 =>
199                                 if free = '1' then
200                                         case istate_int is
201                                                 when IS_CR1_2_NL1 => state_next <= S_NL1;
202                                                 when IS_BACK_2_BLANK => state_next <= S_BLANK;
203                                                 when IS_BLANK_2_BACK => state_next <= S_BACK;
204                                                 when IS_NL1_2_ZEILEUP => state_next <= S_ZEILEUP;
205                                                 when IS_RESULT2_2_CR1 => state_next <= S_CR1;
206                                                 when IS_OTHER_2_NL1 => state_next <= S_NL1;
207
208                                                 when IS_NL1_2_RESULT0 => state_next <= S_READ_RESULT_0;
209                                                 when IS_RESULT0_2_RESULT1 => state_next <= S_READ_RESULT_1;
210                                                 when IS_RESULT1_2_RESULT2 => state_next <= S_READ_RESULT_2;
211
212                                                 when IS_ZEILEUP_2_PS10 => state_next <= S_PS1_0;
213                                                 when IS_PS10_2_PS11 => state_next <= S_PS1_1;
214                                                 when IS_PS11_2_PS12 => state_next <= S_PS1_2;
215                                                 when IS_PS12_2_PS13 => state_next <= S_PS1_3;
216                                                 when IS_PS13_2_PS14 => state_next <= S_PS1_4;
217                                                 when IS_PS14_2_PS15 => state_next <= S_PS1_5;
218                                                 when IS_RANDOM_2_IDLE => state_next <= SIDLE;
219                                         end case;
220                                 end if;
221                 end case;
222         end process;
223
224         -- out
225         process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
226                 command_data_int, d_char)
227         begin
228                 d_zeile_next <= d_zeile_int;
229                 d_spalte_next <= d_spalte_int;
230                 d_get_next <= '0';
231                 command_next <= command_int;
232                 command_data_next <= command_data_int;
233
234                 case state_int is
235                         when S_INIT => null;
236
237                         when S_PS1_0 =>
238                                 command_next <= COMMAND_SET_CHAR;
239                                 command_data_next <= x"0000ff" & x"28"; -- '('
240                         when S_PS1_1 =>
241                                 command_next <= COMMAND_SET_CHAR;
242                                 command_data_next <= x"00ff00" & zeile2char(d_zeile_int,1); -- 'x'
243                         when S_PS1_2 =>
244                                 command_next <= COMMAND_SET_CHAR;
245                                 command_data_next <= x"00ff00" & zeile2char(d_zeile_int,2); -- 'y'
246                         when S_PS1_3 =>
247                                 command_next <= COMMAND_SET_CHAR;
248                                 command_data_next <= x"0000ff" & x"29"; -- ')'
249                         when S_PS1_4 =>
250                                 command_next <= COMMAND_SET_CHAR;
251                                 command_data_next <= x"00ffff" & x"24"; -- '$'
252                         when S_PS1_5 =>
253                                 command_next <= COMMAND_SET_CHAR;
254                                 command_data_next <= x"ffffff" & x"20"; -- ' '
255
256                         when SIDLE => null;
257                         when S_NEW_RESULT => null;
258                         when S_NEW_INPUT => null;
259
260                         when S_NEW_BS =>
261                                 -- underflow check schon im history modul
262                                 d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) - 1);
263                         when S_BACK =>
264                                 -- einen schritt zurueck, +6 wegen $PS1
265                                 command_next <= COMMAND_SET_CURSOR_COLUMN;
266                                 command_data_next <= x"ffffff" & '0' & std_logic_vector(unsigned(d_spalte_int) + 6);
267                         when S_BLANK =>
268                                 command_next <= COMMAND_SET_CHAR;
269                                 command_data_next <= x"ffffff" & x"20"; -- white space
270
271                         when S_ZEILEUP =>
272                                 d_spalte_next <= (others => '0');
273                                 case d_zeile_int is
274                                         when
275                                         std_logic_vector(to_unsigned(HZEILE_MAX-1,d_zeile_int'length)) => d_zeile_next <= (others => '0');
276                                         when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
277                                 end case;
278
279                         when S_CR1 =>
280                                 command_next <= COMMAND_SET_CHAR;
281                                 command_data_next <= x"ffffff" & x"0d"; -- carrige return
282                         when S_NL1 =>
283                                 command_next <= COMMAND_SET_CHAR;
284                                 command_data_next <= x"ffffff" & x"0a"; -- newline
285
286                         when S_READ_RESULT_0 =>
287                                 command_next <= COMMAND_SET_CHAR;
288                                 command_data_next <= x"ff0000" & x"3e"; -- '>'
289                         when S_READ_RESULT_1 =>
290                                 command_next <= COMMAND_SET_CHAR;
291                                 command_data_next <= x"ffffff" & x"20"; -- ' '
292                         when S_READ_RESULT_2 => null;
293
294                         when S_COUNTUP =>
295                                 d_get_next <= '1';
296                                 d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1);
297                         when S_GETCH =>
298                                 d_get_next <= '1';
299                         when S_PUTCH1 =>
300                                 command_next <= COMMAND_SET_CHAR;
301                                 if d_char = x"00" then
302                                         command_data_next <= x"ffffff" & x"20";
303                                 else
304                                         command_data_next <= x"ffffff" & std_logic_vector(d_char);
305                                 end if;
306                         when S_PUTCH2 => null;
307                         when S_WAIT | S_NOP1 =>
308                                 command_next <= COMMAND_NOP;
309                                 command_data_next <= x"00000000";
310                 end case;
311         end process;
312 end architecture beh;