src/beh_history_tb.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5 use work.textmode_vga_component_pkg.all;
   6 use work.textmode_vga_pkg.all;
   7 use work.textmode_vga_platform_dependent_pkg.all;
   8
   9 entity beh_history_tb is
  10 end entity beh_history_tb;
  11
  12 architecture sim of beh_history_tb is
  13         -- system
  14         signal sys_clk, sys_res_n : std_logic;
  15         -- history/display
  16         signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
  17         signal d_zeile : hzeile;
  18         signal d_spalte : hspalte;
  19         signal d_get, d_done : std_logic;
  20         signal d_char : hbyte;
  21         -- history/scanner
  22         signal s_char : hbyte;
  23         signal s_take, s_done, s_backspace : std_logic;
  24         -- ps/2
  25         signal new_data : std_logic;
  26         signal data : std_logic_vector(7 downto 0);
  27         -- vga/display
  28         signal free : std_logic;
  29         signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
  30         signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
  31         -- history/parser
  32         signal p_rget : std_logic;
  33         signal p_rdone : std_logic;
  34         signal p_read : hbyte;
  35         signal p_wtake : std_logic;
  36         signal p_wdone : std_logic;
  37         signal p_write : hbyte;
  38         signal p_finished : std_logic;
  39         -- parser/scanner
  40         signal do_it, finished : std_logic;
  41         --uart_tx
  42         signal tx_data : std_logic_vector(7 downto 0);
  43         signal tx_new, tx_done, txd : std_logic;
  44         --pc_communication
  45         signal pc_zeile : hzeile;
  46         signal pc_spalte : hspalte;
  47         signal pc_get, pc_done : std_logic;
  48         signal pc_char : hbyte;
  49         --dummy button
  50         signal btn_a_int : std_logic;
  51
  52         signal stop : boolean := false;
  53 begin
  54         -- history
  55         inst : history
  56         port map (
  57                 sys_clk => sys_clk,
  58                 sys_res_n => sys_res_n,
  59                 -- scanner
  60                 s_char => s_char,
  61                 s_take => s_take,
  62                 s_done => s_done,
  63                 s_backspace => s_backspace,
  64                 -- display
  65                 d_new_eingabe => d_new_eingabe,
  66                 d_new_result => d_new_result,
  67                 d_new_bs => d_new_bs,
  68                 d_zeile => d_zeile,
  69                 d_spalte => d_spalte,
  70                 d_get => d_get,
  71                 d_done => d_done,
  72                 d_char => d_char,
  73                 -- parser
  74                 p_rget => p_rget,
  75                 p_rdone => p_rdone,
  76                 p_read => p_read,
  77                 p_wtake => p_wtake,
  78                 p_wdone => p_wdone,
  79                 p_write => p_write,
  80                 p_finished => p_finished,
  81                 -- PC-komm
  82                 pc_get    => pc_get,
  83                 pc_spalte => pc_spalte,
  84                 pc_zeile  => pc_zeile,
  85                 pc_char   => pc_char,
  86                 pc_done   => pc_done
  87         );
  88
  89         -- display
  90         inst_disp : display
  91         port map (
  92                 sys_clk => sys_clk,
  93                 sys_res_n => sys_res_n,
  94                 -- history
  95                 d_new_eingabe => d_new_eingabe,
  96                 d_new_result => d_new_result,
  97                 d_new_bs => d_new_bs,
  98                 d_zeile => d_zeile,
  99                 d_spalte => d_spalte,
 100                 d_get => d_get,
 101                 d_done => d_done,
 102                 d_char => d_char,
 103                 -- vga
 104                 command => command,
 105                 command_data => command_data,
 106                 free => free
 107         );
 108
 109         -- parser
 110         inst_parser : parser
 111         port map (
 112                 sys_clk => sys_clk,
 113                 sys_res_n => sys_res_n,
 114                 -- history
 115                 p_rget => p_rget,
 116                 p_rdone => p_rdone,
 117                 p_read => p_read,
 118                 p_wtake => p_wtake,
 119                 p_wdone => p_wdone,
 120                 p_write => p_write,
 121                 p_finished => p_finished,
 122                 -- scanner
 123                 do_it => do_it,
 124                 finished => finished
 125         );
 126
 127         -- scanner
 128         inst_scan : scanner
 129         port map (
 130                 sys_clk => sys_clk,
 131                 sys_res_n => sys_res_n,
 132                 -- ps/2
 133                 new_data => new_data,
 134                 data => data,
 135                 -- history
 136                 s_char => s_char,
 137                 s_take => s_take,
 138                 s_done => s_done,
 139                 s_backspace => s_backspace,
 140                 -- Parser
 141                 do_it => do_it,
 142                 finished => finished
 143         );
 144         --uart_tx
 145         inst_uart : uart_tx
 146         port map (
 147                 sys_clk => sys_clk,
 148                 sys_res_n => sys_res_n,
 149                 txd => txd,
 150                 tx_data =>tx_data,
 151                 tx_new => tx_new,
 152                 tx_done => tx_done
 153         );
 154
 155         --pc_communication
 156         inst_pc_com : pc_communication
 157         port map(
 158                 sys_clk => sys_clk,
 159                 sys_res_n => sys_res_n,
 160                 --button
 161                 btn_a => btn_a_int,
 162                 --uart_tx
 163                 tx_data => tx_data,
 164                 tx_new => tx_new,
 165                 tx_done => tx_done,
 166                 --uart_rx
 167                 rx_data => (others => '0'),
 168                 rx_new => '0',
 169                 -- History
 170                 pc_zeile  => pc_zeile,
 171                 pc_spalte => pc_spalte,
 172                 pc_get    => pc_get,
 173                 pc_done   => pc_done,
 174                 pc_char   => pc_char
 175         );
 176
 177         process
 178         begin
 179                 sys_clk <= '0';
 180                 wait for 15 ns;
 181                 sys_clk <= '1';
 182                 wait for 15 ns;
 183                 if stop = true then
 184                         wait;
 185                 end if;
 186         end process;
 187
 188         process
 189         begin
 190                 free <= '0';
 191                 wait for 15 ns;
 192                 free <= '1';
 193                 wait for 30 ns;
 194                 if stop = true then
 195                         wait;
 196                 end if;
 197         end process;
 198
 199         process
 200                 -- textio stuff
 201                 use std.textio.all;
 202                 file f : text open read_mode is "../../src/history.test";
 203                 variable l : line;
 204
 205                 variable input : string(1 to 100);
 206
 207                 variable run_tc, run_inner : boolean := true;
 208                 variable i, j, y : natural;
 209         begin
 210                 -- init & reset
 211                 sys_res_n <= '0';
 212                 new_data <= '0';
 213                 data <= (others => '0');
 214
 215                 icwait(sys_clk, 20);
 216                 sys_res_n <= '1';
 217
 218                 i := 1;
 219                 f_loop : while not endfile(f) loop
 220                         data <= (others => '0');
 221
 222                         f1_loop : while not endfile(f) loop
 223                                 readline (f, l);
 224                                 input := (others => nul);
 225                                 if (l'length <= 100) then
 226                                         input(1 to l'length) := l.all;
 227                                         if (input(1) = '#') then
 228                                                 next f1_loop;
 229                                         else
 230                                                 exit f1_loop;
 231                                         end if;
 232                                 else
 233                                         report "fehler in history.test: eingabe zu lange in testfall " & natural'image(i);
 234                                         next f_loop;
 235                                 end if;
 236                         end loop f1_loop;
 237
 238                         report "testcase(" & natural'image(i) & ").input: " & input;
 239                         i := i + 1;
 240
 241                         icwait(sys_clk, 5);
 242                         run_tc := true;
 243                         j := 0;
 244
 245                         mainl : while run_tc loop
 246                                 icwait(sys_clk, 10);
 247                                 j := j + 1;
 248
 249                                 if j = 101 then
 250                                         run_tc := false;
 251                                         assert(false) report "wtf @ schleife";
 252                                         next mainl;
 253                                 end if;
 254
 255                                 new_data <= '1';
 256
 257                                 case input(j) is
 258                                         when nul => data <= ascii2sc(x"1c"); -- $ (enter)
 259                                         when '!' => data <= ascii2sc(x"0e"); -- ! (backspace)
 260                                         when '/' =>
 261                                                 data <= x"e0";
 262                                                 icwait(sys_clk, 1);
 263                                                 new_data <= '0';
 264                                                 icwait(sys_clk, 1);
 265                                                 new_data <= '1';
 266                                                 data <= SC_KP_DIV;
 267                                         when others => data <= ascii2sc(std_logic_vector(to_unsigned(character'pos(input(j)),8)));
 268                                 end case;
 269
 270                                 -- ack'en skippen, falls es ein "spezielles" zeichen ist (steht
 271                                 -- in abhaengigkeit zum vorherigen zeichen)
 272                                 if(not valid_char(data)) then
 273                                         next mainl;
 274                                 end if;
 275
 276                                 -- wuenschswert waere das hier:
 277                                 -- > wait on s_backspace, s_take, do_it;
 278                                 -- geht aber leider nicht, weil sich die signale vllt schon
 279                                 -- geaendert haben
 280                                 run_inner := true;
 281                                 main_inner : while run_inner loop
 282                                         icwait(sys_clk, 1);
 283
 284                                         run_inner := false;
 285                                         if s_backspace = '1' or s_take = '1' then
 286                                                 icwait(sys_clk, 1);
 287                                                 wait on s_take; -- = '0'
 288                                                 icwait(sys_clk, 1);
 289                                         elsif do_it = '1' then
 290                                                 -- dauert normalweiser noch laenger (parser braucht
 291                                                 -- relativ lange)
 292                                                 icwait(sys_clk, 7);
 293                                                 wait on do_it; -- = '0'
 294                                                 icwait(sys_clk, 850);
 295
 296                                                 run_tc := false;
 297                                         else
 298                                                 -- assert(false) report "history_tb: kann passieren. wenn tb haengt, dann hier auskommentieren";
 299                                                 run_inner := true;
 300                                         end if;
 301                                 end loop;
 302                         end loop;
 303                         report "==================";
 304                 end loop f_loop;
 305
 306                 -- uart ist ziemlich langsam...
 307                 icwait(sys_clk, 1000000000);
 308                 stop <= true;
 309                 wait;
 310         end process;
 311
 312         btn_pressed : process is
 313         begin
 314                 btn_a_int <= '1';
 315                 wait until sys_res_n = '1';
 316                 icwait(sys_clk, 50000);
 317                 wait until rising_edge(sys_clk);
 318                 btn_a_int <= '0';
 319                 wait for 30 ns;
 320                 btn_a_int <= '1';
 321                 wait;
 322         end process btn_pressed;
 323 end architecture sim;