implemented Setup.hs to build boehm cpp libs and install them;
[hs-boehmgc.git] / gc-7.2 / libatomic_ops / src / atomic_ops / sysdeps / msftc / x86_64.h
1 /*
2  * Copyright (c) 2003 Hewlett-Packard Development Company, L.P.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a copy
5  * of this software and associated documentation files (the "Software"), to deal
6  * in the Software without restriction, including without limitation the rights
7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8  * copies of the Software, and to permit persons to whom the Software is
9  * furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20  * SOFTWARE.
21  */
22
23 #include "../all_aligned_atomic_load_store.h"
24
25 /* Real X86 implementations appear                                      */
26 /* to enforce ordering between memory operations, EXCEPT that a later   */
27 /* read can pass earlier writes, presumably due to the visible          */
28 /* presence of store buffers.                                           */
29 /* We ignore the fact that the official specs                           */
30 /* seem to be much weaker (and arguably too weak to be usable).         */
31
32 #include "../ordered_except_wr.h"
33
34 #ifdef AO_ASM_X64_AVAILABLE
35 # include "../test_and_set_t_is_char.h"
36 #else
37 # include "../test_and_set_t_is_ao_t.h"
38 #endif
39
40 #include "../standard_ao_double_t.h"
41
42 #include <windows.h>
43         /* Seems like over-kill, but that's what MSDN recommends.       */
44         /* And apparently winbase.h is not always self-contained.       */
45
46 /* Assume _MSC_VER >= 1400 */
47 #include <intrin.h>
48
49 #pragma intrinsic (_ReadWriteBarrier)
50
51 #pragma intrinsic (_InterlockedIncrement64)
52 #pragma intrinsic (_InterlockedDecrement64)
53 #pragma intrinsic (_InterlockedExchange64)
54 #pragma intrinsic (_InterlockedExchangeAdd64)
55 #pragma intrinsic (_InterlockedCompareExchange64)
56
57 AO_INLINE AO_t
58 AO_fetch_and_add_full (volatile AO_t *p, AO_t incr)
59 {
60   return _InterlockedExchangeAdd64((LONGLONG volatile *)p, (LONGLONG)incr);
61 }
62 #define AO_HAVE_fetch_and_add_full
63
64 AO_INLINE AO_t
65 AO_fetch_and_add1_full (volatile AO_t *p)
66 {
67   return _InterlockedIncrement64((LONGLONG volatile *)p) - 1;
68 }
69 #define AO_HAVE_fetch_and_add1_full
70
71 AO_INLINE AO_t
72 AO_fetch_and_sub1_full (volatile AO_t *p)
73 {
74   return _InterlockedDecrement64((LONGLONG volatile *)p) + 1;
75 }
76 #define AO_HAVE_fetch_and_sub1_full
77
78 AO_INLINE int
79 AO_compare_and_swap_full(volatile AO_t *addr,
80                          AO_t old, AO_t new_val)
81 {
82     return _InterlockedCompareExchange64((LONGLONG volatile *)addr,
83                                          (LONGLONG)new_val, (LONGLONG)old)
84            == (LONGLONG)old;
85 }
86 #define AO_HAVE_compare_and_swap_full
87
88 /* As far as we can tell, the lfence and sfence instructions are not    */
89 /* currently needed or useful for cached memory accesses.               */
90
91 #ifdef AO_ASM_X64_AVAILABLE
92
93 AO_INLINE void
94 AO_nop_full(void)
95 {
96   /* Note: "mfence" (SSE2) is supported on all x86_64/amd64 chips.      */
97   __asm { mfence }
98 }
99 #define AO_HAVE_nop_full
100
101 AO_INLINE AO_TS_VAL_t
102 AO_test_and_set_full(volatile AO_TS_t *addr)
103 {
104     __asm
105     {
106         mov     rax,AO_TS_SET           ;
107         mov     rbx,addr                ;
108         xchg    byte ptr [rbx],al       ;
109     }
110 }
111 #define AO_HAVE_test_and_set_full
112
113 #endif /* AO_ASM_X64_AVAILABLE */
114
115 #ifdef AO_CMPXCHG16B_AVAILABLE
116 /* AO_compare_double_and_swap_double_full needs implementation for Win64.
117  * Also see ../gcc/x86_64.h for partial old Opteron workaround.
118  */
119
120 # if _MSC_VER >= 1500
121
122 #pragma intrinsic (_InterlockedCompareExchange128)
123
124 AO_INLINE int
125 AO_compare_double_and_swap_double_full(volatile AO_double_t *addr,
126                                        AO_t old_val1, AO_t old_val2,
127                                        AO_t new_val1, AO_t new_val2)
128 {
129    __int64 comparandResult[2];
130    comparandResult[0] = old_val1; /* low */
131    comparandResult[1] = old_val2; /* high */
132    return _InterlockedCompareExchange128((volatile __int64 *)addr,
133                 new_val2 /* high */, new_val1 /* low */, comparandResult);
134 }
135 #   define AO_HAVE_compare_double_and_swap_double_full
136
137 # elif defined(AO_ASM_X64_AVAILABLE)
138     /* If there is no intrinsic _InterlockedCompareExchange128 then we  */
139     /* need basically what's given below.                               */
140 AO_INLINE int
141 AO_compare_double_and_swap_double_full(volatile AO_double_t *addr,
142                                        AO_t old_val1, AO_t old_val2,
143                                        AO_t new_val1, AO_t new_val2)
144 {
145         __asm
146         {
147                 mov     rdx,QWORD PTR [old_val2]        ;
148                 mov     rax,QWORD PTR [old_val1]        ;
149                 mov     rcx,QWORD PTR [new_val2]        ;
150                 mov     rbx,QWORD PTR [new_val1]        ;
151                 lock cmpxchg16b [addr]                  ;
152                 setz    rax                             ;
153         }
154 }
155 #   define AO_HAVE_compare_double_and_swap_double_full
156 # endif /* _MSC_VER >= 1500 || AO_ASM_X64_AVAILABLE */
157
158 #endif /* AO_CMPXCHG16B_AVAILABLE */