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3 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
4 * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
7 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
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18 /* FIXME: untested. */
19 /* The relevant documentation appears to be at */
20 /* http://publibz.boulder.ibm.com/epubs/pdf/dz9zr003.pdf */
21 /* around page 5-96. Apparently: */
22 /* - Memory references in general are atomic only for a single */
23 /* byte. But it appears that the most common load/store */
24 /* instructions also guarantee atomicity for aligned */
25 /* operands of standard types. WE FOOLISHLY ASSUME that */
26 /* compilers only generate those. If that turns out to be */
27 /* wrong, we need inline assembly code for AO_load and */
29 /* - A store followed by a load is unordered since the store */
30 /* may be delayed. Otherwise everything is ordered. */
31 /* - There is a hardware compare-and-swap (CS) instruction. */
33 #include "../ordered_except_wr.h"
34 #include "../all_aligned_atomic_load_store.h"
36 #include "../test_and_set_t_is_ao_t.h"
37 /* FIXME: Is there a way to do byte-sized test-and-set? */
39 /* FIXME: AO_nop_full should probably be implemented directly. */
40 /* It appears that certain BCR instructions have that effect. */
41 /* Presumably they're cheaper than CS? */
43 AO_INLINE int AO_compare_and_swap_full(volatile AO_t *addr,
44 AO_t old, AO_t new_val)
47 __asm__ __volatile__ (
55 : "=&d" (retval), "+d" (old)
56 : "d" (new_val), "a" (addr)
60 #define AO_HAVE_compare_and_swap_full
62 /* FIXME: Add double-wide compare-and-swap for 32-bit executables. */