2 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
3 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
4 * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
7 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
8 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
10 * Permission is hereby granted to use or copy this program
11 * for any purpose, provided the above notices are retained on all copies.
12 * Permission to modify the code and to distribute modified code is granted,
13 * provided the above notices are retained, and a notice that the code was
14 * modified is included with the above copyright notice.
18 #include "../read_ordered.h"
20 #include "../test_and_set_t_is_ao_t.h" /* Probably suboptimal */
22 /* NEC LE-IT: ARMv6 is the first architecture providing support for */
23 /* simple LL/SC. A data memory barrier must be raised via CP15 command */
24 /* (see documentation). */
25 /* ARMv7 is compatible to ARMv6 but has a simpler command for issuing */
26 /* a memory barrier (DMB). Raising it via CP15 should still work as */
27 /* told me by the support engineers. If it turns out to be much quicker */
28 /* than we should implement custom code for ARMv7 using the asm { dmb } */
30 /* If only a single processor is used, we can define AO_UNIPROCESSOR */
31 /* and do not need to access CP15 for ensuring a DMB. */
33 #if defined(__thumb__) && !defined(__thumb2__)
34 /* Thumb One mode does not have ARM "mcr", "swp" and some load/store */
35 /* instructions, so we temporarily switch to ARM mode and go back */
36 /* afterwards (clobbering "r3" register). */
37 # define AO_THUMB_GO_ARM \
43 # define AO_THUMB_RESTORE_MODE \
48 # define AO_THUMB_SWITCH_CLOBBERS "r3",
50 # define AO_THUMB_GO_ARM /* empty */
51 # define AO_THUMB_RESTORE_MODE /* empty */
52 # define AO_THUMB_SWITCH_CLOBBERS /* empty */
53 #endif /* !__thumb__ */
55 /* NEC LE-IT: gcc has no way to easily check the arm architecture */
56 /* but it defines only one (or several) of __ARM_ARCH_x__ to be true. */
57 #if !defined(__ARM_ARCH_2__) && !defined(__ARM_ARCH_3__) \
58 && !defined(__ARM_ARCH_3M__) && !defined(__ARM_ARCH_4__) \
59 && !defined(__ARM_ARCH_4T__) \
60 && ((!defined(__ARM_ARCH_5__) && !defined(__ARM_ARCH_5E__) \
61 && !defined(__ARM_ARCH_5T__) && !defined(__ARM_ARCH_5TE__) \
62 && !defined(__ARM_ARCH_5TEJ__) && !defined(__ARM_ARCH_6M__)) \
63 || defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__))
65 #include "../standard_ao_double_t.h"
70 # ifndef AO_UNIPROCESSOR
73 /* Issue a data memory barrier (keeps ordering of memory */
74 /* transactions before and after this operation). */
75 __asm__ __volatile__("@AO_nop_full\n"
77 " mcr p15,0,%0,c7,c10,5\n"
81 : AO_THUMB_SWITCH_CLOBBERS "memory");
84 #define AO_HAVE_nop_full
86 /* NEC LE-IT: AO_t load is simple reading */
88 AO_load(const volatile AO_t *addr)
90 /* Cast away the volatile for architectures like IA64 where */
91 /* volatile adds barrier semantics. */
92 return (*(const AO_t *)addr);
96 /* NEC LE-IT: atomic "store" - according to ARM documentation this is
97 * the only safe way to set variables also used in LL/SC environment.
98 * A direct write won't be recognized by the LL/SC construct on the _same_ CPU.
100 * Support engineers response for behaviour of ARMv6:
103 ===================================
106 -----------------------------------
110 -----------------------------------
114 -----------------------------------
116 * ARMv7 behaves similar, see documentation CortexA8 TRM, point 8.5
118 * HB: I think this is only a problem if interrupt handlers do not clear
119 * the reservation, as they almost certainly should. Probably change this back
122 AO_INLINE void AO_store(volatile AO_t *addr, AO_t value)
126 __asm__ __volatile__("@AO_store\n"
128 "1: ldrex %0, [%2]\n"
129 " strex %0, %3, [%2]\n"
132 AO_THUMB_RESTORE_MODE
133 : "=&r"(flag), "+m"(*addr)
134 : "r" (addr), "r"(value)
135 : AO_THUMB_SWITCH_CLOBBERS "cc");
137 #define AO_HAVE_store
139 /* NEC LE-IT: replace the SWAP as recommended by ARM:
140 "Applies to: ARM11 Cores
141 Though the SWP instruction will still work with ARM V6 cores, it is
142 recommended to use the new V6 synchronization instructions. The SWP
143 instruction produces 'locked' read and write accesses which are atomic,
144 i.e. another operation cannot be done between these locked accesses which
145 ties up external bus (AHB, AXI) bandwidth and can increase worst case
146 interrupt latencies. LDREX, STREX are more flexible, other instructions
147 can be done between the LDREX and STREX accesses."
149 #if !defined(AO_FORCE_USE_SWP) || defined(__thumb2__)
150 /* But, on the other hand, there could be a considerable performance */
151 /* degradation in case of a race. Eg., test_atomic.c executing */
152 /* test_and_set test on a dual-core ARMv7 processor using LDREX/STREX */
153 /* showed around 35 times lower performance than that using SWP. */
154 /* To force use of SWP instruction, use -D AO_FORCE_USE_SWP option */
155 /* (this is ignored in the Thumb-2 mode as SWP is missing there). */
156 AO_INLINE AO_TS_VAL_t
157 AO_test_and_set(volatile AO_TS_t *addr)
162 __asm__ __volatile__("@AO_test_and_set\n"
164 "1: ldrex %0, [%3]\n"
165 " strex %1, %4, [%3]\n"
168 AO_THUMB_RESTORE_MODE
169 : "=&r"(oldval), "=&r"(flag), "+m"(*addr)
171 : AO_THUMB_SWITCH_CLOBBERS "cc");
174 # define AO_HAVE_test_and_set
175 #endif /* !AO_FORCE_USE_SWP */
177 /* NEC LE-IT: fetch and add for ARMv6 */
179 AO_fetch_and_add(volatile AO_t *p, AO_t incr)
181 unsigned long flag, tmp;
184 __asm__ __volatile__("@AO_fetch_and_add\n"
186 "1: ldrex %0, [%5]\n" /* get original */
187 " add %2, %0, %4\n" /* sum up in incr */
188 " strex %1, %2, [%5]\n" /* store them */
191 AO_THUMB_RESTORE_MODE
192 : "=&r"(result), "=&r"(flag), "=&r"(tmp), "+m"(*p) /* 0..3 */
193 : "r"(incr), "r"(p) /* 4..5 */
194 : AO_THUMB_SWITCH_CLOBBERS "cc");
197 #define AO_HAVE_fetch_and_add
199 /* NEC LE-IT: fetch and add1 for ARMv6 */
201 AO_fetch_and_add1(volatile AO_t *p)
203 unsigned long flag, tmp;
206 __asm__ __volatile__("@AO_fetch_and_add1\n"
208 "1: ldrex %0, [%4]\n" /* get original */
209 " add %1, %0, #1\n" /* increment */
210 " strex %2, %1, [%4]\n" /* store them */
213 AO_THUMB_RESTORE_MODE
214 : "=&r"(result), "=&r"(tmp), "=&r"(flag), "+m"(*p)
216 : AO_THUMB_SWITCH_CLOBBERS "cc");
219 #define AO_HAVE_fetch_and_add1
221 /* NEC LE-IT: fetch and sub for ARMv6 */
223 AO_fetch_and_sub1(volatile AO_t *p)
225 unsigned long flag, tmp;
228 __asm__ __volatile__("@AO_fetch_and_sub1\n"
230 "1: ldrex %0, [%4]\n" /* get original */
231 " sub %1, %0, #1\n" /* decrement */
232 " strex %2, %1, [%4]\n" /* store them */
235 AO_THUMB_RESTORE_MODE
236 : "=&r"(result), "=&r"(tmp), "=&r"(flag), "+m"(*p)
238 : AO_THUMB_SWITCH_CLOBBERS "cc");
241 #define AO_HAVE_fetch_and_sub1
243 /* NEC LE-IT: compare and swap */
244 /* Returns nonzero if the comparison succeeded. */
246 AO_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val)
250 __asm__ __volatile__("@AO_compare_and_swap\n"
252 "1: mov %0, #2\n" /* store a flag */
253 " ldrex %1, [%3]\n" /* get original */
254 " teq %1, %4\n" /* see if match */
258 " strexeq %0, %5, [%3]\n" /* store new one if matched */
260 " beq 1b\n" /* if update failed, repeat */
261 AO_THUMB_RESTORE_MODE
262 : "=&r"(result), "=&r"(tmp), "+m"(*addr)
263 : "r"(addr), "r"(old_val), "r"(new_val)
264 : AO_THUMB_SWITCH_CLOBBERS "cc");
265 return !(result&2); /* if succeded, return 1, else 0 */
267 #define AO_HAVE_compare_and_swap
269 #if !defined(__ARM_ARCH_6__) && !defined(__ARM_ARCH_6J__) \
270 && !defined(__ARM_ARCH_6T2__) && !defined(__ARM_ARCH_6Z__) \
271 && !defined(__ARM_ARCH_6ZT2__) && (!defined(__thumb__) \
272 || (defined(__thumb2__) && !defined(__ARM_ARCH_7__) \
273 && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)))
274 /* LDREXD/STREXD present in ARMv6K/M+ (see gas/config/tc-arm.c) */
275 /* In the Thumb mode, this works only starting from ARMv7 (except for */
276 /* the base and 'M' models). */
278 AO_compare_double_and_swap_double(volatile AO_double_t *addr,
279 AO_t old_val1, AO_t old_val2,
280 AO_t new_val1, AO_t new_val2)
282 double_ptr_storage old_val =
283 ((double_ptr_storage)old_val2 << 32) | old_val1;
284 double_ptr_storage new_val =
285 ((double_ptr_storage)new_val2 << 32) | new_val1;
286 double_ptr_storage tmp;
290 __asm__ __volatile__("@AO_compare_double_and_swap_double\n"
291 " ldrexd %0, [%1]\n" /* get original to r1 & r2 */
297 __asm__ __volatile__(
298 " strexd %0, %2, [%3]\n" /* store new one if matched */
299 : "=&r"(result), "+m"(*addr)
300 : "r"(new_val), "r"(addr)
303 return !result; /* if succeded, return 1 else 0 */
305 # define AO_HAVE_compare_double_and_swap_double
309 /* pre ARMv6 architectures ... */
311 /* I found a slide set that, if I read it correctly, claims that */
312 /* Loads followed by either a Load or Store are ordered, but nothing */
314 /* It appears that SWP is the only simple memory barrier. */
315 #include "../all_atomic_load_store.h"
317 /* The code should run correctly on a multi-core ARMv6+ as well. */
318 /* There is only a single concern related to AO_store (defined in */
319 /* atomic_load_store.h file): */
320 /* HB: Based on subsequent discussion, I think it would be OK to use an */
321 /* ordinary store here if we knew that interrupt handlers always */
322 /* cleared the reservation. They should, but there is some doubt that */
323 /* this is currently always the case, e.g., for Linux. */
325 /* ARMv6M does not support ARM mode. */
326 #endif /* __ARM_ARCH_x */
328 #if !defined(AO_HAVE_test_and_set_full) && !defined(AO_HAVE_test_and_set) \
329 && !defined(__ARM_ARCH_2__) && !defined(__ARM_ARCH_6M__)
330 AO_INLINE AO_TS_VAL_t
331 AO_test_and_set_full(volatile AO_TS_t *addr)
334 /* SWP on ARM is very similar to XCHG on x86. */
335 /* The first operand is the result, the second the value */
336 /* to be stored. Both registers must be different from addr. */
337 /* Make the address operand an early clobber output so it */
338 /* doesn't overlap with the other operands. The early clobber */
339 /* on oldval is necessary to prevent the compiler allocating */
340 /* them to the same register if they are both unused. */
342 __asm__ __volatile__("@AO_test_and_set_full\n"
344 " swp %0, %2, [%3]\n"
345 /* Ignore GCC "SWP is deprecated for this architecture" */
346 /* warning here (for ARMv6+). */
347 AO_THUMB_RESTORE_MODE
348 : "=&r"(oldval), "=&r"(addr)
350 : AO_THUMB_SWITCH_CLOBBERS "memory");
353 # define AO_HAVE_test_and_set_full
354 #endif /* !AO_HAVE_test_and_set[_full] */