2 * Copyright (c) 2007 by NEC LE-IT: All rights reserved.
3 * A transcription of ARMv6 atomic operations for the ARM Realview Toolchain.
4 * This code works with armcc from RVDS 3.1
5 * This is based on work in gcc/arm.h by
6 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
7 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
8 * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
12 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
13 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
15 * Permission is hereby granted to use or copy this program
16 * for any purpose, provided the above notices are retained on all copies.
17 * Permission to modify the code and to distribute modified code is granted,
18 * provided the above notices are retained, and a notice that the code was
19 * modified is included with the above copyright notice.
22 #include "../read_ordered.h"
23 #include "../test_and_set_t_is_ao_t.h" /* Probably suboptimal */
25 #if __TARGET_ARCH_ARM < 6
26 Dont use with ARM instruction sets lower than v6
29 #include "../standard_ao_double_t.h"
31 /* NEC LE-IT: ARMv6 is the first architecture providing support for simple LL/SC
32 * A data memory barrier must be raised via CP15 command (see documentation).
34 * ARMv7 is compatible to ARMv6 but has a simpler command for issuing a
35 * memory barrier (DMB). Raising it via CP15 should still work as told me by the
36 * support engineers. If it turns out to be much quicker than we should implement
37 * custom code for ARMv7 using the asm { dmb } command.
39 * If only a single processor is used, we can define AO_UNIPROCESSOR
40 * and do not need to access CP15 for ensuring a DMB at all.
46 # ifndef AO_UNIPROCESSOR
48 /* issue an data memory barrier (keeps ordering of memory transactions */
49 /* before and after this operation) */
51 mcr p15,0,dest,c7,c10,5
55 #define AO_HAVE_nop_full
58 AO_load(const volatile AO_t *addr)
60 /* Cast away the volatile in case it adds fence semantics */
61 return (*(const AO_t *)addr);
65 /* NEC LE-IT: atomic "store" - according to ARM documentation this is
66 * the only safe way to set variables also used in LL/SC environment.
67 * A direct write won't be recognized by the LL/SC construct in other CPUs.
69 * HB: Based on subsequent discussion, I think it would be OK to use an
70 * ordinary store here if we knew that interrupt handlers always cleared
71 * the reservation. They should, but there is some doubt that this is
72 * currently always the case for e.g. Linux.
74 AO_INLINE void AO_store(volatile AO_t *addr, AO_t value)
81 strex tmp, value, [addr]
88 /* NEC LE-IT: replace the SWAP as recommended by ARM:
90 "Applies to: ARM11 Cores
91 Though the SWP instruction will still work with ARM V6 cores, it is recommended
92 to use the new V6 synchronization instructions. The SWP instruction produces
93 locked read and write accesses which are atomic, i.e. another operation cannot
94 be done between these locked accesses which ties up external bus (AHB,AXI)
95 bandwidth and can increase worst case interrupt latencies. LDREX,STREX are
96 more flexible, other instructions can be done between the LDREX and STREX accesses.
100 AO_test_and_set(volatile AO_TS_t *addr) {
104 unsigned long one = 1;
108 strex tmp, one, [addr]
115 #define AO_HAVE_test_and_set
117 /* NEC LE-IT: fetch and add for ARMv6 */
119 AO_fetch_and_add(volatile AO_t *p, AO_t incr)
121 unsigned long tmp,tmp2;
127 add tmp, incr, result
135 #define AO_HAVE_fetch_and_add
137 /* NEC LE-IT: fetch and add1 for ARMv6 */
139 AO_fetch_and_add1(volatile AO_t *p)
141 unsigned long tmp,tmp2;
155 #define AO_HAVE_fetch_and_add1
157 /* NEC LE-IT: fetch and sub for ARMv6 */
159 AO_fetch_and_sub1(volatile AO_t *p)
161 unsigned long tmp,tmp2;
175 #define AO_HAVE_fetch_and_sub1
177 /* NEC LE-IT: compare and swap */
178 /* Returns nonzero if the comparison succeeded. */
180 AO_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val)
192 strexeq result, new_val, [addr]
199 #define AO_HAVE_compare_and_swap
201 /* helper functions for the Realview compiler: LDREXD is not usable
202 * with inline assembler, so use the "embedded" assembler as
203 * suggested by ARM Dev. support (June 2008). */
204 __asm inline double_ptr_storage load_ex(volatile AO_double_t *addr) {
208 __asm inline int store_ex(AO_t val1, AO_t val2, volatile AO_double_t *addr) {
214 AO_compare_double_and_swap_double(volatile AO_double_t *addr,
215 AO_t old_val1, AO_t old_val2,
216 AO_t new_val1, AO_t new_val2)
218 double_ptr_storage old_val =
219 ((double_ptr_storage)old_val2 << 32) | old_val1;
220 double_ptr_storage tmp;
225 if(tmp != old_val) return 0;
226 result = store_ex(new_val1, new_val2, addr);
227 if(!result) return 1;
230 #define AO_HAVE_compare_double_and_swap_double
232 #endif // __TARGET_ARCH_ARM