From 2e69ab76da77197b041789f8d0d8908d3ded918e Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Thu, 29 Oct 2009 17:40:27 +0100 Subject: [PATCH 1/1] 4er slot (3. bsp fertig) --- .../ppr/download/db/vga_pll.(0).cnf.cdb | Bin 0 -> 1996 bytes .../ppr/download/db/vga_pll.(0).cnf.hdb | Bin 0 -> 1422 bytes .../ppr/download/db/vga_pll.(1).cnf.cdb | Bin 0 -> 6224 bytes .../ppr/download/db/vga_pll.(1).cnf.hdb | Bin 0 -> 2265 bytes .../ppr/download/db/vga_pll.(2).cnf.cdb | Bin 0 -> 11935 bytes .../ppr/download/db/vga_pll.(2).cnf.hdb | Bin 0 -> 3620 bytes .../ppr/download/db/vga_pll.(3).cnf.cdb | Bin 0 -> 1858 bytes .../ppr/download/db/vga_pll.(3).cnf.hdb | Bin 0 -> 863 bytes .../ppr/download/db/vga_pll.(4).cnf.cdb | Bin 0 -> 1158 bytes .../ppr/download/db/vga_pll.(4).cnf.hdb | Bin 0 -> 1240 bytes .../ppr/download/db/vga_pll.(5).cnf.cdb | Bin 0 -> 1814 bytes .../ppr/download/db/vga_pll.(5).cnf.hdb | Bin 0 -> 989 bytes .../ppr/download/db/vga_pll.asm.qmsg | 5 + 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.../Designflow/sim/post/work/@_opt/vopt2j5bkg | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopt2mhxts | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/vopt2n4d8r | Bin 0 -> 575 bytes .../Designflow/sim/post/work/@_opt/vopt2ydh57 | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt2zz0w8 | Bin 0 -> 392 bytes .../Designflow/sim/post/work/@_opt/vopt32qnct | Bin 0 -> 1100 bytes .../Designflow/sim/post/work/@_opt/vopt35k5wn | Bin 0 -> 9760 bytes .../Designflow/sim/post/work/@_opt/vopt3cfxrm | Bin 0 -> 1871 bytes .../Designflow/sim/post/work/@_opt/vopt3kd3wc | Bin 0 -> 4450 bytes .../Designflow/sim/post/work/@_opt/vopt3n9xvk | Bin 0 -> 2356 bytes .../Designflow/sim/post/work/@_opt/vopt3s62qk | Bin 0 -> 13693 bytes .../Designflow/sim/post/work/@_opt/vopt3v2cwx | Bin 0 -> 26888 bytes .../Designflow/sim/post/work/@_opt/vopt40shqr | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt466cvr | Bin 0 -> 1412 bytes .../Designflow/sim/post/work/@_opt/vopt478w7a | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/vopt4b2e0j | Bin 0 -> 3885 bytes .../Designflow/sim/post/work/@_opt/vopt4h7x0t | Bin 0 -> 1232 bytes .../Designflow/sim/post/work/@_opt/vopt4qq65j | Bin 0 -> 9644 bytes .../Designflow/sim/post/work/@_opt/vopt4rb1ts | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopt4tekwx | Bin 0 -> 9760 bytes .../Designflow/sim/post/work/@_opt/vopt4ttffc | Bin 0 -> 2439 bytes .../Designflow/sim/post/work/@_opt/vopt4zyxm4 | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt5287sw | Bin 0 -> 688 bytes .../Designflow/sim/post/work/@_opt/vopt52eq6n | Bin 0 -> 10405 bytes .../Designflow/sim/post/work/@_opt/vopt55g40n | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt5gtiwz | Bin 0 -> 2636 bytes .../Designflow/sim/post/work/@_opt/vopt5k57cn | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt5si1tq | Bin 0 -> 13693 bytes .../Designflow/sim/post/work/@_opt/vopt68a3cn | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt6as2k8 | Bin 0 -> 31680 bytes .../Designflow/sim/post/work/@_opt/vopt6i91n9 | Bin 0 -> 1587 bytes .../Designflow/sim/post/work/@_opt/vopt6iehg9 | Bin 0 -> 1568 bytes .../Designflow/sim/post/work/@_opt/vopt6nbb7g | Bin 0 -> 772 bytes .../Designflow/sim/post/work/@_opt/vopt6nhxfn | Bin 0 -> 8357 bytes .../Designflow/sim/post/work/@_opt/vopt6rhy0e | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt6w3eqg | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt6wr2ez | 417 + .../Designflow/sim/post/work/@_opt/vopt70fsca | Bin 0 -> 1412 bytes .../Designflow/sim/post/work/@_opt/vopt716s76 | Bin 0 -> 4360 bytes .../Designflow/sim/post/work/@_opt/vopt71gszc | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopt785ncr | Bin 0 -> 533 bytes .../Designflow/sim/post/work/@_opt/vopt7dmrts | Bin 0 -> 13693 bytes .../Designflow/sim/post/work/@_opt/vopt7dw2jd | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopt7hs9d2 | Bin 0 -> 13693 bytes .../Designflow/sim/post/work/@_opt/vopt7ndivd | Bin 0 -> 6744 bytes .../Designflow/sim/post/work/@_opt/vopt7y2es7 | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt7y4h7c | Bin 0 -> 6580 bytes .../Designflow/sim/post/work/@_opt/vopt7y5y26 | Bin 0 -> 2422 bytes .../Designflow/sim/post/work/@_opt/vopt80kb6s | Bin 0 -> 919 bytes .../Designflow/sim/post/work/@_opt/vopt85cx2g | Bin 0 -> 9708 bytes .../Designflow/sim/post/work/@_opt/vopt8bvh4c | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt8e77ct | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/vopt8ij05x | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopt8j0mtg | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/vopt8k66qj | Bin 0 -> 31680 bytes .../Designflow/sim/post/work/@_opt/vopt8m56re | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt8ng6xh | Bin 0 -> 1412 bytes .../Designflow/sim/post/work/@_opt/vopt8njaqt | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopt8yhe3w | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopt8ziwrw | Bin 0 -> 6582 bytes .../Designflow/sim/post/work/@_opt/vopt95ij4a | Bin 0 -> 4488 bytes .../Designflow/sim/post/work/@_opt/vopt9a1jxm | Bin 0 -> 1504 bytes .../Designflow/sim/post/work/@_opt/vopt9d1qrj | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt9h8r68 | Bin 0 -> 253 bytes .../Designflow/sim/post/work/@_opt/vopt9knfnt | Bin 0 -> 10110 bytes .../Designflow/sim/post/work/@_opt/vopt9ks3v6 | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopt9kvygh | Bin 0 -> 878 bytes .../Designflow/sim/post/work/@_opt/vopt9rw4ta | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/vopt9vfz01 | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/vopt9xxyy1 | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/vopta3vqte | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopta6gskx | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/voptajhv81 | Bin 0 -> 6447 bytes .../Designflow/sim/post/work/@_opt/voptasd3s8 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptb1fbks | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptbbfkjn | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptbe3c1g | Bin 0 -> 1292 bytes .../Designflow/sim/post/work/@_opt/voptbehey2 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptbeq6gd | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptbr95i6 | Bin 0 -> 10882 bytes .../Designflow/sim/post/work/@_opt/voptbrg3gz | Bin 0 -> 844 bytes .../Designflow/sim/post/work/@_opt/voptbsx1xs | Bin 0 -> 24144 bytes .../Designflow/sim/post/work/@_opt/voptbtfiwb | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/voptbycmqt | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/voptbzgbat | 1227 ++ .../Designflow/sim/post/work/@_opt/voptc2vmiz | Bin 0 -> 1504 bytes .../Designflow/sim/post/work/@_opt/voptc5c5bq | Bin 0 -> 1696 bytes .../Designflow/sim/post/work/@_opt/voptc745ki | Bin 0 -> 9884 bytes .../Designflow/sim/post/work/@_opt/voptccnfkd | Bin 0 -> 228 bytes .../Designflow/sim/post/work/@_opt/voptcmsfjz | Bin 0 -> 44016 bytes .../Designflow/sim/post/work/@_opt/voptcq3297 | Bin 0 -> 3713 bytes .../Designflow/sim/post/work/@_opt/voptczegea | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptd0tja7 | Bin 0 -> 3228 bytes .../Designflow/sim/post/work/@_opt/voptd2nx7v | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/voptda9n7k | Bin 0 -> 6584 bytes .../Designflow/sim/post/work/@_opt/voptde43s5 | Bin 0 -> 31680 bytes .../Designflow/sim/post/work/@_opt/voptdgzq4m | Bin 0 -> 1419 bytes .../Designflow/sim/post/work/@_opt/voptdt1kqd | Bin 0 -> 2314 bytes .../Designflow/sim/post/work/@_opt/vopte38ew9 | Bin 0 -> 6447 bytes .../Designflow/sim/post/work/@_opt/vopte3c0b8 | Bin 0 -> 5712 bytes .../Designflow/sim/post/work/@_opt/vopte6bm43 | Bin 0 -> 1356 bytes .../Designflow/sim/post/work/@_opt/vopte6tw9f | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/vopte6vewz | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopte7cdjw | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptec5k4k | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopted2bjz | Bin 0 -> 1452 bytes .../Designflow/sim/post/work/@_opt/voptee9zbv | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptehc8qt | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptemmexf | Bin 0 -> 1172 bytes .../Designflow/sim/post/work/@_opt/voptenvrm7 | Bin 0 -> 45488 bytes .../Designflow/sim/post/work/@_opt/vopteq3s6b | Bin 0 -> 1568 bytes .../Designflow/sim/post/work/@_opt/voptervh7c | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptexb4sn | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/voptf3xim8 | Bin 0 -> 8080 bytes .../Designflow/sim/post/work/@_opt/voptfbjxgg | Bin 0 -> 13693 bytes .../Designflow/sim/post/work/@_opt/voptfd96yv | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptfg8mkb | Bin 0 -> 169 bytes .../Designflow/sim/post/work/@_opt/voptfgziqm | Bin 0 -> 1416 bytes .../Designflow/sim/post/work/@_opt/voptfjdkq2 | Bin 0 -> 1953 bytes .../Designflow/sim/post/work/@_opt/voptfnzcsx | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptfqwwnk | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptfwwe01 | Bin 0 -> 9760 bytes .../Designflow/sim/post/work/@_opt/voptg33dir | Bin 0 -> 1248 bytes .../Designflow/sim/post/work/@_opt/voptg4a5e2 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptg5gxf2 | Bin 0 -> 31680 bytes .../Designflow/sim/post/work/@_opt/voptg98wsq | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/voptg9hyxh | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptgehny4 | Bin 0 -> 1232 bytes .../Designflow/sim/post/work/@_opt/voptgf4fb8 | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptgfmnqn | Bin 0 -> 2903 bytes .../Designflow/sim/post/work/@_opt/voptggzebt | Bin 0 -> 3572 bytes .../Designflow/sim/post/work/@_opt/voptgq2ee5 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptgrj5dx | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptgt7ck1 | Bin 0 -> 9696 bytes .../Designflow/sim/post/work/@_opt/voptgv1vae | Bin 0 -> 1172 bytes .../Designflow/sim/post/work/@_opt/voptgw96k6 | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptgx98fc | Bin 0 -> 6516 bytes .../Designflow/sim/post/work/@_opt/vopth0r1q1 | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopthf9fm2 | Bin 0 -> 1348 bytes .../Designflow/sim/post/work/@_opt/vopthh22i5 | Bin 0 -> 2080 bytes .../Designflow/sim/post/work/@_opt/vopthi1hkx | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/vopthi41g1 | Bin 0 -> 57624 bytes .../Designflow/sim/post/work/@_opt/vopthqq36t | Bin 0 -> 9704 bytes .../Designflow/sim/post/work/@_opt/vopthsj9c1 | Bin 0 -> 9480 bytes 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| Bin 0 -> 1516 bytes .../Designflow/sim/post/work/@_opt/voptjmz2fq | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/voptjrba9g | Bin 0 -> 2091 bytes .../Designflow/sim/post/work/@_opt/voptk299q0 | Bin 0 -> 3516 bytes .../Designflow/sim/post/work/@_opt/voptk3m8eg | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptk71at1 | Bin 0 -> 1288 bytes .../Designflow/sim/post/work/@_opt/voptka4h5r | Bin 0 -> 57624 bytes .../Designflow/sim/post/work/@_opt/voptkfq0ks | Bin 0 -> 31680 bytes .../Designflow/sim/post/work/@_opt/voptkik6hi | Bin 0 -> 31680 bytes .../Designflow/sim/post/work/@_opt/voptkjcf41 | Bin 0 -> 13693 bytes .../Designflow/sim/post/work/@_opt/voptkk7zn7 | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptknakms | Bin 0 -> 1440 bytes .../Designflow/sim/post/work/@_opt/voptkwfg7b | Bin 0 -> 26888 bytes .../Designflow/sim/post/work/@_opt/voptm289ge | Bin 0 -> 20696 bytes .../Designflow/sim/post/work/@_opt/voptm2tjnz | Bin 0 -> 720 bytes .../Designflow/sim/post/work/@_opt/voptm5rsfd | 148 + .../Designflow/sim/post/work/@_opt/voptm788y2 | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptmas2y3 | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptmbqb5s | Bin 0 -> 3288 bytes .../Designflow/sim/post/work/@_opt/voptmc2amk | Bin 0 -> 256 bytes .../Designflow/sim/post/work/@_opt/voptmenshy | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptmfsea8 | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/voptmhrw9j | Bin 0 -> 18134 bytes .../Designflow/sim/post/work/@_opt/voptn99e2j | Bin 0 -> 1568 bytes .../Designflow/sim/post/work/@_opt/voptngrjm4 | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptnsszm7 | Bin 0 -> 9636 bytes .../Designflow/sim/post/work/@_opt/voptq0ijic | Bin 0 -> 9644 bytes .../Designflow/sim/post/work/@_opt/voptq3cbn0 | Bin 0 -> 601561 bytes .../Designflow/sim/post/work/@_opt/voptq6jizj | Bin 0 -> 5512 bytes .../Designflow/sim/post/work/@_opt/voptq758xd | Bin 0 -> 3512 bytes .../Designflow/sim/post/work/@_opt/voptq8x19g | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptq9jyiy | Bin 0 -> 1592 bytes .../Designflow/sim/post/work/@_opt/voptqbtaqb | Bin 0 -> 9644 bytes .../Designflow/sim/post/work/@_opt/voptqe37id | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/voptqizctz | Bin 0 -> 6644 bytes .../Designflow/sim/post/work/@_opt/voptqra3gr | Bin 0 -> 1631 bytes .../Designflow/sim/post/work/@_opt/voptqzq8en | Bin 0 -> 24144 bytes .../Designflow/sim/post/work/@_opt/voptr0v6kq | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptr6403x | Bin 0 -> 9760 bytes .../Designflow/sim/post/work/@_opt/voptrcqggt | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptrehctx | Bin 0 -> 24144 bytes .../Designflow/sim/post/work/@_opt/voptrgin7n | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptrh7jg3 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptrkqkb6 | Bin 0 -> 1894 bytes .../Designflow/sim/post/work/@_opt/voptrqqi3r | Bin 0 -> 1356 bytes .../Designflow/sim/post/work/@_opt/voptrqy1ym | Bin 0 -> 2840 bytes .../Designflow/sim/post/work/@_opt/voptrtgskv | Bin 0 -> 462 bytes .../Designflow/sim/post/work/@_opt/voptrtj0ec | Bin 0 -> 1416 bytes .../Designflow/sim/post/work/@_opt/vopts7vksi | 78 + .../Designflow/sim/post/work/@_opt/voptsj7ma9 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptsmgy31 | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptsmwm69 | Bin 0 -> 6037 bytes .../Designflow/sim/post/work/@_opt/voptt00gdd | Bin 0 -> 3056 bytes .../Designflow/sim/post/work/@_opt/voptt3acvn | Bin 0 -> 677 bytes .../Designflow/sim/post/work/@_opt/voptt5ebyt | Bin 0 -> 24144 bytes .../Designflow/sim/post/work/@_opt/voptt8w0rj | Bin 0 -> 1452 bytes .../Designflow/sim/post/work/@_opt/vopttdxxj4 | Bin 0 -> 40216 bytes .../Designflow/sim/post/work/@_opt/vopttehte1 | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/vopttf098e | Bin 0 -> 4770 bytes .../Designflow/sim/post/work/@_opt/vopttjxskh | Bin 0 -> 884 bytes .../Designflow/sim/post/work/@_opt/voptts38h1 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopttwr2kt | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopttx2t7a | Bin 0 -> 6582 bytes .../Designflow/sim/post/work/@_opt/vopttyy3mx | Bin 0 -> 3720 bytes .../Designflow/sim/post/work/@_opt/vopttzmffh | Bin 0 -> 6684 bytes .../Designflow/sim/post/work/@_opt/voptv0zb1d | Bin 0 -> 222071 bytes .../Designflow/sim/post/work/@_opt/voptv63t1g | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptv9yyfx | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptvbs1k9 | Bin 0 -> 9696 bytes .../Designflow/sim/post/work/@_opt/voptvee1bs | Bin 0 -> 1416 bytes .../Designflow/sim/post/work/@_opt/voptvgh3x6 | Bin 0 -> 9644 bytes .../Designflow/sim/post/work/@_opt/voptvhifra | Bin 0 -> 1176 bytes .../Designflow/sim/post/work/@_opt/voptvi2hi3 | Bin 0 -> 6285 bytes .../Designflow/sim/post/work/@_opt/voptvjvbjr | Bin 0 -> 3632 bytes .../Designflow/sim/post/work/@_opt/voptvkq1q6 | Bin 0 -> 1504 bytes .../Designflow/sim/post/work/@_opt/voptvn0yh7 | Bin 0 -> 3110 bytes .../Designflow/sim/post/work/@_opt/voptvr74r3 | Bin 0 -> 9760 bytes .../Designflow/sim/post/work/@_opt/voptvstekn | Bin 0 -> 9708 bytes .../Designflow/sim/post/work/@_opt/voptvxwhvk | Bin 0 -> 9760 bytes .../Designflow/sim/post/work/@_opt/voptw0q5q4 | Bin 0 -> 4715 bytes .../Designflow/sim/post/work/@_opt/voptw3zvzg | Bin 0 -> 7750 bytes .../Designflow/sim/post/work/@_opt/voptwcraje | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptwdeqf8 | Bin 0 -> 1352 bytes .../Designflow/sim/post/work/@_opt/voptwj1h56 | Bin 0 -> 6104 bytes .../Designflow/sim/post/work/@_opt/voptwn8bd8 | Bin 0 -> 1168 bytes .../Designflow/sim/post/work/@_opt/voptx1a26g | Bin 0 -> 1821 bytes .../Designflow/sim/post/work/@_opt/voptxcxqtx | Bin 0 -> 1356 bytes .../Designflow/sim/post/work/@_opt/voptxdahza | Bin 0 -> 10882 bytes .../Designflow/sim/post/work/@_opt/voptxj446w | Bin 0 -> 640 bytes .../Designflow/sim/post/work/@_opt/voptxy0mgt | Bin 0 -> 1673 bytes .../Designflow/sim/post/work/@_opt/vopty4nqz9 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/vopty9tfij | Bin 0 -> 1267 bytes .../Designflow/sim/post/work/@_opt/voptyhmtbi | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptyhngfr | Bin 0 -> 6582 bytes .../Designflow/sim/post/work/@_opt/voptykrs0a | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptymsefg | Bin 0 -> 13693 bytes .../Designflow/sim/post/work/@_opt/voptyn1f5j | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptyqya85 | Bin 0 -> 20833 bytes .../Designflow/sim/post/work/@_opt/voptyrwyt3 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptyskb8t | Bin 0 -> 1234 bytes .../Designflow/sim/post/work/@_opt/voptz3jt2s | Bin 0 -> 8696 bytes .../Designflow/sim/post/work/@_opt/voptza8gh6 | Bin 0 -> 9480 bytes .../Designflow/sim/post/work/@_opt/voptzcy49x | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptzgnc75 | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptznc0g5 | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptzww4tv | Bin 0 -> 36904 bytes .../Designflow/sim/post/work/@_opt/voptzwzy11 | Bin 0 -> 1575 bytes .../Designflow/sim/post/work/@_opt/voptzy6fxn | Bin 0 -> 9033 bytes .../Designflow/sim/post/work/@_opt/voptzztzz4 | Bin 0 -> 408 bytes bsp3/Designflow/sim/post/work/_info | 134 + bsp3/Designflow/sim/post/work/_vmake | 3 + .../Designflow/sim/post/work/vga/_primary.dat | Bin 0 -> 1100 bytes .../Designflow/sim/post/work/vga/_primary.dbs | Bin 0 -> 2356 bytes .../sim/post/work/vga/structure.dat | Bin 0 -> 87467 bytes .../sim/post/work/vga/structure.dbs | Bin 0 -> 222071 bytes .../sim/post/work/vga_conf_pos/_primary.dat | Bin 0 -> 169 bytes .../sim/post/work/vga_conf_pos/_primary.dbs | Bin 0 -> 462 bytes .../sim/post/work/vga_pak/_primary.dat | Bin 0 -> 2439 bytes .../sim/post/work/vga_pak/_primary.dbs | Bin 0 -> 3713 bytes .../sim/post/work/vga_pos_tb/_primary.dat | Bin 0 -> 228 bytes .../sim/post/work/vga_pos_tb/_primary.dbs | Bin 0 -> 575 bytes .../sim/post/work/vga_pos_tb/structure.dat | Bin 0 -> 2439 bytes .../sim/post/work/vga_pos_tb/structure.dbs | Bin 0 -> 6157 bytes bsp3/Designflow/sim/pre/modelsim.ini | 1305 ++ bsp3/Designflow/sim/pre/vsim.wlf | Bin 0 -> 155648 bytes bsp3/Designflow/sim/pre/work/@_opt/_deps | Bin 0 -> 22463 bytes bsp3/Designflow/sim/pre/work/@_opt/vopt0am9rm | 78 + bsp3/Designflow/sim/pre/work/@_opt/vopt0i6c4w | Bin 0 -> 6582 bytes bsp3/Designflow/sim/pre/work/@_opt/vopt0k8345 | Bin 0 -> 2276 bytes bsp3/Designflow/sim/pre/work/@_opt/vopt0x4vyk | Bin 0 -> 20833 bytes bsp3/Designflow/sim/pre/work/@_opt/vopt0y2684 | Bin 0 -> 1761 bytes bsp3/Designflow/sim/pre/work/@_opt/vopt10awzd | Bin 0 -> 7750 bytes bsp3/Designflow/sim/pre/work/@_opt/vopt122z3y | Bin 0 -> 31744 bytes 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=> vga:inst.reset_pin +d_vsync <= vga:inst.d_vsync +d_set_column_counter <= vga:inst.d_set_column_counter +d_set_line_counter <= vga:inst.d_set_line_counter +d_set_hsync_counter <= vga:inst.d_set_hsync_counter +d_set_vsync_counter <= vga:inst.d_set_vsync_counter +d_r <= vga:inst.d_r +d_g <= vga:inst.d_g +d_b <= vga:inst.d_b +d_h_enable <= vga:inst.d_h_enable +d_v_enable <= vga:inst.d_v_enable +d_state_clk <= vga:inst.d_state_clk +r0_pin <= vga:inst.r0_pin +r1_pin <= vga:inst.r1_pin +r2_pin <= vga:inst.r2_pin +g0_pin <= vga:inst.g0_pin +g1_pin <= vga:inst.g1_pin +g2_pin <= vga:inst.g2_pin +b0_pin <= vga:inst.b0_pin +b1_pin <= vga:inst.b1_pin +hsync_pin <= vga:inst.hsync_pin +vsync_pin <= vga:inst.vsync_pin +d_column_counter[0] <= vga:inst.d_column_counter[0] +d_column_counter[1] <= vga:inst.d_column_counter[1] +d_column_counter[2] <= vga:inst.d_column_counter[2] +d_column_counter[3] <= vga:inst.d_column_counter[3] +d_column_counter[4] <= vga:inst.d_column_counter[4] +d_column_counter[5] <= vga:inst.d_column_counter[5] +d_column_counter[6] <= vga:inst.d_column_counter[6] +d_column_counter[7] <= vga:inst.d_column_counter[7] +d_column_counter[8] <= vga:inst.d_column_counter[8] +d_column_counter[9] <= vga:inst.d_column_counter[9] +d_hsync_counter[0] <= vga:inst.d_hsync_counter[0] +d_hsync_counter[1] <= vga:inst.d_hsync_counter[1] +d_hsync_counter[2] <= vga:inst.d_hsync_counter[2] +d_hsync_counter[3] <= vga:inst.d_hsync_counter[3] +d_hsync_counter[4] <= vga:inst.d_hsync_counter[4] +d_hsync_counter[5] <= vga:inst.d_hsync_counter[5] +d_hsync_counter[6] <= vga:inst.d_hsync_counter[6] +d_hsync_counter[7] <= vga:inst.d_hsync_counter[7] +d_hsync_counter[8] <= vga:inst.d_hsync_counter[8] +d_hsync_counter[9] <= vga:inst.d_hsync_counter[9] +d_hsync_state[6] <= vga:inst.d_hsync_state[6] +d_hsync_state[5] <= vga:inst.d_hsync_state[5] +d_hsync_state[4] <= vga:inst.d_hsync_state[4] +d_hsync_state[3] <= vga:inst.d_hsync_state[3] +d_hsync_state[2] <= vga:inst.d_hsync_state[2] +d_hsync_state[1] <= vga:inst.d_hsync_state[1] +d_hsync_state[0] <= vga:inst.d_hsync_state[0] +d_line_counter[0] <= vga:inst.d_line_counter[0] +d_line_counter[1] <= vga:inst.d_line_counter[1] +d_line_counter[2] <= vga:inst.d_line_counter[2] +d_line_counter[3] <= vga:inst.d_line_counter[3] +d_line_counter[4] <= vga:inst.d_line_counter[4] +d_line_counter[5] <= vga:inst.d_line_counter[5] +d_line_counter[6] <= vga:inst.d_line_counter[6] +d_line_counter[7] <= vga:inst.d_line_counter[7] +d_line_counter[8] <= vga:inst.d_line_counter[8] +d_vsync_counter[0] <= vga:inst.d_vsync_counter[0] +d_vsync_counter[1] <= vga:inst.d_vsync_counter[1] +d_vsync_counter[2] <= vga:inst.d_vsync_counter[2] +d_vsync_counter[3] <= vga:inst.d_vsync_counter[3] +d_vsync_counter[4] <= vga:inst.d_vsync_counter[4] +d_vsync_counter[5] <= vga:inst.d_vsync_counter[5] +d_vsync_counter[6] <= vga:inst.d_vsync_counter[6] +d_vsync_counter[7] <= vga:inst.d_vsync_counter[7] +d_vsync_counter[8] <= vga:inst.d_vsync_counter[8] +d_vsync_counter[9] <= vga:inst.d_vsync_counter[9] +d_vsync_state[6] <= vga:inst.d_vsync_state[6] +d_vsync_state[5] <= vga:inst.d_vsync_state[5] +d_vsync_state[4] <= vga:inst.d_vsync_state[4] +d_vsync_state[3] <= vga:inst.d_vsync_state[3] +d_vsync_state[2] <= vga:inst.d_vsync_state[2] +d_vsync_state[1] <= vga:inst.d_vsync_state[1] +d_vsync_state[0] <= vga:inst.d_vsync_state[0] +seven_seg_pin[0] <= vga:inst.seven_seg_pin[0] +seven_seg_pin[1] <= vga:inst.seven_seg_pin[1] +seven_seg_pin[2] <= vga:inst.seven_seg_pin[2] +seven_seg_pin[3] <= vga:inst.seven_seg_pin[3] +seven_seg_pin[4] <= vga:inst.seven_seg_pin[4] +seven_seg_pin[5] <= vga:inst.seven_seg_pin[5] +seven_seg_pin[6] <= vga:inst.seven_seg_pin[6] +seven_seg_pin[7] <= vga:inst.seven_seg_pin[7] +seven_seg_pin[8] <= vga:inst.seven_seg_pin[8] +seven_seg_pin[9] <= vga:inst.seven_seg_pin[9] +seven_seg_pin[10] <= vga:inst.seven_seg_pin[10] +seven_seg_pin[11] <= vga:inst.seven_seg_pin[11] +seven_seg_pin[12] <= vga:inst.seven_seg_pin[12] +seven_seg_pin[13] <= vga:inst.seven_seg_pin[13] + + +|vga_pll|vga:inst +clk_pin => clk_pin_in.PADIO +reset_pin => reset_pin_in.PADIO +r0_pin <= r0_pin_out.PADIO +r1_pin <= r1_pin_out.PADIO +r2_pin <= r2_pin_out.PADIO +g0_pin <= g0_pin_out.PADIO +g1_pin <= g1_pin_out.PADIO +g2_pin <= g2_pin_out.PADIO +b0_pin <= b0_pin_out.PADIO +b1_pin <= b1_pin_out.PADIO +hsync_pin <= hsync_pin_out.PADIO +vsync_pin <= vsync_pin_out.PADIO +seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO +seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO +seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO +seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO +seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO +seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO +seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO +seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO +seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO +seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO +seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO +seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO +seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO +seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO +d_hsync <= d_hsync_out.PADIO +d_vsync <= d_vsync_out.PADIO +d_column_counter[0] <= d_column_counter_out_0_.PADIO +d_column_counter[1] <= d_column_counter_out_1_.PADIO +d_column_counter[2] <= d_column_counter_out_2_.PADIO +d_column_counter[3] <= d_column_counter_out_3_.PADIO +d_column_counter[4] <= d_column_counter_out_4_.PADIO +d_column_counter[5] <= d_column_counter_out_5_.PADIO +d_column_counter[6] <= d_column_counter_out_6_.PADIO +d_column_counter[7] <= d_column_counter_out_7_.PADIO +d_column_counter[8] <= d_column_counter_out_8_.PADIO +d_column_counter[9] <= d_column_counter_out_9_.PADIO +d_line_counter[0] <= d_line_counter_out_0_.PADIO +d_line_counter[1] <= d_line_counter_out_1_.PADIO +d_line_counter[2] <= d_line_counter_out_2_.PADIO +d_line_counter[3] <= d_line_counter_out_3_.PADIO +d_line_counter[4] <= d_line_counter_out_4_.PADIO +d_line_counter[5] <= d_line_counter_out_5_.PADIO +d_line_counter[6] <= d_line_counter_out_6_.PADIO +d_line_counter[7] <= d_line_counter_out_7_.PADIO +d_line_counter[8] <= d_line_counter_out_8_.PADIO +d_set_column_counter <= d_set_column_counter_out.PADIO +d_set_line_counter <= d_set_line_counter_out.PADIO +d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO +d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO +d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO +d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO +d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO +d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO +d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO +d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO +d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO +d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO +d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO +d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO +d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO +d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO +d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO +d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO +d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO +d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO +d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO +d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO +d_set_hsync_counter <= d_set_hsync_counter_out.PADIO +d_set_vsync_counter <= d_set_vsync_counter_out.PADIO +d_h_enable <= d_h_enable_out.PADIO +d_v_enable <= d_v_enable_out.PADIO +d_r <= d_r_out.PADIO +d_g <= d_g_out.PADIO +d_b <= d_b_out.PADIO +d_hsync_state[6] <= d_hsync_state_out_6_.PADIO +d_hsync_state[5] <= d_hsync_state_out_5_.PADIO +d_hsync_state[4] <= d_hsync_state_out_4_.PADIO +d_hsync_state[3] <= d_hsync_state_out_3_.PADIO +d_hsync_state[2] <= d_hsync_state_out_2_.PADIO +d_hsync_state[1] <= d_hsync_state_out_1_.PADIO +d_hsync_state[0] <= d_hsync_state_out_0_.PADIO +d_vsync_state[6] <= d_vsync_state_out_6_.PADIO +d_vsync_state[5] <= d_vsync_state_out_5_.PADIO +d_vsync_state[4] <= d_vsync_state_out_4_.PADIO +d_vsync_state[3] <= d_vsync_state_out_3_.PADIO +d_vsync_state[2] <= d_vsync_state_out_2_.PADIO +d_vsync_state[1] <= d_vsync_state_out_1_.PADIO +d_vsync_state[0] <= d_vsync_state_out_0_.PADIO +d_state_clk <= d_state_clk_out.PADIO + + +|vga_pll|vga:inst|vga_driver:vga_driver_unit +line_counter_sig_0 <= line_counter_sig_0_.REGOUT +line_counter_sig_1 <= line_counter_sig_1_.REGOUT +line_counter_sig_2 <= line_counter_sig_2_.REGOUT +line_counter_sig_3 <= line_counter_sig_3_.REGOUT +line_counter_sig_4 <= line_counter_sig_4_.REGOUT +line_counter_sig_5 <= line_counter_sig_5_.REGOUT +line_counter_sig_6 <= line_counter_sig_6_.REGOUT +line_counter_sig_7 <= line_counter_sig_7_.REGOUT +line_counter_sig_8 <= line_counter_sig_8_.REGOUT +dly_counter_1 => vsync_state_6_.DATAC +dly_counter_1 => h_sync_Z.DATAC +dly_counter_1 => v_sync_Z.DATAC +dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC +dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC +dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC +dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC +dly_counter_0 => vsync_state_6_.DATAB +dly_counter_0 => h_sync_Z.DATAB +dly_counter_0 => v_sync_Z.DATAB +dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB +dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB +dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB +dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB +vsync_state_2 <= vsync_state_2_.REGOUT +vsync_state_5 <= vsync_state_5_.REGOUT +vsync_state_3 <= vsync_state_3_.REGOUT +vsync_state_6 <= vsync_state_6_.REGOUT +vsync_state_4 <= vsync_state_4_.REGOUT +vsync_state_1 <= vsync_state_1_.REGOUT +vsync_state_0 <= vsync_state_0_.REGOUT +hsync_state_2 <= hsync_state_2_.REGOUT +hsync_state_4 <= hsync_state_4_.REGOUT +hsync_state_0 <= hsync_state_0_.REGOUT +hsync_state_5 <= hsync_state_5_.REGOUT +hsync_state_1 <= hsync_state_1_.REGOUT +hsync_state_3 <= hsync_state_3_.REGOUT +hsync_state_6 <= hsync_state_6_.REGOUT +column_counter_sig_0 <= column_counter_sig_0_.REGOUT +column_counter_sig_1 <= column_counter_sig_1_.REGOUT +column_counter_sig_2 <= column_counter_sig_2_.REGOUT +column_counter_sig_3 <= column_counter_sig_3_.REGOUT +column_counter_sig_4 <= column_counter_sig_4_.REGOUT +column_counter_sig_5 <= column_counter_sig_5_.REGOUT +column_counter_sig_6 <= column_counter_sig_6_.REGOUT +column_counter_sig_7 <= column_counter_sig_7_.REGOUT +column_counter_sig_8 <= column_counter_sig_8_.REGOUT +column_counter_sig_9 <= column_counter_sig_9_.REGOUT +vsync_counter_9 <= vsync_counter_9_.REGOUT +vsync_counter_8 <= vsync_counter_8_.REGOUT +vsync_counter_7 <= vsync_counter_7_.REGOUT +vsync_counter_6 <= vsync_counter_6_.REGOUT +vsync_counter_5 <= vsync_counter_5_.REGOUT +vsync_counter_4 <= vsync_counter_4_.REGOUT +vsync_counter_3 <= vsync_counter_3_.REGOUT +vsync_counter_2 <= vsync_counter_2_.REGOUT +vsync_counter_1 <= vsync_counter_1_.REGOUT +vsync_counter_0 <= vsync_counter_0_.REGOUT +hsync_counter_9 <= hsync_counter_9_.REGOUT +hsync_counter_8 <= hsync_counter_8_.REGOUT +hsync_counter_7 <= hsync_counter_7_.REGOUT +hsync_counter_6 <= hsync_counter_6_.REGOUT +hsync_counter_5 <= hsync_counter_5_.REGOUT +hsync_counter_4 <= hsync_counter_4_.REGOUT +hsync_counter_3 <= hsync_counter_3_.REGOUT +hsync_counter_2 <= hsync_counter_2_.REGOUT +hsync_counter_1 <= hsync_counter_1_.REGOUT +hsync_counter_0 <= hsync_counter_0_.REGOUT +d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT +un10_column_counter_siglt6_1 <= COLUMN_COUNT_next_un10_column_counter_siglt6_1.COMBOUT +un10_column_counter_siglt6_3 <= COLUMN_COUNT_next_un10_column_counter_siglt6_3.COMBOUT +v_sync <= v_sync_Z.REGOUT +h_sync <= h_sync_Z.REGOUT +h_enable_sig <= h_enable_sig_Z.REGOUT +v_enable_sig <= v_enable_sig_Z.REGOUT +reset_pin_c => vsync_state_6_.DATAA +reset_pin_c => h_sync_Z.DATAA +reset_pin_c => v_sync_Z.DATAA +reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA +reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA +reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA +reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA +un6_dly_counter_0_x <= vsync_state_6_.COMBOUT +d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT +clk_pin_c => hsync_counter_0_.CLK +clk_pin_c => hsync_counter_1_.CLK +clk_pin_c => hsync_counter_2_.CLK +clk_pin_c => hsync_counter_3_.CLK +clk_pin_c => hsync_counter_4_.CLK +clk_pin_c => hsync_counter_5_.CLK +clk_pin_c => hsync_counter_6_.CLK +clk_pin_c => hsync_counter_7_.CLK +clk_pin_c => hsync_counter_8_.CLK +clk_pin_c => hsync_counter_9_.CLK +clk_pin_c => vsync_counter_0_.CLK +clk_pin_c => vsync_counter_1_.CLK +clk_pin_c => vsync_counter_2_.CLK +clk_pin_c => vsync_counter_3_.CLK +clk_pin_c => vsync_counter_4_.CLK +clk_pin_c => vsync_counter_5_.CLK +clk_pin_c => vsync_counter_6_.CLK +clk_pin_c => vsync_counter_7_.CLK +clk_pin_c => vsync_counter_8_.CLK +clk_pin_c => vsync_counter_9_.CLK +clk_pin_c => column_counter_sig_9_.CLK +clk_pin_c => column_counter_sig_8_.CLK +clk_pin_c => column_counter_sig_7_.CLK +clk_pin_c => column_counter_sig_6_.CLK +clk_pin_c => column_counter_sig_5_.CLK +clk_pin_c => column_counter_sig_4_.CLK +clk_pin_c => column_counter_sig_3_.CLK +clk_pin_c => column_counter_sig_2_.CLK +clk_pin_c => column_counter_sig_1_.CLK +clk_pin_c => column_counter_sig_0_.CLK +clk_pin_c => hsync_state_6_.CLK +clk_pin_c => vsync_state_0_.CLK +clk_pin_c => vsync_state_1_.CLK +clk_pin_c => vsync_state_6_.CLK +clk_pin_c => line_counter_sig_8_.CLK +clk_pin_c => line_counter_sig_7_.CLK +clk_pin_c => line_counter_sig_6_.CLK +clk_pin_c => line_counter_sig_5_.CLK +clk_pin_c => line_counter_sig_4_.CLK +clk_pin_c => line_counter_sig_3_.CLK +clk_pin_c => line_counter_sig_2_.CLK +clk_pin_c => line_counter_sig_1_.CLK +clk_pin_c => line_counter_sig_0_.CLK +clk_pin_c => v_enable_sig_Z.CLK +clk_pin_c => h_enable_sig_Z.CLK +clk_pin_c => h_sync_Z.CLK +clk_pin_c => v_sync_Z.CLK +clk_pin_c => vsync_state_5_.CLK +clk_pin_c => vsync_state_4_.CLK +clk_pin_c => vsync_state_3_.CLK +clk_pin_c => vsync_state_2_.CLK +clk_pin_c => hsync_state_5_.CLK +clk_pin_c => hsync_state_4_.CLK +clk_pin_c => hsync_state_3_.CLK +clk_pin_c => hsync_state_2_.CLK +clk_pin_c => hsync_state_1_.CLK +clk_pin_c => hsync_state_0_.CLK + + +|vga_pll|vga:inst|vga_control:vga_control_unit +column_counter_sig_1 => g_next_i_o3_cZ.DATAB +column_counter_sig_7 => r_next_i_o7_cZ.DATAA +column_counter_sig_2 => b_next_i_o3_0_cZ.DATAC +column_counter_sig_2 => g_next_i_o3_cZ.DATAA +column_counter_sig_0 => b_next_i_a7_1_cZ.DATAC +column_counter_sig_4 => N_23_i_0_g0_a_cZ.DATAB +column_counter_sig_4 => b_next_i_o3_0_cZ.DATAB +column_counter_sig_3 => N_23_i_0_g0_a_cZ.DATAA +column_counter_sig_3 => b_next_i_o3_0_cZ.DATAA +column_counter_sig_5 => g_Z.DATAB +column_counter_sig_5 => N_4_i_0_g0_1_cZ.DATAA +column_counter_sig_5 => N_6_i_0_g0_0_cZ.DATAA +column_counter_sig_5 => b_next_i_a7_1_cZ.DATAA +column_counter_sig_5 => b_next_i_o3_0_cZ.DATAD +column_counter_sig_6 => b_Z.DATAA +column_counter_sig_6 => r_Z.DATAA +column_counter_sig_6 => g_Z.DATAA +column_counter_sig_6 => N_4_i_0_g0_1_cZ.DATAB +column_counter_sig_6 => N_6_i_0_g0_0_cZ.DATAB +column_counter_sig_6 => b_next_i_a7_1_cZ.DATAB +h_enable_sig => r_next_i_o7_cZ.DATAC +v_enable_sig => r_next_i_o7_cZ.DATAB +un10_column_counter_siglt6_1 => N_23_i_0_g0_a_cZ.DATAD +g <= g_Z.REGOUT +un10_column_counter_siglt6_3 => r_Z.DATAB +un10_column_counter_siglt6_3 => N_6_i_0_g0_0_cZ.DATAC +r <= r_Z.REGOUT +un6_dly_counter_0_x => b_Z.ACLR +un6_dly_counter_0_x => r_Z.ACLR +un6_dly_counter_0_x => g_Z.ACLR +clk_pin_c => b_Z.CLK +clk_pin_c => r_Z.CLK +clk_pin_c => g_Z.CLK +b <= b_Z.REGOUT + + +|vga_pll|vpll:inst1 +inclk0 => altpll:altpll_component.inclk[0] +c0 <= altpll:altpll_component.clk[0] + + +|vga_pll|vpll:inst1|altpll:altpll_component +inclk[0] => pll.CLK +inclk[1] => ~NO_FANOUT~ +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => ~NO_FANOUT~ +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => pll.ENA1 +clkena[2] => pll.ENA2 +clkena[3] => pll.ENA3 +clkena[4] => pll.ENA4 +clkena[5] => pll.ENA5 +extclkena[0] => pll.EXTCLKENA +extclkena[1] => pll.EXTCLKENA1 +extclkena[2] => pll.EXTCLKENA2 +extclkena[3] => pll.EXTCLKENA3 +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <= +clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= +clk[2] <= +clk[3] <= +clk[4] <= +clk[5] <= +extclk[0] <= +extclk[1] <= +extclk[2] <= +extclk[3] <= +clkbad[0] <= +clkbad[1] <= +enable1 <= +enable0 <= +activeclock <= +clkloss <= +locked <= +scandataout <= +scandone <= +sclkout0 <= +sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE +phasedone <= +vcooverrange <= +vcounderrange <= +fbout <= + + diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.hif b/bsp3/Designflow/ppr/download/db/vga_pll.hif new file mode 100644 index 0000000..5409a6a --- /dev/null +++ b/bsp3/Designflow/ppr/download/db/vga_pll.hif @@ -0,0 +1,1669 @@ +Version 9.0 Build 132 02/25/2009 SJ Full Version +45 +3235 +OFF +OFF +OFF +ON +ON +OFF +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +synplcty.lmf +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +vga_pll +# storage +db|vga_pll.(0).cnf +db|vga_pll.(0).cnf +# case_insensitive +# source_file +..|..|src|vga_pll.bdf +d3e7ceaac9b26558f3ae0434c87e1 +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +| +} +# lmf +|opt|quartus|quartus|lmf|synplcty.lmf +3057712873b497a38b70a3917f30cc38 +# macro_sequence + +# end +# entity +vga +# storage +db|vga_pll.(1).cnf +db|vga_pll.(1).cnf +# case_sensitive +# source_file +..|..|syn|rev_1|vga.vqm +75b23e99ee7fd7794044e77b9ba64bf9 +28 +# hierarchies { +vga:inst +} +# lmf +|opt|quartus|quartus|lmf|synplcty.lmf +3057712873b497a38b70a3917f30cc38 +# macro_sequence + +# end +# entity +vga_driver +# storage +db|vga_pll.(2).cnf +db|vga_pll.(2).cnf +# case_sensitive +# source_file +..|..|syn|rev_1|vga.vqm +75b23e99ee7fd7794044e77b9ba64bf9 +28 +# hierarchies { +vga:inst|vga_driver:vga_driver_unit +} +# lmf +|opt|quartus|quartus|lmf|synplcty.lmf +3057712873b497a38b70a3917f30cc38 +# macro_sequence + +# end +# entity +vga_control +# storage +db|vga_pll.(3).cnf +db|vga_pll.(3).cnf +# case_sensitive +# source_file +..|..|syn|rev_1|vga.vqm +75b23e99ee7fd7794044e77b9ba64bf9 +28 +# hierarchies { +vga:inst|vga_control:vga_control_unit +} +# lmf +|opt|quartus|quartus|lmf|synplcty.lmf +3057712873b497a38b70a3917f30cc38 +# macro_sequence + +# end +# entity +vpll +# storage +db|vga_pll.(4).cnf +db|vga_pll.(4).cnf +# logic_option { +AUTO_RAM_RECOGNITION +ON +} +# case_insensitive +# source_file +..|..|src|vpll.vhd +ccc2bcb05887d5721243fd22481948be +5 +# internal_option { +HDL_INITIAL_FANOUT_LIMIT +OFF +AUTO_RESOURCE_SHARING +OFF +AUTO_RAM_RECOGNITION +ON +AUTO_ROM_RECOGNITION +ON +} +# hierarchies { +vpll:inst1 +} +# lmf +|opt|quartus|quartus|lmf|maxplus2.lmf +9a59d39b0706640b4b2718e8a1ff1f +# macro_sequence + +# end +# entity +altpll +# storage +db|vga_pll.(5).cnf +db|vga_pll.(5).cnf +# case_insensitive +# source_file +|opt|quartus|quartus|libraries|megafunctions|altpll.tdf +d980162588d7aa8b78874932c782e18 +7 +# user_parameter { +OPERATION_MODE +NORMAL +PARAMETER_UNKNOWN +USR +PLL_TYPE +AUTO +PARAMETER_UNKNOWN +USR +QUALIFY_CONF_DONE +OFF +PARAMETER_UNKNOWN +DEF +COMPENSATE_CLOCK +CLK0 +PARAMETER_UNKNOWN +USR +SCAN_CHAIN +LONG +PARAMETER_UNKNOWN +DEF +PRIMARY_CLOCK +INCLK0 +PARAMETER_UNKNOWN +DEF +INCLK0_INPUT_FREQUENCY +30003 +PARAMETER_SIGNED_DEC +USR +INCLK1_INPUT_FREQUENCY +0 +PARAMETER_UNKNOWN +DEF +GATE_LOCK_SIGNAL +NO +PARAMETER_UNKNOWN +USR +GATE_LOCK_COUNTER +0 +PARAMETER_UNKNOWN +DEF +LOCK_HIGH +1 +PARAMETER_UNKNOWN +DEF +LOCK_LOW +1 +PARAMETER_UNKNOWN +DEF +VALID_LOCK_MULTIPLIER +1 +PARAMETER_SIGNED_DEC +USR +INVALID_LOCK_MULTIPLIER +5 +PARAMETER_SIGNED_DEC +USR +SWITCH_OVER_ON_LOSSCLK +OFF +PARAMETER_UNKNOWN +DEF +SWITCH_OVER_ON_GATED_LOCK +OFF +PARAMETER_UNKNOWN +DEF +ENABLE_SWITCH_OVER_COUNTER +OFF +PARAMETER_UNKNOWN +DEF +SKIP_VCO +OFF +PARAMETER_UNKNOWN +DEF +SWITCH_OVER_COUNTER +0 +PARAMETER_UNKNOWN +DEF +SWITCH_OVER_TYPE +AUTO +PARAMETER_UNKNOWN +DEF +FEEDBACK_SOURCE +EXTCLK0 +PARAMETER_UNKNOWN +DEF +BANDWIDTH +0 +PARAMETER_UNKNOWN +DEF +BANDWIDTH_TYPE +AUTO +PARAMETER_UNKNOWN +USR +SPREAD_FREQUENCY +0 +PARAMETER_SIGNED_DEC +USR +DOWN_SPREAD +0 +PARAMETER_UNKNOWN +DEF +SELF_RESET_ON_GATED_LOSS_LOCK +OFF +PARAMETER_UNKNOWN +DEF +SELF_RESET_ON_LOSS_LOCK +OFF +PARAMETER_UNKNOWN +DEF +CLK9_MULTIPLY_BY +0 +PARAMETER_UNKNOWN +DEF +CLK8_MULTIPLY_BY +0 +PARAMETER_UNKNOWN +DEF +CLK7_MULTIPLY_BY +0 +PARAMETER_UNKNOWN +DEF +CLK6_MULTIPLY_BY +0 +PARAMETER_UNKNOWN +DEF +CLK5_MULTIPLY_BY +1 +PARAMETER_UNKNOWN +DEF +CLK4_MULTIPLY_BY +1 +PARAMETER_UNKNOWN +DEF +CLK3_MULTIPLY_BY +1 +PARAMETER_UNKNOWN +DEF +CLK2_MULTIPLY_BY +1 +PARAMETER_UNKNOWN +DEF +CLK1_MULTIPLY_BY +1 +PARAMETER_UNKNOWN +DEF +CLK0_MULTIPLY_BY +5435 +PARAMETER_SIGNED_DEC +USR +CLK9_DIVIDE_BY +0 +PARAMETER_UNKNOWN +DEF +CLK8_DIVIDE_BY +0 +PARAMETER_UNKNOWN +DEF +CLK7_DIVIDE_BY +0 +PARAMETER_UNKNOWN +DEF +CLK6_DIVIDE_BY +0 +PARAMETER_UNKNOWN +DEF +CLK5_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +CLK4_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +CLK3_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +CLK2_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +CLK1_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +CLK0_DIVIDE_BY +6666 +PARAMETER_SIGNED_DEC +USR +CLK9_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +CLK8_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +CLK7_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +CLK6_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +CLK5_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +CLK4_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +CLK3_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +CLK2_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +CLK1_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +CLK0_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +USR +CLK5_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +CLK4_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +CLK3_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +CLK2_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +CLK1_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +CLK0_TIME_DELAY +0 +PARAMETER_UNKNOWN +USR +CLK9_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +CLK8_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +CLK7_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +CLK6_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +CLK5_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +CLK4_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +CLK3_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +CLK2_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +CLK1_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +CLK0_DUTY_CYCLE +50 +PARAMETER_SIGNED_DEC +USR +CLK9_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK8_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK7_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK6_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK5_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK4_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK3_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK2_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK1_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK0_USE_EVEN_COUNTER_MODE +OFF +PARAMETER_UNKNOWN +DEF +CLK9_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +CLK8_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +CLK7_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +CLK6_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +CLK5_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +CLK4_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +CLK3_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +CLK2_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +CLK1_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +CLK0_USE_EVEN_COUNTER_VALUE +OFF +PARAMETER_UNKNOWN +DEF +LOCK_WINDOW_UI + 0.05 +PARAMETER_UNKNOWN +DEF +LOCK_WINDOW_UI_BITS +UNUSED +PARAMETER_UNKNOWN +DEF +VCO_RANGE_DETECTOR_LOW_BITS +UNUSED +PARAMETER_UNKNOWN +DEF +VCO_RANGE_DETECTOR_HIGH_BITS +UNUSED +PARAMETER_UNKNOWN +DEF +DPA_MULTIPLY_BY +0 +PARAMETER_UNKNOWN +DEF +DPA_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +DPA_DIVIDER +0 +PARAMETER_UNKNOWN +DEF +EXTCLK3_MULTIPLY_BY +1 +PARAMETER_UNKNOWN +DEF +EXTCLK2_MULTIPLY_BY +1 +PARAMETER_UNKNOWN +DEF +EXTCLK1_MULTIPLY_BY +1 +PARAMETER_UNKNOWN +DEF +EXTCLK0_MULTIPLY_BY +1 +PARAMETER_UNKNOWN +DEF +EXTCLK3_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +EXTCLK2_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +EXTCLK1_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +EXTCLK0_DIVIDE_BY +1 +PARAMETER_UNKNOWN +DEF +EXTCLK3_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +EXTCLK2_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +EXTCLK1_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +EXTCLK0_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +EXTCLK3_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +EXTCLK2_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +EXTCLK1_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +EXTCLK0_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +EXTCLK3_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +EXTCLK2_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +EXTCLK1_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +EXTCLK0_DUTY_CYCLE +50 +PARAMETER_UNKNOWN +DEF +VCO_MULTIPLY_BY +0 +PARAMETER_UNKNOWN +DEF +VCO_DIVIDE_BY +0 +PARAMETER_UNKNOWN +DEF +SCLKOUT0_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +SCLKOUT1_PHASE_SHIFT +0 +PARAMETER_UNKNOWN +DEF +VCO_MIN +0 +PARAMETER_UNKNOWN +DEF +VCO_MAX +0 +PARAMETER_UNKNOWN +DEF +VCO_CENTER +0 +PARAMETER_UNKNOWN +DEF +PFD_MIN +0 +PARAMETER_UNKNOWN +DEF +PFD_MAX +0 +PARAMETER_UNKNOWN +DEF +M_INITIAL +0 +PARAMETER_UNKNOWN +DEF +M +0 +PARAMETER_UNKNOWN +DEF +N +1 +PARAMETER_UNKNOWN +DEF +M2 +1 +PARAMETER_UNKNOWN +DEF +N2 +1 +PARAMETER_UNKNOWN +DEF +SS +1 +PARAMETER_UNKNOWN +DEF +C0_HIGH +0 +PARAMETER_UNKNOWN +DEF +C1_HIGH +0 +PARAMETER_UNKNOWN +DEF +C2_HIGH +0 +PARAMETER_UNKNOWN +DEF +C3_HIGH +0 +PARAMETER_UNKNOWN +DEF +C4_HIGH +0 +PARAMETER_UNKNOWN +DEF +C5_HIGH +0 +PARAMETER_UNKNOWN +DEF +C6_HIGH +0 +PARAMETER_UNKNOWN +DEF +C7_HIGH +0 +PARAMETER_UNKNOWN +DEF +C8_HIGH +0 +PARAMETER_UNKNOWN +DEF +C9_HIGH +0 +PARAMETER_UNKNOWN +DEF +C0_LOW +0 +PARAMETER_UNKNOWN +DEF +C1_LOW +0 +PARAMETER_UNKNOWN +DEF +C2_LOW +0 +PARAMETER_UNKNOWN +DEF +C3_LOW +0 +PARAMETER_UNKNOWN +DEF +C4_LOW +0 +PARAMETER_UNKNOWN +DEF +C5_LOW +0 +PARAMETER_UNKNOWN +DEF +C6_LOW +0 +PARAMETER_UNKNOWN +DEF +C7_LOW +0 +PARAMETER_UNKNOWN +DEF +C8_LOW +0 +PARAMETER_UNKNOWN +DEF +C9_LOW +0 +PARAMETER_UNKNOWN +DEF +C0_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C1_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C2_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C3_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C4_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C5_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C6_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C7_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C8_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C9_INITIAL +0 +PARAMETER_UNKNOWN +DEF +C0_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C1_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C2_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C3_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C4_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C5_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C6_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C7_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C8_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C9_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +C0_PH +0 +PARAMETER_UNKNOWN +DEF +C1_PH +0 +PARAMETER_UNKNOWN +DEF +C2_PH +0 +PARAMETER_UNKNOWN +DEF +C3_PH +0 +PARAMETER_UNKNOWN +DEF +C4_PH +0 +PARAMETER_UNKNOWN +DEF +C5_PH +0 +PARAMETER_UNKNOWN +DEF +C6_PH +0 +PARAMETER_UNKNOWN +DEF +C7_PH +0 +PARAMETER_UNKNOWN +DEF +C8_PH +0 +PARAMETER_UNKNOWN +DEF +C9_PH +0 +PARAMETER_UNKNOWN +DEF +L0_HIGH +1 +PARAMETER_UNKNOWN +DEF +L1_HIGH +1 +PARAMETER_UNKNOWN +DEF +G0_HIGH +1 +PARAMETER_UNKNOWN +DEF +G1_HIGH +1 +PARAMETER_UNKNOWN +DEF +G2_HIGH +1 +PARAMETER_UNKNOWN +DEF +G3_HIGH +1 +PARAMETER_UNKNOWN +DEF +E0_HIGH +1 +PARAMETER_UNKNOWN +DEF +E1_HIGH +1 +PARAMETER_UNKNOWN +DEF +E2_HIGH +1 +PARAMETER_UNKNOWN +DEF +E3_HIGH +1 +PARAMETER_UNKNOWN +DEF +L0_LOW +1 +PARAMETER_UNKNOWN +DEF +L1_LOW +1 +PARAMETER_UNKNOWN +DEF +G0_LOW +1 +PARAMETER_UNKNOWN +DEF +G1_LOW +1 +PARAMETER_UNKNOWN +DEF +G2_LOW +1 +PARAMETER_UNKNOWN +DEF +G3_LOW +1 +PARAMETER_UNKNOWN +DEF +E0_LOW +1 +PARAMETER_UNKNOWN +DEF +E1_LOW +1 +PARAMETER_UNKNOWN +DEF +E2_LOW +1 +PARAMETER_UNKNOWN +DEF +E3_LOW +1 +PARAMETER_UNKNOWN +DEF +L0_INITIAL +1 +PARAMETER_UNKNOWN +DEF +L1_INITIAL +1 +PARAMETER_UNKNOWN +DEF +G0_INITIAL +1 +PARAMETER_UNKNOWN +DEF +G1_INITIAL +1 +PARAMETER_UNKNOWN +DEF +G2_INITIAL +1 +PARAMETER_UNKNOWN +DEF +G3_INITIAL +1 +PARAMETER_UNKNOWN +DEF +E0_INITIAL +1 +PARAMETER_UNKNOWN +DEF +E1_INITIAL +1 +PARAMETER_UNKNOWN +DEF +E2_INITIAL +1 +PARAMETER_UNKNOWN +DEF +E3_INITIAL +1 +PARAMETER_UNKNOWN +DEF +L0_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +L1_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +G0_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +G1_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +G2_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +G3_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +E0_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +E1_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +E2_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +E3_MODE +BYPASS +PARAMETER_UNKNOWN +DEF +L0_PH +0 +PARAMETER_UNKNOWN +DEF +L1_PH +0 +PARAMETER_UNKNOWN +DEF +G0_PH +0 +PARAMETER_UNKNOWN +DEF +G1_PH +0 +PARAMETER_UNKNOWN +DEF +G2_PH +0 +PARAMETER_UNKNOWN +DEF +G3_PH +0 +PARAMETER_UNKNOWN +DEF +E0_PH +0 +PARAMETER_UNKNOWN +DEF +E1_PH +0 +PARAMETER_UNKNOWN +DEF +E2_PH +0 +PARAMETER_UNKNOWN +DEF +E3_PH +0 +PARAMETER_UNKNOWN +DEF +M_PH +0 +PARAMETER_UNKNOWN +DEF +C1_USE_CASC_IN +OFF +PARAMETER_UNKNOWN +DEF +C2_USE_CASC_IN +OFF +PARAMETER_UNKNOWN +DEF +C3_USE_CASC_IN +OFF +PARAMETER_UNKNOWN +DEF +C4_USE_CASC_IN +OFF +PARAMETER_UNKNOWN +DEF +C5_USE_CASC_IN +OFF +PARAMETER_UNKNOWN +DEF +C6_USE_CASC_IN +OFF +PARAMETER_UNKNOWN +DEF +C7_USE_CASC_IN +OFF +PARAMETER_UNKNOWN +DEF +C8_USE_CASC_IN +OFF +PARAMETER_UNKNOWN +DEF +C9_USE_CASC_IN +OFF +PARAMETER_UNKNOWN +DEF +CLK0_COUNTER +G0 +PARAMETER_UNKNOWN +DEF +CLK1_COUNTER +G0 +PARAMETER_UNKNOWN +DEF +CLK2_COUNTER +G0 +PARAMETER_UNKNOWN +DEF +CLK3_COUNTER +G0 +PARAMETER_UNKNOWN +DEF +CLK4_COUNTER +G0 +PARAMETER_UNKNOWN +DEF +CLK5_COUNTER +G0 +PARAMETER_UNKNOWN +DEF +CLK6_COUNTER +E0 +PARAMETER_UNKNOWN +DEF +CLK7_COUNTER +E1 +PARAMETER_UNKNOWN +DEF +CLK8_COUNTER +E2 +PARAMETER_UNKNOWN +DEF +CLK9_COUNTER +E3 +PARAMETER_UNKNOWN +DEF +L0_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +L1_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +G0_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +G1_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +G2_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +G3_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +E0_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +E1_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +E2_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +E3_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +M_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +N_TIME_DELAY +0 +PARAMETER_UNKNOWN +DEF +EXTCLK3_COUNTER +E3 +PARAMETER_UNKNOWN +DEF +EXTCLK2_COUNTER +E2 +PARAMETER_UNKNOWN +DEF +EXTCLK1_COUNTER +E1 +PARAMETER_UNKNOWN +DEF +EXTCLK0_COUNTER +E0 +PARAMETER_UNKNOWN +DEF +ENABLE0_COUNTER +L0 +PARAMETER_UNKNOWN +DEF +ENABLE1_COUNTER +L0 +PARAMETER_UNKNOWN +DEF +CHARGE_PUMP_CURRENT +2 +PARAMETER_UNKNOWN +DEF +LOOP_FILTER_R + 1.000000 +PARAMETER_UNKNOWN +DEF +LOOP_FILTER_C +5 +PARAMETER_UNKNOWN +DEF +CHARGE_PUMP_CURRENT_BITS +9999 +PARAMETER_UNKNOWN +DEF +LOOP_FILTER_R_BITS +9999 +PARAMETER_UNKNOWN +DEF +LOOP_FILTER_C_BITS +9999 +PARAMETER_UNKNOWN +DEF +VCO_POST_SCALE +0 +PARAMETER_UNKNOWN +DEF +CLK2_OUTPUT_FREQUENCY +0 +PARAMETER_UNKNOWN +DEF +CLK1_OUTPUT_FREQUENCY +0 +PARAMETER_UNKNOWN +DEF +CLK0_OUTPUT_FREQUENCY +0 +PARAMETER_UNKNOWN +DEF +INTENDED_DEVICE_FAMILY +Stratix +PARAMETER_UNKNOWN +USR +PORT_CLKENA0 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLKENA1 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLKENA2 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLKENA3 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLKENA4 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLKENA5 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_EXTCLKENA0 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_EXTCLKENA1 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_EXTCLKENA2 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_EXTCLKENA3 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_EXTCLK0 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_EXTCLK1 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_EXTCLK2 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_EXTCLK3 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLKBAD0 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLKBAD1 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLK0 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLK1 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLK2 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLK3 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLK4 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLK5 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLK6 +PORT_UNUSED +PARAMETER_UNKNOWN +DEF +PORT_CLK7 +PORT_UNUSED +PARAMETER_UNKNOWN +DEF +PORT_CLK8 +PORT_UNUSED +PARAMETER_UNKNOWN +DEF +PORT_CLK9 +PORT_UNUSED +PARAMETER_UNKNOWN +DEF +PORT_SCANDATA +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_SCANDATAOUT +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_SCANDONE +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_SCLKOUT1 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_SCLKOUT0 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_ACTIVECLOCK +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLKLOSS +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_INCLK1 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_INCLK0 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_FBIN +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_PLLENA +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CLKSWITCH +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_ARESET +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_PFDENA +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_SCANCLK +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_SCANACLR +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_SCANREAD +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_SCANWRITE +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_ENABLE0 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_ENABLE1 +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_LOCKED +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_CONFIGUPDATE +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_FBOUT +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_PHASEDONE +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_PHASESTEP +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_PHASEUPDOWN +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_SCANCLKENA +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_PHASECOUNTERSELECT +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_VCOOVERRANGE +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +PORT_VCOUNDERRANGE +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +M_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C0_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C1_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C2_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C3_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C4_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C5_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C6_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C7_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C8_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +C9_TEST_SOURCE +5 +PARAMETER_UNKNOWN +DEF +CBXI_PARAMETER +NOTHING +PARAMETER_UNKNOWN +DEF +VCO_FREQUENCY_CONTROL +AUTO +PARAMETER_UNKNOWN +DEF +VCO_PHASE_SHIFT_STEP +0 +PARAMETER_UNKNOWN +DEF +WIDTH_CLOCK +6 +PARAMETER_UNKNOWN +DEF +WIDTH_PHASECOUNTERSELECT +4 +PARAMETER_UNKNOWN +DEF +USING_FBMIMICBIDIR_PORT +OFF +PARAMETER_UNKNOWN +DEF +DEVICE_FAMILY +Stratix +PARAMETER_UNKNOWN +USR +SCAN_CHAIN_MIF_FILE +UNUSED +PARAMETER_UNKNOWN +DEF +SIM_GATE_LOCK_DEVICE_BEHAVIOR +OFF +PARAMETER_UNKNOWN +DEF +AUTO_CARRY_CHAINS +ON +AUTO_CARRY +USR +IGNORE_CARRY_BUFFERS +OFF +IGNORE_CARRY +USR +AUTO_CASCADE_CHAINS +ON +AUTO_CASCADE +USR +IGNORE_CASCADE_BUFFERS +OFF +IGNORE_CASCADE +USR +} +# used_port { +inclk0 +-1 +3 +clk0 +-1 +3 +inclk1 +-1 +1 +extclkena3 +-1 +1 +extclkena2 +-1 +1 +extclkena1 +-1 +1 +extclkena0 +-1 +1 +clkena5 +-1 +1 +clkena4 +-1 +1 +clkena3 +-1 +1 +clkena2 +-1 +1 +clkena1 +-1 +1 +areset +-1 +1 +pllena +-1 +2 +clkena0 +-1 +2 +} +# include_file { +|opt|quartus|quartus|libraries|megafunctions|aglobal90.inc +99832fdf63412df51d7531202d74e75 +|opt|quartus|quartus|libraries|megafunctions|stratixii_pll.inc +6d1985e16ab5f59a1fd6b0ae20978a4e +|opt|quartus|quartus|libraries|megafunctions|cycloneii_pll.inc +39a0d9d1237d1db39c848c3f9faffc +|opt|quartus|quartus|libraries|megafunctions|stratix_pll.inc +5f8211898149ceae8264a0ea5036254f +} +# hierarchies { +vpll:inst1|altpll:altpll_component +} +# lmf +|opt|quartus|quartus|lmf|synplcty.lmf +3057712873b497a38b70a3917f30cc38 +# macro_sequence + +# end +# complete + \ No newline at end of file diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.lpc.html b/bsp3/Designflow/ppr/download/db/vga_pll.lpc.html new file mode 100644 index 0000000..ebfddf5 --- /dev/null +++ b/bsp3/Designflow/ppr/download/db/vga_pll.lpc.html @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
inst11000100000000
inst|vga_control_unit14000300000000
inst|vga_driver_unit40006200000000
inst20008900000000
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zcmd;QU|?9w&B%}dgoZ$NSZYymW`3T6rJjL;Q)y;Sih`lBk%EDdzLBZEk%57wLa>*D zTWL;?0#u;@P!9;?LnsC#C_M{GS1|ti|NnnIn+k~k|9=IeP;xQ@lbgabwnqu+=PSgo bC-|4|4;FN@c38y2qm?kJv60h@8LSilJ$@#@ literal 0 HcmV?d00001 diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.syn_hier_info b/bsp3/Designflow/ppr/download/db/vga_pll.syn_hier_info new file mode 100644 index 0000000..e69de29 diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.tan.qmsg b/bsp3/Designflow/ppr/download/db/vga_pll.tan.qmsg new file mode 100644 index 0000000..b9665a2 --- /dev/null +++ b/bsp3/Designflow/ppr/download/db/vga_pll.tan.qmsg @@ -0,0 +1,15 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:13:27 2009 " "Info: Processing started: Thu Oct 29 17:13:27 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" { } { } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0 -1} +{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 register vga:inst\|vga_control:vga_control_unit\|b 29.381 ns " "Info: Slack time is 29.381 ns for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9\" and destination register \"vga:inst\|vga_control:vga_control_unit\|b\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "135.21 MHz 7.396 ns " "Info: Fmax is 135.21 MHz (period= 7.396 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.604 ns + Largest register register " "Info: + Largest register to register requirement is 36.604 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "36.777 ns + " "Info: + Setup relationship between source and destination is 36.777 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 35.747 ns " "Info: + Latch edge is 35.747 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.013 ns + Largest " "Info: + Largest clock skew is 0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.053 ns + Shortest register " "Info: + Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.053 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.493 ns) + CELL(0.560 ns) 2.053 ns vga:inst\|vga_control:vga_control_unit\|b 2 REG LC_X78_Y32_N4 3 " "Info: 2: + IC(1.493 ns) + CELL(0.560 ns) = 2.053 ns; Loc. = LC_X78_Y32_N4; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.28 % ) " "Info: Total cell delay = 0.560 ns ( 27.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.493 ns ( 72.72 % ) " "Info: Total interconnect delay = 1.493 ns ( 72.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.040 ns - Longest register " "Info: - Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.480 ns) + CELL(0.560 ns) 2.040 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 2 REG LC_X78_Y33_N0 4 " "Info: 2: + IC(1.480 ns) + CELL(0.560 ns) = 2.040 ns; Loc. = LC_X78_Y33_N0; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.45 % ) " "Info: Total cell delay = 0.560 ns ( 27.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.480 ns ( 72.55 % ) " "Info: Total interconnect delay = 1.480 ns ( 72.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.223 ns - Longest register register " "Info: - Longest register to register delay is 7.223 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 1 REG LC_X78_Y33_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X78_Y33_N0; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.360 ns) + CELL(0.087 ns) 2.447 ns vga:inst\|vga_control:vga_control_unit\|r_next_i_o7 2 COMB LC_X56_Y45_N5 3 " "Info: 2: + IC(2.360 ns) + CELL(0.087 ns) = 2.447 ns; Loc. = LC_X56_Y45_N5; Fanout = 3; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|r_next_i_o7'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.447 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3207 19 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.773 ns) + CELL(0.332 ns) 5.552 ns vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0 3 COMB LC_X76_Y33_N4 1 " "Info: 3: + IC(2.773 ns) + CELL(0.332 ns) = 5.552 ns; Loc. = LC_X76_Y33_N4; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.105 ns" { vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3205 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.307 ns) + CELL(0.364 ns) 7.223 ns vga:inst\|vga_control:vga_control_unit\|b 4 REG LC_X78_Y32_N4 3 " "Info: 4: + IC(1.307 ns) + CELL(0.364 ns) = 7.223 ns; Loc. = LC_X78_Y32_N4; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.671 ns" { vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.783 ns ( 10.84 % ) " "Info: Total cell delay = 0.783 ns ( 10.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.440 ns ( 89.16 % ) " "Info: Total interconnect delay = 6.440 ns ( 89.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} vga:inst|vga_control:vga_control_unit|r_next_i_o7 {} vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 2.360ns 2.773ns 1.307ns } { 0.000ns 0.087ns 0.332ns 0.364ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} vga:inst|vga_control:vga_control_unit|r_next_i_o7 {} vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 2.360ns 2.773ns 1.307ns } { 0.000ns 0.087ns 0.332ns 0.364ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Info" "ITAN_NO_REG2REG_EXIST" "board_clk " "Info: No valid register-to-register data paths exist for clock \"board_clk\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 register vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 737 ps " "Info: Minimum slack time is 737 ps for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9\" and destination register \"vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.661 ns + Shortest register register " "Info: + Shortest register to register delay is 0.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 1 REG LC_X35_Y33_N9 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.235 ns) 0.661 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 2 REG LC_X35_Y33_N9 9 " "Info: 2: + IC(0.426 ns) + CELL(0.235 ns) = 0.661 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.235 ns ( 35.55 % ) " "Info: Total cell delay = 0.235 ns ( 35.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.426 ns ( 64.45 % ) " "Info: Total interconnect delay = 0.426 ns ( 64.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 0.426ns } { 0.000ns 0.235ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.076 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.076 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.030 ns " "Info: + Latch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.054 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.560 ns) 2.054 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 2 REG LC_X35_Y33_N9 9 " "Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.26 % ) " "Info: Total cell delay = 0.560 ns ( 27.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns ( 72.74 % ) " "Info: Total interconnect delay = 1.494 ns ( 72.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.054 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.560 ns) 2.054 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 2 REG LC_X35_Y33_N9 9 " "Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.26 % ) " "Info: Total cell delay = 0.560 ns ( 27.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns ( 72.74 % ) " "Info: Total interconnect delay = 1.494 ns ( 72.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 0.426ns } { 0.000ns 0.235ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Info" "ITDB_TSU_RESULT" "vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig reset board_clk 11.030 ns register " "Info: tsu for register \"vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig\" (data pin = \"reset\", clock pin = \"board_clk\") is 11.030 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.049 ns + Longest pin register " "Info: + Longest pin to register delay is 12.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 96 528 696 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.711 ns) + CELL(0.459 ns) 7.311 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X36_Y33_N7 32 " "Info: 2: + IC(5.711 ns) + CELL(0.459 ns) = 7.311 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.170 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.863 ns) + CELL(0.332 ns) 9.506 ns vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4 3 COMB LC_X34_Y34_N6 1 " "Info: 3: + IC(1.863 ns) + CELL(0.332 ns) = 9.506 ns; Loc. = LC_X34_Y34_N6; Fanout = 1; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.195 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 248 36 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(0.726 ns) 12.049 ns vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig 4 REG LC_X52_Y35_N2 2 " "Info: 4: + IC(1.817 ns) + CELL(0.726 ns) = 12.049 ns; Loc. = LC_X52_Y35_N2; Fanout = 2; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.543 ns" { vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.658 ns ( 22.06 % ) " "Info: Total cell delay = 2.658 ns ( 22.06 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.391 ns ( 77.94 % ) " "Info: Total interconnect delay = 9.391 ns ( 77.94 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "12.049 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "12.049 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig {} } { 0.000ns 0.000ns 5.711ns 1.863ns 1.817ns } { 0.000ns 1.141ns 0.459ns 0.332ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns - " "Info: - Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 80 240 408 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.059 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.499 ns) + CELL(0.560 ns) 2.059 ns vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig 2 REG LC_X52_Y35_N2 2 " "Info: 2: + IC(1.499 ns) + CELL(0.560 ns) = 2.059 ns; Loc. = LC_X52_Y35_N2; Fanout = 2; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.20 % ) " "Info: Total cell delay = 0.560 ns ( 27.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.499 ns ( 72.80 % ) " "Info: Total interconnect delay = 1.499 ns ( 72.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig {} } { 0.000ns 1.499ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "12.049 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "12.049 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig {} } { 0.000ns 0.000ns 5.711ns 1.863ns 1.817ns } { 0.000ns 1.141ns 0.459ns 0.332ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig {} } { 0.000ns 1.499ns } { 0.000ns 0.560ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TCO_RESULT" "board_clk seven_seg_pin\[7\] vga:inst\|dly_counter\[0\] 9.803 ns register " "Info: tco from clock \"board_clk\" to destination pin \"seven_seg_pin\[7\]\" through register \"vga:inst\|dly_counter\[0\]\" is 9.803 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns + " "Info: + Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 80 240 408 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.054 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.560 ns) 2.054 ns vga:inst\|dly_counter\[0\] 2 REG LC_X36_Y33_N3 10 " "Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X36_Y33_N3; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.26 % ) " "Info: Total cell delay = 0.560 ns ( 27.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns ( 72.74 % ) " "Info: Total interconnect delay = 1.494 ns ( 72.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.603 ns + Longest register pin " "Info: + Longest register to pin delay is 8.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|dly_counter\[0\] 1 REG LC_X36_Y33_N3 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y33_N3; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.213 ns) 0.713 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X36_Y33_N7 32 " "Info: 2: + IC(0.500 ns) + CELL(0.213 ns) = 0.713 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.713 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.699 ns) + CELL(4.191 ns) 8.603 ns seven_seg_pin\[7\] 3 PIN PIN_Y11 0 " "Info: 3: + IC(3.699 ns) + CELL(4.191 ns) = 8.603 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin\[7\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.890 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 240 912 1132 256 "seven_seg_pin\[13..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.404 ns ( 51.19 % ) " "Info: Total cell delay = 4.404 ns ( 51.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.199 ns ( 48.81 % ) " "Info: Total interconnect delay = 4.199 ns ( 48.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "8.603 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "8.603 ns" { vga:inst|dly_counter[0] {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 0.500ns 3.699ns } { 0.000ns 0.213ns 4.191ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "8.603 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "8.603 ns" { vga:inst|dly_counter[0] {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 0.500ns 3.699ns } { 0.000ns 0.213ns 4.191ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TPD_RESULT" "reset seven_seg_pin\[7\] 15.201 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"seven_seg_pin\[7\]\" is 15.201 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 96 528 696 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.711 ns) + CELL(0.459 ns) 7.311 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X36_Y33_N7 32 " "Info: 2: + IC(5.711 ns) + CELL(0.459 ns) = 7.311 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.170 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.699 ns) + CELL(4.191 ns) 15.201 ns seven_seg_pin\[7\] 3 PIN PIN_Y11 0 " "Info: 3: + IC(3.699 ns) + CELL(4.191 ns) = 15.201 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin\[7\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.890 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 240 912 1132 256 "seven_seg_pin\[13..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.791 ns ( 38.10 % ) " "Info: Total cell delay = 5.791 ns ( 38.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.410 ns ( 61.90 % ) " "Info: Total interconnect delay = 9.410 ns ( 61.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "15.201 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "15.201 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 0.000ns 5.711ns 3.699ns } { 0.000ns 1.141ns 0.459ns 4.191ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_TH_RESULT" "vga:inst\|vga_driver:vga_driver_unit\|v_sync reset board_clk -5.484 ns register " "Info: th for register \"vga:inst\|vga_driver:vga_driver_unit\|v_sync\" (data pin = \"reset\", clock pin = \"board_clk\") is -5.484 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns + " "Info: + Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 80 240 408 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.040 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.480 ns) + CELL(0.560 ns) 2.040 ns vga:inst\|vga_driver:vga_driver_unit\|v_sync 2 REG LC_X34_Y34_N7 3 " "Info: 2: + IC(1.480 ns) + CELL(0.560 ns) = 2.040 ns; Loc. = LC_X34_Y34_N7; Fanout = 3; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|v_sync'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 152 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.45 % ) " "Info: Total cell delay = 0.560 ns ( 27.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.480 ns ( 72.55 % ) " "Info: Total interconnect delay = 1.480 ns ( 72.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|v_sync {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 152 16 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.594 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 96 528 696 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.964 ns) + CELL(0.489 ns) 6.594 ns vga:inst\|vga_driver:vga_driver_unit\|v_sync 2 REG LC_X34_Y34_N7 3 " "Info: 2: + IC(4.964 ns) + CELL(0.489 ns) = 6.594 ns; Loc. = LC_X34_Y34_N7; Fanout = 3; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|v_sync'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.453 ns" { reset vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 152 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.630 ns ( 24.72 % ) " "Info: Total cell delay = 1.630 ns ( 24.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.964 ns ( 75.28 % ) " "Info: Total interconnect delay = 4.964 ns ( 75.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.594 ns" { reset vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.594 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|v_sync {} } { 0.000ns 0.000ns 4.964ns } { 0.000ns 1.141ns 0.489ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|v_sync {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.594 ns" { reset vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.594 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|v_sync {} } { 0.000ns 0.000ns 4.964ns } { 0.000ns 1.141ns 0.489ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Peak virtual memory: 141 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 17:13:27 2009 " "Info: Processing ended: Thu Oct 29 17:13:27 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.tis_db_list.ddb b/bsp3/Designflow/ppr/download/db/vga_pll.tis_db_list.ddb new file mode 100644 index 0000000000000000000000000000000000000000..7a45114581bb8ff3e53543d803e264030a96c865 GIT binary patch literal 178 zcmd;QU|?9w&B%}dgoZ$NSZYymW`3T6rJjL;Q)y;Sih`lBk%EDdzLBZEk%57wLa>*D zTWL;?0#utZ?_Pd=!4HP(3lh#h5D4Etp~BzZyuNmu?tKR>Nr{RBD$LBnQ`o@T0n5=c AP5=M^ literal 0 HcmV?d00001 diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.tmw_info b/bsp3/Designflow/ppr/download/db/vga_pll.tmw_info new file mode 100644 index 0000000..dcf7367 --- /dev/null +++ b/bsp3/Designflow/ppr/download/db/vga_pll.tmw_info @@ -0,0 +1,7 @@ +start_full_compilation:s:00:01:06 +start_analysis_synthesis:s:00:00:07-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:32-start_full_compilation +start_assembler:s:00:00:20-start_full_compilation +start_timing_analyzer:s:00:00:03-start_full_compilation +start_eda_netlist_writer:s:00:00:04-start_full_compilation diff --git a/bsp3/Designflow/ppr/download/db/vga_pll_global_asgn_op.abo b/bsp3/Designflow/ppr/download/db/vga_pll_global_asgn_op.abo new file mode 100644 index 0000000..4b50faf --- /dev/null +++ b/bsp3/Designflow/ppr/download/db/vga_pll_global_asgn_op.abo @@ -0,0 +1,12368 @@ +Version: + 9.0 Build 132 02/25/2009 SJ Full Version + +Chip Device Options: + Device Name: EP1S25F672C6 + Device JTAG code: ffffffff + Programming_mode: Passive Serial + NWS_NRS_NCS: UNRESERVED + RDYNBUSY: UNRESERVED + DATA 7 to 1: UNRESERVED + nCEO: UNRESERVED + UNUSED PINS: RESERVED_GND + Default IO Standard:: 3.3-V LVTTL + User Start-up Clock: 0 + Auto Restart on Error: 1 + Release Clears Before Tristates: 0 + Device Clear: 0 + Test And Scan: 0 + Device OE: 0 + Enable Lock Output: 0 + Enable Init Done: 0 + Enable JTAG BST: 0 + Enable Vref A: 0 + Enable Vref B: 0 + + + +**************************** +******Individual Atoms****** +**************************** + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|h_sync_Z -- UNIQUE + Atom Hier Name: + Atom Id: 178 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|h_sync LIT INDEX 0 FANOUTS 3 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff7f + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|v_sync_Z -- UNIQUE + Atom Hier Name: + Atom Id: 179 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|v_sync LIT INDEX 0 FANOUTS 3 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff7f + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 180 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 181 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 182 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 FANOUTS 5 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|d_set_vsync_counter_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 183 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|r_Z -- UNIQUE + Atom Hier Name: + Atom Id: 184 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_control:vga_control_unit|b_next_i_o3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_control:vga_control_unit|N_4_i_0_g0_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 1b00 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|g_Z -- UNIQUE + Atom Hier Name: + Atom Id: 185 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_control:vga_control_unit|r_next_i_o7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_control:vga_control_unit|N_23_i_0_g0_a LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_control:vga_control_unit|g LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0400 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|b_Z -- UNIQUE + Atom Hier Name: + Atom Id: 186 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_control:vga_control_unit|b_next_i_o3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_control:vga_control_unit|b_next_i_a7_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_control:vga_control_unit|b LIT INDEX 0 FANOUTS 3 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0700 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|h_enable_sig_Z -- UNIQUE + Atom Hier Name: + Atom Id: 187 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 FANOUTS 2 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|v_enable_sig_Z -- UNIQUE + Atom Hier Name: + Atom Id: 188 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 FANOUTS 2 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vpll:inst1|altpll:altpll_component|pll -- UNIQUE + Atom Hier Name: + Atom Id: 189 + Atom Type: stratix_pll (WYSIWYG) + +User mode PLL + INPUTS (Driven By): + 0: NO ITERM + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [INCLK] board_clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: [INCLK] DISCONNECTED + 11: [CLKENA] DISCONNECTED + 12: [CLKENA] DISCONNECTED + 13: [CLKENA] DISCONNECTED + 14: [CLKENA] DISCONNECTED + 15: [CLKENA] DISCONNECTED + 16: [CLKENA] DISCONNECTED + 17: [EXTCLKENA] DISCONNECTED + 18: [EXTCLKENA] DISCONNECTED + 19: [EXTCLKENA] DISCONNECTED + 20: [EXTCLKENA] DISCONNECTED + OUTPUTS (Int. Connections): + 0: [ACTIVECLOCK] vpll:inst1|altpll:altpll_component|pll~ACTIVECLOCK LIT INDEX 0 FANOUTS 0 + 1: [CLKLOSS] vpll:inst1|altpll:altpll_component|pll~GLOCKED LIT INDEX 0 FANOUTS 0 + 2: [LOCKED] vpll:inst1|altpll:altpll_component|pll~LOCKED LIT INDEX 0 FANOUTS 0 + 3: [SCANDATAOUT] vpll:inst1|altpll:altpll_component|pll~SCANDATAOUT LIT INDEX 0 FANOUTS 0 + 4: [ENABLE0] vpll:inst1|altpll:altpll_component|pll~ENAOUT0 LIT INDEX 0 FANOUTS 0 + 5: [ENABLE1] vpll:inst1|altpll:altpll_component|pll~ENAOUT1 LIT INDEX 0 FANOUTS 0 + 6: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 FANOUTS 63 + 7: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK1 LIT INDEX 1 FANOUTS 0 + 8: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK2 LIT INDEX 2 FANOUTS 0 + 9: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK3 LIT INDEX 3 FANOUTS 0 + 10: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK4 LIT INDEX 4 FANOUTS 0 + 11: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK5 LIT INDEX 5 FANOUTS 0 + 12: [EXTCLK] vpll:inst1|altpll:altpll_component|pll~EXTCLK0 LIT INDEX 0 FANOUTS 0 + 13: [EXTCLK] vpll:inst1|altpll:altpll_component|pll~EXTCLK1 LIT INDEX 1 FANOUTS 0 + 14: [EXTCLK] vpll:inst1|altpll:altpll_component|pll~EXTCLK2 LIT INDEX 2 FANOUTS 0 + 15: [EXTCLK] vpll:inst1|altpll:altpll_component|pll~EXTCLK3 LIT INDEX 3 FANOUTS 0 + 16: [CLKBAD] vpll:inst1|altpll:altpll_component|pll~CLKBAD0 LIT INDEX 0 FANOUTS 0 + 17: [CLKBAD] vpll:inst1|altpll:altpll_component|pll~CLKBAD1 LIT INDEX 1 FANOUTS 0 + + PARAMETER LIST: + operation_mode = normal + pll_type = auto + qualify_conf_done = off + valid_lock_multiplier = 1 + invalid_lock_multiplier = 5 + scan_chain_mif_file = + compensate_clock = clk0 + feedback_source = + inclk0_input_frequency = 30003 + inclk1_input_frequency = 30003 + pfd_min = 2380 + pfd_max = 333333 + vco_min = 1250 + vco_max = 3334 + vco_center = 1666 + pll_compensation_delay = 3806 + input_comp_delay_chain_bits = 0 + feedback_comp_delay_chain_bits = 0 + common_rx_tx = on + skip_vco = off + rx_outclock_resource = auto + primary_clock = inclk0 + switch_over_on_lossclk = off + switch_over_on_gated_lock = off + enable_switch_over_counter = off + gate_lock_signal = no + scan_chain = + gate_lock_counter = 0 + switch_over_counter = 1 + ======= Real External and Internal Parameters ======= = + bandwidth_type = auto + bandwidth = 8043251 + spread_frequency = 0 + down_spread = 0 % + clk0_multiply_by = 53 + clk1_multiply_by = 1 + clk2_multiply_by = 1 + clk3_multiply_by = 1 + clk4_multiply_by = 1 + clk5_multiply_by = 1 + extclk0_multiply_by = 1 + extclk1_multiply_by = 1 + extclk2_multiply_by = 1 + extclk3_multiply_by = 1 + clk0_divide_by = 65 + clk1_divide_by = 1 + clk2_divide_by = 1 + clk3_divide_by = 1 + clk4_divide_by = 1 + clk5_divide_by = 1 + extclk0_divide_by = 1 + extclk1_divide_by = 1 + extclk2_divide_by = 1 + extclk3_divide_by = 1 + clk0_phase_shift = 0 + clk1_phase_shift = 0 + clk2_phase_shift = 0 + clk3_phase_shift = 0 + clk4_phase_shift = 0 + clk5_phase_shift = 0 + extclk0_phase_shift = 0 + extclk1_phase_shift = 0 + extclk2_phase_shift = 0 + extclk3_phase_shift = 0 + clk0_time_delay = 0 + clk1_time_delay = 0 + clk2_time_delay = 0 + clk3_time_delay = 0 + clk4_time_delay = 0 + clk5_time_delay = 0 + extclk0_time_delay = 0 + extclk1_time_delay = 0 + extclk2_time_delay = 0 + extclk3_time_delay = 0 + clk0_duty_cycle = 50 + clk1_duty_cycle = 50 + clk2_duty_cycle = 50 + clk3_duty_cycle = 50 + clk4_duty_cycle = 50 + clk5_duty_cycle = 50 + extclk0_duty_cycle = 50 + extclk1_duty_cycle = 50 + extclk2_duty_cycle = 50 + extclk3_duty_cycle = 50 + clk0_use_even_counter_mode = off + clk1_use_even_counter_mode = off + clk2_use_even_counter_mode = off + clk3_use_even_counter_mode = off + clk4_use_even_counter_mode = off + clk5_use_even_counter_mode = off + extclk0_use_even_counter_mode = off + extclk1_use_even_counter_mode = off + extclk2_use_even_counter_mode = off + extclk3_use_even_counter_mode = off + clk0_use_even_counter_value = off + clk1_use_even_counter_value = off + clk2_use_even_counter_value = off + clk3_use_even_counter_value = off + clk4_use_even_counter_value = off + clk5_use_even_counter_value = off + extclk0_use_even_counter_value = off + extclk1_use_even_counter_value = off + extclk2_use_even_counter_value = off + extclk3_use_even_counter_value = off + m = 106 + n = 5 + m2 = 1 + n2 = 1 + ss = 0 + charge_pump_current = 50 + loop_filter_c = 10 + loop_filter_r = 1.021000 + enable0_counter = + enable1_counter = + clk0_counter = g0 + clk1_counter = + clk2_counter = + clk3_counter = + clk4_counter = + clk5_counter = + extclk0_counter = + extclk1_counter = + extclk2_counter = + extclk3_counter = + l0_is_used = no + l1_is_used = no + g0_is_used = yes + g1_is_used = no + g2_is_used = no + g3_is_used = no + e0_is_used = no + e1_is_used = no + e2_is_used = no + e3_is_used = no + l0_mode = odd + l1_mode = bypass + g0_mode = even + g1_mode = bypass + g2_mode = bypass + g3_mode = bypass + e0_mode = bypass + e1_mode = bypass + e2_mode = bypass + e3_mode = bypass + l0_high = 10 + l1_high = 0 + g0_high = 13 + g1_high = 0 + g2_high = 0 + g3_high = 0 + e0_high = 0 + e1_high = 0 + e2_high = 0 + e3_high = 0 + l0_low = 9 + l1_low = 0 + g0_low = 13 + g1_low = 0 + g2_low = 0 + g3_low = 0 + e0_low = 0 + e1_low = 0 + e2_low = 0 + e3_low = 0 + m_initial = 1 + l0_initial = 1 + l1_initial = 1 + g0_initial = 1 + g1_initial = 1 + g2_initial = 1 + g3_initial = 1 + e0_initial = 1 + e1_initial = 1 + e2_initial = 1 + e3_initial = 1 + m_ph = 0 + l0_ph = 0 + l1_ph = 0 + g0_ph = 0 + g1_ph = 0 + g2_ph = 0 + g3_ph = 0 + e0_ph = 0 + e1_ph = 0 + e2_ph = 0 + e3_ph = 0 + m_time_delay = 0 + n_time_delay = 0 + l0_time_delay = 0 + l1_time_delay = 0 + g0_time_delay = 0 + g1_time_delay = 0 + g2_time_delay = 0 + g3_time_delay = 0 + e0_time_delay = 0 + e1_time_delay = 0 + e2_time_delay = 0 + e3_time_delay = 0 + ======= User External and Internal Parameters ======= = + bandwidth_type = auto + bandwidth = 0 + spread_frequency = 0 + down_spread = 0 + clk0_multiply_by = 5435 + clk1_multiply_by = 1 + clk2_multiply_by = 1 + clk3_multiply_by = 1 + clk4_multiply_by = 1 + clk5_multiply_by = 1 + extclk0_multiply_by = 1 + extclk1_multiply_by = 1 + extclk2_multiply_by = 1 + extclk3_multiply_by = 1 + clk0_divide_by = 6666 + clk1_divide_by = 1 + clk2_divide_by = 1 + clk3_divide_by = 1 + clk4_divide_by = 1 + clk5_divide_by = 1 + extclk0_divide_by = 1 + extclk1_divide_by = 1 + extclk2_divide_by = 1 + extclk3_divide_by = 1 + clk0_phase_shift = 0 + clk1_phase_shift = 0 + clk2_phase_shift = 0 + clk3_phase_shift = 0 + clk4_phase_shift = 0 + clk5_phase_shift = 0 + extclk0_phase_shift = 0 + extclk1_phase_shift = 0 + extclk2_phase_shift = 0 + extclk3_phase_shift = 0 + clk0_time_delay = 0 + clk1_time_delay = 0 + clk2_time_delay = 0 + clk3_time_delay = 0 + clk4_time_delay = 0 + clk5_time_delay = 0 + extclk0_time_delay = 0 + extclk1_time_delay = 0 + extclk2_time_delay = 0 + extclk3_time_delay = 0 + clk0_duty_cycle = 50 + clk1_duty_cycle = 50 + clk2_duty_cycle = 50 + clk3_duty_cycle = 50 + clk4_duty_cycle = 50 + clk5_duty_cycle = 50 + extclk0_duty_cycle = 50 + extclk1_duty_cycle = 50 + extclk2_duty_cycle = 50 + extclk3_duty_cycle = 50 + clk0_use_even_counter_mode = off + clk1_use_even_counter_mode = off + clk2_use_even_counter_mode = off + clk3_use_even_counter_mode = off + clk4_use_even_counter_mode = off + clk5_use_even_counter_mode = off + extclk0_use_even_counter_mode = off + extclk1_use_even_counter_mode = off + extclk2_use_even_counter_mode = off + extclk3_use_even_counter_mode = off + clk0_use_even_counter_value = off + clk1_use_even_counter_value = off + clk2_use_even_counter_value = off + clk3_use_even_counter_value = off + clk4_use_even_counter_value = off + clk5_use_even_counter_value = off + extclk0_use_even_counter_value = off + extclk1_use_even_counter_value = off + extclk2_use_even_counter_value = off + extclk3_use_even_counter_value = off + m = 234 + n = 7 + m2 = 1 + n2 = 1 + ss = 0 + charge_pump_current = 0 + loop_filter_c = 0 + loop_filter_r = 0.000000 + enable0_counter = + enable1_counter = + clk0_counter = l0 + clk1_counter = + clk2_counter = + clk3_counter = + clk4_counter = + clk5_counter = + extclk0_counter = + extclk1_counter = + extclk2_counter = + extclk3_counter = + l0_is_used = yes + l1_is_used = no + g0_is_used = no + g1_is_used = no + g2_is_used = no + g3_is_used = no + e0_is_used = no + e1_is_used = no + e2_is_used = no + e3_is_used = no + l0_mode = odd + l1_mode = bypass + g0_mode = bypass + g1_mode = bypass + g2_mode = bypass + g3_mode = bypass + e0_mode = bypass + e1_mode = bypass + e2_mode = bypass + e3_mode = bypass + l0_high = 21 + l1_high = 0 + g0_high = 0 + g1_high = 0 + g2_high = 0 + g3_high = 0 + e0_high = 0 + e1_high = 0 + e2_high = 0 + e3_high = 0 + l0_low = 20 + l1_low = 0 + g0_low = 0 + g1_low = 0 + g2_low = 0 + g3_low = 0 + e0_low = 0 + e1_low = 0 + e2_low = 0 + e3_low = 0 + m_initial = 1 + l0_initial = 1 + l1_initial = 1 + g0_initial = 1 + g1_initial = 1 + g2_initial = 1 + g3_initial = 1 + e0_initial = 1 + e1_initial = 1 + e2_initial = 1 + e3_initial = 1 + m_ph = 0 + l0_ph = 0 + l1_ph = 0 + g0_ph = 0 + g1_ph = 0 + g2_ph = 0 + g3_ph = 0 + e0_ph = 0 + e1_ph = 0 + e2_ph = 0 + e3_ph = 0 + m_time_delay = 0 + n_time_delay = 0 + l0_time_delay = 0 + l1_time_delay = 0 + g0_time_delay = 0 + g1_time_delay = 0 + g2_time_delay = 0 + g3_time_delay = 0 + e0_time_delay = 0 + e1_time_delay = 0 + e2_time_delay = 0 + e3_time_delay = 0 + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 190 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 191 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 FANOUTS 10 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 192 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 FANOUTS 9 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 193 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 194 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 195 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 196 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 197 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 198 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 199 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7777 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 200 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 201 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[8] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 202 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 FANOUTS 7 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[7] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 203 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 FANOUTS 7 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[6] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 204 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[5] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 205 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 FANOUTS 7 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[4] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 206 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[3] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 207 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[2] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 208 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 209 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[0] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 55aa + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 210 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8888 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 211 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8888 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 212 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = aaaa + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 213 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 214 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 215 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff00 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 216 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 FANOUTS 3 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 217 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 218 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 219 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 220 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 221 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 222 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 223 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 224 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 225 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 FANOUTS 9 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 226 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[8] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 227 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[7] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 228 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[6] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 229 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[5] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 230 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[4] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 231 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[3] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 232 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[2] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 233 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 234 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 FANOUTS 9 REGED POS + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[0] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 6688 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 235 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 30ba + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 236 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 237 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = aaaa + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 238 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 2000 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 239 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 240 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 FANOUTS 32 + 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7f7f + output_mode = reg_and_comb + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|dly_counter_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 242 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|dly_counter[0] LIT INDEX 0 FANOUTS 9 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = a2a2 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|dly_counter_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 243 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga:inst|dly_counter[1] LIT INDEX 0 FANOUTS 9 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = a8a8 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 244 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ccd8 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 245 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_2_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ccd8 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 -- UNIQUE + Atom Hier Name: + Atom Id: 246 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0808 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 -- UNIQUE + Atom Hier Name: + Atom Id: 247 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 FANOUTS 4 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0101 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 248 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0008 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 249 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 FANOUTS 6 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = f0f1 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 -- UNIQUE + Atom Hier Name: + Atom Id: 250 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0001 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 -- UNIQUE + Atom Hier Name: + Atom Id: 251 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 -- UNIQUE + Atom Hier Name: + Atom Id: 252 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6_3 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7777 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|b_next_i_o3_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 253 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|b_next_i_o3_0 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff80 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|N_4_i_0_g0_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 254 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_control:vga_control_unit|g_next_i_o3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_control:vga_control_unit|r_next_i_o7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|N_4_i_0_g0_1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 00ec + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|r_next_i_o7_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 255 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|r_next_i_o7 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bfbf + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|N_23_i_0_g0_a_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 256 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_control:vga_control_unit|g_next_i_o3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|N_23_i_0_g0_a LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 6c6e + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|b_next_i_a7_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 257 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_control:vga_control_unit|g_next_i_o3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|b_next_i_a7_1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0001 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 258 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_control:vga_control_unit|r_next_i_o7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 00ef + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 259 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = f1f1 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 260 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = f1f1 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 262 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[9] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = c6c6 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 -- UNIQUE + Atom Hier Name: + Atom Id: 263 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 1f0f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 264 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 265 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[8] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a5a5 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 266 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[7] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[7] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 6c7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 267 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[6] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[6] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 268 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[5] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[5] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = c608 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 269 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[4] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[4] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a508 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 270 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[3] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[3] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 6c7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 271 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[2] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[2] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 272 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[1] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 6688 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 273 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|G_2 -- UNIQUE + Atom Hier Name: + Atom Id: 274 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|G_2_i LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0f1f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 -- UNIQUE + Atom Hier Name: + Atom Id: 275 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9 LIT INDEX 0 FANOUTS 11 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = f7ff + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter -- UNIQUE + Atom Hier Name: + Atom Id: 276 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 1000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter -- UNIQUE + Atom Hier Name: + Atom Id: 277 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 278 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0101 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 -- UNIQUE + Atom Hier Name: + Atom Id: 279 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 -- UNIQUE + Atom Hier Name: + Atom Id: 280 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 FANOUTS 9 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff7f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 281 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[9] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = c6c6 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 282 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 LIT INDEX 0 FANOUTS 9 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 283 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[8] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a5a5 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 284 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[7] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[7] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 6c7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 285 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[6] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[6] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 286 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[5] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[5] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = c608 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 287 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[4] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[4] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a508 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 288 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[3] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 6c7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 289 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_a_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[2] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[2] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 290 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[1] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 6688 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 291 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|G_16 -- UNIQUE + Atom Hier Name: + Atom Id: 292 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|G_16_i LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0f1f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 -- UNIQUE + Atom Hier Name: + Atom Id: 293 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9 LIT INDEX 0 FANOUTS 11 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = fff7 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 294 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 295 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 FANOUTS 5 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = aaab + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 -- UNIQUE + Atom Hier Name: + Atom Id: 296 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 FANOUTS 4 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8888 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_3_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 298 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_3_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_2_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 299 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_2_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 300 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 2aaa + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 301 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 2aaa + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 302 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0ace + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 303 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0001 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_control:vga_control_unit|g_next_i_o3_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 304 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|g_next_i_o3 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 -- UNIQUE + Atom Hier Name: + Atom Id: 305 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6_1 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7f7f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 -- UNIQUE + Atom Hier Name: + Atom Id: 306 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = fff7 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 307 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_0_~COMBOUT LIT INDEX 0 FANOUTS 0 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[0] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff88 + output_mode = none + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 -- UNIQUE + Atom Hier Name: + Atom Id: 308 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7fff + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 -- UNIQUE + Atom Hier Name: + Atom Id: 309 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 -- UNIQUE + Atom Hier Name: + Atom Id: 310 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_2 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 311 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0020 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 -- UNIQUE + Atom Hier Name: + Atom Id: 312 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter_4 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0010 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 -- UNIQUE + Atom Hier Name: + Atom Id: 313 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglt4_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto5 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0f07 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_a_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 314 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT LIT INDEX 0 FANOUTS 0 + 1: NONE + 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_a_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff88 + output_mode = none + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 -- UNIQUE + Atom Hier Name: + Atom Id: 315 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9_5 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7fff + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 -- UNIQUE + Atom Hier Name: + Atom Id: 316 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9_6 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7fff + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 -- UNIQUE + Atom Hier Name: + Atom Id: 317 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0001 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 -- UNIQUE + Atom Hier Name: + Atom Id: 318 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 1010 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 319 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = d0f0 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 320 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 70f0 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 321 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff2a + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 -- UNIQUE + Atom Hier Name: + Atom Id: 322 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglt4_2 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7f7f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 323 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0008 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 324 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 2a2a + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: board_clk -- NON-UNIQUE + Atom Hier Name: + Atom Id: 261 + Atom Type: stratix_io + + INPUTS (Driven By): + 0: NO ITERM + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] board_clk LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: [PADIO] board_clk LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = input + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_out -- UNIQUE + Atom Hier Name: + Atom Id: 89 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_out -- UNIQUE + Atom Hier Name: + Atom Id: 90 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_set_column_counter_out -- UNIQUE + Atom Hier Name: + Atom Id: 91 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_set_column_counter LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_set_line_counter_out -- UNIQUE + Atom Hier Name: + Atom Id: 92 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_set_line_counter LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_set_hsync_counter_out -- UNIQUE + Atom Hier Name: + Atom Id: 93 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_set_hsync_counter LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_set_vsync_counter_out -- UNIQUE + Atom Hier Name: + Atom Id: 94 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_set_vsync_counter LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_r_out -- UNIQUE + Atom Hier Name: + Atom Id: 95 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_r LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_g_out -- UNIQUE + Atom Hier Name: + Atom Id: 96 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|g LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_g LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_b_out -- UNIQUE + Atom Hier Name: + Atom Id: 97 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_b LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_h_enable_out -- UNIQUE + Atom Hier Name: + Atom Id: 98 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_h_enable LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_v_enable_out -- UNIQUE + Atom Hier Name: + Atom Id: 99 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_v_enable LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_state_clk_out -- UNIQUE + Atom Hier Name: + Atom Id: 100 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_state_clk LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|r0_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 101 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] r0_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|r1_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 102 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] r1_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|r2_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 103 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] r2_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|g0_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 104 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|g LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] g0_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|g1_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 105 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|g LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] g1_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|g2_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 106 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|g LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] g2_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|b0_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 107 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] b0_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|b1_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 108 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] b1_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|hsync_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 109 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] hsync_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|vsync_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 110 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] vsync_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 111 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[9] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 112 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 113 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 114 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 115 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 116 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 117 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 118 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 119 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_column_counter_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 120 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 121 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[9] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 122 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 123 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 124 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 125 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 126 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 127 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 128 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 129 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_counter_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 130 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_state_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 131 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_state_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 132 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_state_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 133 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_state_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 134 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_state_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 135 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_state_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 136 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_hsync_state_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 137 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_line_counter_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 138 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_line_counter_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 139 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_line_counter_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 140 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_line_counter_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 141 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_line_counter_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 142 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_line_counter_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 143 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_line_counter_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 144 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_line_counter_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 145 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_line_counter_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 146 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 147 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[9] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 148 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 149 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 150 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 151 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 152 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 153 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 154 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 155 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_counter_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 156 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_state_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 157 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_state_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 158 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_state_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 159 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_state_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 160 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_state_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 161 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_state_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 162 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|d_vsync_state_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 163 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_tri_13_ -- UNIQUE + Atom Hier Name: + Atom Id: 164 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[13] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_out_12_ -- UNIQUE + Atom Hier Name: + Atom Id: 165 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[12] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_out_11_ -- UNIQUE + Atom Hier Name: + Atom Id: 166 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[11] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_out_10_ -- UNIQUE + Atom Hier Name: + Atom Id: 167 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[10] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_out_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 168 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[9] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 169 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 170 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_tri_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 171 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_tri_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 172 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_tri_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 173 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_tri_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 174 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 175 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 176 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|seven_seg_pin_tri_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 177 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga:inst|reset_pin_in -- UNIQUE + Atom Hier Name: + Atom Id: 241 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: NO ITERM + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [PADIO] DISCONNECTED + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] reset LIT INDEX 0 FANOUTS 9 + 1: NONE + 2: NONE + 3: [PADIO] reset LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = input + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: ~STRATIX_FITTER_CREATED_GND~I -- NON-UNIQUE + Atom Hier Name: + Atom Id: 325 + Atom Type: stratix_lcell + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 FANOUTS 6 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: ~DATA0~ -- NON-UNIQUE + Atom Hier Name: + Atom Id: 326 + Atom Type: stratix_io + + INPUTS (Driven By): + 0: NO ITERM + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] ~DATA0~ LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = input + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + diff --git a/bsp3/Designflow/ppr/download/incremental_db/README b/bsp3/Designflow/ppr/download/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/bsp3/Designflow/ppr/download/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/bsp3/Designflow/ppr/download/incremental_db/compiled_partitions/vga_pll.root_partition.map.kpt b/bsp3/Designflow/ppr/download/incremental_db/compiled_partitions/vga_pll.root_partition.map.kpt new file mode 100644 index 0000000..0ed963a --- /dev/null +++ b/bsp3/Designflow/ppr/download/incremental_db/compiled_partitions/vga_pll.root_partition.map.kpt @@ -0,0 +1,1250 @@ + + + + inst/vga_driver_unit/hsync_state_0_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_state_5_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_state_5_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_9_ + stratix_lcell + le + + + inst/vga_control_unit/b_Z + stratix_lcell + le + + + inst/dly_counter_1_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_state_6_ + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_3_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_state_1_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_state_4_ + stratix_lcell + le + + + inst/vga_driver_unit/v_sync_Z + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_6_ + stratix_lcell + le + + + inst/vga_driver_unit/v_enable_sig_Z + stratix_lcell + le + + + inst/vga_driver_unit/h_sync_Z + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_8_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_4_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_9_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_5_ + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_8_ + stratix_lcell + le + + + inst/vga_driver_unit/line_counter_sig_3_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_state_4_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_6_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_state_3_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_state_2_ + stratix_lcell + le + + + inst/vga_control_unit/g_Z + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_6_ + stratix_lcell + le + + + inst/vga_control_unit/r_Z + stratix_lcell + le + + + inst/dly_counter_0_ + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_4_ + stratix_lcell + le + + + inst/vga_driver_unit/line_counter_sig_1_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_2_ + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_2_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_5_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_state_1_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_3_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_4_ + stratix_lcell + le + + + inst/vga_driver_unit/line_counter_sig_7_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_0_ + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_0_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_0_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_7_ + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_9_ + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_7_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_state_2_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_8_ + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_5_ + stratix_lcell + le + + + inst/vga_driver_unit/line_counter_sig_5_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_state_3_ + stratix_lcell + le + + + inst/vga_driver_unit/line_counter_sig_8_ + stratix_lcell + le + + + inst/vga_driver_unit/line_counter_sig_6_ + stratix_lcell + le + + + inst/vga_driver_unit/line_counter_sig_0_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_state_0_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_1_ + stratix_lcell + le + + + inst/vga_driver_unit/hsync_counter_1_ + stratix_lcell + le + + + inst/vga_driver_unit/line_counter_sig_2_ + stratix_lcell + le + + + inst/vga_driver_unit/h_enable_sig_Z + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_2_ + stratix_lcell + le + + + inst/vga_driver_unit/column_counter_sig_1_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_state_6_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_3_ + stratix_lcell + le + + + inst/vga_driver_unit/vsync_counter_7_ + stratix_lcell + le + + + inst/vga_driver_unit/line_counter_sig_4_ + stratix_lcell + le + + + + + + + vga:inst|vga_control:vga_control_unit|r + + + vga:inst|vga_driver:vga_driver_unit|h_enable_sig + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 + + + vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 + + + vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 + + + vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 + + + vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 + + + vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 + + + vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 + + + vga:inst|vga_driver:vga_driver_unit|v_enable_sig + + + vga:inst|vga_driver:vga_driver_unit|hsync_state_5 + + + vga:inst|vga_driver:vga_driver_unit|v_sync + + + vga:inst|vga_driver:vga_driver_unit|hsync_state_4 + + + vga:inst|vga_driver:vga_driver_unit|hsync_state_3 + + + vga:inst|vga_driver:vga_driver_unit|hsync_state_2 + + + vga:inst|vga_driver:vga_driver_unit|hsync_state_6 + + + vga:inst|vga_driver:vga_driver_unit|hsync_state_1 + + + vga:inst|vga_driver:vga_driver_unit|hsync_state_0 + + + vga:inst|vga_control:vga_control_unit|g + + + vga:inst|vga_control:vga_control_unit|b + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 + + + vga:inst|vga_driver:vga_driver_unit|h_sync + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 + + + vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 + + + vga:inst|vga_driver:vga_driver_unit|vsync_state_2 + + + vga:inst|vga_driver:vga_driver_unit|vsync_state_3 + + + vga:inst|vga_driver:vga_driver_unit|vsync_state_0 + + + vga:inst|vga_driver:vga_driver_unit|vsync_state_1 + + + vga:inst|vga_driver:vga_driver_unit|vsync_state_6 + + + vga:inst|vga_driver:vga_driver_unit|vsync_state_4 + + + vga:inst|dly_counter[1] + + + vga:inst|vga_driver:vga_driver_unit|vsync_state_5 + + + vga:inst|dly_counter[0] + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 + + + vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 + + + vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 + + + vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 + + + vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 + + + vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.sft b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.sft new file mode 100644 index 0000000..5aed62e --- /dev/null +++ b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.sft @@ -0,0 +1,4 @@ +set tool_name "ModelSim-Altera (Verilog)" +set corner_file_list { + {{"Slow Model"} {vga_pll.vo vga_pll_v.sdo}} +} diff --git a/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.vo b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.vo new file mode 100644 index 0000000..75e886a --- /dev/null +++ b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.vo @@ -0,0 +1,9013 @@ +// Copyright (C) 1991-2009 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II" +// VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version" + +// DATE "10/29/2009 17:13:31" + +// +// Device: Altera EP1S25F672C6 Package FBGA672 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_pll ( + d_hsync, + board_clk, + reset, + d_vsync, + d_set_column_counter, + d_set_line_counter, + d_set_hsync_counter, + d_set_vsync_counter, + d_r, + d_g, + d_b, + d_h_enable, + d_v_enable, + d_state_clk, + r0_pin, + r1_pin, + r2_pin, + g0_pin, + g1_pin, + g2_pin, + b0_pin, + b1_pin, + hsync_pin, + vsync_pin, + d_column_counter, + d_hsync_counter, + d_hsync_state, + d_line_counter, + d_vsync_counter, + d_vsync_state, + seven_seg_pin); +output d_hsync; +input board_clk; +input reset; +output d_vsync; +output d_set_column_counter; +output d_set_line_counter; +output d_set_hsync_counter; +output d_set_vsync_counter; +output d_r; +output d_g; +output d_b; +output d_h_enable; +output d_v_enable; +output d_state_clk; +output r0_pin; +output r1_pin; +output r2_pin; +output g0_pin; +output g1_pin; +output g2_pin; +output b0_pin; +output b1_pin; +output hsync_pin; +output vsync_pin; +output [9:0] d_column_counter; +output [9:0] d_hsync_counter; +output [0:6] d_hsync_state; +output [8:0] d_line_counter; +output [9:0] d_vsync_counter; +output [0:6] d_vsync_state; +output [13:0] seven_seg_pin; + +wire gnd = 1'b0; +wire vcc = 1'b1; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_pll_v.sdo"); +// synopsys translate_on + +wire \inst1|altpll_component|pll~CLK1 ; +wire \inst1|altpll_component|pll~CLK2 ; +wire \inst1|altpll_component|pll~CLK3 ; +wire \inst1|altpll_component|pll~CLK4 ; +wire \inst1|altpll_component|pll~CLK5 ; +wire \inst|vga_driver_unit|un2_column_counter_next_0_~COMBOUT ; +wire \inst|vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT ; +wire \board_clk~combout ; +wire \inst1|altpll_component|_clk0 ; +wire \reset~combout ; +wire \inst|vga_driver_unit|un6_dly_counter_0_x ; +wire \inst|vga_driver_unit|hsync_state_6 ; +wire \inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ; +wire \inst|vga_driver_unit|hsync_counter_1 ; +wire \inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ; +wire \inst|vga_driver_unit|hsync_counter_2 ; +wire \inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ; +wire \inst|vga_driver_unit|hsync_counter_3 ; +wire \inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ; +wire \inst|vga_driver_unit|hsync_counter_5 ; +wire \inst|vga_driver_unit|un13_hsync_counter_7 ; +wire \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ; +wire \inst|vga_driver_unit|hsync_counter_6 ; +wire \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ; +wire \inst|vga_driver_unit|hsync_counter_7 ; +wire \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ; +wire \inst|vga_driver_unit|hsync_counter_8 ; +wire \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ; +wire \inst|vga_driver_unit|hsync_counter_9 ; +wire \inst|vga_driver_unit|un9_hsync_counterlt9_3 ; +wire \inst|vga_driver_unit|un9_hsync_counterlt9 ; +wire \inst|vga_driver_unit|G_2_i ; +wire \inst|vga_driver_unit|hsync_counter_0 ; +wire \inst|vga_driver_unit|un12_hsync_counter_3 ; +wire \inst|vga_driver_unit|un12_hsync_counter_4 ; +wire \inst|vga_driver_unit|un12_hsync_counter ; +wire \inst|vga_driver_unit|un10_hsync_counter_1 ; +wire \inst|vga_driver_unit|un11_hsync_counter_3 ; +wire \inst|vga_driver_unit|un11_hsync_counter_2 ; +wire \inst|vga_driver_unit|un10_hsync_counter_4 ; +wire \inst|vga_driver_unit|un10_hsync_counter_3 ; +wire \inst|vga_driver_unit|hsync_state_5 ; +wire \inst|vga_driver_unit|hsync_state_4 ; +wire \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ; +wire \inst|vga_driver_unit|hsync_state_1 ; +wire \inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ; +wire \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ; +wire \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; +wire \inst|vga_driver_unit|hsync_state_2 ; +wire \inst|vga_driver_unit|hsync_state_0 ; +wire \inst|vga_driver_unit|d_set_hsync_counter ; +wire \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ; +wire \inst|vga_driver_unit|hsync_counter_4 ; +wire \inst|vga_driver_unit|un13_hsync_counter_2 ; +wire \inst|vga_driver_unit|un13_hsync_counter ; +wire \inst|vga_driver_unit|hsync_state_3 ; +wire \inst|vga_driver_unit|un1_hsync_state_3_0 ; +wire \inst|vga_driver_unit|h_sync_1_0_0_0_g1 ; +wire \inst|vga_driver_unit|h_sync ; +wire \inst|vga_driver_unit|vsync_state_6 ; +wire \inst|vga_driver_unit|vsync_counter_0 ; +wire \inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ; +wire \inst|vga_driver_unit|vsync_counter_1 ; +wire \inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ; +wire \inst|vga_driver_unit|vsync_counter_2 ; +wire \inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ; +wire \inst|vga_driver_unit|vsync_counter_3 ; +wire \inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ; +wire \inst|vga_driver_unit|vsync_counter_4 ; +wire \inst|vga_driver_unit|vsync_counter_5 ; +wire \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ; +wire \inst|vga_driver_unit|vsync_counter_6 ; +wire \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ; +wire \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ; +wire \inst|vga_driver_unit|vsync_counter_8 ; +wire \inst|vga_driver_unit|un9_vsync_counterlt9_5 ; +wire \inst|vga_driver_unit|un9_vsync_counterlt9_6 ; +wire \inst|vga_driver_unit|un9_vsync_counterlt9 ; +wire \inst|vga_driver_unit|G_16_i ; +wire \inst|vga_driver_unit|vsync_counter_7 ; +wire \inst|vga_driver_unit|un12_vsync_counter_6 ; +wire \inst|vga_driver_unit|un12_vsync_counter_7 ; +wire \inst|vga_driver_unit|un14_vsync_counter_8 ; +wire \inst|vga_driver_unit|un13_vsync_counter_3 ; +wire \inst|vga_driver_unit|un13_vsync_counter_4 ; +wire \inst|vga_driver_unit|vsync_state_1 ; +wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ; +wire \inst|vga_driver_unit|un15_vsync_counter_3 ; +wire \inst|vga_driver_unit|un15_vsync_counter_4 ; +wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ; +wire \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ; +wire \inst|vga_driver_unit|vsync_state_5 ; +wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ; +wire \inst|vga_driver_unit|vsync_state_next_2_sqmuxa ; +wire \inst|vga_driver_unit|vsync_state_3 ; +wire \inst|vga_driver_unit|vsync_state_2 ; +wire \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ; +wire \inst|vga_driver_unit|vsync_state_0 ; +wire \inst|vga_driver_unit|d_set_vsync_counter ; +wire \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ; +wire \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ; +wire \inst|vga_driver_unit|vsync_counter_9 ; +wire \inst|vga_driver_unit|vsync_state_4 ; +wire \inst|vga_driver_unit|un1_vsync_state_2_0 ; +wire \inst|vga_driver_unit|v_sync_1_0_0_0_g1 ; +wire \inst|vga_driver_unit|v_sync ; +wire \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; +wire \inst|vga_driver_unit|column_counter_sig_0 ; +wire \inst|vga_driver_unit|column_counter_sig_1 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ; +wire \inst|vga_driver_unit|column_counter_sig_3 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ; +wire \inst|vga_driver_unit|column_counter_sig_2 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ; +wire \inst|vga_driver_unit|column_counter_sig_4 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ; +wire \inst|vga_driver_unit|column_counter_sig_5 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ; +wire \inst|vga_driver_unit|column_counter_sig_8 ; +wire \inst|vga_driver_unit|un10_column_counter_siglt6_1 ; +wire \inst|vga_driver_unit|un10_column_counter_siglt6 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ; +wire \inst|vga_driver_unit|column_counter_sig_9 ; +wire \inst|vga_driver_unit|un10_column_counter_siglto9 ; +wire \inst|vga_driver_unit|column_counter_sig_7 ; +wire \inst|vga_driver_unit|column_counter_sig_6 ; +wire \inst|vga_driver_unit|un10_column_counter_siglt6_3 ; +wire \inst|vga_control_unit|b_next_i_o3_0 ; +wire \inst|vga_control_unit|g_next_i_o3 ; +wire \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ; +wire \inst|vga_driver_unit|v_enable_sig ; +wire \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ; +wire \inst|vga_driver_unit|h_enable_sig ; +wire \inst|vga_control_unit|r_next_i_o7 ; +wire \inst|vga_control_unit|N_4_i_0_g0_1 ; +wire \inst|vga_control_unit|r ; +wire \inst|vga_control_unit|N_23_i_0_g0_a ; +wire \inst|vga_control_unit|g ; +wire \inst|vga_control_unit|N_6_i_0_g0_0 ; +wire \inst|vga_control_unit|b_next_i_a7_1 ; +wire \inst|vga_control_unit|b ; +wire \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; +wire \inst|vga_driver_unit|line_counter_sig_0 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ; +wire \inst|vga_driver_unit|line_counter_sig_2 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ; +wire \inst|vga_driver_unit|line_counter_sig_1 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ; +wire \inst|vga_driver_unit|line_counter_sig_3 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ; +wire \inst|vga_driver_unit|line_counter_sig_4 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ; +wire \inst|vga_driver_unit|line_counter_sig_5 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ; +wire \inst|vga_driver_unit|line_counter_sig_6 ; +wire \inst|vga_driver_unit|un10_line_counter_siglt4_2 ; +wire \inst|vga_driver_unit|un10_line_counter_siglto5 ; +wire \inst|vga_driver_unit|un10_line_counter_siglto8 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ; +wire \inst|vga_driver_unit|line_counter_sig_7 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ; +wire \inst|vga_driver_unit|line_counter_sig_8 ; +wire \~STRATIX_FITTER_CREATED_GND~I_combout ; +wire [8:0] \inst|vga_driver_unit|hsync_counter_cout ; +wire [1:1] \inst|vga_driver_unit|un1_line_counter_sig_a_cout ; +wire [9:1] \inst|vga_driver_unit|un1_line_counter_sig_combout ; +wire [7:1] \inst|vga_driver_unit|un1_line_counter_sig_cout ; +wire [9:1] \inst|vga_driver_unit|un2_column_counter_next_combout ; +wire [7:0] \inst|vga_driver_unit|un2_column_counter_next_cout ; +wire [8:0] \inst|vga_driver_unit|vsync_counter_cout ; +wire [1:0] \inst|dly_counter ; + +wire [5:0] \inst1|altpll_component|pll_CLK_bus ; + +assign \inst1|altpll_component|_clk0 = \inst1|altpll_component|pll_CLK_bus [0]; +assign \inst1|altpll_component|pll~CLK1 = \inst1|altpll_component|pll_CLK_bus [1]; +assign \inst1|altpll_component|pll~CLK2 = \inst1|altpll_component|pll_CLK_bus [2]; +assign \inst1|altpll_component|pll~CLK3 = \inst1|altpll_component|pll_CLK_bus [3]; +assign \inst1|altpll_component|pll~CLK4 = \inst1|altpll_component|pll_CLK_bus [4]; +assign \inst1|altpll_component|pll~CLK5 = \inst1|altpll_component|pll_CLK_bus [5]; + +// atom is at PIN_N3 +stratix_io \board_clk~I ( + .datain(gnd), + .ddiodatain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\board_clk~combout ), + .regout(), + .ddioregout(), + .padio(board_clk), + .dqsundelayedout()); +// synopsys translate_off +defparam \board_clk~I .ddio_mode = "none"; +defparam \board_clk~I .input_async_reset = "none"; +defparam \board_clk~I .input_power_up = "low"; +defparam \board_clk~I .input_register_mode = "none"; +defparam \board_clk~I .input_sync_reset = "none"; +defparam \board_clk~I .oe_async_reset = "none"; +defparam \board_clk~I .oe_power_up = "low"; +defparam \board_clk~I .oe_register_mode = "none"; +defparam \board_clk~I .oe_sync_reset = "none"; +defparam \board_clk~I .operation_mode = "input"; +defparam \board_clk~I .output_async_reset = "none"; +defparam \board_clk~I .output_power_up = "low"; +defparam \board_clk~I .output_register_mode = "none"; +defparam \board_clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PLL_1 +stratix_pll \inst1|altpll_component|pll ( + .fbin(vcc), + .ena(vcc), + .clkswitch(gnd), + .areset(gnd), + .pfdena(vcc), + .scanclk(gnd), + .scanaclr(gnd), + .scandata(gnd), + .comparator(gnd), + .inclk({gnd,\board_clk~combout }), + .clkena(6'b111111), + .extclkena(4'b1111), + .activeclock(), + .clkloss(), + .locked(), + .scandataout(), + .enable0(), + .enable1(), + .clk(\inst1|altpll_component|pll_CLK_bus ), + .extclk(), + .clkbad()); +// synopsys translate_off +defparam \inst1|altpll_component|pll .clk0_counter = "g0"; +defparam \inst1|altpll_component|pll .clk0_divide_by = 38; +defparam \inst1|altpll_component|pll .clk0_duty_cycle = 50; +defparam \inst1|altpll_component|pll .clk0_multiply_by = 31; +defparam \inst1|altpll_component|pll .clk0_phase_shift = "-725"; +defparam \inst1|altpll_component|pll .clk1_divide_by = 1; +defparam \inst1|altpll_component|pll .clk1_duty_cycle = 50; +defparam \inst1|altpll_component|pll .clk1_multiply_by = 1; +defparam \inst1|altpll_component|pll .clk1_phase_shift = "0"; +defparam \inst1|altpll_component|pll .clk2_divide_by = 1; +defparam \inst1|altpll_component|pll .clk2_duty_cycle = 50; +defparam \inst1|altpll_component|pll .clk2_multiply_by = 1; +defparam \inst1|altpll_component|pll .clk2_phase_shift = "0"; +defparam \inst1|altpll_component|pll .compensate_clock = "clk0"; +defparam \inst1|altpll_component|pll .enable_switch_over_counter = "off"; +defparam \inst1|altpll_component|pll .g0_high = 10; +defparam \inst1|altpll_component|pll .g0_initial = 1; +defparam \inst1|altpll_component|pll .g0_low = 9; +defparam \inst1|altpll_component|pll .g0_mode = "odd"; +defparam \inst1|altpll_component|pll .g0_ph = 0; +defparam \inst1|altpll_component|pll .gate_lock_counter = 0; +defparam \inst1|altpll_component|pll .gate_lock_signal = "no"; +defparam \inst1|altpll_component|pll .inclk0_input_frequency = 30003; +defparam \inst1|altpll_component|pll .inclk1_input_frequency = 30003; +defparam \inst1|altpll_component|pll .invalid_lock_multiplier = 5; +defparam \inst1|altpll_component|pll .l0_high = 13; +defparam \inst1|altpll_component|pll .l0_initial = 1; +defparam \inst1|altpll_component|pll .l0_low = 13; +defparam \inst1|altpll_component|pll .l0_mode = "even"; +defparam \inst1|altpll_component|pll .l0_ph = 0; +defparam \inst1|altpll_component|pll .l1_mode = "bypass"; +defparam \inst1|altpll_component|pll .l1_ph = 0; +defparam \inst1|altpll_component|pll .m = 31; +defparam \inst1|altpll_component|pll .m_initial = 1; +defparam \inst1|altpll_component|pll .m_ph = 3; +defparam \inst1|altpll_component|pll .n = 2; +defparam \inst1|altpll_component|pll .operation_mode = "normal"; +defparam \inst1|altpll_component|pll .pfd_max = 100000; +defparam \inst1|altpll_component|pll .pfd_min = 2000; +defparam \inst1|altpll_component|pll .pll_compensation_delay = 1713; +defparam \inst1|altpll_component|pll .pll_type = "fast"; +defparam \inst1|altpll_component|pll .primary_clock = "inclk0"; +defparam \inst1|altpll_component|pll .qualify_conf_done = "off"; +defparam \inst1|altpll_component|pll .simulation_type = "timing"; +defparam \inst1|altpll_component|pll .skip_vco = "off"; +defparam \inst1|altpll_component|pll .switch_over_counter = 1; +defparam \inst1|altpll_component|pll .switch_over_on_gated_lock = "off"; +defparam \inst1|altpll_component|pll .switch_over_on_lossclk = "off"; +defparam \inst1|altpll_component|pll .valid_lock_multiplier = 1; +defparam \inst1|altpll_component|pll .vco_center = 1250; +defparam \inst1|altpll_component|pll .vco_max = 3334; +defparam \inst1|altpll_component|pll .vco_min = 1000; +// synopsys translate_on + +// atom is at PIN_A5 +stratix_io \inst|reset_pin_in~I ( + .datain(gnd), + .ddiodatain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\reset~combout ), + .regout(), + .ddioregout(), + .padio(reset), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|reset_pin_in~I .ddio_mode = "none"; +defparam \inst|reset_pin_in~I .input_async_reset = "none"; +defparam \inst|reset_pin_in~I .input_power_up = "low"; +defparam \inst|reset_pin_in~I .input_register_mode = "none"; +defparam \inst|reset_pin_in~I .input_sync_reset = "none"; +defparam \inst|reset_pin_in~I .oe_async_reset = "none"; +defparam \inst|reset_pin_in~I .oe_power_up = "low"; +defparam \inst|reset_pin_in~I .oe_register_mode = "none"; +defparam \inst|reset_pin_in~I .oe_sync_reset = "none"; +defparam \inst|reset_pin_in~I .operation_mode = "input"; +defparam \inst|reset_pin_in~I .output_async_reset = "none"; +defparam \inst|reset_pin_in~I .output_power_up = "low"; +defparam \inst|reset_pin_in~I .output_register_mode = "none"; +defparam \inst|reset_pin_in~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N3 +stratix_lcell \inst|dly_counter_0_ ( +// Equation(s): +// \inst|dly_counter [0] = DFFEAS(\reset~combout & (\inst|dly_counter [1] # !\inst|dly_counter [0]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\reset~combout ), + .datab(vcc), + .datac(\inst|dly_counter [0]), + .datad(\inst|dly_counter [1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|dly_counter [0]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|dly_counter_0_ .lut_mask = "aa0a"; +defparam \inst|dly_counter_0_ .operation_mode = "normal"; +defparam \inst|dly_counter_0_ .output_mode = "reg_only"; +defparam \inst|dly_counter_0_ .register_cascade_mode = "off"; +defparam \inst|dly_counter_0_ .sum_lutc_input = "datac"; +defparam \inst|dly_counter_0_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N9 +stratix_lcell \inst|dly_counter_1_ ( +// Equation(s): +// \inst|dly_counter [1] = DFFEAS(\reset~combout & (\inst|dly_counter [0] # \inst|dly_counter [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\reset~combout ), + .datab(vcc), + .datac(\inst|dly_counter [0]), + .datad(\inst|dly_counter [1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|dly_counter [1]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|dly_counter_1_ .lut_mask = "aaa0"; +defparam \inst|dly_counter_1_ .operation_mode = "normal"; +defparam \inst|dly_counter_1_ .output_mode = "reg_only"; +defparam \inst|dly_counter_1_ .register_cascade_mode = "off"; +defparam \inst|dly_counter_1_ .sum_lutc_input = "datac"; +defparam \inst|dly_counter_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N7 +stratix_lcell \inst|vga_driver_unit|vsync_state_6_ ( +// Equation(s): +// \inst|vga_driver_unit|un6_dly_counter_0_x = !\inst|dly_counter [1] # !\inst|dly_counter [0] # !\reset~combout +// \inst|vga_driver_unit|vsync_state_6 = DFFEAS(\inst|vga_driver_unit|un6_dly_counter_0_x , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\reset~combout ), + .datab(vcc), + .datac(\inst|dly_counter [0]), + .datad(\inst|dly_counter [1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .regout(\inst|vga_driver_unit|vsync_state_6 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_6_ .lut_mask = "5fff"; +defparam \inst|vga_driver_unit|vsync_state_6_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_6_ .output_mode = "reg_and_comb"; +defparam \inst|vga_driver_unit|vsync_state_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_6_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_6_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N2 +stratix_lcell \inst|vga_driver_unit|hsync_state_6_ ( +// Equation(s): +// \inst|vga_driver_unit|d_set_hsync_counter = E1_hsync_state_6 # \inst|vga_driver_unit|hsync_state_0 +// \inst|vga_driver_unit|hsync_state_6 = DFFEAS(\inst|vga_driver_unit|d_set_hsync_counter , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|un6_dly_counter_0_x , , , VCC) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|hsync_state_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|d_set_hsync_counter ), + .regout(\inst|vga_driver_unit|hsync_state_6 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_6_ .lut_mask = "fff0"; +defparam \inst|vga_driver_unit|hsync_state_6_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_6_ .output_mode = "reg_and_comb"; +defparam \inst|vga_driver_unit|hsync_state_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_6_ .sum_lutc_input = "qfbk"; +defparam \inst|vga_driver_unit|hsync_state_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N0 +stratix_lcell \inst|vga_driver_unit|hsync_counter_0_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_0 = DFFEAS(!\inst|vga_driver_unit|hsync_counter_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , +// !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [0] = CARRY(\inst|vga_driver_unit|hsync_counter_0 ) +// \inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 = CARRY(\inst|vga_driver_unit|hsync_counter_0 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_0 ), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_0 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [0]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_0_ .lut_mask = "33cc"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N1 +stratix_lcell \inst|vga_driver_unit|hsync_counter_1_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_1 = DFFEAS(\inst|vga_driver_unit|hsync_counter_1 $ \inst|vga_driver_unit|hsync_counter_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [1] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [0] # !\inst|vga_driver_unit|hsync_counter_1 ) +// \inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 # !\inst|vga_driver_unit|hsync_counter_1 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_1 ), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [0]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_1 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [1]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_1_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .lut_mask = "3c3f"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N2 +stratix_lcell \inst|vga_driver_unit|hsync_counter_2_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_2 = DFFEAS(\inst|vga_driver_unit|hsync_counter_2 $ (!\inst|vga_driver_unit|hsync_counter_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [2] = CARRY(\inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_cout [1])) +// \inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 = CARRY(\inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_2 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [1]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_2 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [2]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_2_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N3 +stratix_lcell \inst|vga_driver_unit|hsync_counter_3_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_3 = DFFEAS(\inst|vga_driver_unit|hsync_counter_3 $ (\inst|vga_driver_unit|hsync_counter_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [3] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [2] # !\inst|vga_driver_unit|hsync_counter_3 ) +// \inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 # !\inst|vga_driver_unit|hsync_counter_3 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_3 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [2]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_3 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [3]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_3_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .lut_mask = "5a5f"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N4 +stratix_lcell \inst|vga_driver_unit|hsync_counter_4_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_4 = DFFEAS(\inst|vga_driver_unit|hsync_counter_4 $ (!\inst|vga_driver_unit|hsync_counter_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [4] = CARRY(\inst|vga_driver_unit|hsync_counter_4 & (!\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_4 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [3]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_4 ), + .cout(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_4_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N5 +stratix_lcell \inst|vga_driver_unit|hsync_counter_5_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_5 = DFFEAS(\inst|vga_driver_unit|hsync_counter_5 $ \inst|vga_driver_unit|hsync_counter_cout [4], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [5] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [4] # !\inst|vga_driver_unit|hsync_counter_5 ) +// \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [4] # !\inst|vga_driver_unit|hsync_counter_5 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_5 ), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_5 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [5]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_5_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .lut_mask = "3c3f"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N1 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 ( +// Equation(s): +// \inst|vga_driver_unit|un13_hsync_counter_7 = \inst|vga_driver_unit|hsync_counter_2 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_0 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_2 ), + .datab(\inst|vga_driver_unit|hsync_counter_1 ), + .datac(\inst|vga_driver_unit|hsync_counter_3 ), + .datad(\inst|vga_driver_unit|hsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_hsync_counter_7 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .lut_mask = "8000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N6 +stratix_lcell \inst|vga_driver_unit|hsync_counter_6_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_6 = DFFEAS(\inst|vga_driver_unit|hsync_counter_6 $ !(!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [5]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & +// \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [6] = CARRY(\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_cout [5]) +// \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 = CARRY(\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_6 ), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [5]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_6 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [6]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_6_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .lut_mask = "c30c"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N7 +stratix_lcell \inst|vga_driver_unit|hsync_counter_7_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_7 = DFFEAS(\inst|vga_driver_unit|hsync_counter_7 $ ((!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [6]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & +// \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [7] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [6] # !\inst|vga_driver_unit|hsync_counter_7 ) +// \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 # !\inst|vga_driver_unit|hsync_counter_7 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_7 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [6]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_7 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [7]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_7_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .lut_mask = "5a5f"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N8 +stratix_lcell \inst|vga_driver_unit|hsync_counter_8_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_8 = DFFEAS(\inst|vga_driver_unit|hsync_counter_8 $ (!(!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [7]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & +// \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [8] = CARRY(\inst|vga_driver_unit|hsync_counter_8 & (!\inst|vga_driver_unit|hsync_counter_cout [7])) +// \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 = CARRY(\inst|vga_driver_unit|hsync_counter_8 & (!\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_8 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [7]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_8 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [8]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_8_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N9 +stratix_lcell \inst|vga_driver_unit|hsync_counter_9_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_9 = DFFEAS((!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [8]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ) $ +// \inst|vga_driver_unit|hsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(\inst|vga_driver_unit|hsync_counter_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [8]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_9 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_9_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .lut_mask = "0ff0"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N2 +stratix_lcell \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 ( +// Equation(s): +// \inst|vga_driver_unit|un9_hsync_counterlt9_3 = !\inst|vga_driver_unit|hsync_counter_6 # !\inst|vga_driver_unit|hsync_counter_8 # !\inst|vga_driver_unit|hsync_counter_9 # !\inst|vga_driver_unit|hsync_counter_7 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_7 ), + .datab(\inst|vga_driver_unit|hsync_counter_9 ), + .datac(\inst|vga_driver_unit|hsync_counter_8 ), + .datad(\inst|vga_driver_unit|hsync_counter_6 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_hsync_counterlt9_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .lut_mask = "7fff"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N4 +stratix_lcell \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 ( +// Equation(s): +// \inst|vga_driver_unit|un9_hsync_counterlt9 = \inst|vga_driver_unit|un9_hsync_counterlt9_3 # !\inst|vga_driver_unit|un13_hsync_counter_7 # !\inst|vga_driver_unit|hsync_counter_4 # !\inst|vga_driver_unit|hsync_counter_5 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_5 ), + .datab(\inst|vga_driver_unit|hsync_counter_4 ), + .datac(\inst|vga_driver_unit|un13_hsync_counter_7 ), + .datad(\inst|vga_driver_unit|un9_hsync_counterlt9_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .lut_mask = "ff7f"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N5 +stratix_lcell \inst|vga_driver_unit|G_2 ( +// Equation(s): +// \inst|vga_driver_unit|G_2_i = !\inst|vga_driver_unit|hsync_state_6 & !\inst|vga_driver_unit|hsync_state_0 & !\inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|un9_hsync_counterlt9 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_state_6 ), + .datab(\inst|vga_driver_unit|hsync_state_0 ), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|G_2_i ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|G_2 .lut_mask = "01ff"; +defparam \inst|vga_driver_unit|G_2 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|G_2 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|G_2 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|G_2 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|G_2 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N5 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un12_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_9 & \inst|vga_driver_unit|hsync_counter_2 & !\inst|vga_driver_unit|hsync_counter_5 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_3 ), + .datab(\inst|vga_driver_unit|hsync_counter_9 ), + .datac(\inst|vga_driver_unit|hsync_counter_2 ), + .datad(\inst|vga_driver_unit|hsync_counter_5 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_hsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .lut_mask = "0040"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N6 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 ( +// Equation(s): +// \inst|vga_driver_unit|un12_hsync_counter_4 = !\inst|vga_driver_unit|hsync_counter_4 & !\inst|vga_driver_unit|hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|hsync_counter_8 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_4 ), + .datab(\inst|vga_driver_unit|hsync_counter_7 ), + .datac(\inst|vga_driver_unit|hsync_counter_6 ), + .datad(\inst|vga_driver_unit|hsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_hsync_counter_4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .lut_mask = "0100"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N8 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter ( +// Equation(s): +// \inst|vga_driver_unit|un12_hsync_counter = \inst|vga_driver_unit|hsync_counter_0 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|un12_hsync_counter_3 & \inst|vga_driver_unit|un12_hsync_counter_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_0 ), + .datab(\inst|vga_driver_unit|hsync_counter_1 ), + .datac(\inst|vga_driver_unit|un12_hsync_counter_3 ), + .datad(\inst|vga_driver_unit|un12_hsync_counter_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_hsync_counter ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .lut_mask = "8000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N8 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 ( +// Equation(s): +// \inst|vga_driver_unit|un10_hsync_counter_1 = !\inst|vga_driver_unit|hsync_counter_5 & !\inst|vga_driver_unit|hsync_counter_9 & !\inst|vga_driver_unit|hsync_counter_8 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_5 ), + .datac(\inst|vga_driver_unit|hsync_counter_9 ), + .datad(\inst|vga_driver_unit|hsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .lut_mask = "0003"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N3 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un11_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_3 & !\inst|vga_driver_unit|hsync_counter_4 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|hsync_counter_0 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_3 ), + .datab(\inst|vga_driver_unit|hsync_counter_4 ), + .datac(\inst|vga_driver_unit|hsync_counter_1 ), + .datad(\inst|vga_driver_unit|hsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un11_hsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .lut_mask = "1000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N1 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 ( +// Equation(s): +// \inst|vga_driver_unit|un11_hsync_counter_2 = \inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|hsync_counter_7 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_2 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_6 ), + .datad(\inst|vga_driver_unit|hsync_counter_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un11_hsync_counter_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .lut_mask = "0a00"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N7 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 ( +// Equation(s): +// \inst|vga_driver_unit|un10_hsync_counter_4 = \inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|hsync_counter_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_3 ), + .datab(\inst|vga_driver_unit|hsync_counter_1 ), + .datac(\inst|vga_driver_unit|hsync_counter_6 ), + .datad(\inst|vga_driver_unit|hsync_counter_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_hsync_counter_4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .lut_mask = "8000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N9 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un10_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_2 & !\inst|vga_driver_unit|hsync_counter_0 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_7 ), + .datac(\inst|vga_driver_unit|hsync_counter_2 ), + .datad(\inst|vga_driver_unit|hsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_hsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .lut_mask = "0003"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N8 +stratix_lcell \inst|vga_driver_unit|hsync_state_5_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_5 = DFFEAS(\inst|vga_driver_unit|hsync_state_6 # \inst|vga_driver_unit|hsync_state_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_state_6 ), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|hsync_state_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_5 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_5_ .lut_mask = "ffaa"; +defparam \inst|vga_driver_unit|hsync_state_5_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_5_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N6 +stratix_lcell \inst|vga_driver_unit|hsync_state_4_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_4 = DFFEAS(\inst|vga_driver_unit|un10_hsync_counter_4 & \inst|vga_driver_unit|un10_hsync_counter_3 & \inst|vga_driver_unit|hsync_state_5 & \inst|vga_driver_unit|un10_hsync_counter_1 , +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_hsync_counter_4 ), + .datab(\inst|vga_driver_unit|un10_hsync_counter_3 ), + .datac(\inst|vga_driver_unit|hsync_state_5 ), + .datad(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_4 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_4_ .lut_mask = "8000"; +defparam \inst|vga_driver_unit|hsync_state_4_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_4_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N4 +stratix_lcell \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 = \inst|vga_driver_unit|hsync_state_4 & (!\inst|vga_driver_unit|un11_hsync_counter_2 # !\inst|vga_driver_unit|un11_hsync_counter_3 # !\inst|vga_driver_unit|un10_hsync_counter_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .datab(\inst|vga_driver_unit|un11_hsync_counter_3 ), + .datac(\inst|vga_driver_unit|un11_hsync_counter_2 ), + .datad(\inst|vga_driver_unit|hsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .lut_mask = "7f00"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N4 +stratix_lcell \inst|vga_driver_unit|hsync_state_1_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_1 = DFFEAS(\inst|vga_driver_unit|un10_hsync_counter_1 & \inst|vga_driver_unit|un11_hsync_counter_2 & \inst|vga_driver_unit|un11_hsync_counter_3 & \inst|vga_driver_unit|hsync_state_4 , +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .datab(\inst|vga_driver_unit|un11_hsync_counter_2 ), + .datac(\inst|vga_driver_unit|un11_hsync_counter_3 ), + .datad(\inst|vga_driver_unit|hsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_1 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_1_ .lut_mask = "8000"; +defparam \inst|vga_driver_unit|hsync_state_1_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N9 +stratix_lcell \inst|vga_driver_unit|hsync_state_3_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 = \inst|vga_driver_unit|un13_hsync_counter & (E1_hsync_state_3 & !\inst|vga_driver_unit|un12_hsync_counter ) # !\inst|vga_driver_unit|un13_hsync_counter & (\inst|vga_driver_unit|hsync_state_2 # +// E1_hsync_state_3 & !\inst|vga_driver_unit|un12_hsync_counter ) +// \inst|vga_driver_unit|hsync_state_3 = DFFEAS(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , \inst|vga_driver_unit|hsync_state_1 , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , VCC) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un13_hsync_counter ), + .datab(\inst|vga_driver_unit|hsync_state_2 ), + .datac(\inst|vga_driver_unit|hsync_state_1 ), + .datad(\inst|vga_driver_unit|un12_hsync_counter ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(vcc), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ), + .regout(\inst|vga_driver_unit|hsync_state_3 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_3_ .lut_mask = "44f4"; +defparam \inst|vga_driver_unit|hsync_state_3_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_3_ .output_mode = "reg_and_comb"; +defparam \inst|vga_driver_unit|hsync_state_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_3_ .sum_lutc_input = "qfbk"; +defparam \inst|vga_driver_unit|hsync_state_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N0 +stratix_lcell \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 = \inst|vga_driver_unit|hsync_state_5 & (!\inst|vga_driver_unit|un10_hsync_counter_1 # !\inst|vga_driver_unit|un10_hsync_counter_4 # !\inst|vga_driver_unit|un10_hsync_counter_3 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un10_hsync_counter_3 ), + .datab(\inst|vga_driver_unit|hsync_state_5 ), + .datac(\inst|vga_driver_unit|un10_hsync_counter_4 ), + .datad(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .lut_mask = "4ccc"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N7 +stratix_lcell \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 & !\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 & +// !\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ), + .datab(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .lut_mask = "f0f1"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N6 +stratix_lcell \inst|vga_driver_unit|hsync_state_2_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_2 = DFFEAS(\inst|vga_driver_unit|un12_hsync_counter & \inst|vga_driver_unit|hsync_state_3 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un12_hsync_counter ), + .datad(\inst|vga_driver_unit|hsync_state_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_2 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_2_ .lut_mask = "f000"; +defparam \inst|vga_driver_unit|hsync_state_2_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_2_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N9 +stratix_lcell \inst|vga_driver_unit|hsync_state_0_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_0 = DFFEAS(\inst|vga_driver_unit|hsync_state_2 & (\inst|vga_driver_unit|un13_hsync_counter ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_state_2 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|un13_hsync_counter ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_0 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_0_ .lut_mask = "cc00"; +defparam \inst|vga_driver_unit|hsync_state_0_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N1 +stratix_lcell \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa = \reset~combout & \inst|dly_counter [1] & \inst|dly_counter [0] & !\inst|vga_driver_unit|d_set_hsync_counter + + .clk(gnd), + .dataa(\reset~combout ), + .datab(\inst|dly_counter [1]), + .datac(\inst|dly_counter [0]), + .datad(\inst|vga_driver_unit|d_set_hsync_counter ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .lut_mask = "0080"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N2 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 ( +// Equation(s): +// \inst|vga_driver_unit|un13_hsync_counter_2 = \inst|vga_driver_unit|hsync_counter_4 & !\inst|vga_driver_unit|hsync_counter_5 & \inst|vga_driver_unit|hsync_counter_9 & \inst|vga_driver_unit|hsync_counter_8 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_4 ), + .datab(\inst|vga_driver_unit|hsync_counter_5 ), + .datac(\inst|vga_driver_unit|hsync_counter_9 ), + .datad(\inst|vga_driver_unit|hsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_hsync_counter_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .lut_mask = "2000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N3 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter ( +// Equation(s): +// \inst|vga_driver_unit|un13_hsync_counter = \inst|vga_driver_unit|un13_hsync_counter_2 & !\inst|vga_driver_unit|hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|un13_hsync_counter_7 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un13_hsync_counter_2 ), + .datab(\inst|vga_driver_unit|hsync_counter_7 ), + .datac(\inst|vga_driver_unit|hsync_counter_6 ), + .datad(\inst|vga_driver_unit|un13_hsync_counter_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_hsync_counter ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .lut_mask = "0200"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N3 +stratix_lcell \inst|vga_driver_unit|un1_hsync_state_3_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|un1_hsync_state_3_0 = \inst|vga_driver_unit|hsync_state_3 # \inst|vga_driver_unit|hsync_state_1 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_state_3 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|hsync_state_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_hsync_state_3_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .lut_mask = "ffcc"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N2 +stratix_lcell \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|h_sync_1_0_0_0_g1 = \inst|vga_driver_unit|un1_hsync_state_3_0 & \inst|vga_driver_unit|h_sync # !\inst|vga_driver_unit|un1_hsync_state_3_0 & (\inst|vga_driver_unit|hsync_state_2 & \inst|vga_driver_unit|h_sync # +// !\inst|vga_driver_unit|hsync_state_2 & (\inst|vga_driver_unit|hsync_state_4 )) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un1_hsync_state_3_0 ), + .datab(\inst|vga_driver_unit|h_sync ), + .datac(\inst|vga_driver_unit|hsync_state_2 ), + .datad(\inst|vga_driver_unit|hsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .lut_mask = "cdc8"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N9 +stratix_lcell \inst|vga_driver_unit|h_sync_Z ( +// Equation(s): +// \inst|vga_driver_unit|h_sync = DFFEAS(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 # !\inst|dly_counter [0] # !\reset~combout # !\inst|dly_counter [1], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|dly_counter [1]), + .datab(\reset~combout ), + .datac(\inst|dly_counter [0]), + .datad(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|h_sync ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|h_sync_Z .lut_mask = "ff7f"; +defparam \inst|vga_driver_unit|h_sync_Z .operation_mode = "normal"; +defparam \inst|vga_driver_unit|h_sync_Z .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|h_sync_Z .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|h_sync_Z .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|h_sync_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N0 +stratix_lcell \inst|vga_driver_unit|vsync_counter_0_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_0 = DFFEAS(\inst|vga_driver_unit|vsync_counter_0 $ \inst|vga_driver_unit|d_set_hsync_counter , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [0] = CARRY(\inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|d_set_hsync_counter ) +// \inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 = CARRY(\inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|d_set_hsync_counter ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_0 ), + .datab(\inst|vga_driver_unit|d_set_hsync_counter ), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_0 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [0]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_0_ .lut_mask = "6688"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N1 +stratix_lcell \inst|vga_driver_unit|vsync_counter_1_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_1 = DFFEAS(\inst|vga_driver_unit|vsync_counter_1 $ \inst|vga_driver_unit|vsync_counter_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [1] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [0] # !\inst|vga_driver_unit|vsync_counter_1 ) +// \inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 # !\inst|vga_driver_unit|vsync_counter_1 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|vsync_counter_1 ), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [0]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_1 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [1]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_1_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .lut_mask = "3c3f"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N2 +stratix_lcell \inst|vga_driver_unit|vsync_counter_2_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_2 = DFFEAS(\inst|vga_driver_unit|vsync_counter_2 $ (!\inst|vga_driver_unit|vsync_counter_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [2] = CARRY(\inst|vga_driver_unit|vsync_counter_2 & (!\inst|vga_driver_unit|vsync_counter_cout [1])) +// \inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 = CARRY(\inst|vga_driver_unit|vsync_counter_2 & (!\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_2 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [1]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_2 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [2]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_2_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N3 +stratix_lcell \inst|vga_driver_unit|vsync_counter_3_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_3 = DFFEAS(\inst|vga_driver_unit|vsync_counter_3 $ (\inst|vga_driver_unit|vsync_counter_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [3] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [2] # !\inst|vga_driver_unit|vsync_counter_3 ) +// \inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 # !\inst|vga_driver_unit|vsync_counter_3 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_3 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [2]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_3 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [3]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_3_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .lut_mask = "5a5f"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N4 +stratix_lcell \inst|vga_driver_unit|vsync_counter_4_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_4 = DFFEAS(\inst|vga_driver_unit|vsync_counter_4 $ (!\inst|vga_driver_unit|vsync_counter_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [4] = CARRY(\inst|vga_driver_unit|vsync_counter_4 & (!\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_4 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [3]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_4 ), + .cout(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_4_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N5 +stratix_lcell \inst|vga_driver_unit|vsync_counter_5_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_5 = DFFEAS(\inst|vga_driver_unit|vsync_counter_5 $ \inst|vga_driver_unit|vsync_counter_cout [4], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [5] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [4] # !\inst|vga_driver_unit|vsync_counter_5 ) +// \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [4] # !\inst|vga_driver_unit|vsync_counter_5 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|vsync_counter_5 ), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_5 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [5]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_5_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .lut_mask = "3c3f"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N6 +stratix_lcell \inst|vga_driver_unit|vsync_counter_6_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_6 = DFFEAS(\inst|vga_driver_unit|vsync_counter_6 $ !(!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [5]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & +// \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [6] = CARRY(\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_cout [5]) +// \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 = CARRY(\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [5]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_6 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [6]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_6_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .lut_mask = "c30c"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N7 +stratix_lcell \inst|vga_driver_unit|vsync_counter_7_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_7 = DFFEAS(\inst|vga_driver_unit|vsync_counter_7 $ ((!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [6]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & +// \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [7] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [6] # !\inst|vga_driver_unit|vsync_counter_7 ) +// \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 # !\inst|vga_driver_unit|vsync_counter_7 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_7 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [6]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_7 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [7]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_7_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .lut_mask = "5a5f"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N8 +stratix_lcell \inst|vga_driver_unit|vsync_counter_8_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_8 = DFFEAS(\inst|vga_driver_unit|vsync_counter_8 $ (!(!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [7]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & +// \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [8] = CARRY(\inst|vga_driver_unit|vsync_counter_8 & (!\inst|vga_driver_unit|vsync_counter_cout [7])) +// \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 = CARRY(\inst|vga_driver_unit|vsync_counter_8 & (!\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_8 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [7]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_8 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [8]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_8_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N9 +stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 ( +// Equation(s): +// \inst|vga_driver_unit|un9_vsync_counterlt9_5 = !\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|vsync_counter_8 # !\inst|vga_driver_unit|vsync_counter_7 # !\inst|vga_driver_unit|vsync_counter_6 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_6 ), + .datab(\inst|vga_driver_unit|vsync_counter_7 ), + .datac(\inst|vga_driver_unit|vsync_counter_8 ), + .datad(\inst|vga_driver_unit|vsync_counter_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_vsync_counterlt9_5 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .lut_mask = "7fff"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N2 +stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 ( +// Equation(s): +// \inst|vga_driver_unit|un9_vsync_counterlt9_6 = !\inst|vga_driver_unit|vsync_counter_2 # !\inst|vga_driver_unit|vsync_counter_0 # !\inst|vga_driver_unit|vsync_counter_3 # !\inst|vga_driver_unit|vsync_counter_1 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_1 ), + .datab(\inst|vga_driver_unit|vsync_counter_3 ), + .datac(\inst|vga_driver_unit|vsync_counter_0 ), + .datad(\inst|vga_driver_unit|vsync_counter_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_vsync_counterlt9_6 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .lut_mask = "7fff"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N5 +stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 ( +// Equation(s): +// \inst|vga_driver_unit|un9_vsync_counterlt9 = \inst|vga_driver_unit|un9_vsync_counterlt9_5 # \inst|vga_driver_unit|un9_vsync_counterlt9_6 # !\inst|vga_driver_unit|vsync_counter_5 # !\inst|vga_driver_unit|vsync_counter_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_4 ), + .datab(\inst|vga_driver_unit|un9_vsync_counterlt9_5 ), + .datac(\inst|vga_driver_unit|vsync_counter_5 ), + .datad(\inst|vga_driver_unit|un9_vsync_counterlt9_6 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .lut_mask = "ffdf"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N4 +stratix_lcell \inst|vga_driver_unit|G_16 ( +// Equation(s): +// \inst|vga_driver_unit|G_16_i = !\inst|vga_driver_unit|vsync_state_6 & !\inst|vga_driver_unit|vsync_state_0 & !\inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|un9_vsync_counterlt9 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_state_6 ), + .datab(\inst|vga_driver_unit|vsync_state_0 ), + .datac(\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|G_16_i ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|G_16 .lut_mask = "0f1f"; +defparam \inst|vga_driver_unit|G_16 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|G_16 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|G_16 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|G_16 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|G_16 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N6 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 ( +// Equation(s): +// \inst|vga_driver_unit|un12_vsync_counter_6 = !\inst|vga_driver_unit|vsync_counter_7 & !\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_5 & !\inst|vga_driver_unit|vsync_counter_8 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_7 ), + .datab(\inst|vga_driver_unit|vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_counter_5 ), + .datad(\inst|vga_driver_unit|vsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_vsync_counter_6 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .lut_mask = "0001"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N9 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 ( +// Equation(s): +// \inst|vga_driver_unit|un12_vsync_counter_7 = !\inst|vga_driver_unit|vsync_counter_1 & !\inst|vga_driver_unit|vsync_counter_4 & !\inst|vga_driver_unit|vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_2 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_1 ), + .datab(\inst|vga_driver_unit|vsync_counter_4 ), + .datac(\inst|vga_driver_unit|vsync_counter_3 ), + .datad(\inst|vga_driver_unit|vsync_counter_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_vsync_counter_7 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .lut_mask = "0001"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N4 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 ( +// Equation(s): +// \inst|vga_driver_unit|un14_vsync_counter_8 = \inst|vga_driver_unit|un12_vsync_counter_7 & (\inst|vga_driver_unit|un12_vsync_counter_6 ) + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un12_vsync_counter_7 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|un12_vsync_counter_6 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .lut_mask = "cc00"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N5 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un13_vsync_counter_3 = !\inst|vga_driver_unit|vsync_counter_7 & !\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_9 & !\inst|vga_driver_unit|vsync_counter_8 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_7 ), + .datab(\inst|vga_driver_unit|vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_counter_9 ), + .datad(\inst|vga_driver_unit|vsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_vsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .lut_mask = "0001"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N0 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 ( +// Equation(s): +// \inst|vga_driver_unit|un13_vsync_counter_4 = \inst|vga_driver_unit|vsync_counter_5 & (\inst|vga_driver_unit|un13_vsync_counter_3 & \inst|vga_driver_unit|vsync_counter_0 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_5 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|un13_vsync_counter_3 ), + .datad(\inst|vga_driver_unit|vsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_vsync_counter_4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .lut_mask = "a000"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N4 +stratix_lcell \inst|vga_driver_unit|vsync_state_1_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_1 = DFFEAS(\inst|vga_driver_unit|un12_vsync_counter_7 & \inst|vga_driver_unit|un13_vsync_counter_4 & !\inst|vga_driver_unit|un6_dly_counter_0_x & \inst|vga_driver_unit|vsync_state_4 , +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un12_vsync_counter_7 ), + .datab(\inst|vga_driver_unit|un13_vsync_counter_4 ), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|vsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_1 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_1_ .lut_mask = "0800"; +defparam \inst|vga_driver_unit|vsync_state_1_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N0 +stratix_lcell \inst|vga_driver_unit|vsync_state_3_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 = E1_vsync_state_3 & (!\inst|vga_driver_unit|vsync_counter_0 # !\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|un14_vsync_counter_8 ) +// \inst|vga_driver_unit|vsync_state_3 = DFFEAS(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , \inst|vga_driver_unit|vsync_state_1 , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , VCC) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .datab(\inst|vga_driver_unit|vsync_counter_9 ), + .datac(\inst|vga_driver_unit|vsync_state_1 ), + .datad(\inst|vga_driver_unit|vsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(vcc), + .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ), + .regout(\inst|vga_driver_unit|vsync_state_3 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_3_ .lut_mask = "70f0"; +defparam \inst|vga_driver_unit|vsync_state_3_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_3_ .output_mode = "reg_and_comb"; +defparam \inst|vga_driver_unit|vsync_state_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_3_ .sum_lutc_input = "qfbk"; +defparam \inst|vga_driver_unit|vsync_state_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N3 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un15_vsync_counter_3 = \inst|vga_driver_unit|vsync_counter_9 & \inst|vga_driver_unit|vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_0 & !\inst|vga_driver_unit|vsync_counter_2 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_9 ), + .datab(\inst|vga_driver_unit|vsync_counter_3 ), + .datac(\inst|vga_driver_unit|vsync_counter_0 ), + .datad(\inst|vga_driver_unit|vsync_counter_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un15_vsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .lut_mask = "0008"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N8 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 ( +// Equation(s): +// \inst|vga_driver_unit|un15_vsync_counter_4 = !\inst|vga_driver_unit|vsync_counter_4 & (\inst|vga_driver_unit|un15_vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_4 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|un15_vsync_counter_3 ), + .datad(\inst|vga_driver_unit|vsync_counter_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un15_vsync_counter_4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .lut_mask = "0050"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N1 +stratix_lcell \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 = \inst|vga_driver_unit|vsync_state_4 & (!\inst|vga_driver_unit|un13_vsync_counter_4 # !\inst|vga_driver_unit|un12_vsync_counter_7 ) + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un12_vsync_counter_7 ), + .datac(\inst|vga_driver_unit|vsync_state_4 ), + .datad(\inst|vga_driver_unit|un13_vsync_counter_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .lut_mask = "30f0"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N5 +stratix_lcell \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 = \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 # \inst|vga_driver_unit|vsync_state_2 & (!\inst|vga_driver_unit|un12_vsync_counter_6 # !\inst|vga_driver_unit|un15_vsync_counter_4 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un15_vsync_counter_4 ), + .datab(\inst|vga_driver_unit|un12_vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ), + .datad(\inst|vga_driver_unit|vsync_state_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .lut_mask = "f7f0"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N3 +stratix_lcell \inst|vga_driver_unit|vsync_state_5_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_5 = DFFEAS(\inst|vga_driver_unit|vsync_state_0 # \inst|vga_driver_unit|vsync_state_6 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|vsync_state_0 ), + .datac(\inst|vga_driver_unit|vsync_state_6 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_5 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_5_ .lut_mask = "fcfc"; +defparam \inst|vga_driver_unit|vsync_state_5_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_5_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N0 +stratix_lcell \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 = \inst|vga_driver_unit|vsync_state_5 & (\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|vsync_counter_0 # !\inst|vga_driver_unit|un14_vsync_counter_8 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_9 ), + .datab(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .datac(\inst|vga_driver_unit|vsync_state_5 ), + .datad(\inst|vga_driver_unit|vsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .lut_mask = "b0f0"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N2 +stratix_lcell \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_next_2_sqmuxa = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 & !\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 & +// !\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ), + .datab(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datac(\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ), + .datad(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .lut_mask = "cccd"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N8 +stratix_lcell \inst|vga_driver_unit|vsync_state_2_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_2 = DFFEAS(\inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|un14_vsync_counter_8 & \inst|vga_driver_unit|vsync_state_3 & \inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), +// VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_0 ), + .datab(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .datac(\inst|vga_driver_unit|vsync_state_3 ), + .datad(\inst|vga_driver_unit|vsync_counter_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_2 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_2_ .lut_mask = "8000"; +defparam \inst|vga_driver_unit|vsync_state_2_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_2_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N7 +stratix_lcell \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 = \inst|vga_driver_unit|un12_vsync_counter_6 & \inst|vga_driver_unit|vsync_state_2 & \inst|vga_driver_unit|un15_vsync_counter_4 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un12_vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_state_2 ), + .datad(\inst|vga_driver_unit|un15_vsync_counter_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .lut_mask = "c000"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N6 +stratix_lcell \inst|vga_driver_unit|vsync_state_0_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_0 = DFFEAS(\inst|vga_driver_unit|un6_dly_counter_0_x & \inst|vga_driver_unit|vsync_state_0 & (!\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ) # !\inst|vga_driver_unit|un6_dly_counter_0_x & +// (\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 # \inst|vga_driver_unit|vsync_state_0 & !\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datab(\inst|vga_driver_unit|vsync_state_0 ), + .datac(\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ), + .datad(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_0 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_0_ .lut_mask = "50dc"; +defparam \inst|vga_driver_unit|vsync_state_0_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_0_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N1 +stratix_lcell \inst|vga_driver_unit|d_set_vsync_counter_cZ ( +// Equation(s): +// \inst|vga_driver_unit|d_set_vsync_counter = \inst|vga_driver_unit|vsync_state_0 # \inst|vga_driver_unit|vsync_state_6 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_state_0 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_state_6 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|d_set_vsync_counter ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .lut_mask = "fafa"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N4 +stratix_lcell \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa = \inst|dly_counter [0] & \reset~combout & \inst|dly_counter [1] & !\inst|vga_driver_unit|d_set_vsync_counter + + .clk(gnd), + .dataa(\inst|dly_counter [0]), + .datab(\reset~combout ), + .datac(\inst|dly_counter [1]), + .datad(\inst|vga_driver_unit|d_set_vsync_counter ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .lut_mask = "0080"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N9 +stratix_lcell \inst|vga_driver_unit|vsync_counter_9_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_9 = DFFEAS((!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [8]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ) $ +// \inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(\inst|vga_driver_unit|vsync_counter_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [8]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_9 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_9_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .lut_mask = "0ff0"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N7 +stratix_lcell \inst|vga_driver_unit|vsync_state_4_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_4 = DFFEAS(!\inst|vga_driver_unit|vsync_counter_9 & \inst|vga_driver_unit|un14_vsync_counter_8 & \inst|vga_driver_unit|vsync_state_5 & \inst|vga_driver_unit|vsync_counter_0 , GLOBAL(\inst1|altpll_component|_clk0 ), +// VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_9 ), + .datab(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .datac(\inst|vga_driver_unit|vsync_state_5 ), + .datad(\inst|vga_driver_unit|vsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_4 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_4_ .lut_mask = "4000"; +defparam \inst|vga_driver_unit|vsync_state_4_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_4_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N8 +stratix_lcell \inst|vga_driver_unit|un1_vsync_state_2_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|un1_vsync_state_2_0 = \inst|vga_driver_unit|vsync_state_1 # \inst|vga_driver_unit|vsync_state_3 + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_state_1 ), + .datad(\inst|vga_driver_unit|vsync_state_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_vsync_state_2_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .lut_mask = "fff0"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N5 +stratix_lcell \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|v_sync_1_0_0_0_g1 = \inst|vga_driver_unit|vsync_state_2 & \inst|vga_driver_unit|v_sync # !\inst|vga_driver_unit|vsync_state_2 & (\inst|vga_driver_unit|un1_vsync_state_2_0 & \inst|vga_driver_unit|v_sync # +// !\inst|vga_driver_unit|un1_vsync_state_2_0 & (\inst|vga_driver_unit|vsync_state_4 )) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|v_sync ), + .datab(\inst|vga_driver_unit|vsync_state_4 ), + .datac(\inst|vga_driver_unit|vsync_state_2 ), + .datad(\inst|vga_driver_unit|un1_vsync_state_2_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .lut_mask = "aaac"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N7 +stratix_lcell \inst|vga_driver_unit|v_sync_Z ( +// Equation(s): +// \inst|vga_driver_unit|v_sync = DFFEAS(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 # !\inst|dly_counter [1] # !\reset~combout # !\inst|dly_counter [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|dly_counter [0]), + .datab(\reset~combout ), + .datac(\inst|dly_counter [1]), + .datad(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|v_sync ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|v_sync_Z .lut_mask = "ff7f"; +defparam \inst|vga_driver_unit|v_sync_Z .operation_mode = "normal"; +defparam \inst|vga_driver_unit|v_sync_Z .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|v_sync_Z .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|v_sync_Z .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|v_sync_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N8 +stratix_lcell \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 = \reset~combout & \inst|dly_counter [1] & \inst|dly_counter [0] & !\inst|vga_driver_unit|hsync_state_1 + + .clk(gnd), + .dataa(\reset~combout ), + .datab(\inst|dly_counter [1]), + .datac(\inst|dly_counter [0]), + .datad(\inst|vga_driver_unit|hsync_state_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .lut_mask = "0080"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N5 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_0_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_0 = DFFEAS(!\inst|vga_driver_unit|column_counter_sig_0 # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(\inst|vga_driver_unit|column_counter_sig_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_0 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_0_ .lut_mask = "0fff"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N5 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_1_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [1] = \inst|vga_driver_unit|column_counter_sig_0 $ \inst|vga_driver_unit|column_counter_sig_1 +// \inst|vga_driver_unit|un2_column_counter_next_cout [1] = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_0 ), + .datab(\inst|vga_driver_unit|column_counter_sig_1 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [1]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [1]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .lut_mask = "6688"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N2 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_1_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_1 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [1] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un2_column_counter_next_combout [1]), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_1 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_1_ .lut_mask = "afaf"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N6 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_3_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [3] = \inst|vga_driver_unit|column_counter_sig_3 $ (\inst|vga_driver_unit|column_counter_sig_2 & \inst|vga_driver_unit|un2_column_counter_next_cout [1]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [3] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [1] # !\inst|vga_driver_unit|column_counter_sig_2 # !\inst|vga_driver_unit|column_counter_sig_3 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 # !\inst|vga_driver_unit|column_counter_sig_2 # !\inst|vga_driver_unit|column_counter_sig_3 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_3 ), + .datab(\inst|vga_driver_unit|column_counter_sig_2 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [1]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [3]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [3]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .lut_mask = "6a7f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N2 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_3_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_3 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [3] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [3]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_3 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_3_ .lut_mask = "ff55"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N5 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_0_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_cout [0] = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_0 ), + .datab(\inst|vga_driver_unit|column_counter_sig_1 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_0_~COMBOUT ), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [0]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .lut_mask = "ff88"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .output_mode = "none"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N6 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_2_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [2] = \inst|vga_driver_unit|column_counter_sig_2 $ (\inst|vga_driver_unit|un2_column_counter_next_cout [0]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [2] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [0] # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_2 ), + .datab(\inst|vga_driver_unit|column_counter_sig_3 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [0]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [2]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [2]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .lut_mask = "5a7f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N4 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_2_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_2 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [2] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [2]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_2 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_2_ .lut_mask = "ff0f"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N7 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_4_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [4] = \inst|vga_driver_unit|column_counter_sig_4 $ !\inst|vga_driver_unit|un2_column_counter_next_cout [2] +// \inst|vga_driver_unit|un2_column_counter_next_cout [4] = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [2]) +// \inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_5 ), + .datab(\inst|vga_driver_unit|column_counter_sig_4 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [2]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [4]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [4]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .lut_mask = "c308"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N8 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_4_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_4 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [4] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [4]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_4 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_4_ .lut_mask = "ff0f"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N7 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_5_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [5] = \inst|vga_driver_unit|column_counter_sig_5 $ (\inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [3]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [5] = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [3]) +// \inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_5 ), + .datab(\inst|vga_driver_unit|column_counter_sig_4 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [3]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [5]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [5]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .lut_mask = "a608"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N9 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_5_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_5 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [5] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datac(\inst|vga_driver_unit|un2_column_counter_next_combout [5]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_5 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_5_ .lut_mask = "f3f3"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N8 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_6_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [6] = \inst|vga_driver_unit|column_counter_sig_6 $ (\inst|vga_driver_unit|un2_column_counter_next_cout [4]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [6] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [4] # !\inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|column_counter_sig_6 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 # !\inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|column_counter_sig_6 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_6 ), + .datab(\inst|vga_driver_unit|column_counter_sig_7 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [4]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [6]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [6]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .lut_mask = "5a7f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N9 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_8_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [8] = \inst|vga_driver_unit|un2_column_counter_next_cout [6] $ !\inst|vga_driver_unit|column_counter_sig_8 + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|column_counter_sig_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [6]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [8]), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .lut_mask = "f00f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N2 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_8_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_8 = DFFEAS(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 & \inst|vga_driver_unit|un10_column_counter_siglto9 & \inst|vga_driver_unit|un2_column_counter_next_combout [8], +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [8]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_8 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_8_ .lut_mask = "c000"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N7 +stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 ( +// Equation(s): +// \inst|vga_driver_unit|un10_column_counter_siglt6_1 = !\inst|vga_driver_unit|column_counter_sig_1 # !\inst|vga_driver_unit|column_counter_sig_2 # !\inst|vga_driver_unit|column_counter_sig_0 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_0 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|column_counter_sig_2 ), + .datad(\inst|vga_driver_unit|column_counter_sig_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_column_counter_siglt6_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .lut_mask = "5fff"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N3 +stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 ( +// Equation(s): +// \inst|vga_driver_unit|un10_column_counter_siglt6 = \inst|vga_driver_unit|un10_column_counter_siglt6_3 # \inst|vga_driver_unit|un10_column_counter_siglt6_1 # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_4 ), + .datab(\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), + .datac(\inst|vga_driver_unit|un10_column_counter_siglt6_1 ), + .datad(\inst|vga_driver_unit|column_counter_sig_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_column_counter_siglt6 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .lut_mask = "fdff"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N8 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_7_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [7] = \inst|vga_driver_unit|column_counter_sig_7 $ (\inst|vga_driver_unit|column_counter_sig_6 & \inst|vga_driver_unit|un2_column_counter_next_cout [5]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [7] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [5] # !\inst|vga_driver_unit|column_counter_sig_6 # !\inst|vga_driver_unit|column_counter_sig_7 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 # !\inst|vga_driver_unit|column_counter_sig_6 # !\inst|vga_driver_unit|column_counter_sig_7 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_7 ), + .datab(\inst|vga_driver_unit|column_counter_sig_6 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [5]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [7]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [7]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .lut_mask = "6a7f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N9 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_9_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [9] = \inst|vga_driver_unit|column_counter_sig_9 $ (\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_driver_unit|un2_column_counter_next_cout [7]) + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|column_counter_sig_8 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|column_counter_sig_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [7]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [9]), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .lut_mask = "f30c"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N0 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_9_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_9 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [9] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [9]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_9 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_9_ .lut_mask = "ff55"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N1 +stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 ( +// Equation(s): +// \inst|vga_driver_unit|un10_column_counter_siglto9 = !\inst|vga_driver_unit|column_counter_sig_7 & !\inst|vga_driver_unit|column_counter_sig_8 & \inst|vga_driver_unit|un10_column_counter_siglt6 # !\inst|vga_driver_unit|column_counter_sig_9 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_7 ), + .datab(\inst|vga_driver_unit|column_counter_sig_8 ), + .datac(\inst|vga_driver_unit|un10_column_counter_siglt6 ), + .datad(\inst|vga_driver_unit|column_counter_sig_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .lut_mask = "10ff"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N4 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_7_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_7 = DFFEAS(\inst|vga_driver_unit|un10_column_counter_siglto9 & (\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 & \inst|vga_driver_unit|un2_column_counter_next_combout [7]), +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [7]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_7 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_7_ .lut_mask = "a000"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N6 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_6_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_6 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [6] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un2_column_counter_next_combout [6]), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_6 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_6_ .lut_mask = "cfcf"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N0 +stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 ( +// Equation(s): +// \inst|vga_driver_unit|un10_column_counter_siglt6_3 = !\inst|vga_driver_unit|column_counter_sig_5 # !\inst|vga_driver_unit|column_counter_sig_6 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|column_counter_sig_6 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|column_counter_sig_5 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .lut_mask = "33ff"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N1 +stratix_lcell \inst|vga_control_unit|b_next_i_o3_0_cZ ( +// Equation(s): +// \inst|vga_control_unit|b_next_i_o3_0 = \inst|vga_driver_unit|column_counter_sig_7 # \inst|vga_driver_unit|column_counter_sig_6 & \inst|vga_driver_unit|column_counter_sig_4 & \inst|vga_driver_unit|column_counter_sig_5 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_6 ), + .datab(\inst|vga_driver_unit|column_counter_sig_7 ), + .datac(\inst|vga_driver_unit|column_counter_sig_4 ), + .datad(\inst|vga_driver_unit|column_counter_sig_5 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|b_next_i_o3_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .lut_mask = "eccc"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N3 +stratix_lcell \inst|vga_control_unit|g_next_i_o3_cZ ( +// Equation(s): +// \inst|vga_control_unit|g_next_i_o3 = \inst|vga_driver_unit|column_counter_sig_4 # \inst|vga_driver_unit|column_counter_sig_3 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|column_counter_sig_4 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|column_counter_sig_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|g_next_i_o3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|g_next_i_o3_cZ .lut_mask = "ffcc"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N2 +stratix_lcell \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ ( +// Equation(s): +// \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|hsync_state_5 & !\inst|vga_driver_unit|hsync_state_4 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_state_5 ), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|hsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .lut_mask = "f0f3"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N0 +stratix_lcell \inst|vga_driver_unit|v_enable_sig_Z ( +// Equation(s): +// \inst|vga_driver_unit|v_enable_sig = DFFEAS(\inst|vga_driver_unit|hsync_state_3 # \inst|vga_driver_unit|hsync_state_1 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_state_3 ), + .datad(\inst|vga_driver_unit|hsync_state_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|v_enable_sig ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|v_enable_sig_Z .lut_mask = "fff0"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .operation_mode = "normal"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N6 +stratix_lcell \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ ( +// Equation(s): +// \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|vsync_state_4 & !\inst|vga_driver_unit|vsync_state_5 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datac(\inst|vga_driver_unit|vsync_state_4 ), + .datad(\inst|vga_driver_unit|vsync_state_5 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .lut_mask = "cccf"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X52_Y35_N2 +stratix_lcell \inst|vga_driver_unit|h_enable_sig_Z ( +// Equation(s): +// \inst|vga_driver_unit|h_enable_sig = DFFEAS(\inst|vga_driver_unit|vsync_state_3 # \inst|vga_driver_unit|vsync_state_1 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_state_3 ), + .datad(\inst|vga_driver_unit|vsync_state_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|h_enable_sig ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|h_enable_sig_Z .lut_mask = "fff0"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .operation_mode = "normal"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N5 +stratix_lcell \inst|vga_control_unit|r_next_i_o7_cZ ( +// Equation(s): +// \inst|vga_control_unit|r_next_i_o7 = \inst|vga_driver_unit|column_counter_sig_9 # !\inst|vga_driver_unit|h_enable_sig # !\inst|vga_driver_unit|v_enable_sig + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|v_enable_sig ), + .datac(\inst|vga_driver_unit|h_enable_sig ), + .datad(\inst|vga_driver_unit|column_counter_sig_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|r_next_i_o7 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|r_next_i_o7_cZ .lut_mask = "ff3f"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N3 +stratix_lcell \inst|vga_control_unit|N_4_i_0_g0_1_cZ ( +// Equation(s): +// \inst|vga_control_unit|N_4_i_0_g0_1 = !\inst|vga_control_unit|r_next_i_o7 & (\inst|vga_driver_unit|column_counter_sig_8 # \inst|vga_control_unit|g_next_i_o3 & \inst|vga_driver_unit|column_counter_sig_7 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_8 ), + .datab(\inst|vga_control_unit|g_next_i_o3 ), + .datac(\inst|vga_control_unit|r_next_i_o7 ), + .datad(\inst|vga_driver_unit|column_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|N_4_i_0_g0_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .lut_mask = "0e0a"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N0 +stratix_lcell \inst|vga_control_unit|r_Z ( +// Equation(s): +// \inst|vga_control_unit|r = DFFEAS(\inst|vga_control_unit|N_4_i_0_g0_1 & (\inst|vga_driver_unit|column_counter_sig_8 & (!\inst|vga_control_unit|b_next_i_o3_0 ) # !\inst|vga_driver_unit|column_counter_sig_8 & +// !\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), + .datab(\inst|vga_control_unit|b_next_i_o3_0 ), + .datac(\inst|vga_control_unit|N_4_i_0_g0_1 ), + .datad(\inst|vga_driver_unit|column_counter_sig_8 ), + .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_control_unit|r ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|r_Z .lut_mask = "3050"; +defparam \inst|vga_control_unit|r_Z .operation_mode = "normal"; +defparam \inst|vga_control_unit|r_Z .output_mode = "reg_only"; +defparam \inst|vga_control_unit|r_Z .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|r_Z .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|r_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X76_Y33_N5 +stratix_lcell \inst|vga_control_unit|N_23_i_0_g0_a_cZ ( +// Equation(s): +// \inst|vga_control_unit|N_23_i_0_g0_a = \inst|vga_driver_unit|column_counter_sig_5 & (\inst|vga_driver_unit|column_counter_sig_6 & (!\inst|vga_control_unit|g_next_i_o3 ) # !\inst|vga_driver_unit|column_counter_sig_6 & +// (\inst|vga_control_unit|g_next_i_o3 # !\inst|vga_driver_unit|un10_column_counter_siglt6_1 )) # !\inst|vga_driver_unit|column_counter_sig_5 & (\inst|vga_driver_unit|column_counter_sig_6 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglt6_1 ), + .datab(\inst|vga_driver_unit|column_counter_sig_5 ), + .datac(\inst|vga_driver_unit|column_counter_sig_6 ), + .datad(\inst|vga_control_unit|g_next_i_o3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|N_23_i_0_g0_a ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .lut_mask = "3cf4"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X76_Y33_N2 +stratix_lcell \inst|vga_control_unit|g_Z ( +// Equation(s): +// \inst|vga_control_unit|g = DFFEAS(!\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_control_unit|r_next_i_o7 & \inst|vga_control_unit|N_23_i_0_g0_a & \inst|vga_driver_unit|column_counter_sig_7 , GLOBAL(\inst1|altpll_component|_clk0 ), +// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|column_counter_sig_8 ), + .datab(\inst|vga_control_unit|r_next_i_o7 ), + .datac(\inst|vga_control_unit|N_23_i_0_g0_a ), + .datad(\inst|vga_driver_unit|column_counter_sig_7 ), + .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_control_unit|g ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|g_Z .lut_mask = "1000"; +defparam \inst|vga_control_unit|g_Z .operation_mode = "normal"; +defparam \inst|vga_control_unit|g_Z .output_mode = "reg_only"; +defparam \inst|vga_control_unit|g_Z .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|g_Z .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|g_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X76_Y33_N4 +stratix_lcell \inst|vga_control_unit|N_6_i_0_g0_0_cZ ( +// Equation(s): +// \inst|vga_control_unit|N_6_i_0_g0_0 = !\inst|vga_control_unit|r_next_i_o7 & (\inst|vga_driver_unit|column_counter_sig_8 # \inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|un10_column_counter_siglt6_3 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_8 ), + .datab(\inst|vga_control_unit|r_next_i_o7 ), + .datac(\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), + .datad(\inst|vga_driver_unit|column_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|N_6_i_0_g0_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .lut_mask = "3323"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N1 +stratix_lcell \inst|vga_control_unit|b_next_i_a7_1_cZ ( +// Equation(s): +// \inst|vga_control_unit|b_next_i_a7_1 = !\inst|vga_control_unit|g_next_i_o3 & !\inst|vga_driver_unit|column_counter_sig_2 & !\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_driver_unit|column_counter_sig_7 + + .clk(gnd), + .dataa(\inst|vga_control_unit|g_next_i_o3 ), + .datab(\inst|vga_driver_unit|column_counter_sig_2 ), + .datac(\inst|vga_driver_unit|column_counter_sig_8 ), + .datad(\inst|vga_driver_unit|column_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|b_next_i_a7_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .lut_mask = "0001"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N4 +stratix_lcell \inst|vga_control_unit|b_Z ( +// Equation(s): +// \inst|vga_control_unit|b = DFFEAS(\inst|vga_control_unit|N_6_i_0_g0_0 & !\inst|vga_control_unit|b_next_i_a7_1 & (!\inst|vga_control_unit|b_next_i_o3_0 # !\inst|vga_driver_unit|column_counter_sig_8 ), GLOBAL(\inst1|altpll_component|_clk0 ), +// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|column_counter_sig_8 ), + .datab(\inst|vga_control_unit|b_next_i_o3_0 ), + .datac(\inst|vga_control_unit|N_6_i_0_g0_0 ), + .datad(\inst|vga_control_unit|b_next_i_a7_1 ), + .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_control_unit|b ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|b_Z .lut_mask = "0070"; +defparam \inst|vga_control_unit|b_Z .operation_mode = "normal"; +defparam \inst|vga_control_unit|b_Z .output_mode = "reg_only"; +defparam \inst|vga_control_unit|b_Z .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|b_Z .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|b_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N5 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_1_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [1] = \inst|vga_driver_unit|d_set_hsync_counter $ \inst|vga_driver_unit|line_counter_sig_0 +// \inst|vga_driver_unit|un1_line_counter_sig_cout [1] = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|d_set_hsync_counter ), + .datab(\inst|vga_driver_unit|line_counter_sig_0 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [1]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [1]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .lut_mask = "6688"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N6 +stratix_lcell \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 = \reset~combout & !\inst|vga_driver_unit|vsync_state_1 & \inst|dly_counter [0] & \inst|dly_counter [1] + + .clk(gnd), + .dataa(\reset~combout ), + .datab(\inst|vga_driver_unit|vsync_state_1 ), + .datac(\inst|dly_counter [0]), + .datad(\inst|dly_counter [1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .lut_mask = "2000"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N6 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_0_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_0 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [1] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un1_line_counter_sig_combout [1]), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_0 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_0_ .lut_mask = "afaf"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N6 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_3_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [3] = \inst|vga_driver_unit|line_counter_sig_2 $ (\inst|vga_driver_unit|line_counter_sig_1 & \inst|vga_driver_unit|un1_line_counter_sig_cout [1]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [3] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [1] # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_1 ), + .datab(\inst|vga_driver_unit|line_counter_sig_2 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [1]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [3]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [3]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .lut_mask = "6c7f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y31_N2 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_2_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_2 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [3] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un1_line_counter_sig_combout [3]), + .datac(vcc), + .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_2 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_2_ .lut_mask = "ccff"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N0 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_a_1_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_a_cout [1] = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 ) +// \inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|d_set_hsync_counter ), + .datab(\inst|vga_driver_unit|line_counter_sig_0 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT ), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .lut_mask = "ff88"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .output_mode = "none"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N1 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_2_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [2] = \inst|vga_driver_unit|line_counter_sig_1 $ (\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [2] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1] # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_1 ), + .datab(\inst|vga_driver_unit|line_counter_sig_2 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [2]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [2]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .lut_mask = "5a7f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N7 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_1_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_1 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [2] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un1_line_counter_sig_combout [2]), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_1 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_1_ .lut_mask = "cfcf"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N2 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_4_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [4] = \inst|vga_driver_unit|line_counter_sig_3 $ !\inst|vga_driver_unit|un1_line_counter_sig_cout [2] +// \inst|vga_driver_unit|un1_line_counter_sig_cout [4] = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [2]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_4 ), + .datab(\inst|vga_driver_unit|line_counter_sig_3 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [2]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [4]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [4]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .lut_mask = "c308"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N5 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_3_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_3 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [4] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [4]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_3 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_3_ .lut_mask = "ff0f"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N7 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_5_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [5] = \inst|vga_driver_unit|line_counter_sig_4 $ (\inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [3]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [5] = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [3]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_4 ), + .datab(\inst|vga_driver_unit|line_counter_sig_3 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [3]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [5]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [5]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .lut_mask = "a608"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N4 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_4_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_4 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [5] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un1_line_counter_sig_combout [5]), + .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_4 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_4_ .lut_mask = "f0ff"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N3 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_6_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [6] = \inst|vga_driver_unit|line_counter_sig_5 $ (\inst|vga_driver_unit|un1_line_counter_sig_cout [4]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [6] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [4] # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_5 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_5 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_5 ), + .datab(\inst|vga_driver_unit|line_counter_sig_6 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [4]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [6]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [6]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .lut_mask = "5a7f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N8 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_5_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_5 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [6] & \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 & \inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), +// VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un1_line_counter_sig_combout [6]), + .datab(\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_5 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_5_ .lut_mask = "8080"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N8 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_7_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [7] = \inst|vga_driver_unit|line_counter_sig_6 $ (\inst|vga_driver_unit|line_counter_sig_5 & \inst|vga_driver_unit|un1_line_counter_sig_cout [5]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [7] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [5] # !\inst|vga_driver_unit|line_counter_sig_5 # !\inst|vga_driver_unit|line_counter_sig_6 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 # !\inst|vga_driver_unit|line_counter_sig_5 # !\inst|vga_driver_unit|line_counter_sig_6 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_6 ), + .datab(\inst|vga_driver_unit|line_counter_sig_5 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [5]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [7]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [7]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .lut_mask = "6a7f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y31_N4 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_6_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_6 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [7] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un1_line_counter_sig_combout [7]), + .datac(vcc), + .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_6 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_6_ .lut_mask = "ccff"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N1 +stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 ( +// Equation(s): +// \inst|vga_driver_unit|un10_line_counter_siglt4_2 = !\inst|vga_driver_unit|line_counter_sig_3 # !\inst|vga_driver_unit|line_counter_sig_0 # !\inst|vga_driver_unit|line_counter_sig_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_4 ), + .datab(\inst|vga_driver_unit|line_counter_sig_0 ), + .datac(\inst|vga_driver_unit|line_counter_sig_3 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_line_counter_siglt4_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .lut_mask = "7f7f"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N3 +stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 ( +// Equation(s): +// \inst|vga_driver_unit|un10_line_counter_siglto5 = !\inst|vga_driver_unit|line_counter_sig_5 & (\inst|vga_driver_unit|un10_line_counter_siglt4_2 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_1 ), + .datab(\inst|vga_driver_unit|un10_line_counter_siglt4_2 ), + .datac(\inst|vga_driver_unit|line_counter_sig_5 ), + .datad(\inst|vga_driver_unit|line_counter_sig_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_line_counter_siglto5 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .lut_mask = "0d0f"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N2 +stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 ( +// Equation(s): +// \inst|vga_driver_unit|un10_line_counter_siglto8 = \inst|vga_driver_unit|un10_line_counter_siglto5 # !\inst|vga_driver_unit|line_counter_sig_7 # !\inst|vga_driver_unit|line_counter_sig_8 # !\inst|vga_driver_unit|line_counter_sig_6 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_6 ), + .datab(\inst|vga_driver_unit|line_counter_sig_8 ), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto5 ), + .datad(\inst|vga_driver_unit|line_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .lut_mask = "f7ff"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N4 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_8_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [8] = \inst|vga_driver_unit|un1_line_counter_sig_cout [6] $ !\inst|vga_driver_unit|line_counter_sig_7 + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|line_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [6]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [8]), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .lut_mask = "f00f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N9 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_7_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_7 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [8] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [8]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_7 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_7_ .lut_mask = "ff0f"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N9 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_9_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [9] = \inst|vga_driver_unit|line_counter_sig_8 $ (!\inst|vga_driver_unit|un1_line_counter_sig_cout [7] & \inst|vga_driver_unit|line_counter_sig_7 ) + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|line_counter_sig_8 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|line_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [7]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [9]), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .lut_mask = "c3cc"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N0 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_8_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_8 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [9] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un1_line_counter_sig_combout [9]), + .datac(vcc), + .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_8 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_8_ .lut_mask = "ccff"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X41_Y19_N2 +stratix_lcell \~STRATIX_FITTER_CREATED_GND~I ( +// Equation(s): +// \~STRATIX_FITTER_CREATED_GND~I_combout = GND + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\~STRATIX_FITTER_CREATED_GND~I_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \~STRATIX_FITTER_CREATED_GND~I .lut_mask = "0000"; +defparam \~STRATIX_FITTER_CREATED_GND~I .operation_mode = "normal"; +defparam \~STRATIX_FITTER_CREATED_GND~I .output_mode = "comb_only"; +defparam \~STRATIX_FITTER_CREATED_GND~I .register_cascade_mode = "off"; +defparam \~STRATIX_FITTER_CREATED_GND~I .sum_lutc_input = "datac"; +defparam \~STRATIX_FITTER_CREATED_GND~I .synch_mode = "off"; +// synopsys translate_on + +// atom is at PIN_L7 +stratix_io \inst|d_hsync_out~I ( + .datain(\inst|vga_driver_unit|h_sync ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_out~I .ddio_mode = "none"; +defparam \inst|d_hsync_out~I .input_async_reset = "none"; +defparam \inst|d_hsync_out~I .input_power_up = "low"; +defparam \inst|d_hsync_out~I .input_register_mode = "none"; +defparam \inst|d_hsync_out~I .input_sync_reset = "none"; +defparam \inst|d_hsync_out~I .oe_async_reset = "none"; +defparam \inst|d_hsync_out~I .oe_power_up = "low"; +defparam \inst|d_hsync_out~I .oe_register_mode = "none"; +defparam \inst|d_hsync_out~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_out~I .operation_mode = "output"; +defparam \inst|d_hsync_out~I .output_async_reset = "none"; +defparam \inst|d_hsync_out~I .output_power_up = "low"; +defparam \inst|d_hsync_out~I .output_register_mode = "none"; +defparam \inst|d_hsync_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L5 +stratix_io \inst|d_vsync_out~I ( + .datain(\inst|vga_driver_unit|v_sync ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_out~I .ddio_mode = "none"; +defparam \inst|d_vsync_out~I .input_async_reset = "none"; +defparam \inst|d_vsync_out~I .input_power_up = "low"; +defparam \inst|d_vsync_out~I .input_register_mode = "none"; +defparam \inst|d_vsync_out~I .input_sync_reset = "none"; +defparam \inst|d_vsync_out~I .oe_async_reset = "none"; +defparam \inst|d_vsync_out~I .oe_power_up = "low"; +defparam \inst|d_vsync_out~I .oe_register_mode = "none"; +defparam \inst|d_vsync_out~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_out~I .operation_mode = "output"; +defparam \inst|d_vsync_out~I .output_async_reset = "none"; +defparam \inst|d_vsync_out~I .output_power_up = "low"; +defparam \inst|d_vsync_out~I .output_register_mode = "none"; +defparam \inst|d_vsync_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_Y23 +stratix_io \inst|d_set_column_counter_out~I ( + .datain(\inst|vga_driver_unit|hsync_state_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_set_column_counter), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_set_column_counter_out~I .ddio_mode = "none"; +defparam \inst|d_set_column_counter_out~I .input_async_reset = "none"; +defparam \inst|d_set_column_counter_out~I .input_power_up = "low"; +defparam \inst|d_set_column_counter_out~I .input_register_mode = "none"; +defparam \inst|d_set_column_counter_out~I .input_sync_reset = "none"; +defparam \inst|d_set_column_counter_out~I .oe_async_reset = "none"; +defparam \inst|d_set_column_counter_out~I .oe_power_up = "low"; +defparam \inst|d_set_column_counter_out~I .oe_register_mode = "none"; +defparam \inst|d_set_column_counter_out~I .oe_sync_reset = "none"; +defparam \inst|d_set_column_counter_out~I .operation_mode = "output"; +defparam \inst|d_set_column_counter_out~I .output_async_reset = "none"; +defparam \inst|d_set_column_counter_out~I .output_power_up = "low"; +defparam \inst|d_set_column_counter_out~I .output_register_mode = "none"; +defparam \inst|d_set_column_counter_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F21 +stratix_io \inst|d_set_line_counter_out~I ( + .datain(\inst|vga_driver_unit|vsync_state_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_set_line_counter), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_set_line_counter_out~I .ddio_mode = "none"; +defparam \inst|d_set_line_counter_out~I .input_async_reset = "none"; +defparam \inst|d_set_line_counter_out~I .input_power_up = "low"; +defparam \inst|d_set_line_counter_out~I .input_register_mode = "none"; +defparam \inst|d_set_line_counter_out~I .input_sync_reset = "none"; +defparam \inst|d_set_line_counter_out~I .oe_async_reset = "none"; +defparam \inst|d_set_line_counter_out~I .oe_power_up = "low"; +defparam \inst|d_set_line_counter_out~I .oe_register_mode = "none"; +defparam \inst|d_set_line_counter_out~I .oe_sync_reset = "none"; +defparam \inst|d_set_line_counter_out~I .operation_mode = "output"; +defparam \inst|d_set_line_counter_out~I .output_async_reset = "none"; +defparam \inst|d_set_line_counter_out~I .output_power_up = "low"; +defparam \inst|d_set_line_counter_out~I .output_register_mode = "none"; +defparam \inst|d_set_line_counter_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F26 +stratix_io \inst|d_set_hsync_counter_out~I ( + .datain(\inst|vga_driver_unit|d_set_hsync_counter ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_set_hsync_counter), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_set_hsync_counter_out~I .ddio_mode = "none"; +defparam \inst|d_set_hsync_counter_out~I .input_async_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .input_power_up = "low"; +defparam \inst|d_set_hsync_counter_out~I .input_register_mode = "none"; +defparam \inst|d_set_hsync_counter_out~I .input_sync_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .oe_async_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .oe_power_up = "low"; +defparam \inst|d_set_hsync_counter_out~I .oe_register_mode = "none"; +defparam \inst|d_set_hsync_counter_out~I .oe_sync_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .operation_mode = "output"; +defparam \inst|d_set_hsync_counter_out~I .output_async_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .output_power_up = "low"; +defparam \inst|d_set_hsync_counter_out~I .output_register_mode = "none"; +defparam \inst|d_set_hsync_counter_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F24 +stratix_io \inst|d_set_vsync_counter_out~I ( + .datain(\inst|vga_driver_unit|d_set_vsync_counter ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_set_vsync_counter), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_set_vsync_counter_out~I .ddio_mode = "none"; +defparam \inst|d_set_vsync_counter_out~I .input_async_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .input_power_up = "low"; +defparam \inst|d_set_vsync_counter_out~I .input_register_mode = "none"; +defparam \inst|d_set_vsync_counter_out~I .input_sync_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .oe_async_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .oe_power_up = "low"; +defparam \inst|d_set_vsync_counter_out~I .oe_register_mode = "none"; +defparam \inst|d_set_vsync_counter_out~I .oe_sync_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .operation_mode = "output"; +defparam \inst|d_set_vsync_counter_out~I .output_async_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .output_power_up = "low"; +defparam \inst|d_set_vsync_counter_out~I .output_register_mode = "none"; +defparam \inst|d_set_vsync_counter_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L3 +stratix_io \inst|d_r_out~I ( + .datain(\inst|vga_control_unit|r ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_r), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_r_out~I .ddio_mode = "none"; +defparam \inst|d_r_out~I .input_async_reset = "none"; +defparam \inst|d_r_out~I .input_power_up = "low"; +defparam \inst|d_r_out~I .input_register_mode = "none"; +defparam \inst|d_r_out~I .input_sync_reset = "none"; +defparam \inst|d_r_out~I .oe_async_reset = "none"; +defparam \inst|d_r_out~I .oe_power_up = "low"; +defparam \inst|d_r_out~I .oe_register_mode = "none"; +defparam \inst|d_r_out~I .oe_sync_reset = "none"; +defparam \inst|d_r_out~I .operation_mode = "output"; +defparam \inst|d_r_out~I .output_async_reset = "none"; +defparam \inst|d_r_out~I .output_power_up = "low"; +defparam \inst|d_r_out~I .output_register_mode = "none"; +defparam \inst|d_r_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K24 +stratix_io \inst|d_g_out~I ( + .datain(\inst|vga_control_unit|g ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_g), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_g_out~I .ddio_mode = "none"; +defparam \inst|d_g_out~I .input_async_reset = "none"; +defparam \inst|d_g_out~I .input_power_up = "low"; +defparam \inst|d_g_out~I .input_register_mode = "none"; +defparam \inst|d_g_out~I .input_sync_reset = "none"; +defparam \inst|d_g_out~I .oe_async_reset = "none"; +defparam \inst|d_g_out~I .oe_power_up = "low"; +defparam \inst|d_g_out~I .oe_register_mode = "none"; +defparam \inst|d_g_out~I .oe_sync_reset = "none"; +defparam \inst|d_g_out~I .operation_mode = "output"; +defparam \inst|d_g_out~I .output_async_reset = "none"; +defparam \inst|d_g_out~I .output_power_up = "low"; +defparam \inst|d_g_out~I .output_register_mode = "none"; +defparam \inst|d_g_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K20 +stratix_io \inst|d_b_out~I ( + .datain(\inst|vga_control_unit|b ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_b), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_b_out~I .ddio_mode = "none"; +defparam \inst|d_b_out~I .input_async_reset = "none"; +defparam \inst|d_b_out~I .input_power_up = "low"; +defparam \inst|d_b_out~I .input_register_mode = "none"; +defparam \inst|d_b_out~I .input_sync_reset = "none"; +defparam \inst|d_b_out~I .oe_async_reset = "none"; +defparam \inst|d_b_out~I .oe_power_up = "low"; +defparam \inst|d_b_out~I .oe_register_mode = "none"; +defparam \inst|d_b_out~I .oe_sync_reset = "none"; +defparam \inst|d_b_out~I .operation_mode = "output"; +defparam \inst|d_b_out~I .output_async_reset = "none"; +defparam \inst|d_b_out~I .output_power_up = "low"; +defparam \inst|d_b_out~I .output_register_mode = "none"; +defparam \inst|d_b_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_J21 +stratix_io \inst|d_h_enable_out~I ( + .datain(\inst|vga_driver_unit|h_enable_sig ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_h_enable), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_h_enable_out~I .ddio_mode = "none"; +defparam \inst|d_h_enable_out~I .input_async_reset = "none"; +defparam \inst|d_h_enable_out~I .input_power_up = "low"; +defparam \inst|d_h_enable_out~I .input_register_mode = "none"; +defparam \inst|d_h_enable_out~I .input_sync_reset = "none"; +defparam \inst|d_h_enable_out~I .oe_async_reset = "none"; +defparam \inst|d_h_enable_out~I .oe_power_up = "low"; +defparam \inst|d_h_enable_out~I .oe_register_mode = "none"; +defparam \inst|d_h_enable_out~I .oe_sync_reset = "none"; +defparam \inst|d_h_enable_out~I .operation_mode = "output"; +defparam \inst|d_h_enable_out~I .output_async_reset = "none"; +defparam \inst|d_h_enable_out~I .output_power_up = "low"; +defparam \inst|d_h_enable_out~I .output_register_mode = "none"; +defparam \inst|d_h_enable_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_H18 +stratix_io \inst|d_v_enable_out~I ( + .datain(\inst|vga_driver_unit|v_enable_sig ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_v_enable), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_v_enable_out~I .ddio_mode = "none"; +defparam \inst|d_v_enable_out~I .input_async_reset = "none"; +defparam \inst|d_v_enable_out~I .input_power_up = "low"; +defparam \inst|d_v_enable_out~I .input_register_mode = "none"; +defparam \inst|d_v_enable_out~I .input_sync_reset = "none"; +defparam \inst|d_v_enable_out~I .oe_async_reset = "none"; +defparam \inst|d_v_enable_out~I .oe_power_up = "low"; +defparam \inst|d_v_enable_out~I .oe_register_mode = "none"; +defparam \inst|d_v_enable_out~I .oe_sync_reset = "none"; +defparam \inst|d_v_enable_out~I .operation_mode = "output"; +defparam \inst|d_v_enable_out~I .output_async_reset = "none"; +defparam \inst|d_v_enable_out~I .output_power_up = "low"; +defparam \inst|d_v_enable_out~I .output_register_mode = "none"; +defparam \inst|d_v_enable_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K3 +stratix_io \inst|d_state_clk_out~I ( + .datain(\inst1|altpll_component|_clk0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_state_clk), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_state_clk_out~I .ddio_mode = "none"; +defparam \inst|d_state_clk_out~I .input_async_reset = "none"; +defparam \inst|d_state_clk_out~I .input_power_up = "low"; +defparam \inst|d_state_clk_out~I .input_register_mode = "none"; +defparam \inst|d_state_clk_out~I .input_sync_reset = "none"; +defparam \inst|d_state_clk_out~I .oe_async_reset = "none"; +defparam \inst|d_state_clk_out~I .oe_power_up = "low"; +defparam \inst|d_state_clk_out~I .oe_register_mode = "none"; +defparam \inst|d_state_clk_out~I .oe_sync_reset = "none"; +defparam \inst|d_state_clk_out~I .operation_mode = "output"; +defparam \inst|d_state_clk_out~I .output_async_reset = "none"; +defparam \inst|d_state_clk_out~I .output_power_up = "low"; +defparam \inst|d_state_clk_out~I .output_register_mode = "none"; +defparam \inst|d_state_clk_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_E22 +stratix_io \inst|r0_pin_out~I ( + .datain(\inst|vga_control_unit|r ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(r0_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|r0_pin_out~I .ddio_mode = "none"; +defparam \inst|r0_pin_out~I .input_async_reset = "none"; +defparam \inst|r0_pin_out~I .input_power_up = "low"; +defparam \inst|r0_pin_out~I .input_register_mode = "none"; +defparam \inst|r0_pin_out~I .input_sync_reset = "none"; +defparam \inst|r0_pin_out~I .oe_async_reset = "none"; +defparam \inst|r0_pin_out~I .oe_power_up = "low"; +defparam \inst|r0_pin_out~I .oe_register_mode = "none"; +defparam \inst|r0_pin_out~I .oe_sync_reset = "none"; +defparam \inst|r0_pin_out~I .operation_mode = "output"; +defparam \inst|r0_pin_out~I .output_async_reset = "none"; +defparam \inst|r0_pin_out~I .output_power_up = "low"; +defparam \inst|r0_pin_out~I .output_register_mode = "none"; +defparam \inst|r0_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T4 +stratix_io \inst|r1_pin_out~I ( + .datain(\inst|vga_control_unit|r ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(r1_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|r1_pin_out~I .ddio_mode = "none"; +defparam \inst|r1_pin_out~I .input_async_reset = "none"; +defparam \inst|r1_pin_out~I .input_power_up = "low"; +defparam \inst|r1_pin_out~I .input_register_mode = "none"; +defparam \inst|r1_pin_out~I .input_sync_reset = "none"; +defparam \inst|r1_pin_out~I .oe_async_reset = "none"; +defparam \inst|r1_pin_out~I .oe_power_up = "low"; +defparam \inst|r1_pin_out~I .oe_register_mode = "none"; +defparam \inst|r1_pin_out~I .oe_sync_reset = "none"; +defparam \inst|r1_pin_out~I .operation_mode = "output"; +defparam \inst|r1_pin_out~I .output_async_reset = "none"; +defparam \inst|r1_pin_out~I .output_power_up = "low"; +defparam \inst|r1_pin_out~I .output_register_mode = "none"; +defparam \inst|r1_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T7 +stratix_io \inst|r2_pin_out~I ( + .datain(\inst|vga_control_unit|r ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(r2_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|r2_pin_out~I .ddio_mode = "none"; +defparam \inst|r2_pin_out~I .input_async_reset = "none"; +defparam \inst|r2_pin_out~I .input_power_up = "low"; +defparam \inst|r2_pin_out~I .input_register_mode = "none"; +defparam \inst|r2_pin_out~I .input_sync_reset = "none"; +defparam \inst|r2_pin_out~I .oe_async_reset = "none"; +defparam \inst|r2_pin_out~I .oe_power_up = "low"; +defparam \inst|r2_pin_out~I .oe_register_mode = "none"; +defparam \inst|r2_pin_out~I .oe_sync_reset = "none"; +defparam \inst|r2_pin_out~I .operation_mode = "output"; +defparam \inst|r2_pin_out~I .output_async_reset = "none"; +defparam \inst|r2_pin_out~I .output_power_up = "low"; +defparam \inst|r2_pin_out~I .output_register_mode = "none"; +defparam \inst|r2_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_E23 +stratix_io \inst|g0_pin_out~I ( + .datain(\inst|vga_control_unit|g ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(g0_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|g0_pin_out~I .ddio_mode = "none"; +defparam \inst|g0_pin_out~I .input_async_reset = "none"; +defparam \inst|g0_pin_out~I .input_power_up = "low"; +defparam \inst|g0_pin_out~I .input_register_mode = "none"; +defparam \inst|g0_pin_out~I .input_sync_reset = "none"; +defparam \inst|g0_pin_out~I .oe_async_reset = "none"; +defparam \inst|g0_pin_out~I .oe_power_up = "low"; +defparam \inst|g0_pin_out~I .oe_register_mode = "none"; +defparam \inst|g0_pin_out~I .oe_sync_reset = "none"; +defparam \inst|g0_pin_out~I .operation_mode = "output"; +defparam \inst|g0_pin_out~I .output_async_reset = "none"; +defparam \inst|g0_pin_out~I .output_power_up = "low"; +defparam \inst|g0_pin_out~I .output_register_mode = "none"; +defparam \inst|g0_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T5 +stratix_io \inst|g1_pin_out~I ( + .datain(\inst|vga_control_unit|g ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(g1_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|g1_pin_out~I .ddio_mode = "none"; +defparam \inst|g1_pin_out~I .input_async_reset = "none"; +defparam \inst|g1_pin_out~I .input_power_up = "low"; +defparam \inst|g1_pin_out~I .input_register_mode = "none"; +defparam \inst|g1_pin_out~I .input_sync_reset = "none"; +defparam \inst|g1_pin_out~I .oe_async_reset = "none"; +defparam \inst|g1_pin_out~I .oe_power_up = "low"; +defparam \inst|g1_pin_out~I .oe_register_mode = "none"; +defparam \inst|g1_pin_out~I .oe_sync_reset = "none"; +defparam \inst|g1_pin_out~I .operation_mode = "output"; +defparam \inst|g1_pin_out~I .output_async_reset = "none"; +defparam \inst|g1_pin_out~I .output_power_up = "low"; +defparam \inst|g1_pin_out~I .output_register_mode = "none"; +defparam \inst|g1_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T24 +stratix_io \inst|g2_pin_out~I ( + .datain(\inst|vga_control_unit|g ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(g2_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|g2_pin_out~I .ddio_mode = "none"; +defparam \inst|g2_pin_out~I .input_async_reset = "none"; +defparam \inst|g2_pin_out~I .input_power_up = "low"; +defparam \inst|g2_pin_out~I .input_register_mode = "none"; +defparam \inst|g2_pin_out~I .input_sync_reset = "none"; +defparam \inst|g2_pin_out~I .oe_async_reset = "none"; +defparam \inst|g2_pin_out~I .oe_power_up = "low"; +defparam \inst|g2_pin_out~I .oe_register_mode = "none"; +defparam \inst|g2_pin_out~I .oe_sync_reset = "none"; +defparam \inst|g2_pin_out~I .operation_mode = "output"; +defparam \inst|g2_pin_out~I .output_async_reset = "none"; +defparam \inst|g2_pin_out~I .output_power_up = "low"; +defparam \inst|g2_pin_out~I .output_register_mode = "none"; +defparam \inst|g2_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_E24 +stratix_io \inst|b0_pin_out~I ( + .datain(\inst|vga_control_unit|b ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(b0_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|b0_pin_out~I .ddio_mode = "none"; +defparam \inst|b0_pin_out~I .input_async_reset = "none"; +defparam \inst|b0_pin_out~I .input_power_up = "low"; +defparam \inst|b0_pin_out~I .input_register_mode = "none"; +defparam \inst|b0_pin_out~I .input_sync_reset = "none"; +defparam \inst|b0_pin_out~I .oe_async_reset = "none"; +defparam \inst|b0_pin_out~I .oe_power_up = "low"; +defparam \inst|b0_pin_out~I .oe_register_mode = "none"; +defparam \inst|b0_pin_out~I .oe_sync_reset = "none"; +defparam \inst|b0_pin_out~I .operation_mode = "output"; +defparam \inst|b0_pin_out~I .output_async_reset = "none"; +defparam \inst|b0_pin_out~I .output_power_up = "low"; +defparam \inst|b0_pin_out~I .output_register_mode = "none"; +defparam \inst|b0_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T6 +stratix_io \inst|b1_pin_out~I ( + .datain(\inst|vga_control_unit|b ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(b1_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|b1_pin_out~I .ddio_mode = "none"; +defparam \inst|b1_pin_out~I .input_async_reset = "none"; +defparam \inst|b1_pin_out~I .input_power_up = "low"; +defparam \inst|b1_pin_out~I .input_register_mode = "none"; +defparam \inst|b1_pin_out~I .input_sync_reset = "none"; +defparam \inst|b1_pin_out~I .oe_async_reset = "none"; +defparam \inst|b1_pin_out~I .oe_power_up = "low"; +defparam \inst|b1_pin_out~I .oe_register_mode = "none"; +defparam \inst|b1_pin_out~I .oe_sync_reset = "none"; +defparam \inst|b1_pin_out~I .operation_mode = "output"; +defparam \inst|b1_pin_out~I .output_async_reset = "none"; +defparam \inst|b1_pin_out~I .output_power_up = "low"; +defparam \inst|b1_pin_out~I .output_register_mode = "none"; +defparam \inst|b1_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F1 +stratix_io \inst|hsync_pin_out~I ( + .datain(\inst|vga_driver_unit|h_sync ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(hsync_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|hsync_pin_out~I .ddio_mode = "none"; +defparam \inst|hsync_pin_out~I .input_async_reset = "none"; +defparam \inst|hsync_pin_out~I .input_power_up = "low"; +defparam \inst|hsync_pin_out~I .input_register_mode = "none"; +defparam \inst|hsync_pin_out~I .input_sync_reset = "none"; +defparam \inst|hsync_pin_out~I .oe_async_reset = "none"; +defparam \inst|hsync_pin_out~I .oe_power_up = "low"; +defparam \inst|hsync_pin_out~I .oe_register_mode = "none"; +defparam \inst|hsync_pin_out~I .oe_sync_reset = "none"; +defparam \inst|hsync_pin_out~I .operation_mode = "output"; +defparam \inst|hsync_pin_out~I .output_async_reset = "none"; +defparam \inst|hsync_pin_out~I .output_power_up = "low"; +defparam \inst|hsync_pin_out~I .output_register_mode = "none"; +defparam \inst|hsync_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F2 +stratix_io \inst|vsync_pin_out~I ( + .datain(\inst|vga_driver_unit|v_sync ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(vsync_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|vsync_pin_out~I .ddio_mode = "none"; +defparam \inst|vsync_pin_out~I .input_async_reset = "none"; +defparam \inst|vsync_pin_out~I .input_power_up = "low"; +defparam \inst|vsync_pin_out~I .input_register_mode = "none"; +defparam \inst|vsync_pin_out~I .input_sync_reset = "none"; +defparam \inst|vsync_pin_out~I .oe_async_reset = "none"; +defparam \inst|vsync_pin_out~I .oe_power_up = "low"; +defparam \inst|vsync_pin_out~I .oe_register_mode = "none"; +defparam \inst|vsync_pin_out~I .oe_sync_reset = "none"; +defparam \inst|vsync_pin_out~I .operation_mode = "output"; +defparam \inst|vsync_pin_out~I .output_async_reset = "none"; +defparam \inst|vsync_pin_out~I .output_power_up = "low"; +defparam \inst|vsync_pin_out~I .output_register_mode = "none"; +defparam \inst|vsync_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K5 +stratix_io \inst|d_column_counter_out_9_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_9 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[9]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_9_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_9_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_9_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_9_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_9_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_9_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_9_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_9_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_9_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K19 +stratix_io \inst|d_column_counter_out_8_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_8 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_8_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_8_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_8_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_8_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_8_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_8_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_8_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_8_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K23 +stratix_io \inst|d_column_counter_out_7_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_7 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_7_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_7_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_7_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_7_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_7_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_7_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_7_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_7_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L2 +stratix_io \inst|d_column_counter_out_6_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_6_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_6_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_6_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_6_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_6_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L4 +stratix_io \inst|d_column_counter_out_5_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_5_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_5_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_5_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_5_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_5_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L6 +stratix_io \inst|d_column_counter_out_4_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_4_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_4_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_4_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_4_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_4_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L20 +stratix_io \inst|d_column_counter_out_3_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_3_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_3_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_3_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_3_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_3_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L21 +stratix_io \inst|d_column_counter_out_2_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_2_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_2_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_2_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_2_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_2_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L22 +stratix_io \inst|d_column_counter_out_1_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_1_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_1_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_1_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_1_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_1_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L23 +stratix_io \inst|d_column_counter_out_0_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_0_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_0_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_0_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_0_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_0_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G18 +stratix_io \inst|d_hsync_counter_out_9_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_9 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[9]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_9_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_9_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_9_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_9_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_9_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_9_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_9_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_9_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_9_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G22 +stratix_io \inst|d_hsync_counter_out_8_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_8 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_8_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_8_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_8_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_8_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_8_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_8_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_8_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_8_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G25 +stratix_io \inst|d_hsync_counter_out_7_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_7 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_7_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_7_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_7_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_7_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_7_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_7_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_7_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_7_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_A17 +stratix_io \inst|d_hsync_counter_out_6_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_6_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_6_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_6_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_6_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_6_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F25 +stratix_io \inst|d_hsync_counter_out_5_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_5_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_5_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_5_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_5_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_5_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_D17 +stratix_io \inst|d_hsync_counter_out_4_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_4_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_4_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_4_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_4_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_4_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AE16 +stratix_io \inst|d_hsync_counter_out_3_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_3_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_3_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_3_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_3_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_3_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G17 +stratix_io \inst|d_hsync_counter_out_2_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_2_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_2_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_2_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_2_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_2_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AA17 +stratix_io \inst|d_hsync_counter_out_1_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_1_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_1_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_1_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_1_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_1_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_H4 +stratix_io \inst|d_hsync_counter_out_0_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_0_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_0_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_0_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_0_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_0_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_Y5 +stratix_io \inst|d_hsync_state_out_0_~I ( + .datain(\inst|vga_driver_unit|hsync_state_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_0_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_0_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_0_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_0_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_0_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F19 +stratix_io \inst|d_hsync_state_out_1_~I ( + .datain(\inst|vga_driver_unit|hsync_state_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_1_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_1_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_1_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_1_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_1_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F17 +stratix_io \inst|d_hsync_state_out_2_~I ( + .datain(\inst|vga_driver_unit|hsync_state_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_2_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_2_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_2_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_2_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_2_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_Y2 +stratix_io \inst|d_hsync_state_out_3_~I ( + .datain(\inst|vga_driver_unit|hsync_state_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_3_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_3_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_3_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_3_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_3_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F10 +stratix_io \inst|d_hsync_state_out_4_~I ( + .datain(\inst|vga_driver_unit|hsync_state_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_4_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_4_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_4_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_4_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_4_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F9 +stratix_io \inst|d_hsync_state_out_5_~I ( + .datain(\inst|vga_driver_unit|hsync_state_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_5_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_5_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_5_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_5_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_5_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F6 +stratix_io \inst|d_hsync_state_out_6_~I ( + .datain(\inst|vga_driver_unit|hsync_state_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_6_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_6_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_6_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_6_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_6_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L25 +stratix_io \inst|d_line_counter_out_8_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_8 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_8_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_8_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_8_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_8_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_8_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_8_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_8_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_8_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L24 +stratix_io \inst|d_line_counter_out_7_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_7 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_7_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_7_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_7_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_7_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_7_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_7_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_7_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_7_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M5 +stratix_io \inst|d_line_counter_out_6_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_6_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_6_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_6_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_6_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_6_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M6 +stratix_io \inst|d_line_counter_out_5_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_5_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_5_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_5_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_5_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_5_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M8 +stratix_io \inst|d_line_counter_out_4_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_4_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_4_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_4_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_4_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_4_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M9 +stratix_io \inst|d_line_counter_out_3_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_3_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_3_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_3_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_3_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_3_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_J22 +stratix_io \inst|d_line_counter_out_2_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_2_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_2_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_2_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_2_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_2_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K4 +stratix_io \inst|d_line_counter_out_1_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_1_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_1_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_1_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_1_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_1_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K6 +stratix_io \inst|d_line_counter_out_0_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_0_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_0_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_0_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_0_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_0_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G2 +stratix_io \inst|d_vsync_counter_out_9_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_9 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[9]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_9_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_9_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_9_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_9_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_9_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_9_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_9_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_9_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_9_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G4 +stratix_io \inst|d_vsync_counter_out_8_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_8 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_8_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_8_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_8_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_8_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_8_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_8_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_8_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_8_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G6 +stratix_io \inst|d_vsync_counter_out_7_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_7 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_7_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_7_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_7_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_7_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_7_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_7_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_7_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_7_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K21 +stratix_io \inst|d_vsync_counter_out_6_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_6_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_6_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_6_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_6_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_6_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AA14 +stratix_io \inst|d_vsync_counter_out_5_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_5_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_5_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_5_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_5_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_5_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AB12 +stratix_io \inst|d_vsync_counter_out_4_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_4_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_4_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_4_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_4_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_4_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K7 +stratix_io \inst|d_vsync_counter_out_3_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_3_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_3_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_3_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_3_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_3_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_E12 +stratix_io \inst|d_vsync_counter_out_2_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_2_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_2_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_2_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_2_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_2_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F14 +stratix_io \inst|d_vsync_counter_out_1_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_1_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_1_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_1_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_1_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_1_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G9 +stratix_io \inst|d_vsync_counter_out_0_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_0_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_0_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_0_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_0_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_0_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F5 +stratix_io \inst|d_vsync_state_out_0_~I ( + .datain(\inst|vga_driver_unit|vsync_state_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_0_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_0_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_0_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_0_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_0_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F4 +stratix_io \inst|d_vsync_state_out_1_~I ( + .datain(\inst|vga_driver_unit|vsync_state_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_1_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_1_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_1_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_1_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_1_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F3 +stratix_io \inst|d_vsync_state_out_2_~I ( + .datain(\inst|vga_driver_unit|vsync_state_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_2_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_2_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_2_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_2_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_2_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M19 +stratix_io \inst|d_vsync_state_out_3_~I ( + .datain(\inst|vga_driver_unit|vsync_state_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_3_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_3_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_3_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_3_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_3_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M18 +stratix_io \inst|d_vsync_state_out_4_~I ( + .datain(\inst|vga_driver_unit|vsync_state_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_4_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_4_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_4_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_4_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_4_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M7 +stratix_io \inst|d_vsync_state_out_5_~I ( + .datain(\inst|vga_driver_unit|vsync_state_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_5_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_5_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_5_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_5_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_5_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M4 +stratix_io \inst|d_vsync_state_out_6_~I ( + .datain(\inst|vga_driver_unit|vsync_state_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_6_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_6_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_6_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_6_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_6_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T2 +stratix_io \inst|seven_seg_pin_tri_13_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[13]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_13_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_13_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_13_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_13_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_13_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AA11 +stratix_io \inst|seven_seg_pin_out_12_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[12]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_12_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_12_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_12_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_12_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_12_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_12_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_12_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_12_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_12_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R6 +stratix_io \inst|seven_seg_pin_out_11_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[11]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_11_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_11_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_11_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_11_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_11_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_11_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_11_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_11_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_11_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R4 +stratix_io \inst|seven_seg_pin_out_10_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[10]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_10_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_10_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_10_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_10_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_10_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_10_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_10_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_10_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_10_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_N8 +stratix_io \inst|seven_seg_pin_out_9_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[9]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_9_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_9_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_9_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_9_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_9_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_9_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_9_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_9_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_9_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_N7 +stratix_io \inst|seven_seg_pin_out_8_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_8_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_8_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_8_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_8_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_8_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_8_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_8_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_8_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_Y11 +stratix_io \inst|seven_seg_pin_out_7_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_7_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_7_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_7_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_7_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_7_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_7_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_7_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_7_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R23 +stratix_io \inst|seven_seg_pin_tri_6_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_6_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_6_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_6_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_6_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_6_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R22 +stratix_io \inst|seven_seg_pin_tri_5_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_5_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_5_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_5_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_5_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_5_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R21 +stratix_io \inst|seven_seg_pin_tri_4_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_4_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_4_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_4_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_4_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_4_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R20 +stratix_io \inst|seven_seg_pin_tri_3_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_3_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_3_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_3_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_3_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_3_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R19 +stratix_io \inst|seven_seg_pin_out_2_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_2_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_2_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_2_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_2_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_2_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_2_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_2_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_2_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R9 +stratix_io \inst|seven_seg_pin_out_1_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_1_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_1_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_1_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_1_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_1_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_1_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_1_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_1_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R8 +stratix_io \inst|seven_seg_pin_tri_0_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_0_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_0_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_0_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_0_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_0_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll_modelsim.xrf b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll_modelsim.xrf new file mode 100644 index 0000000..adfa90e --- /dev/null +++ b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll_modelsim.xrf @@ -0,0 +1,246 @@ +vendor_name = ModelSim +source_file = 1, /homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf +source_file = 1, /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm +source_file = 1, /homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.bsf +source_file = 1, /homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd +source_file = 1, /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/db/vga_pll.cbx.xml +source_file = 1, /opt/quartus/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, /opt/quartus/quartus/libraries/megafunctions/aglobal90.inc +source_file = 1, /opt/quartus/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, /opt/quartus/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, /opt/quartus/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, /opt/quartus/quartus/libraries/megafunctions/cbx.lst +design_name = vga_pll +instance = comp, \board_clk~I , board_clk, vga_pll, 1 +instance = comp, \inst1|altpll_component|pll , inst1|altpll_component|pll, vga_pll, 1 +instance = comp, \inst|reset_pin_in~I , inst|reset_pin_in, vga_pll, 1 +instance = comp, \inst|dly_counter_0_ , inst|dly_counter_0_, vga_pll, 1 +instance = comp, \inst|dly_counter_1_ , inst|dly_counter_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_6_ , inst|vga_driver_unit|vsync_state_6_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_6_ , inst|vga_driver_unit|hsync_state_6_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_0_ , inst|vga_driver_unit|hsync_counter_0_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_1_ , inst|vga_driver_unit|hsync_counter_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_2_ , inst|vga_driver_unit|hsync_counter_2_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_3_ , inst|vga_driver_unit|hsync_counter_3_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_4_ , inst|vga_driver_unit|hsync_counter_4_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_5_ , inst|vga_driver_unit|hsync_counter_5_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 , inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_6_ , inst|vga_driver_unit|hsync_counter_6_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_7_ , inst|vga_driver_unit|hsync_counter_7_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_8_ , inst|vga_driver_unit|hsync_counter_8_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_9_ , inst|vga_driver_unit|hsync_counter_9_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 , inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 , inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|G_2 , inst|vga_driver_unit|G_2, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 , inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 , inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter , inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 , inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 , inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 , inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 , inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 , inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_5_ , inst|vga_driver_unit|hsync_state_5_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_4_ , inst|vga_driver_unit|hsync_state_4_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ , inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_1_ , inst|vga_driver_unit|hsync_state_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_3_ , inst|vga_driver_unit|hsync_state_3_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ , inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ , inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_2_ , inst|vga_driver_unit|hsync_state_2_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_state_0_ , inst|vga_driver_unit|hsync_state_0_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ , inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 , inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter , inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_hsync_state_3_0_cZ , inst|vga_driver_unit|un1_hsync_state_3_0_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ , inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|h_sync_Z , inst|vga_driver_unit|h_sync_Z, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_0_ , inst|vga_driver_unit|vsync_counter_0_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_1_ , inst|vga_driver_unit|vsync_counter_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_2_ , inst|vga_driver_unit|vsync_counter_2_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_3_ , inst|vga_driver_unit|vsync_counter_3_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_4_ , inst|vga_driver_unit|vsync_counter_4_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_5_ , inst|vga_driver_unit|vsync_counter_5_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_6_ , inst|vga_driver_unit|vsync_counter_6_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_7_ , inst|vga_driver_unit|vsync_counter_7_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_8_ , inst|vga_driver_unit|vsync_counter_8_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 , inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 , inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 , inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|G_16 , inst|vga_driver_unit|G_16, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 , inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 , inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 , inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 , inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 , inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_1_ , inst|vga_driver_unit|vsync_state_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_3_ , inst|vga_driver_unit|vsync_state_3_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 , inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 , inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ , inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ , inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_5_ , inst|vga_driver_unit|vsync_state_5_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ , inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ , inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_2_ , inst|vga_driver_unit|vsync_state_2_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ , inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_0_ , inst|vga_driver_unit|vsync_state_0_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|d_set_vsync_counter_cZ , inst|vga_driver_unit|d_set_vsync_counter_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ , inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_counter_9_ , inst|vga_driver_unit|vsync_counter_9_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|vsync_state_4_ , inst|vga_driver_unit|vsync_state_4_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_vsync_state_2_0_cZ , inst|vga_driver_unit|un1_vsync_state_2_0_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ , inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|v_sync_Z , inst|vga_driver_unit|v_sync_Z, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ , inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_0_ , inst|vga_driver_unit|column_counter_sig_0_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_1_ , inst|vga_driver_unit|un2_column_counter_next_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_1_ , inst|vga_driver_unit|column_counter_sig_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_3_ , inst|vga_driver_unit|un2_column_counter_next_3_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_3_ , inst|vga_driver_unit|column_counter_sig_3_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_0_ , inst|vga_driver_unit|un2_column_counter_next_0_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_2_ , inst|vga_driver_unit|un2_column_counter_next_2_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_2_ , inst|vga_driver_unit|column_counter_sig_2_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_4_ , inst|vga_driver_unit|un2_column_counter_next_4_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_4_ , inst|vga_driver_unit|column_counter_sig_4_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_5_ , inst|vga_driver_unit|un2_column_counter_next_5_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_5_ , inst|vga_driver_unit|column_counter_sig_5_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_6_ , inst|vga_driver_unit|un2_column_counter_next_6_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_8_ , inst|vga_driver_unit|un2_column_counter_next_8_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_8_ , inst|vga_driver_unit|column_counter_sig_8_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 , inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 , inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_7_ , inst|vga_driver_unit|un2_column_counter_next_7_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un2_column_counter_next_9_ , inst|vga_driver_unit|un2_column_counter_next_9_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_9_ , inst|vga_driver_unit|column_counter_sig_9_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 , inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_7_ , inst|vga_driver_unit|column_counter_sig_7_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|column_counter_sig_6_ , inst|vga_driver_unit|column_counter_sig_6_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 , inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3, vga_pll, 1 +instance = comp, \inst|vga_control_unit|b_next_i_o3_0_cZ , inst|vga_control_unit|b_next_i_o3_0_cZ, vga_pll, 1 +instance = comp, \inst|vga_control_unit|g_next_i_o3_cZ , inst|vga_control_unit|g_next_i_o3_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ , inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|v_enable_sig_Z , inst|vga_driver_unit|v_enable_sig_Z, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ , inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|h_enable_sig_Z , inst|vga_driver_unit|h_enable_sig_Z, vga_pll, 1 +instance = comp, \inst|vga_control_unit|r_next_i_o7_cZ , inst|vga_control_unit|r_next_i_o7_cZ, vga_pll, 1 +instance = comp, \inst|vga_control_unit|N_4_i_0_g0_1_cZ , inst|vga_control_unit|N_4_i_0_g0_1_cZ, vga_pll, 1 +instance = comp, \inst|vga_control_unit|r_Z , inst|vga_control_unit|r_Z, vga_pll, 1 +instance = comp, \inst|vga_control_unit|N_23_i_0_g0_a_cZ , inst|vga_control_unit|N_23_i_0_g0_a_cZ, vga_pll, 1 +instance = comp, \inst|vga_control_unit|g_Z , inst|vga_control_unit|g_Z, vga_pll, 1 +instance = comp, \inst|vga_control_unit|N_6_i_0_g0_0_cZ , inst|vga_control_unit|N_6_i_0_g0_0_cZ, vga_pll, 1 +instance = comp, \inst|vga_control_unit|b_next_i_a7_1_cZ , inst|vga_control_unit|b_next_i_a7_1_cZ, vga_pll, 1 +instance = comp, \inst|vga_control_unit|b_Z , inst|vga_control_unit|b_Z, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_1_ , inst|vga_driver_unit|un1_line_counter_sig_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ , inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_sig_0_ , inst|vga_driver_unit|line_counter_sig_0_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_3_ , inst|vga_driver_unit|un1_line_counter_sig_3_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_sig_2_ , inst|vga_driver_unit|line_counter_sig_2_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_a_1_ , inst|vga_driver_unit|un1_line_counter_sig_a_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_2_ , inst|vga_driver_unit|un1_line_counter_sig_2_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_sig_1_ , inst|vga_driver_unit|line_counter_sig_1_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_4_ , inst|vga_driver_unit|un1_line_counter_sig_4_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_sig_3_ , inst|vga_driver_unit|line_counter_sig_3_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_5_ , inst|vga_driver_unit|un1_line_counter_sig_5_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_sig_4_ , inst|vga_driver_unit|line_counter_sig_4_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_6_ , inst|vga_driver_unit|un1_line_counter_sig_6_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_sig_5_ , inst|vga_driver_unit|line_counter_sig_5_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_7_ , inst|vga_driver_unit|un1_line_counter_sig_7_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_sig_6_ , inst|vga_driver_unit|line_counter_sig_6_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 , inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 , inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 , inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_8_ , inst|vga_driver_unit|un1_line_counter_sig_8_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_sig_7_ , inst|vga_driver_unit|line_counter_sig_7_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_9_ , inst|vga_driver_unit|un1_line_counter_sig_9_, vga_pll, 1 +instance = comp, \inst|vga_driver_unit|line_counter_sig_8_ , inst|vga_driver_unit|line_counter_sig_8_, vga_pll, 1 +instance = comp, \~STRATIX_FITTER_CREATED_GND~I , ~STRATIX_FITTER_CREATED_GND~I, vga_pll, 1 +instance = comp, \inst|d_hsync_out~I , inst|d_hsync_out, vga_pll, 1 +instance = comp, \inst|d_vsync_out~I , inst|d_vsync_out, vga_pll, 1 +instance = comp, \inst|d_set_column_counter_out~I , inst|d_set_column_counter_out, vga_pll, 1 +instance = comp, \inst|d_set_line_counter_out~I , inst|d_set_line_counter_out, vga_pll, 1 +instance = comp, \inst|d_set_hsync_counter_out~I , inst|d_set_hsync_counter_out, vga_pll, 1 +instance = comp, \inst|d_set_vsync_counter_out~I , inst|d_set_vsync_counter_out, vga_pll, 1 +instance = comp, \inst|d_r_out~I , inst|d_r_out, vga_pll, 1 +instance = comp, \inst|d_g_out~I , inst|d_g_out, vga_pll, 1 +instance = comp, \inst|d_b_out~I , inst|d_b_out, vga_pll, 1 +instance = comp, \inst|d_h_enable_out~I , inst|d_h_enable_out, vga_pll, 1 +instance = comp, \inst|d_v_enable_out~I , inst|d_v_enable_out, vga_pll, 1 +instance = comp, \inst|d_state_clk_out~I , inst|d_state_clk_out, vga_pll, 1 +instance = comp, \inst|r0_pin_out~I , inst|r0_pin_out, vga_pll, 1 +instance = comp, \inst|r1_pin_out~I , inst|r1_pin_out, vga_pll, 1 +instance = comp, \inst|r2_pin_out~I , inst|r2_pin_out, vga_pll, 1 +instance = comp, \inst|g0_pin_out~I , inst|g0_pin_out, vga_pll, 1 +instance = comp, \inst|g1_pin_out~I , inst|g1_pin_out, vga_pll, 1 +instance = comp, \inst|g2_pin_out~I , inst|g2_pin_out, vga_pll, 1 +instance = comp, \inst|b0_pin_out~I , inst|b0_pin_out, vga_pll, 1 +instance = comp, \inst|b1_pin_out~I , inst|b1_pin_out, vga_pll, 1 +instance = comp, \inst|hsync_pin_out~I , inst|hsync_pin_out, vga_pll, 1 +instance = comp, \inst|vsync_pin_out~I , inst|vsync_pin_out, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_9_~I , inst|d_column_counter_out_9_, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_8_~I , inst|d_column_counter_out_8_, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_7_~I , inst|d_column_counter_out_7_, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_6_~I , inst|d_column_counter_out_6_, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_5_~I , inst|d_column_counter_out_5_, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_4_~I , inst|d_column_counter_out_4_, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_3_~I , inst|d_column_counter_out_3_, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_2_~I , inst|d_column_counter_out_2_, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_1_~I , inst|d_column_counter_out_1_, vga_pll, 1 +instance = comp, \inst|d_column_counter_out_0_~I , inst|d_column_counter_out_0_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_9_~I , inst|d_hsync_counter_out_9_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_8_~I , inst|d_hsync_counter_out_8_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_7_~I , inst|d_hsync_counter_out_7_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_6_~I , inst|d_hsync_counter_out_6_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_5_~I , inst|d_hsync_counter_out_5_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_4_~I , inst|d_hsync_counter_out_4_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_3_~I , inst|d_hsync_counter_out_3_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_2_~I , inst|d_hsync_counter_out_2_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_1_~I , inst|d_hsync_counter_out_1_, vga_pll, 1 +instance = comp, \inst|d_hsync_counter_out_0_~I , inst|d_hsync_counter_out_0_, vga_pll, 1 +instance = comp, \inst|d_hsync_state_out_0_~I , inst|d_hsync_state_out_0_, vga_pll, 1 +instance = comp, \inst|d_hsync_state_out_1_~I , inst|d_hsync_state_out_1_, vga_pll, 1 +instance = comp, \inst|d_hsync_state_out_2_~I , inst|d_hsync_state_out_2_, vga_pll, 1 +instance = comp, \inst|d_hsync_state_out_3_~I , inst|d_hsync_state_out_3_, vga_pll, 1 +instance = comp, \inst|d_hsync_state_out_4_~I , inst|d_hsync_state_out_4_, vga_pll, 1 +instance = comp, \inst|d_hsync_state_out_5_~I , inst|d_hsync_state_out_5_, vga_pll, 1 +instance = comp, \inst|d_hsync_state_out_6_~I , inst|d_hsync_state_out_6_, vga_pll, 1 +instance = comp, \inst|d_line_counter_out_8_~I , inst|d_line_counter_out_8_, vga_pll, 1 +instance = comp, \inst|d_line_counter_out_7_~I , inst|d_line_counter_out_7_, vga_pll, 1 +instance = comp, \inst|d_line_counter_out_6_~I , inst|d_line_counter_out_6_, vga_pll, 1 +instance = comp, \inst|d_line_counter_out_5_~I , inst|d_line_counter_out_5_, vga_pll, 1 +instance = comp, \inst|d_line_counter_out_4_~I , inst|d_line_counter_out_4_, vga_pll, 1 +instance = comp, \inst|d_line_counter_out_3_~I , inst|d_line_counter_out_3_, vga_pll, 1 +instance = comp, \inst|d_line_counter_out_2_~I , inst|d_line_counter_out_2_, vga_pll, 1 +instance = comp, \inst|d_line_counter_out_1_~I , inst|d_line_counter_out_1_, vga_pll, 1 +instance = comp, \inst|d_line_counter_out_0_~I , inst|d_line_counter_out_0_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_9_~I , inst|d_vsync_counter_out_9_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_8_~I , inst|d_vsync_counter_out_8_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_7_~I , inst|d_vsync_counter_out_7_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_6_~I , inst|d_vsync_counter_out_6_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_5_~I , inst|d_vsync_counter_out_5_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_4_~I , inst|d_vsync_counter_out_4_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_3_~I , inst|d_vsync_counter_out_3_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_2_~I , inst|d_vsync_counter_out_2_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_1_~I , inst|d_vsync_counter_out_1_, vga_pll, 1 +instance = comp, \inst|d_vsync_counter_out_0_~I , inst|d_vsync_counter_out_0_, vga_pll, 1 +instance = comp, \inst|d_vsync_state_out_0_~I , inst|d_vsync_state_out_0_, vga_pll, 1 +instance = comp, \inst|d_vsync_state_out_1_~I , inst|d_vsync_state_out_1_, vga_pll, 1 +instance = comp, \inst|d_vsync_state_out_2_~I , inst|d_vsync_state_out_2_, vga_pll, 1 +instance = comp, \inst|d_vsync_state_out_3_~I , inst|d_vsync_state_out_3_, vga_pll, 1 +instance = comp, \inst|d_vsync_state_out_4_~I , inst|d_vsync_state_out_4_, vga_pll, 1 +instance = comp, \inst|d_vsync_state_out_5_~I , inst|d_vsync_state_out_5_, vga_pll, 1 +instance = comp, \inst|d_vsync_state_out_6_~I , inst|d_vsync_state_out_6_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_tri_13_~I , inst|seven_seg_pin_tri_13_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_out_12_~I , inst|seven_seg_pin_out_12_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_out_11_~I , inst|seven_seg_pin_out_11_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_out_10_~I , inst|seven_seg_pin_out_10_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_out_9_~I , inst|seven_seg_pin_out_9_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_out_8_~I , inst|seven_seg_pin_out_8_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_out_7_~I , inst|seven_seg_pin_out_7_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_tri_6_~I , inst|seven_seg_pin_tri_6_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_tri_5_~I , inst|seven_seg_pin_tri_5_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_tri_4_~I , inst|seven_seg_pin_tri_4_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_tri_3_~I , inst|seven_seg_pin_tri_3_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_out_2_~I , inst|seven_seg_pin_out_2_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_out_1_~I , inst|seven_seg_pin_out_1_, vga_pll, 1 +instance = comp, \inst|seven_seg_pin_tri_0_~I , inst|seven_seg_pin_tri_0_, vga_pll, 1 diff --git a/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo new file mode 100644 index 0000000..cfc33a7 --- /dev/null +++ b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo @@ -0,0 +1,4389 @@ +// Copyright (C) 1991-2009 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP1S25F672C6 Package FBGA672 +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga_pll") + (DATE "10/29/2009 17:13:31") + (VENDOR "Altera") + (PROGRAM "Quartus II") + (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE board_clk\~I.inst1) + (DELAY + (ABSOLUTE + (IOPATH padio combout (760:760:760) (760:760:760)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_pll") + (INSTANCE inst1\|altpll_component\|pll) + (DELAY + (ABSOLUTE + (PORT inclk[0] (649:649:649) (649:649:649)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|reset_pin_in\~I.inst1) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1141:1141:1141) (1141:1141:1141)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|dly_counter_0_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (5718:5718:5718) (5718:5718:5718)) + (PORT datac (495:495:495) (495:495:495)) + (PORT datad (487:487:487) (487:487:487)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|dly_counter_0_.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|dly_counter_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (5717:5717:5717) (5717:5717:5717)) + (PORT datac (498:498:498) (498:498:498)) + (PORT datad (485:485:485) (485:485:485)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|dly_counter_1_.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (5711:5711:5711) (5711:5711:5711)) + (PORT datac (500:500:500) (500:500:500)) + (PORT datad (487:487:487) (487:487:487)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (403:403:403) (403:403:403)) + (PORT datad (2362:2362:2362) (2362:2362:2362)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH qfbkin combout (291:291:291) (291:291:291)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lereg) + (DELAY + (ABSOLUTE + (PORT datac (493:493:493) (493:493:493)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (423:423:423) (423:423:423)) + (PORT datac (2734:2734:2734) (2734:2734:2734)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2824:2824:2824) (2824:2824:2824)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (419:419:419)) + (PORT datac (2732:2732:2732) (2732:2732:2732)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2822:2822:2822) (2822:2822:2822)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (444:444:444)) + (PORT datac (2731:2731:2731) (2731:2731:2731)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2821:2821:2821) (2821:2821:2821)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (437:437:437)) + (PORT datac (2730:2730:2730) (2730:2730:2730)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2820:2820:2820) (2820:2820:2820)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (445:445:445)) + (PORT datac (2730:2730:2730) (2730:2730:2730)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout (551:551:551) (551:551:551)) + (IOPATH cin0 cout (135:135:135) (135:135:135)) + (IOPATH cin1 cout (123:123:123) (123:123:123)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2820:2820:2820) (2820:2820:2820)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (420:420:420)) + (PORT datac (2720:2720:2720) (2720:2720:2720)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2810:2810:2810) (2810:2810:2810)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1169:1169:1169)) + (PORT datab (1153:1153:1153) (1153:1153:1153)) + (PORT datac (1176:1176:1176) (1176:1176:1176)) + (PORT datad (1128:1128:1128) (1128:1128:1128)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (422:422:422) (422:422:422)) + (PORT datac (2719:2719:2719) (2719:2719:2719)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2809:2809:2809) (2809:2809:2809)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (436:436:436)) + (PORT datac (2722:2722:2722) (2722:2722:2722)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2812:2812:2812) (2812:2812:2812)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (445:445:445)) + (PORT datac (2725:2725:2725) (2725:2725:2725)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2815:2815:2815) (2815:2815:2815)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (2727:2727:2727) (2727:2727:2727)) + (PORT datad (432:432:432) (432:432:432)) + (IOPATH datad regin (235:235:235) (235:235:235)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1960:1960:1960) (1960:1960:1960)) + (PORT datac (2817:2817:2817) (2817:2817:2817)) + (PORT sclr (1840:1840:1840) (1840:1840:1840)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2102:2102:2102) (2102:2102:2102)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1358:1358:1358)) + (PORT datab (1452:1452:1452) (1452:1452:1452)) + (PORT datac (1397:1397:1397) (1397:1397:1397)) + (PORT datad (1406:1406:1406) (1406:1406:1406)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1357:1357:1357)) + (PORT datab (1173:1173:1173) (1173:1173:1173)) + (PORT datac (886:886:886) (886:886:886)) + (PORT datad (340:340:340) (340:340:340)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|G_2.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (2904:2904:2904) (2904:2904:2904)) + (PORT datab (432:432:432) (432:432:432)) + (PORT datac (2679:2679:2679) (2679:2679:2679)) + (PORT datad (253:253:253) (253:253:253)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1184:1184:1184) (1184:1184:1184)) + (PORT datab (1201:1201:1201) (1201:1201:1201)) + (PORT datac (1172:1172:1172) (1172:1172:1172)) + (PORT datad (1150:1150:1150) (1150:1150:1150)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1178:1178:1178)) + (PORT datab (1168:1168:1168) (1168:1168:1168)) + (PORT datac (1157:1157:1157) (1157:1157:1157)) + (PORT datad (1187:1187:1187) (1187:1187:1187)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1143:1143:1143) (1143:1143:1143)) + (PORT datab (1153:1153:1153) (1153:1153:1153)) + (PORT datac (364:364:364) (364:364:364)) + (PORT datad (352:352:352) (352:352:352)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (1131:1131:1131) (1131:1131:1131)) + (PORT datac (1167:1167:1167) (1167:1167:1167)) + (PORT datad (1167:1167:1167) (1167:1167:1167)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1196:1196:1196)) + (PORT datab (1207:1207:1207) (1207:1207:1207)) + (PORT datac (1190:1190:1190) (1190:1190:1190)) + (PORT datad (1131:1131:1131) (1131:1131:1131)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1192:1192:1192) (1192:1192:1192)) + (PORT datac (1165:1165:1165) (1165:1165:1165)) + (PORT datad (1190:1190:1190) (1190:1190:1190)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1197:1197:1197)) + (PORT datab (1175:1175:1175) (1175:1175:1175)) + (PORT datac (1162:1162:1162) (1162:1162:1162)) + (PORT datad (1144:1144:1144) (1144:1144:1144)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (1179:1179:1179) (1179:1179:1179)) + (PORT datac (1191:1191:1191) (1191:1191:1191)) + (PORT datad (1133:1133:1133) (1133:1133:1133)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (2904:2904:2904) (2904:2904:2904)) + (PORT datad (436:436:436) (436:436:436)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (3448:3448:3448) (3448:3448:3448)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2105:2105:2105) (2105:2105:2105)) + (PORT ena (1284:1284:1284) (1284:1284:1284)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (357:357:357)) + (PORT datab (351:351:351) (351:351:351)) + (PORT datac (1119:1119:1119) (1119:1119:1119)) + (PORT datad (359:359:359) (359:359:359)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (3460:3460:3460) (3460:3460:3460)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2106:2106:2106) (2106:2106:2106)) + (PORT ena (1780:1780:1780) (1780:1780:1780)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1093:1093:1093)) + (PORT datab (1039:1039:1039) (1039:1039:1039)) + (PORT datac (1087:1087:1087) (1087:1087:1087)) + (PORT datad (1200:1200:1200) (1200:1200:1200)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (374:374:374)) + (PORT datab (336:336:336) (336:336:336)) + (PORT datac (367:367:367) (367:367:367)) + (PORT datad (444:444:444) (444:444:444)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (3460:3460:3460) (3460:3460:3460)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2106:2106:2106) (2106:2106:2106)) + (PORT ena (1780:1780:1780) (1780:1780:1780)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (357:357:357)) + (PORT datab (951:951:951) (951:951:951)) + (PORT datac (1401:1401:1401) (1401:1401:1401)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH qfbkin combout (291:291:291) (291:291:291)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lereg) + (DELAY + (ABSOLUTE + (PORT datac (1491:1491:1491) (1491:1491:1491)) + (PORT sclr (3462:3462:3462) (3462:3462:3462)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2105:2105:2105) (2105:2105:2105)) + (PORT ena (1087:1087:1087) (1087:1087:1087)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1065:1065:1065)) + (PORT datab (613:613:613) (613:613:613)) + (PORT datac (1080:1080:1080) (1080:1080:1080)) + (PORT datad (1084:1084:1084) (1084:1084:1084)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (360:360:360)) + (PORT datab (344:344:344) (344:344:344)) + (PORT datac (2693:2693:2693) (2693:2693:2693)) + (PORT datad (354:354:354) (354:354:354)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (540:540:540) (540:540:540)) + (PORT datad (593:593:593) (593:593:593)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (3448:3448:3448) (3448:3448:3448)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2105:2105:2105) (2105:2105:2105)) + (PORT ena (1284:1284:1284) (1284:1284:1284)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (425:425:425) (425:425:425)) + (PORT datad (554:554:554) (554:554:554)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (3448:3448:3448) (3448:3448:3448)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2105:2105:2105) (2105:2105:2105)) + (PORT ena (1284:1284:1284) (1284:1284:1284)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (5720:5720:5720) (5720:5720:5720)) + (PORT datab (479:479:479) (479:479:479)) + (PORT datac (496:496:496) (496:496:496)) + (PORT datad (339:339:339) (339:339:339)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1174:1174:1174)) + (PORT datab (1140:1140:1140) (1140:1140:1140)) + (PORT datac (1165:1165:1165) (1165:1165:1165)) + (PORT datad (1184:1184:1184) (1184:1184:1184)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (360:360:360)) + (PORT datab (1168:1168:1168) (1168:1168:1168)) + (PORT datac (1162:1162:1162) (1162:1162:1162)) + (PORT datad (595:595:595) (595:595:595)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_hsync_state_3_0_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (2454:2454:2454) (2454:2454:2454)) + (PORT datad (2798:2798:2798) (2798:2798:2798)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|h_sync_1_0_0_0_g1_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (357:357:357)) + (PORT datab (418:418:418) (418:418:418)) + (PORT datac (2732:2732:2732) (2732:2732:2732)) + (PORT datad (2505:2505:2505) (2505:2505:2505)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1388:1388:1388) (1388:1388:1388)) + (PORT datab (4965:4965:4965) (4965:4965:4965)) + (PORT datac (1402:1402:1402) (1402:1402:1402)) + (PORT datad (346:346:346) (346:346:346)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (999:999:999)) + (PORT datab (555:555:555) (555:555:555)) + (PORT datac (1225:1225:1225) (1225:1225:1225)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1315:1315:1315) (1315:1315:1315)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (419:419:419)) + (PORT datac (1228:1228:1228) (1228:1228:1228)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1318:1318:1318) (1318:1318:1318)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (444:444:444)) + (PORT datac (1231:1231:1231) (1231:1231:1231)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1321:1321:1321) (1321:1321:1321)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (437:437:437)) + (PORT datac (1234:1234:1234) (1234:1234:1234)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1324:1324:1324) (1324:1324:1324)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (445:445:445)) + (PORT datac (1236:1236:1236) (1236:1236:1236)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout (551:551:551) (551:551:551)) + (IOPATH cin0 cout (135:135:135) (135:135:135)) + (IOPATH cin1 cout (123:123:123) (123:123:123)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1326:1326:1326) (1326:1326:1326)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (420:420:420)) + (PORT datac (1243:1243:1243) (1243:1243:1243)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1333:1333:1333) (1333:1333:1333)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (416:416:416) (416:416:416)) + (PORT datac (1242:1242:1242) (1242:1242:1242)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1332:1332:1332) (1332:1332:1332)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (436:436:436)) + (PORT datac (1240:1240:1240) (1240:1240:1240)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1330:1330:1330) (1330:1330:1330)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (445:445:445)) + (PORT datac (1239:1239:1239) (1239:1239:1239)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1329:1329:1329) (1329:1329:1329)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1234:1234:1234)) + (PORT datab (1140:1140:1140) (1140:1140:1140)) + (PORT datac (1150:1150:1150) (1150:1150:1150)) + (PORT datad (1248:1248:1248) (1248:1248:1248)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1249:1249:1249)) + (PORT datab (1126:1126:1126) (1126:1126:1126)) + (PORT datac (1214:1214:1214) (1214:1214:1214)) + (PORT datad (1381:1381:1381) (1381:1381:1381)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1247:1247:1247) (1247:1247:1247)) + (PORT datab (349:349:349) (349:349:349)) + (PORT datac (1131:1131:1131) (1131:1131:1131)) + (PORT datad (348:348:348) (348:348:348)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|G_16.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1461:1461:1461) (1461:1461:1461)) + (PORT datab (431:431:431) (431:431:431)) + (PORT datac (365:365:365) (365:365:365)) + (PORT datad (1902:1902:1902) (1902:1902:1902)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1170:1170:1170) (1170:1170:1170)) + (PORT datab (1183:1183:1183) (1183:1183:1183)) + (PORT datac (1150:1150:1150) (1150:1150:1150)) + (PORT datad (1153:1153:1153) (1153:1153:1153)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1204:1204:1204)) + (PORT datab (1433:1433:1433) (1433:1433:1433)) + (PORT datac (1143:1143:1143) (1143:1143:1143)) + (PORT datad (1475:1475:1475) (1475:1475:1475)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (359:359:359)) + (PORT datad (368:368:368) (368:368:368)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (728:728:728)) + (PORT datab (682:682:682) (682:682:682)) + (PORT datac (695:695:695) (695:695:695)) + (PORT datad (595:595:595) (595:595:595)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (677:677:677)) + (PORT datac (367:367:367) (367:367:367)) + (PORT datad (664:664:664) (664:664:664)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1052:1052:1052)) + (PORT datab (366:366:366) (366:366:366)) + (PORT datac (400:400:400) (400:400:400)) + (PORT datad (1171:1171:1171) (1171:1171:1171)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (907:907:907)) + (PORT datab (1230:1230:1230) (1230:1230:1230)) + (PORT datac (1413:1413:1413) (1413:1413:1413)) + (PORT datad (1202:1202:1202) (1202:1202:1202)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH qfbkin combout (291:291:291) (291:291:291)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lereg) + (DELAY + (ABSOLUTE + (PORT datac (1503:1503:1503) (1503:1503:1503)) + (PORT sclr (2649:2649:2649) (2649:2649:2649)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (PORT ena (1575:1575:1575) (1575:1575:1575)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1261:1261:1261) (1261:1261:1261)) + (PORT datab (1126:1126:1126) (1126:1126:1126)) + (PORT datac (1215:1215:1215) (1215:1215:1215)) + (PORT datad (1380:1380:1380) (1380:1380:1380)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1244:1244:1244) (1244:1244:1244)) + (PORT datac (367:367:367) (367:367:367)) + (PORT datad (1237:1237:1237) (1237:1237:1237)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (360:360:360)) + (PORT datac (697:697:697) (697:697:697)) + (PORT datad (1069:1069:1069) (1069:1069:1069)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (876:876:876)) + (PORT datab (359:359:359) (359:359:359)) + (PORT datac (372:372:372) (372:372:372)) + (PORT datad (425:425:425) (425:425:425)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (590:590:590) (590:590:590)) + (PORT datac (1178:1178:1178) (1178:1178:1178)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2648:2648:2648) (2648:2648:2648)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (PORT ena (1086:1086:1086) (1086:1086:1086)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1248:1248:1248)) + (PORT datab (570:570:570) (570:570:570)) + (PORT datac (450:450:450) (450:450:450)) + (PORT datad (1449:1449:1449) (1449:1449:1449)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (868:868:868)) + (PORT datab (1859:1859:1859) (1859:1859:1859)) + (PORT datac (371:371:371) (371:371:371)) + (PORT datad (362:362:362) (362:362:362)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1465:1465:1465)) + (PORT datab (570:570:570) (570:570:570)) + (PORT datac (947:947:947) (947:947:947)) + (PORT datad (1231:1231:1231) (1231:1231:1231)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2648:2648:2648) (2648:2648:2648)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (PORT ena (1086:1086:1086) (1086:1086:1086)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (526:526:526) (526:526:526)) + (PORT datac (634:634:634) (634:634:634)) + (PORT datad (344:344:344) (344:344:344)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1917:1917:1917) (1917:1917:1917)) + (PORT datab (428:428:428) (428:428:428)) + (PORT datac (365:365:365) (365:365:365)) + (PORT datad (570:570:570) (570:570:570)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|d_set_vsync_counter_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (931:931:931)) + (PORT datac (1463:1463:1463) (1463:1463:1463)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datac combout (213:213:213) (213:213:213)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1403:1403:1403) (1403:1403:1403)) + (PORT datab (4962:4962:4962) (4962:4962:4962)) + (PORT datac (1391:1391:1391) (1391:1391:1391)) + (PORT datad (873:873:873) (873:873:873)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (1238:1238:1238) (1238:1238:1238)) + (PORT datad (426:426:426) (426:426:426)) + (IOPATH datad regin (235:235:235) (235:235:235)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1966:1966:1966) (1966:1966:1966)) + (PORT datac (1328:1328:1328) (1328:1328:1328)) + (PORT sclr (1843:1843:1843) (1843:1843:1843)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2054:2054:2054) (2054:2054:2054)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1242:1242:1242)) + (PORT datab (570:570:570) (570:570:570)) + (PORT datac (451:451:451) (451:451:451)) + (PORT datad (1452:1452:1452) (1452:1452:1452)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2648:2648:2648) (2648:2648:2648)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (PORT ena (1086:1086:1086) (1086:1086:1086)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_2_0_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (1414:1414:1414) (1414:1414:1414)) + (PORT datad (429:429:429) (429:429:429)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|v_sync_1_0_0_0_g1_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (437:437:437)) + (PORT datab (996:996:996) (996:996:996)) + (PORT datac (947:947:947) (947:947:947)) + (PORT datad (346:346:346) (346:346:346)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1406:1406:1406) (1406:1406:1406)) + (PORT datab (4964:4964:4964) (4964:4964:4964)) + (PORT datac (1389:1389:1389) (1389:1389:1389)) + (PORT datad (553:553:553) (553:553:553)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (5714:5714:5714) (5714:5714:5714)) + (PORT datab (478:478:478) (478:478:478)) + (PORT datac (499:499:499) (499:499:499)) + (PORT datad (2621:2621:2621) (2621:2621:2621)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (417:417:417) (417:417:417)) + (PORT datad (660:660:660) (660:660:660)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2870:2870:2870) (2870:2870:2870)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (655:655:655)) + (PORT datab (638:638:638) (638:638:638)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (878:878:878)) + (PORT datac (408:408:408) (408:408:408)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2870:2870:2870) (2870:2870:2870)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_3_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (461:461:461)) + (PORT datab (658:658:658) (658:658:658)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (619:619:619)) + (PORT datad (352:352:352) (352:352:352)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2886:2886:2886) (2886:2886:2886)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_0_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1356:1356:1356)) + (PORT datab (1127:1127:1127) (1127:1127:1127)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_2_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1165:1165:1165)) + (PORT datab (1122:1122:1122) (1122:1122:1122)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (411:411:411) (411:411:411)) + (PORT datad (1072:1072:1072) (1072:1072:1072)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2870:2870:2870) (2870:2870:2870)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_4_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1189:1189:1189)) + (PORT datab (1137:1137:1137) (1137:1137:1137)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (415:415:415) (415:415:415)) + (PORT datad (1045:1045:1045) (1045:1045:1045)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2870:2870:2870) (2870:2870:2870)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_5_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (919:919:919)) + (PORT datab (654:654:654) (654:654:654)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (390:390:390) (390:390:390)) + (PORT datac (554:554:554) (554:554:554)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2870:2870:2870) (2870:2870:2870)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_6_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1219:1219:1219)) + (PORT datab (1203:1203:1203) (1203:1203:1203)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_8_.lecomb) + (DELAY + (ABSOLUTE + (PORT datad (458:458:458) (458:458:458)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (2528:2528:2528) (2528:2528:2528)) + (PORT datac (1077:1077:1077) (1077:1077:1077)) + (PORT datad (340:340:340) (340:340:340)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2053:2053:2053) (2053:2053:2053)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_1.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (675:675:675)) + (PORT datac (653:653:653) (653:653:653)) + (PORT datad (427:427:427) (427:427:427)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (438:438:438)) + (PORT datab (346:346:346) (346:346:346)) + (PORT datac (368:368:368) (368:368:368)) + (PORT datad (626:626:626) (626:626:626)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_7_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (458:458:458)) + (PORT datab (684:684:684) (684:684:684)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_9_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (1125:1125:1125) (1125:1125:1125)) + (PORT datad (431:431:431) (431:431:431)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (620:620:620)) + (PORT datad (352:352:352) (352:352:352)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2886:2886:2886) (2886:2886:2886)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1029:1029:1029) (1029:1029:1029)) + (PORT datab (1364:1364:1364) (1364:1364:1364)) + (PORT datac (365:365:365) (365:365:365)) + (PORT datad (940:940:940) (940:940:940)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (619:619:619)) + (PORT datac (2114:2114:2114) (2114:2114:2114)) + (PORT datad (361:361:361) (361:361:361)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (1077:1077:1077) (1077:1077:1077)) + (PORT datac (416:416:416) (416:416:416)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2870:2870:2870) (2870:2870:2870)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_3.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (428:428:428) (428:428:428)) + (PORT datad (434:434:434) (434:434:434)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|b_next_i_o3_0_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1220:1220:1220) (1220:1220:1220)) + (PORT datab (1200:1200:1200) (1200:1200:1200)) + (PORT datac (1156:1156:1156) (1156:1156:1156)) + (PORT datad (1180:1180:1180) (1180:1180:1180)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|g_next_i_o3_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (657:657:657) (657:657:657)) + (PORT datad (445:445:445) (445:445:445)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (1107:1107:1107) (1107:1107:1107)) + (PORT datac (2687:2687:2687) (2687:2687:2687)) + (PORT datad (446:446:446) (446:446:446)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (1116:1116:1116) (1116:1116:1116)) + (PORT datad (435:435:435) (435:435:435)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (3460:3460:3460) (3460:3460:3460)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2106:2106:2106) (2106:2106:2106)) + (PORT ena (1096:1096:1096) (1096:1096:1096)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (1863:1863:1863) (1863:1863:1863)) + (PORT datac (1011:1011:1011) (1011:1011:1011)) + (PORT datad (902:902:902) (902:902:902)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (1885:1885:1885) (1885:1885:1885)) + (PORT datad (1836:1836:1836) (1836:1836:1836)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2982:2982:2982) (2982:2982:2982)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2059:2059:2059) (2059:2059:2059)) + (PORT ena (2543:2543:2543) (2543:2543:2543)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|r_next_i_o7_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (433:433:433) (433:433:433)) + (PORT datac (1869:1869:1869) (1869:1869:1869)) + (PORT datad (2360:2360:2360) (2360:2360:2360)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|N_4_i_0_g0_1_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (468:468:468)) + (PORT datab (1066:1066:1066) (1066:1066:1066)) + (PORT datac (3037:3037:3037) (3037:3037:3037)) + (PORT datad (1210:1210:1210) (1210:1210:1210)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|r_Z.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1086:1086:1086)) + (PORT datab (344:344:344) (344:344:344)) + (PORT datac (360:360:360) (360:360:360)) + (PORT datad (456:456:456) (456:456:456)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_control_unit\|r_Z.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (5165:5165:5165) (5165:5165:5165)) + (PORT clk (2053:2053:2053) (2053:2053:2053)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|N_23_i_0_g0_a_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (538:538:538)) + (PORT datab (642:642:642) (642:642:642)) + (PORT datac (590:590:590) (590:590:590)) + (PORT datad (912:912:912) (912:912:912)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|g_Z.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1411:1411:1411) (1411:1411:1411)) + (PORT datab (2777:2777:2777) (2777:2777:2777)) + (PORT datac (366:366:366) (366:366:366)) + (PORT datad (1039:1039:1039) (1039:1039:1039)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_control_unit\|g_Z.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (5181:5181:5181) (5181:5181:5181)) + (PORT clk (2040:2040:2040) (2040:2040:2040)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|N_6_i_0_g0_0_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1412:1412:1412) (1412:1412:1412)) + (PORT datab (2773:2773:2773) (2773:2773:2773)) + (PORT datac (582:582:582) (582:582:582)) + (PORT datad (1041:1041:1041) (1041:1041:1041)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|b_next_i_a7_1_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (351:351:351)) + (PORT datab (652:652:652) (652:652:652)) + (PORT datac (1154:1154:1154) (1154:1154:1154)) + (PORT datad (445:445:445) (445:445:445)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_control_unit\|b_Z.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (469:469:469) (469:469:469)) + (PORT datab (346:346:346) (346:346:346)) + (PORT datac (1307:1307:1307) (1307:1307:1307)) + (PORT datad (1121:1121:1121) (1121:1121:1121)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_control_unit\|b_Z.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (5165:5165:5165) (5165:5165:5165)) + (PORT clk (2053:2053:2053) (2053:2053:2053)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (2146:2146:2146) (2146:2146:2146)) + (PORT datab (1135:1135:1135) (1135:1135:1135)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (5708:5708:5708) (5708:5708:5708)) + (PORT datab (619:619:619) (619:619:619)) + (PORT datac (501:501:501) (501:501:501)) + (PORT datad (488:488:488) (488:488:488)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1062:1062:1062)) + (PORT datac (1125:1125:1125) (1125:1125:1125)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2653:2653:2653) (2653:2653:2653)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2100:2100:2100) (2100:2100:2100)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_3_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1140:1140:1140)) + (PORT datab (670:670:670) (670:670:670)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (541:541:541) (541:541:541)) + (PORT datad (561:561:561) (561:561:561)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2893:2893:2893) (2893:2893:2893)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2111:2111:2111) (2111:2111:2111)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_a_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (2588:2588:2588) (2588:2588:2588)) + (PORT datab (422:422:422) (422:422:422)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_2_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (439:439:439)) + (PORT datab (1120:1120:1120) (1120:1120:1120)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (344:344:344)) + (PORT datac (1123:1123:1123) (1123:1123:1123)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2653:2653:2653) (2653:2653:2653)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2100:2100:2100) (2100:2100:2100)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_4_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1123:1123:1123)) + (PORT datab (424:424:424) (424:424:424)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (1126:1126:1126) (1126:1126:1126)) + (PORT datad (354:354:354) (354:354:354)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2653:2653:2653) (2653:2653:2653)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2100:2100:2100) (2100:2100:2100)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_5_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (452:452:452)) + (PORT datab (1126:1126:1126) (1126:1126:1126)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (367:367:367) (367:367:367)) + (PORT datad (364:364:364) (364:364:364)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2691:2691:2691) (2691:2691:2691)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2111:2111:2111) (2111:2111:2111)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_6_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (443:443:443)) + (PORT datab (1154:1154:1154) (1154:1154:1154)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (359:359:359)) + (PORT datab (1864:1864:1864) (1864:1864:1864)) + (PORT datac (1122:1122:1122) (1122:1122:1122)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2100:2100:2100) (2100:2100:2100)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_7_.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (673:673:673)) + (PORT datab (1152:1152:1152) (1152:1152:1152)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (537:537:537) (537:537:537)) + (PORT datad (560:560:560) (560:560:560)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2893:2893:2893) (2893:2893:2893)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2111:2111:2111) (2111:2111:2111)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (453:453:453)) + (PORT datab (1138:1138:1138) (1138:1138:1138)) + (PORT datac (1145:1145:1145) (1145:1145:1145)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1139:1139:1139) (1139:1139:1139)) + (PORT datab (336:336:336) (336:336:336)) + (PORT datac (1161:1161:1161) (1161:1161:1161)) + (PORT datad (675:675:675) (675:675:675)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (670:670:670)) + (PORT datab (430:430:430) (430:430:430)) + (PORT datac (365:365:365) (365:365:365)) + (PORT datad (1154:1154:1154) (1154:1154:1154)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_8_.lecomb) + (DELAY + (ABSOLUTE + (PORT datad (426:426:426) (426:426:426)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (1121:1121:1121) (1121:1121:1121)) + (PORT datad (350:350:350) (350:350:350)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2653:2653:2653) (2653:2653:2653)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2100:2100:2100) (2100:2100:2100)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_9_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (432:432:432) (432:432:432)) + (PORT datad (1154:1154:1154) (1154:1154:1154)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (349:349:349)) + (PORT datad (363:363:363) (363:363:363)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2691:2691:2691) (2691:2691:2691)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2111:2111:2111) (2111:2111:2111)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2877:2877:2877) (2877:2877:2877)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2863:2863:2863) (2863:2863:2863)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_set_column_counter_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3627:3627:3627) (3627:3627:3627)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_set_line_counter_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3459:3459:3459) (3459:3459:3459)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_set_hsync_counter_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3006:3006:3006) (3006:3006:3006)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_set_vsync_counter_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2648:2648:2648) (2648:2648:2648)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_r_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3338:3338:3338) (3338:3338:3338)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_g_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1587:1587:1587) (1587:1587:1587)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_b_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1375:1375:1375) (1375:1375:1375)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_h_enable_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2714:2714:2714) (2714:2714:2714)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_v_enable_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1304:1304:1304) (1304:1304:1304)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_state_clk_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2246:2246:2246) (2246:2246:2246)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|r0_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2615:2615:2615) (2615:2615:2615)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|r1_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3920:3920:3920) (3920:3920:3920)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|r2_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3911:3911:3911) (3911:3911:3911)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|g0_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2147:2147:2147) (2147:2147:2147)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|g1_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3965:3965:3965) (3965:3965:3965)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|g2_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2260:2260:2260) (2260:2260:2260)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|b0_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1859:1859:1859) (1859:1859:1859)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|b1_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3616:3616:3616) (3616:3616:3616)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|hsync_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3049:3049:3049) (3049:3049:3049)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|vsync_pin_out\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3155:3155:3155) (3155:3155:3155)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_9_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (4366:4366:4366) (4366:4366:4366)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_8_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1370:1370:1370) (1370:1370:1370)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_7_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1387:1387:1387) (1387:1387:1387)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_6_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2873:2873:2873) (2873:2873:2873)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_5_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3120:3120:3120) (3120:3120:3120)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_4_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3826:3826:3826) (3826:3826:3826)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_3_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1359:1359:1359) (1359:1359:1359)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_2_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1573:1573:1573) (1573:1573:1573)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_1_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1584:1584:1584) (1584:1584:1584)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_column_counter_out_0_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1593:1593:1593) (1593:1593:1593)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_9_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1730:1730:1730) (1730:1730:1730)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_8_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2098:2098:2098) (2098:2098:2098)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_7_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1867:1867:1867) (1867:1867:1867)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_6_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1365:1365:1365) (1365:1365:1365)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_5_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2513:2513:2513) (2513:2513:2513)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_4_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1364:1364:1364) (1364:1364:1364)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_3_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3133:3133:3133) (3133:3133:3133)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_2_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1437:1437:1437) (1437:1437:1437)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_1_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (4102:4102:4102) (4102:4102:4102)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_counter_out_0_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3092:3092:3092) (3092:3092:3092)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_hsync_state_out_0_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (4321:4321:4321) (4321:4321:4321)) + (IOPATH datain padio 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(CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_counter_out_7_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3159:3159:3159) (3159:3159:3159)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_counter_out_6_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3326:3326:3326) (3326:3326:3326)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_counter_out_5_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2901:2901:2901) (2901:2901:2901)) + (IOPATH datain padio (4488:4488:4488) (4488:4488:4488)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_counter_out_4_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3887:3887:3887) (3887:3887:3887)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_counter_out_3_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2618:2618:2618) (2618:2618:2618)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_counter_out_2_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2170:2170:2170) (2170:2170:2170)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_counter_out_1_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2202:2202:2202) (2202:2202:2202)) + (IOPATH datain padio (4488:4488:4488) (4488:4488:4488)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_counter_out_0_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2481:2481:2481) (2481:2481:2481)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_state_out_0_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2900:2900:2900) (2900:2900:2900)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_state_out_1_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2818:2818:2818) (2818:2818:2818)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_state_out_2_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2675:2675:2675) (2675:2675:2675)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_state_out_3_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2504:2504:2504) (2504:2504:2504)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_state_out_4_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2837:2837:2837) (2837:2837:2837)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_state_out_5_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2841:2841:2841) (2841:2841:2841)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|d_vsync_state_out_6_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2870:2870:2870) (2870:2870:2870)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|seven_seg_pin_tri_13_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2666:2666:2666) (2666:2666:2666)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|seven_seg_pin_out_12_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3687:3687:3687) (3687:3687:3687)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE 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(DELAY + (ABSOLUTE + (PORT datain (3699:3699:3699) (3699:3699:3699)) + (IOPATH datain padio (4191:4191:4191) (4191:4191:4191)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|seven_seg_pin_tri_6_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2372:2372:2372) (2372:2372:2372)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|seven_seg_pin_tri_5_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2372:2372:2372) (2372:2372:2372)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|seven_seg_pin_tri_4_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1927:1927:1927) (1927:1927:1927)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|seven_seg_pin_tri_3_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1927:1927:1927) (1927:1927:1927)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|seven_seg_pin_out_2_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3112:3112:3112) (3112:3112:3112)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|seven_seg_pin_out_1_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3163:3163:3163) (3163:3163:3163)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE inst\|seven_seg_pin_tri_0_\~I.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2003:2003:2003) (2003:2003:2003)) + (IOPATH datain padio (4100:4100:4100) (4100:4100:4100)) + ) + ) + ) +) diff --git a/bsp3/Designflow/ppr/download/vga_pll.asm.rpt b/bsp3/Designflow/ppr/download/vga_pll.asm.rpt new file mode 100644 index 0000000..6f2ca90 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.asm.rpt @@ -0,0 +1,128 @@ +Assembler report for vga_pll +Thu Oct 29 17:13:25 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: vga_pll.sof + 6. Assembler Device Options: vga_pll.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Oct 29 17:13:25 2009 ; +; Revision Name ; vga_pll ; +; Top-level Entity Name ; vga_pll ; +; Family ; Stratix ; +; Device ; EP1S25F672C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Auto-increment JTAG user code for multiple configuration devices ; On ; On ; +; Disable CONF_DONE and nSTATUS pull-ups on configuration device ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Use Checkered Pattern as Uninitialized RAM Content ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++---------------------------+ +; Assembler Generated Files ; ++---------------------------+ +; File Name ; ++---------------------------+ +; vga_pll.sof ; +; vga_pll.pof ; ++---------------------------+ + + ++---------------------------------------+ +; Assembler Device Options: vga_pll.sof ; ++----------------+----------------------+ +; Option ; Setting ; ++----------------+----------------------+ +; Device ; EP1S25F672C6 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x002DD409 ; ++----------------+----------------------+ + + ++---------------------------------------+ +; Assembler Device Options: vga_pll.pof ; ++--------------------+------------------+ +; Option ; Setting ; ++--------------------+------------------+ +; Device ; EPC8 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x0BFCDE72 ; +; Compression Ratio ; 1 ; ++--------------------+------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 17:13:07 2009 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 269 megabytes + Info: Processing ended: Thu Oct 29 17:13:25 2009 + Info: Elapsed time: 00:00:18 + Info: Total CPU time (on all processors): 00:00:18 + + diff --git a/bsp3/Designflow/ppr/download/vga_pll.done b/bsp3/Designflow/ppr/download/vga_pll.done new file mode 100644 index 0000000..6440748 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.done @@ -0,0 +1 @@ +Thu Oct 29 17:13:32 2009 diff --git a/bsp3/Designflow/ppr/download/vga_pll.eda.rpt b/bsp3/Designflow/ppr/download/vga_pll.eda.rpt new file mode 100644 index 0000000..46b1ec9 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.eda.rpt @@ -0,0 +1,94 @@ +EDA Netlist Writer report for vga_pll +Thu Oct 29 17:13:31 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Oct 29 17:13:31 2009 ; +; Revision Name ; vga_pll ; +; Top-level Entity Name ; vga_pll ; +; Family ; Stratix ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate netlist for functional simulation only ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------------------------------+ +; /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.vo ; +; /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo ; ++---------------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II EDA Netlist Writer + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 17:13:31 2009 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll +Info: Generated files "vga_pll.vo" and "vga_pll_v.sdo" in directory "/homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/simulation/modelsim/" for EDA simulation tool +Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 162 megabytes + Info: Processing ended: Thu Oct 29 17:13:32 2009 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/bsp3/Designflow/ppr/download/vga_pll.fit.rpt b/bsp3/Designflow/ppr/download/vga_pll.fit.rpt new file mode 100644 index 0000000..3f8d572 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.fit.rpt @@ -0,0 +1,1638 @@ +Fitter report for vga_pll +Thu Oct 29 17:13:03 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Pin-Out File + 6. Fitter Resource Usage Summary + 7. Input Pins + 8. Output Pins + 9. I/O Bank Usage + 10. All Package Pins + 11. PLL Summary + 12. PLL Usage + 13. Output Pin Default Load For Reported TCO + 14. Fitter Resource Utilization by Entity + 15. Delay Chain Summary + 16. Pad To Core Delay Chain Fanout + 17. Control Signals + 18. Global & Other Fast Signals + 19. Non-Global High Fan-Out Signals + 20. Interconnect Usage Summary + 21. LAB Logic Elements + 22. LAB-wide Signals + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. Fitter Device Options + 27. Estimated Delay Added for Hold Timing + 28. Fitter Messages + 29. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------+ +; Fitter Summary ; ++--------------------------+------------------------------------------+ +; Fitter Status ; Successful - Thu Oct 29 17:13:03 2009 ; +; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; +; Revision Name ; vga_pll ; +; Top-level Entity Name ; vga_pll ; +; Family ; Stratix ; +; Device ; EP1S25F672C6 ; +; Timing Models ; Final ; +; Total logic elements ; 141 / 25,660 ( < 1 % ) ; +; Total pins ; 91 / 474 ( 19 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,944,576 ( 0 % ) ; +; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ; +; Total PLLs ; 1 / 6 ( 17 % ) ; +; Total DLLs ; 0 / 2 ( 0 % ) ; ++--------------------------+------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP1S25F672C6 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Slow Slew Rate ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; < 0.1% ; ++----------------------------+-------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll.pin. + + ++--------------------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------------------------------------------+ +; Total logic elements ; 141 / 25,660 ( < 1 % ) ; +; -- Combinational with no register ; 79 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 62 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 53 ; +; -- 3 input functions ; 32 ; +; -- 2 input functions ; 54 ; +; -- 1 input functions ; 1 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 107 ; +; -- arithmetic mode ; 34 ; +; -- qfbk mode ; 3 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 49 ; +; -- asynchronous clear/load mode ; 3 ; +; ; ; +; Total registers ; 62 / 28,424 ( < 1 % ) ; +; Total LABs ; 18 / 2,566 ( < 1 % ) ; +; Logic elements in carry chains ; 40 ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 91 / 474 ( 19 % ) ; +; -- Clock pins ; 1 / 16 ( 6 % ) ; +; Global signals ; 2 ; +; M512s ; 0 / 224 ( 0 % ) ; +; M4Ks ; 0 / 138 ( 0 % ) ; +; M-RAMs ; 0 / 2 ( 0 % ) ; +; Total memory bits ; 0 / 1,944,576 ( 0 % ) ; +; Total RAM block bits ; 0 / 1,944,576 ( 0 % ) ; +; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ; +; PLLs ; 1 / 6 ( 17 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; Regional clocks ; 0 / 16 ( 0 % ) ; +; Fast regional clocks ; 0 / 8 ( 0 % ) ; +; SERDES transmitters ; 0 / 78 ( 0 % ) ; +; SERDES receivers ; 0 / 78 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 1% / 1% / 1% ; +; Maximum fan-out node ; vpll:inst1|altpll:altpll_component|_clk0 ; +; Maximum fan-out ; 63 ; +; Highest non-global fan-out signal ; vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; +; Highest non-global fan-out ; 11 ; +; Total fan-out ; 678 ; +; Average fan-out ; 2.90 ; ++---------------------------------------------+----------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; board_clk ; N3 ; 2 ; 0 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; reset ; A5 ; 3 ; 7 ; 47 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; ++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ +; b0_pin ; E24 ; 5 ; 79 ; 45 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; b1_pin ; T6 ; 1 ; 0 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_b ; K20 ; 5 ; 79 ; 33 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[0] ; L23 ; 5 ; 79 ; 31 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[1] ; L22 ; 5 ; 79 ; 31 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[2] ; L21 ; 5 ; 79 ; 32 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[3] ; L20 ; 5 ; 79 ; 32 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[4] ; L6 ; 2 ; 0 ; 32 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[5] ; L4 ; 2 ; 0 ; 33 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[6] ; L2 ; 2 ; 0 ; 33 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[7] ; K23 ; 5 ; 79 ; 34 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[8] ; K19 ; 5 ; 79 ; 33 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_column_counter[9] ; K5 ; 2 ; 0 ; 34 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_g ; K24 ; 5 ; 79 ; 34 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_h_enable ; J21 ; 5 ; 79 ; 37 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync ; L7 ; 2 ; 0 ; 32 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_counter[0] ; H4 ; 2 ; 0 ; 42 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_counter[1] ; AA17 ; 7 ; 56 ; 0 ; 4 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[2] ; G17 ; 4 ; 56 ; 47 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[3] ; AE16 ; 7 ; 56 ; 0 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[4] ; D17 ; 4 ; 56 ; 47 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[5] ; F25 ; 5 ; 79 ; 44 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[6] ; A17 ; 4 ; 56 ; 47 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[7] ; G25 ; 5 ; 79 ; 43 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_counter[8] ; G22 ; 5 ; 79 ; 42 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_counter[9] ; G18 ; 4 ; 58 ; 47 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_state[0] ; Y5 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_state[1] ; F19 ; 4 ; 62 ; 47 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_state[2] ; F17 ; 4 ; 56 ; 47 ; 5 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_state[3] ; Y2 ; 1 ; 0 ; 4 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_state[4] ; F10 ; 3 ; 23 ; 47 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_state[5] ; F9 ; 3 ; 21 ; 47 ; 4 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_hsync_state[6] ; F6 ; 3 ; 9 ; 47 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_line_counter[0] ; K6 ; 2 ; 0 ; 34 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_line_counter[1] ; K4 ; 2 ; 0 ; 37 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_line_counter[2] ; J22 ; 5 ; 79 ; 37 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_line_counter[3] ; M9 ; 2 ; 0 ; 29 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_line_counter[4] ; M8 ; 2 ; 0 ; 29 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_line_counter[5] ; M6 ; 2 ; 0 ; 31 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_line_counter[6] ; M5 ; 2 ; 0 ; 30 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_line_counter[7] ; L24 ; 5 ; 79 ; 33 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_line_counter[8] ; L25 ; 5 ; 79 ; 33 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_r ; L3 ; 2 ; 0 ; 33 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_set_column_counter ; Y23 ; 6 ; 79 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_set_hsync_counter ; F26 ; 5 ; 79 ; 44 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_set_line_counter ; F21 ; 4 ; 70 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_set_vsync_counter ; F24 ; 5 ; 79 ; 44 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_state_clk ; K3 ; 2 ; 0 ; 37 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_v_enable ; H18 ; 4 ; 56 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync ; L5 ; 2 ; 0 ; 33 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_counter[0] ; G9 ; 3 ; 23 ; 47 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_counter[1] ; F14 ; 9 ; 37 ; 47 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[2] ; E12 ; 9 ; 37 ; 47 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[3] ; K7 ; 2 ; 0 ; 34 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[4] ; AB12 ; 11 ; 37 ; 0 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[5] ; AA14 ; 11 ; 37 ; 0 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[6] ; K21 ; 5 ; 79 ; 34 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[7] ; G6 ; 2 ; 0 ; 44 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_counter[8] ; G4 ; 2 ; 0 ; 43 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_counter[9] ; G2 ; 2 ; 0 ; 43 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_state[0] ; F5 ; 3 ; 9 ; 47 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_state[1] ; F4 ; 2 ; 0 ; 45 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_state[2] ; F3 ; 2 ; 0 ; 45 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_state[3] ; M19 ; 5 ; 79 ; 29 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_state[4] ; M18 ; 5 ; 79 ; 29 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_state[5] ; M7 ; 2 ; 0 ; 31 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; d_vsync_state[6] ; M4 ; 2 ; 0 ; 30 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; g0_pin ; E23 ; 5 ; 79 ; 45 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; g1_pin ; T5 ; 1 ; 0 ; 15 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; g2_pin ; T24 ; 6 ; 79 ; 15 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; hsync_pin ; F1 ; 2 ; 0 ; 44 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; r0_pin ; E22 ; 4 ; 76 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; r1_pin ; T4 ; 1 ; 0 ; 15 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; r2_pin ; T7 ; 1 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[0] ; R8 ; 1 ; 0 ; 19 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[10] ; R4 ; 1 ; 0 ; 18 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[11] ; R6 ; 1 ; 0 ; 19 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[12] ; AA11 ; 8 ; 31 ; 0 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[13] ; T2 ; 1 ; 0 ; 17 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[1] ; R9 ; 1 ; 0 ; 19 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[2] ; R19 ; 6 ; 79 ; 16 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[3] ; R20 ; 6 ; 79 ; 19 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[4] ; R21 ; 6 ; 79 ; 19 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[5] ; R22 ; 6 ; 79 ; 18 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[6] ; R23 ; 6 ; 79 ; 18 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[7] ; Y11 ; 8 ; 29 ; 0 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[8] ; N7 ; 2 ; 0 ; 29 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; seven_seg_pin[9] ; N8 ; 2 ; 0 ; 28 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; vsync_pin ; F2 ; 2 ; 0 ; 44 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; ++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 11 / 61 ( 18 % ) ; 3.3V ; -- ; +; 2 ; 28 / 59 ( 47 % ) ; 3.3V ; -- ; +; 3 ; 6 / 54 ( 11 % ) ; 3.3V ; -- ; +; 4 ; 10 / 56 ( 18 % ) ; 3.3V ; -- ; +; 5 ; 22 / 59 ( 37 % ) ; 3.3V ; -- ; +; 6 ; 7 / 61 ( 11 % ) ; 3.3V ; -- ; +; 7 ; 2 / 57 ( 4 % ) ; 3.3V ; -- ; +; 8 ; 2 / 54 ( 4 % ) ; 3.3V ; -- ; +; 9 ; 2 / 6 ( 33 % ) ; 3.3V ; -- ; +; 11 ; 2 / 6 ( 33 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; Termination ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+ +; A2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; A3 ; 733 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A4 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; A5 ; 725 ; 3 ; reset ; input ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; A6 ; 717 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A7 ; 703 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A8 ; 702 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A9 ; 695 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A10 ; 684 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; A12 ; 656 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; A14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; A15 ; 640 ; 4 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; A16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; A17 ; 602 ; 4 ; d_hsync_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; A18 ; 589 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A19 ; 579 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A20 ; 571 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A21 ; 564 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A22 ; 554 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; A24 ; 552 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A25 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AA1 ; 158 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA2 ; 157 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA3 ; 160 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA4 ; 159 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA5 ; 155 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA6 ; 154 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA7 ; 195 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA8 ; 214 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA9 ; 223 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA10 ; 227 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA11 ; 251 ; 8 ; seven_seg_pin[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; AA12 ; 269 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA13 ; 273 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA14 ; 271 ; 11 ; d_vsync_counter[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AA15 ; 283 ; 7 ; ^nIO_PULLUP ; ; ; ; -- ; -- ; ; -- ; -- ; +; AA16 ; 304 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA17 ; 316 ; 7 ; d_hsync_counter[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AA18 ; 324 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA19 ; 334 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA20 ; 344 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA21 ; 350 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA22 ; 386 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA23 ; 382 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA24 ; 381 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA25 ; 384 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA26 ; 383 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB1 ; 162 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB2 ; 161 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB3 ; 164 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB4 ; 163 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB5 ; 181 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB6 ; 184 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB7 ; 191 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB8 ; 203 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB9 ; 217 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB10 ; 229 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB11 ; 231 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB12 ; 268 ; 11 ; d_vsync_counter[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AB13 ; 272 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB14 ; 270 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB15 ; 292 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AB16 ; 309 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB17 ; 322 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB18 ; 323 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AB19 ; 336 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB20 ; 346 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB21 ; 351 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB22 ; 365 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB23 ; 378 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB24 ; 377 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB25 ; 380 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB26 ; 379 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AC2 ; 165 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC3 ; 168 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC4 ; 167 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC5 ; 171 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC6 ; 185 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC7 ; 186 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC8 ; 201 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC9 ; 215 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC10 ; 224 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC11 ; 239 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC12 ; 257 ; 8 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; AC13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AC14 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AC15 ; 293 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC16 ; 307 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC17 ; 328 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC18 ; 338 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC19 ; 339 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC20 ; 349 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC21 ; 355 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC22 ; 369 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC23 ; 368 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC24 ; 374 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC25 ; 376 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AD1 ; 166 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AD2 ; 172 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD3 ; 174 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD4 ; 178 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD5 ; 170 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD6 ; 188 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD7 ; 192 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD8 ; 204 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD9 ; 216 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD10 ; 220 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD11 ; 247 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD12 ; 256 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD13 ; ; ; VCCG_PLL6 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; AD14 ; ; ; VCCA_PLL6 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; AD15 ; 302 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD16 ; 310 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD17 ; 329 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD18 ; 335 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD19 ; 337 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD20 ; 353 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD21 ; 354 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AD22 ; 370 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD23 ; 364 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD24 ; 367 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD25 ; 373 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AD26 ; 375 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AE2 ; 173 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE3 ; 179 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE4 ; 176 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE5 ; 187 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AE6 ; 194 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE7 ; 189 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE8 ; 206 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE9 ; 218 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AE10 ; 222 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE11 ; 232 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE12 ; 259 ; 8 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; AE13 ; ; 11 ; VCC_PLL6_OUTA ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AE14 ; ; ; GNDG_PLL6 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AE15 ; 274 ; 7 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; AE16 ; 313 ; 7 ; d_hsync_counter[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AE17 ; 319 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE18 ; 330 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE19 ; 340 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE20 ; 343 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE21 ; 352 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE22 ; 363 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE23 ; 366 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE24 ; 371 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE25 ; 358 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AF3 ; 183 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF4 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AF5 ; 190 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF6 ; 198 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF7 ; 197 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF8 ; 207 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF9 ; 219 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF10 ; 230 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AF12 ; 258 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AF14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AF15 ; 276 ; 7 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; AF16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AF17 ; 315 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF18 ; 327 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF19 ; 331 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF20 ; 342 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF21 ; 347 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF22 ; 360 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF23 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AF24 ; 362 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF25 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B3 ; 740 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B4 ; 736 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B5 ; 730 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B6 ; 716 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B7 ; 709 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B8 ; 704 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B9 ; 698 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B10 ; 694 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B11 ; 667 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B12 ; 655 ; 3 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; B13 ; ; ; GNDG_PLL5 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B14 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B15 ; 638 ; 4 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; B16 ; 610 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B17 ; 596 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B18 ; 582 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B19 ; 577 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B20 ; 567 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B21 ; 563 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B22 ; 551 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B23 ; 548 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B24 ; 543 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B25 ; 544 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; C1 ; 0 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; C2 ; 738 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C3 ; 731 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C4 ; 742 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C5 ; 743 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C6 ; 729 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C7 ; 728 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C8 ; 710 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C9 ; 699 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C10 ; 692 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C11 ; 682 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C12 ; 658 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; C14 ; ; ; VCCG_PLL5 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; C15 ; 617 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C16 ; 605 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C17 ; 592 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C18 ; 581 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C19 ; 573 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C20 ; 559 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C21 ; 566 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C22 ; 556 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C23 ; 550 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C24 ; 547 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C25 ; 539 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; C26 ; 541 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; D1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; D2 ; 1 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; D3 ; 744 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D4 ; 741 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D5 ; 735 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D6 ; 722 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D7 ; 727 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; D8 ; 712 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D9 ; 696 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; D10 ; 691 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D11 ; 683 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D12 ; 657 ; 3 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; D13 ; ; 9 ; VCC_PLL5_OUTA ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; D14 ; ; ; VCCA_PLL5 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; D15 ; 630 ; 4 ; #TRST ; input ; ; ; -- ; -- ; ; -- ; -- ; +; D16 ; 604 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D17 ; 600 ; 4 ; d_hsync_counter[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; D18 ; 583 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D19 ; 575 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D20 ; 562 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D21 ; 561 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D22 ; 546 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D23 ; 545 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D24 ; 538 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; D25 ; 540 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; D26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; E1 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E2 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E5 ; 726 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E6 ; 723 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E7 ; 713 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E8 ; 706 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E9 ; 697 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E10 ; 685 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E11 ; 662 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E12 ; 646 ; 9 ; d_vsync_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; E13 ; 642 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E14 ; 644 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E15 ; 629 ; 4 ; #TMS ; input ; ; ; -- ; -- ; ; -- ; -- ; +; E16 ; 607 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E17 ; 597 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E18 ; 586 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E19 ; 578 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E20 ; 576 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E21 ; 569 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E22 ; 549 ; 4 ; r0_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; E23 ; 534 ; 5 ; g0_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; E24 ; 535 ; 5 ; b0_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; E25 ; 536 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E26 ; 537 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F1 ; 8 ; 2 ; hsync_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; F2 ; 9 ; 2 ; vsync_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; F3 ; 6 ; 2 ; d_vsync_state[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; F4 ; 7 ; 2 ; d_vsync_state[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; F5 ; 720 ; 3 ; d_vsync_state[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; F6 ; 719 ; 3 ; d_hsync_state[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; F7 ; 707 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F8 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; F9 ; 690 ; 3 ; d_hsync_state[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; F10 ; 687 ; 3 ; d_hsync_state[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; F11 ; 659 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; F12 ; 645 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F13 ; 641 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F14 ; 643 ; 9 ; d_vsync_counter[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F15 ; 632 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F16 ; 612 ; 4 ; ~DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F17 ; 599 ; 4 ; d_hsync_state[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; F18 ; 591 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; F19 ; 590 ; 4 ; d_hsync_state[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; F20 ; 584 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F21 ; 572 ; 4 ; d_set_line_counter ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; F22 ; 560 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; F23 ; 530 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F24 ; 531 ; 5 ; d_set_vsync_counter ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; F25 ; 532 ; 5 ; d_hsync_counter[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; F26 ; 533 ; 5 ; d_set_hsync_counter ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; G1 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G2 ; 13 ; 2 ; d_vsync_counter[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; G3 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G4 ; 15 ; 2 ; d_vsync_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; G5 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G6 ; 11 ; 2 ; d_vsync_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; G7 ; 700 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; G9 ; 688 ; 3 ; d_vsync_counter[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; G10 ; 686 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; G11 ; 670 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; G12 ; 653 ; 3 ; ^DCLK ; ; ; ; -- ; -- ; ; -- ; -- ; +; G13 ; ; ; TEMPDIODEn ; ; ; ; -- ; -- ; ; -- ; -- ; +; G14 ; 636 ; 4 ; #TDO ; output ; ; ; -- ; -- ; ; -- ; -- ; +; G15 ; 631 ; 4 ; #TCK ; input ; ; ; -- ; -- ; ; -- ; -- ; +; G16 ; 622 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; G17 ; 601 ; 4 ; d_hsync_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; G18 ; 594 ; 4 ; d_hsync_counter[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; G19 ; 585 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; G20 ; 587 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; G21 ; 522 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G22 ; 523 ; 5 ; d_hsync_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; G23 ; 526 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G24 ; 527 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G25 ; 528 ; 5 ; d_hsync_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; G26 ; 529 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H1 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H2 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H3 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H4 ; 19 ; 2 ; d_hsync_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; H5 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H6 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H7 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H8 ; 20 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; H9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; H10 ; 675 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; H11 ; 654 ; 3 ; ^CONF_DONE ; ; ; ; -- ; -- ; ; -- ; -- ; +; H12 ; 652 ; 3 ; ^nCONFIG ; ; ; ; -- ; -- ; ; -- ; -- ; +; H13 ; 651 ; 3 ; ^nSTATUS ; ; ; ; -- ; -- ; ; -- ; -- ; +; H14 ; ; ; TEMPDIODEp ; ; ; ; -- ; -- ; ; -- ; -- ; +; H15 ; 635 ; 4 ; #TDI ; input ; ; ; -- ; -- ; ; -- ; -- ; +; H16 ; 621 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; H17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; H18 ; 603 ; 4 ; d_v_enable ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; H19 ; 506 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H20 ; 505 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H21 ; 514 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H22 ; 513 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H23 ; 518 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H24 ; 517 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H25 ; 524 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H26 ; 525 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J1 ; 34 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J2 ; 33 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J3 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J4 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J5 ; 36 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J6 ; 35 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J7 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J8 ; 48 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; J12 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; J13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J15 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; J16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; J17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J18 ; 521 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; J19 ; 494 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J20 ; 493 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J21 ; 504 ; 5 ; d_h_enable ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; J22 ; 503 ; 5 ; d_line_counter[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; J23 ; 512 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J24 ; 511 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J25 ; 508 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J26 ; 507 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K1 ; 46 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K2 ; 45 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K3 ; 38 ; 2 ; d_state_clk ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; K4 ; 37 ; 2 ; d_line_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; K5 ; 50 ; 2 ; d_column_counter[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; K6 ; 49 ; 2 ; d_line_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; K7 ; 52 ; 2 ; d_vsync_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K8 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K9 ; 47 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; K14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; K18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K19 ; 486 ; 5 ; d_column_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; K20 ; 485 ; 5 ; d_b ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; K21 ; 490 ; 5 ; d_vsync_counter[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K22 ; 489 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K23 ; 492 ; 5 ; d_column_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; K24 ; 491 ; 5 ; d_g ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; K25 ; 496 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K26 ; 495 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; L1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; L2 ; 54 ; 2 ; d_column_counter[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L3 ; 53 ; 2 ; d_r ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L4 ; 56 ; 2 ; d_column_counter[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L5 ; 55 ; 2 ; d_vsync ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L6 ; 60 ; 2 ; d_column_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L7 ; 59 ; 2 ; d_hsync ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L8 ; 61 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; L9 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; L10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; L12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; L16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; L18 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; L19 ; 480 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; L20 ; 482 ; 5 ; d_column_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L21 ; 481 ; 5 ; d_column_counter[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L22 ; 478 ; 5 ; d_column_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L23 ; 479 ; 5 ; d_column_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L24 ; 488 ; 5 ; d_line_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L25 ; 487 ; 5 ; d_line_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; L26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; M1 ; 81 ; 2 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; M2 ; ; ; VCCG_PLL1 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M3 ; ; ; VCCA_PLL1 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M4 ; 66 ; 2 ; d_vsync_state[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; M5 ; 67 ; 2 ; d_line_counter[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; M6 ; 62 ; 2 ; d_line_counter[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; M7 ; 63 ; 2 ; d_vsync_state[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; M8 ; 72 ; 2 ; d_line_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; M9 ; 73 ; 2 ; d_line_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; M11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; M13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; M15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; M17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M18 ; 468 ; 5 ; d_vsync_state[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; M19 ; 469 ; 5 ; d_vsync_state[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; M20 ; 470 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M21 ; 471 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M22 ; 474 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M23 ; 475 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M24 ; 462 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; M25 ; 463 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; M26 ; 460 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N2 ; 78 ; 2 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; N3 ; 79 ; 2 ; board_clk ; input ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; N4 ; ; ; GNDG_PLL1 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N5 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N6 ; 70 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; N7 ; 71 ; 2 ; seven_seg_pin[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; N8 ; 77 ; 2 ; seven_seg_pin[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; N9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N19 ; 453 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; N20 ; 464 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; N21 ; 465 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; N22 ; ; ; GNDG_PLL4 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N23 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N24 ; ; ; VCCG_PLL4 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N25 ; ; ; VCCA_PLL4 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P2 ; ; ; GNDG_PLL2 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P3 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P4 ; ; ; VCCG_PLL2 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P5 ; ; ; VCCA_PLL2 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P6 ; 88 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P7 ; 89 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P8 ; 76 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P19 ; 452 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P20 ; 448 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P21 ; 449 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P22 ; ; ; VCCA_PLL3 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P23 ; ; ; VCCG_PLL3 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P24 ; 457 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; P25 ; 458 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; P26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R1 ; 82 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; R2 ; 83 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; R3 ; 84 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; R4 ; 94 ; 1 ; seven_seg_pin[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; R5 ; 95 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R6 ; 90 ; 1 ; seven_seg_pin[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; R7 ; 91 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R8 ; 92 ; 1 ; seven_seg_pin[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; R9 ; 93 ; 1 ; seven_seg_pin[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; R10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; R17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R18 ; 443 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; R19 ; 436 ; 6 ; seven_seg_pin[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; R20 ; 450 ; 6 ; seven_seg_pin[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; R21 ; 451 ; 6 ; seven_seg_pin[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; R22 ; 446 ; 6 ; seven_seg_pin[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; R23 ; 447 ; 6 ; seven_seg_pin[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; R24 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R25 ; ; ; GNDG_PLL3 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R26 ; 459 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; T1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; T2 ; 100 ; 1 ; seven_seg_pin[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; T3 ; 99 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T4 ; 108 ; 1 ; r1_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; T5 ; 107 ; 1 ; g1_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; T6 ; 106 ; 1 ; b1_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; T7 ; 105 ; 1 ; r2_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; T8 ; 98 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; T9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; T11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; T12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; T13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; T15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; T17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; T18 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; T19 ; 435 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T20 ; 432 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T21 ; 431 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T22 ; 442 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T23 ; 441 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T24 ; 434 ; 6 ; g2_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; T25 ; 433 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; U1 ; 112 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U2 ; 111 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U3 ; 116 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U4 ; 115 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U5 ; 110 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U6 ; 109 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U7 ; 114 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U8 ; 113 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U9 ; 117 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; U11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; U12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; U14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; U15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; U16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; U17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; U18 ; 428 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U19 ; 427 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U20 ; 424 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U21 ; 430 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U22 ; 429 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U23 ; 418 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U24 ; 417 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U25 ; 426 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U26 ; 425 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V1 ; 132 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V2 ; 133 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V3 ; 136 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V4 ; 137 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V5 ; 124 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V6 ; 123 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V7 ; 127 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; V8 ; 118 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; V12 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; V13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V15 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; V16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; V17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V19 ; 423 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V20 ; 414 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; V21 ; 406 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V22 ; 407 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V23 ; 404 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V24 ; 405 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V25 ; 408 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V26 ; 409 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W1 ; 140 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W2 ; 141 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W3 ; 148 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W4 ; 149 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W5 ; 134 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W6 ; 135 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W7 ; 138 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W8 ; 139 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W9 ; 212 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; W10 ; 228 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; W11 ; 255 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; W12 ; 260 ; 8 ; PLL_ENA ; ; ; ; -- ; -- ; ; -- ; -- ; +; W13 ; 263 ; 8 ; ^MSEL2 ; ; ; ; -- ; -- ; ; -- ; -- ; +; W14 ; 279 ; 7 ; ^nCEO ; ; ; ; -- ; -- ; ; -- ; -- ; +; W15 ; 282 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; W16 ; 285 ; 7 ; ^PORSEL ; ; ; ; -- ; -- ; ; -- ; -- ; +; W17 ; 311 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; W18 ; 321 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; W19 ; 402 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W20 ; 403 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W21 ; 394 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W22 ; 395 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W23 ; 392 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W24 ; 393 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W25 ; 400 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W26 ; 401 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y1 ; 153 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y2 ; 152 ; 1 ; d_hsync_state[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; Y3 ; 146 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y4 ; 147 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y5 ; 151 ; 1 ; d_hsync_state[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; Y6 ; 150 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y7 ; 156 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; Y8 ; 210 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y9 ; 209 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y10 ; 226 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y11 ; 244 ; 8 ; seven_seg_pin[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ; +; Y12 ; 261 ; 8 ; ^MSEL0 ; ; ; ; -- ; -- ; ; -- ; -- ; +; Y13 ; 262 ; 8 ; ^MSEL1 ; ; ; ; -- ; -- ; ; -- ; -- ; +; Y14 ; 278 ; 7 ; ^nCE ; ; ; ; -- ; -- ; ; -- ; -- ; +; Y15 ; 284 ; 7 ; ^VCCSEL ; ; ; ; -- ; -- ; ; -- ; -- ; +; Y16 ; 297 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y17 ; 314 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y18 ; 317 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y19 ; 325 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y20 ; 333 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y21 ; 385 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; Y22 ; 387 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y23 ; 391 ; 6 ; d_set_column_counter ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ; +; Y24 ; 390 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y25 ; 389 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y26 ; 388 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; ++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+----------------------------------------+ +; Name ; vpll:inst1|altpll:altpll_component|pll ; ++-------------------------------+----------------------------------------+ +; SDC pin name ; inst1|altpll_component|pll ; +; PLL type ; Fast ; +; Scan chain ; None ; +; PLL mode ; Normal ; +; Feedback source ; -- ; +; Compensate clock ; clock0 ; +; Compensated input/output pins ; -- ; +; Switchover on loss of clock ; -- ; +; Switchover counter ; -- ; +; Primary clock ; -- ; +; Input frequency 0 ; 33.33 MHz ; +; Input frequency 1 ; -- ; +; Nominal PFD frequency ; 16.7 MHz ; +; Nominal VCO frequency ; 516.5 MHz ; +; Freq min lock ; 20.0 MHz ; +; Freq max lock ; 64.52 MHz ; +; Clock Offset ; -707 ps ; +; M VCO Tap ; 3 ; +; M Initial ; 1 ; +; M value ; 31 ; +; N value ; 2 ; +; M counter delay ; -- ; +; N counter delay ; -- ; +; M2 value ; -- ; +; N2 value ; -- ; +; SS counter ; -- ; +; Downspread ; -- ; +; Spread frequency ; -- ; +; Charge pump current ; 20 uA ; +; Loop filter resistance ; 1.021000 KOhm ; +; Loop filter capacitance ; 10 pF ; +; Freq zero ; 0.240 MHz ; +; Bandwidth ; 200 KHz ; +; Freq pole ; 15.844 MHz ; +; enable0 counter ; -- ; +; enable1 counter ; -- ; +; Real time reconfigurable ; -- ; +; Scan chain MIF file ; -- ; +; Preserve PLL counter order ; Off ; +; PLL location ; PLL_1 ; +; Inclk0 signal ; board_clk ; +; Inclk1 signal ; -- ; +; Inclk0 signal type ; Dedicated Pin ; +; Inclk1 signal type ; -- ; ++-------------------------------+----------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++------------------------------------------+--------------+------+-----+------------------+--------------+-------+------------+---------+---------------+---------------+------------+---------+---------+-----------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Delay ; Duty Cycle ; Counter ; Counter Delay ; Counter Value ; High / Low ; Initial ; VCO Tap ; SDC Pin Name ; ++------------------------------------------+--------------+------+-----+------------------+--------------+-------+------------+---------+---------------+---------------+------------+---------+---------+-----------------------------------+ +; vpll:inst1|altpll:altpll_component|_clk0 ; clock0 ; 31 ; 38 ; 27.19 MHz ; -7 (-725 ps) ; 0 ps ; 50/50 ; G0 ; -- ; 19 ; 10/9 Odd ; 1 ; 0 ; inst1|altpll_component|pll|clk[0] ; ++------------------------------------------+--------------+------+-----+------------------+--------------+-------+------------+---------+---------------+---------------+------------+---------+---------+-----------------------------------+ + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 10 pF ; Not Available ; +; 3.3-V LVCMOS ; 10 pF ; Not Available ; +; 2.5 V ; 10 pF ; Not Available ; +; 1.8 V ; 10 pF ; Not Available ; +; 1.5 V ; 10 pF ; Not Available ; +; GTL ; 30 pF ; 25 Ohm (Parallel) ; +; GTL+ ; 30 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 8 pF ; 25 Ohm (Parallel) ; +; Compact PCI ; 10 pF ; 25 Ohm (Parallel) ; +; AGP 1X ; 10 pF ; Not Available ; +; AGP 2X ; 10 pF ; Not Available ; +; CTT ; 30 pF ; 50 Ohm (Parallel) ; +; SSTL-3 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-3 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 20 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 20 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 20 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 20 pF ; 25 Ohm (Parallel) ; +; LVDS ; 4 pF ; 100 Ohm (Differential) ; +; Differential LVPECL ; 4 pF ; 100 Ohm (Differential) ; +; 3.3-V PCML ; 4 pF ; 50 Ohm (Parallel) ; +; HyperTransport ; 4 pF ; 100 Ohm (Differential) ; +; Differential 1.5-V HSTL Class I ; 20 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.8-V HSTL Class I ; 20 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 20 pF ; (See 1.8-V HSTL Class II) ; +; Differential SSTL-2 ; 30 pF ; (See SSTL-2) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++--------------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++--------------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+ +; |vga_pll ; 141 (1) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 91 ; 0 ; 79 (1) ; 0 (0) ; 62 (0) ; 40 (0) ; 3 (0) ; |vga_pll ; work ; +; |vga:inst| ; 140 (2) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 90 ; 0 ; 78 (0) ; 0 (0) ; 62 (2) ; 40 (0) ; 3 (0) ; |vga_pll|vga:inst ; work ; +; |vga_control:vga_control_unit| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |vga_pll|vga:inst|vga_control:vga_control_unit ; work ; +; |vga_driver:vga_driver_unit| ; 128 (128) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 71 (71) ; 0 (0) ; 57 (57) ; 40 (40) ; 3 (3) ; |vga_pll|vga:inst|vga_driver:vga_driver_unit ; work ; +; |vpll:inst1| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1 ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1|altpll:altpll_component ; work ; ++--------------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; Core to Output Register ; Clock Enable to Output Enable Register ; Clock Enable to Output Register ; Clock Enable to Input Register ; TCO ; TCOE ; Falling Edge Output Enable ; ++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+ +; board_clk ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; d_hsync ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_set_column_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_set_line_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_set_hsync_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_set_vsync_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_r ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_g ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_b ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_h_enable ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_v_enable ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_state_clk ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; r0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; r1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; r2_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; g0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; g1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; g2_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; b0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; b1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; hsync_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; vsync_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[13] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[12] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[11] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[10] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; reset ; Input ; ON ; ON ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------------------------------------------------------------+-------------------+---------+ +; board_clk ; ; ; +; vga:inst|reset_pin_in ; ; ; +; - vga:inst|vga_driver:vga_driver_unit|vsync_state_6_ ; 0 ; ON ; +; - vga:inst|vga_driver:vga_driver_unit|h_sync_Z ; 0 ; ON ; +; - vga:inst|vga_driver:vga_driver_unit|v_sync_Z ; 0 ; ON ; +; - vga:inst|dly_counter_0_ ; 0 ; ON ; +; - vga:inst|dly_counter_1_ ; 0 ; ON ; +; - vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ ; 0 ; ON ; +; - vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ ; 0 ; ON ; +; - vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ ; 0 ; ON ; +; - vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ ; 0 ; ON ; ++--------------------------------------------------------------------------------+-------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++----------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++----------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+ +; board_clk ; PIN_N3 ; 1 ; Clock ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|G_16_i ; LC_X35_Y34_N4 ; 10 ; Sync. clear ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|G_2_i ; LC_X55_Y44_N5 ; 10 ; Sync. clear ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; LC_X36_Y33_N8 ; 10 ; Sync. clear ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ; LC_X34_Y34_N6 ; 1 ; Clock enable ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; LC_X56_Y44_N7 ; 6 ; Clock enable ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; LC_X36_Y33_N6 ; 9 ; Sync. clear ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x ; LC_X36_Y33_N7 ; 32 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK12 ; +; vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; LC_X55_Y44_N4 ; 11 ; Sync. load ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9 ; LC_X35_Y34_N5 ; 11 ; Sync. load ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ; LC_X56_Y45_N2 ; 1 ; Clock enable ; no ; -- ; -- ; +; vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa ; LC_X36_Y34_N2 ; 5 ; Clock enable ; no ; -- ; -- ; +; vpll:inst1|altpll:altpll_component|_clk0 ; PLL_1 ; 63 ; Clock ; yes ; Global Clock ; GCLK1 ; ++----------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++---------------------------------------------------------+---------------+---------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; ++---------------------------------------------------------+---------------+---------+----------------------+------------------+ +; vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x ; LC_X36_Y33_N7 ; 32 ; Global Clock ; GCLK12 ; +; vpll:inst1|altpll:altpll_component|_clk0 ; PLL_1 ; 63 ; Global Clock ; GCLK1 ; ++---------------------------------------------------------+---------------+---------+----------------------+------------------+ + + ++--------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++----------------------------------------------------------------------+---------+ +; vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9 ; 11 ; +; vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; 11 ; +; vga:inst|vga_driver:vga_driver_unit|G_16_i ; 10 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa ; 10 ; +; vga:inst|vga_driver:vga_driver_unit|G_2_i ; 10 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa ; 10 ; +; vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; 10 ; +; vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 ; 10 ; +; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; 10 ; +; reset ; 9 ; +; vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; 9 ; +; vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 ; 9 ; +; vga:inst|dly_counter[1] ; 9 ; +; vga:inst|dly_counter[0] ; 9 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; 9 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; 9 ; +; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; 9 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; 7 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; 7 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; 7 ; +; ~STRATIX_FITTER_CREATED_GND~I ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; 6 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[4] ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[4] ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; 5 ; +; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; 5 ; ++----------------------------------------------------------------------+---------+ + + ++-------------------------------------------------------+ +; Interconnect Usage Summary ; ++-----------------------------+-------------------------+ +; Interconnect Resource Type ; Usage ; ++-----------------------------+-------------------------+ +; C16 interconnects ; 45 / 4,620 ( < 1 % ) ; +; C4 interconnects ; 118 / 69,840 ( < 1 % ) ; +; C8 interconnects ; 41 / 15,568 ( < 1 % ) ; +; DIFFIOCLKs ; 0 / 16 ( 0 % ) ; +; DQS bus muxes ; 0 / 102 ( 0 % ) ; +; DQS-16 I/O buses ; 0 / 8 ( 0 % ) ; +; DQS-32 I/O buses ; 0 / 4 ( 0 % ) ; +; DQS-8 I/O buses ; 0 / 20 ( 0 % ) ; +; Direct links ; 40 / 104,060 ( < 1 % ) ; +; Fast regional clocks ; 0 / 8 ( 0 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; I/O buses ; 21 / 320 ( 7 % ) ; +; LUT chains ; 2 / 23,094 ( < 1 % ) ; +; Local routing interconnects ; 102 / 25,660 ( < 1 % ) ; +; R24 interconnects ; 86 / 4,692 ( 2 % ) ; +; R4 interconnects ; 137 / 141,520 ( < 1 % ) ; +; R8 interconnects ; 27 / 22,956 ( < 1 % ) ; +; Regional clocks ; 0 / 16 ( 0 % ) ; ++-----------------------------+-------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 7.83) ; Number of LABs (Total = 18) ; ++--------------------------------------------+------------------------------+ +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 12 ; ++--------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 18) ; ++------------------------------------+------------------------------+ +; 1 Async. clear ; 2 ; +; 1 Clock ; 17 ; +; 1 Clock enable ; 4 ; +; 1 Sync. clear ; 11 ; +; 1 Sync. load ; 2 ; ++------------------------------------+------------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 7.94) ; Number of LABs (Total = 18) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 2 ; +; 10 ; 7 ; +; 11 ; 2 ; +; 12 ; 1 ; ++---------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 5.94) ; Number of LABs (Total = 18) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 2 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 3 ; +; 6 ; 2 ; +; 7 ; 3 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 2 ; +; 11 ; 1 ; ++-------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 11.22) ; Number of LABs (Total = 18) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 3 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 3 ; +; 11 ; 1 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 1 ; +; 17 ; 2 ; +; 18 ; 1 ; +; 19 ; 1 ; +; 20 ; 0 ; +; 21 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Error detection CRC ; Off ; +; nWS, nRS, nCS, CS ; Unreserved ; +; RDYnBUSY ; Unreserved ; +; Data[7..1] ; Unreserved ; +; Data[0] ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 17:12:35 2009 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Info: Selected device EP1S25F672C6 for design "vga_pll" +Warning: Output port clk0 of PLL "vpll:inst1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP1S10F672C6 is compatible + Info: Device EP1S20F672C6 is compatible + Info: Device EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE is compatible +Info: Fitter converted 1 user pins into dedicated programming pins + Info: Pin ~DATA0~ is reserved at location F16 +Warning: No exact pin location assignment(s) for 12 pins of 91 total pins + Info: Pin d_hsync_counter[6] not assigned to an exact location on the device + Info: Pin d_hsync_counter[5] not assigned to an exact location on the device + Info: Pin d_hsync_counter[4] not assigned to an exact location on the device + Info: Pin d_hsync_counter[3] not assigned to an exact location on the device + Info: Pin d_hsync_counter[2] not assigned to an exact location on the device + Info: Pin d_hsync_counter[1] not assigned to an exact location on the device + Info: Pin d_vsync_counter[6] not assigned to an exact location on the device + Info: Pin d_vsync_counter[5] not assigned to an exact location on the device + Info: Pin d_vsync_counter[4] not assigned to an exact location on the device + Info: Pin d_vsync_counter[3] not assigned to an exact location on the device + Info: Pin d_vsync_counter[2] not assigned to an exact location on the device + Info: Pin d_vsync_counter[1] not assigned to an exact location on the device +Info: Fitter is using the Classic Timing Analyzer +Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements +Info: Completed User Assigned Global Signals Promotion Operation +Info: Implementing parameter values for PLL "vpll:inst1|altpll:altpll_component|pll" + Info: Implementing clock multiplication of 31, clock division of 38, and phase shift of 0 degrees (-18 ps) for vpll:inst1|altpll:altpll_component|_clk0 port +Info: Promoted PLL clock signals + Info: Promoted signal "vpll:inst1|altpll:altpll_component|_clk0" to use global clock +Info: Completed PLL Placement Operation +Info: Automatically promoted some destinations of signal "vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x" to use Global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|hsync_state_6_" may be non-global or may not use global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_0_" may be non-global or may not use global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_1_" may be non-global or may not use global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|v_enable_sig_Z" may be non-global or may not use global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|h_enable_sig_Z" may be non-global or may not use global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_5_" may be non-global or may not use global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_4_" may be non-global or may not use global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_3_" may be non-global or may not use global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_2_" may be non-global or may not use global clock + Info: Destination "vga:inst|vga_driver:vga_driver_unit|hsync_state_5_" may be non-global or may not use global clock + Info: Limited to 10 non-global destinations +Info: Completed Auto Global Promotion Operation +Info: Starting register packing +Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option +Info: Finished register packing +Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info: Number of I/O pins in group: 12 (unused VREF, 3.3V VCCIO, 0 input, 12 output, 0 bidirectional) + Info: I/O standards used: 3.3-V LVTTL. +Info: I/O bank details before I/O pin placement + Info: Statistics of I/O banks + Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 11 total pin(s) used -- 50 pins available + Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used -- 32 pins available + Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 6 total pin(s) used -- 48 pins available + Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 7 total pin(s) used -- 49 pins available + Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used -- 39 pins available + Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 7 total pin(s) used -- 54 pins available + Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 57 pins available + Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used -- 52 pins available + Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available + Info: I/O bank number 11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available +Info: Fitter preparation operations ending: elapsed time is 00:00:03 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:03 +Info: Slack time is 29.931 ns between source register "vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9" and destination register "vga:inst|vga_control:vga_control_unit|b" + Info: + Largest register to register requirement is 36.591 ns + Info: Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.138 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'vga:inst|vga_control:vga_control_unit|b' + Info: Total cell delay = 0.560 ns ( 26.19 % ) + Info: Total interconnect delay = 1.578 ns ( 73.81 % ) + Info: Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.138 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'vga:inst|vga_control:vga_control_unit|b' + Info: Total cell delay = 0.560 ns ( 26.19 % ) + Info: Total interconnect delay = 1.578 ns ( 73.81 % ) + Info: Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.138 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9' + Info: Total cell delay = 0.560 ns ( 26.19 % ) + Info: Total interconnect delay = 1.578 ns ( 73.81 % ) + Info: Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.138 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9' + Info: Total cell delay = 0.560 ns ( 26.19 % ) + Info: Total interconnect delay = 1.578 ns ( 73.81 % ) + Info: Micro clock to output delay of source is 0.176 ns + Info: Micro setup delay of destination is 0.010 ns + Info: - Longest register to register delay is 6.660 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9' + Info: 2: + IC(2.108 ns) + CELL(0.459 ns) = 2.567 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'vga:inst|vga_control:vga_control_unit|r_next_i_o7' + Info: 3: + IC(2.405 ns) + CELL(0.087 ns) = 5.059 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0' + Info: 4: + IC(1.366 ns) + CELL(0.235 ns) = 6.660 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'vga:inst|vga_control:vga_control_unit|b' + Info: Total cell delay = 0.781 ns ( 11.73 % ) + Info: Total interconnect delay = 5.879 ns ( 88.27 % ) +Info: Estimated most critical path is register to register delay of 6.660 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X78_Y33; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9' + Info: 2: + IC(2.108 ns) + CELL(0.459 ns) = 2.567 ns; Loc. = LAB_X56_Y45; Fanout = 3; COMB Node = 'vga:inst|vga_control:vga_control_unit|r_next_i_o7' + Info: 3: + IC(2.405 ns) + CELL(0.087 ns) = 5.059 ns; Loc. = LAB_X76_Y33; Fanout = 1; COMB Node = 'vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0' + Info: 4: + IC(1.366 ns) + CELL(0.235 ns) = 6.660 ns; Loc. = LAB_X78_Y32; Fanout = 3; REG Node = 'vga:inst|vga_control:vga_control_unit|b' + Info: Total cell delay = 0.781 ns ( 11.73 % ) + Info: Total interconnect delay = 5.879 ns ( 88.27 % ) +Info: Fitter routing operations beginning +Info: Average interconnect usage is 0% of the available device resources + Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X34_Y24 to location X44_Y35 +Info: Fitter routing operations ending: elapsed time is 00:00:01 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Completed Fixed Delay Chain Operation +Info: Started post-fitting delay annotation +Info: Delay annotation completed successfully +Info: Completed Auto Delay Chain Operation +Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results + Info: Pin seven_seg_pin[13] has GND driving its datain port + Info: Pin seven_seg_pin[6] has GND driving its datain port + Info: Pin seven_seg_pin[5] has GND driving its datain port + Info: Pin seven_seg_pin[4] has GND driving its datain port + Info: Pin seven_seg_pin[3] has GND driving its datain port + Info: Pin seven_seg_pin[0] has GND driving its datain port +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Generated suppressed messages file /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 320 megabytes + Info: Processing ended: Thu Oct 29 17:13:03 2009 + Info: Elapsed time: 00:00:28 + Info: Total CPU time (on all processors): 00:00:28 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll.fit.smsg. + + diff --git a/bsp3/Designflow/ppr/download/vga_pll.fit.smsg b/bsp3/Designflow/ppr/download/vga_pll.fit.smsg new file mode 100644 index 0000000..38de4e4 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.fit.smsg @@ -0,0 +1,8 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Start inferring scan chains for DSP blocks +Extra Info: Inferring scan chains for DSP blocks is complete +Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density +Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks diff --git a/bsp3/Designflow/ppr/download/vga_pll.fit.summary b/bsp3/Designflow/ppr/download/vga_pll.fit.summary new file mode 100644 index 0000000..1153f42 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.fit.summary @@ -0,0 +1,14 @@ +Fitter Status : Successful - Thu Oct 29 17:13:03 2009 +Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version +Revision Name : vga_pll +Top-level Entity Name : vga_pll +Family : Stratix +Device : EP1S25F672C6 +Timing Models : Final +Total logic elements : 141 / 25,660 ( < 1 % ) +Total pins : 91 / 474 ( 19 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,944,576 ( 0 % ) +DSP block 9-bit elements : 0 / 80 ( 0 % ) +Total PLLs : 1 / 6 ( 17 % ) +Total DLLs : 0 / 2 ( 0 % ) diff --git a/bsp3/Designflow/ppr/download/vga_pll.flow.rpt b/bsp3/Designflow/ppr/download/vga_pll.flow.rpt new file mode 100644 index 0000000..b59b8b3 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.flow.rpt @@ -0,0 +1,125 @@ +Flow report for vga_pll +Thu Oct 29 17:13:31 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------+ +; Flow Summary ; ++--------------------------+------------------------------------------+ +; Flow Status ; Successful - Thu Oct 29 17:13:31 2009 ; +; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; +; Revision Name ; vga_pll ; +; Top-level Entity Name ; vga_pll ; +; Family ; Stratix ; +; Device ; EP1S25F672C6 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 141 / 25,660 ( < 1 % ) ; +; Total pins ; 91 / 474 ( 19 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,944,576 ( 0 % ) ; +; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ; +; Total PLLs ; 1 / 6 ( 17 % ) ; +; Total DLLs ; 0 / 2 ( 0 % ) ; ++--------------------------+------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 10/29/2009 17:12:29 ; +; Main task ; Compilation ; +; Revision Name ; vga_pll ; ++-------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+-----------------------------+---------------+-------------+----------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+-----------------------------+---------------+-------------+----------------------+ +; COMPILER_SIGNATURE_ID ; 91815334056.125683274905785 ; -- ; -- ; -- ; +; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Synplify Pro ; ; -- ; -- ; +; EDA_INPUT_DATA_FORMAT ; Vqm ; -- ; -- ; eda_design_synthesis ; +; EDA_LMF_FILE ; synplcty.lmf ; -- ; -- ; eda_design_synthesis ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; ++------------------------------------+-----------------------------+---------------+-------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:04 ; 1.0 ; -- ; 00:00:03 ; +; Fitter ; 00:00:28 ; 1.0 ; -- ; 00:00:28 ; +; Assembler ; 00:00:18 ; 1.0 ; -- ; 00:00:17 ; +; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; -- ; 00:00:00 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; -- ; 00:00:01 ; +; Total ; 00:00:50 ; -- ; -- ; 00:00:49 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------+------------+----------------+ +; Analysis & Synthesis ; ti14 ; Red Hat ; 5 ; x86_64 ; +; Fitter ; ti14 ; Red Hat ; 5 ; x86_64 ; +; Assembler ; ti14 ; Red Hat ; 5 ; x86_64 ; +; Classic Timing Analyzer ; ti14 ; Red Hat ; 5 ; x86_64 ; +; EDA Netlist Writer ; ti14 ; Red Hat ; 5 ; x86_64 ; ++-------------------------+------------------+---------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll +quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll +quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll +quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only +quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll + + + diff --git a/bsp3/Designflow/ppr/download/vga_pll.map.rpt b/bsp3/Designflow/ppr/download/vga_pll.map.rpt new file mode 100644 index 0000000..0e94592 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.map.rpt @@ -0,0 +1,666 @@ +Analysis & Synthesis report for vga_pll +Thu Oct 29 17:12:32 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. General Register Statistics + 8. Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component + 9. altpll Parameter Settings by Entity Instance + 10. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Oct 29 17:12:32 2009 ; +; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; +; Revision Name ; vga_pll ; +; Top-level Entity Name ; vga_pll ; +; Family ; Stratix ; +; Total logic elements ; 143 ; +; Total pins ; 91 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; DSP block 9-bit elements ; 0 ; +; Total PLLs ; 1 ; +; Total DLLs ; 0 ; ++-----------------------------+------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP1S25F672C6 ; ; +; Top-level entity name ; vga_pll ; vga_pll ; +; Family name ; Stratix ; Stratix ; +; Type of Retiming Performed During Resynthesis ; Full ; ; +; Resynthesis Optimization Effort ; Normal ; ; +; Physical Synthesis Level for Resynthesis ; Normal ; ; +; Use Generated Physical Constraints File ; On ; ; +; Use smart compilation ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++----------------------------------------------------------------+--------------------+--------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+ +; ../../src/vga_pll.bdf ; yes ; User Block Diagram/Schematic File ; /homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf ; +; ../../syn/rev_1/vga.vqm ; yes ; User Verilog Quartus Mapping File ; /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm ; +; ../../src/vpll.vhd ; yes ; User Wizard-Generated File ; /homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd ; +; altpll.tdf ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/altpll.tdf ; +; aglobal90.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/aglobal90.inc ; +; stratix_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratix_pll.inc ; +; stratixii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratixii_pll.inc ; +; cycloneii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/cycloneii_pll.inc ; ++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+------------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+------------------------------------------+ +; Total logic elements ; 143 ; +; -- Combinational with no register ; 81 ; +; -- Register only ; 3 ; +; -- Combinational with a register ; 59 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 53 ; +; -- 3 input functions ; 32 ; +; -- 2 input functions ; 54 ; +; -- 1 input functions ; 1 ; +; -- 0 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 109 ; +; -- arithmetic mode ; 34 ; +; -- qfbk mode ; 0 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 48 ; +; -- asynchronous clear/load mode ; 3 ; +; ; ; +; Total registers ; 62 ; +; Total logic cells in carry chains ; 40 ; +; I/O pins ; 91 ; +; Total PLLs ; 1 ; +; Maximum fan-out node ; vpll:inst1|altpll:altpll_component|_clk0 ; +; Maximum fan-out ; 63 ; +; Total fan-out ; 667 ; +; Average fan-out ; 2.84 ; ++---------------------------------------------+------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+ +; |vga_pll ; 143 (0) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 91 ; 0 ; 81 (0) ; 3 (0) ; 59 (0) ; 40 (0) ; 0 (0) ; |vga_pll ; work ; +; |vga:inst| ; 143 (2) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 90 ; 0 ; 81 (0) ; 3 (0) ; 59 (2) ; 40 (0) ; 0 (0) ; |vga_pll|vga:inst ; work ; +; |vga_control:vga_control_unit| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |vga_pll|vga:inst|vga_control:vga_control_unit ; work ; +; |vga_driver:vga_driver_unit| ; 131 (131) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 (74) ; 3 (3) ; 54 (54) ; 40 (40) ; 0 (0) ; |vga_pll|vga:inst|vga_driver:vga_driver_unit ; work ; +; |vpll:inst1| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1 ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1|altpll:altpll_component ; work ; ++--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 62 ; +; Number of registers using Synchronous Clear ; 48 ; +; Number of registers using Synchronous Load ; 20 ; +; Number of registers using Asynchronous Clear ; 3 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 12 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++---------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component ; ++-------------------------------+-------------------+-----------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+-------------------+-----------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 30003 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Signed Integer ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Signed Integer ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Signed Integer ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Untyped ; +; CLK1_MULTIPLY_BY ; 1 ; Untyped ; +; CLK0_MULTIPLY_BY ; 5435 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 1 ; Untyped ; +; CLK1_DIVIDE_BY ; 1 ; Untyped ; +; CLK0_DIVIDE_BY ; 6666 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Untyped ; +; CLK1_DUTY_CYCLE ; 50 ; Untyped ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Stratix ; Untyped ; +; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ; +; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_CONNECTIVITY ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 6 ; Untyped ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Stratix ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+-------------------+-----------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+------------------------------------+ +; Name ; Value ; ++-------------------------------+------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; vpll:inst1|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 30003 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+------------------------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 17:12:28 2009 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll +Info: Revision "vga_pll" was previously opened in Quartus II software version 6.0. Created Quartus II Default Settings File /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 6.0. +Info: Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /opt/quartus/quartus/linux/assignment_defaults.qdf +Info: Found 1 design units, including 1 entities, in source file ../../src/vga_pll.bdf + Info: Found entity 1: vga_pll +Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm + Info: Found entity 1: vga_driver + Info: Found entity 2: vga_control + Info: Found entity 3: vga +Info: Found 2 design units, including 1 entities, in source file ../../src/vpll.vhd + Info: Found design unit 1: vpll-SYN + Info: Found entity 1: vpll +Info: Elaborating entity "vga_pll" for the top level hierarchy +Info: Elaborating entity "vga" for hierarchy "vga:inst" +Info: Elaborating entity "vga_driver" for hierarchy "vga:inst|vga_driver:vga_driver_unit" +Info: Elaborating entity "vga_control" for hierarchy "vga:inst|vga_control:vga_control_unit" +Info: Elaborating entity "vpll" for hierarchy "vpll:inst1" +Warning (10036): Verilog HDL or VHDL warning at vpll.vhd(73): object "locked" assigned a value but never read +Info: Elaborating entity "altpll" for hierarchy "vpll:inst1|altpll:altpll_component" +Info: Elaborated megafunction instantiation "vpll:inst1|altpll:altpll_component" +Info: Instantiated megafunction "vpll:inst1|altpll:altpll_component" with the following parameter: + Info: Parameter "bandwidth_type" = "AUTO" + Info: Parameter "clk0_duty_cycle" = "50" + Info: Parameter "lpm_type" = "altpll" + Info: Parameter "clk0_multiply_by" = "5435" + Info: Parameter "invalid_lock_multiplier" = "5" + Info: Parameter "inclk0_input_frequency" = "30003" + Info: Parameter "gate_lock_signal" = "NO" + Info: Parameter "clk0_divide_by" = "6666" + Info: Parameter "pll_type" = "AUTO" + Info: Parameter "valid_lock_multiplier" = "1" + Info: Parameter "clk0_time_delay" = "0" + Info: Parameter "spread_frequency" = "0" + Info: Parameter "intended_device_family" = "Stratix" + Info: Parameter "operation_mode" = "NORMAL" + Info: Parameter "compensate_clock" = "CLK0" + Info: Parameter "clk0_phase_shift" = "0" +Info: WYSIWYG I/O primitives converted to equivalent logic + Info: WYSIWYG I/O primitive "vga:inst|clk_pin_in" converted to equivalent logic +Info: Implemented 235 device resources after synthesis - the final resource count might be different + Info: Implemented 2 input pins + Info: Implemented 89 output pins + Info: Implemented 143 logic cells + Info: Implemented 1 ClockLock PLLs +Warning: Output port clk0 of PLL "vpll:inst1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 204 megabytes + Info: Processing ended: Thu Oct 29 17:12:32 2009 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/bsp3/Designflow/ppr/download/vga_pll.map.summary b/bsp3/Designflow/ppr/download/vga_pll.map.summary new file mode 100644 index 0000000..3ed3762 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.map.summary @@ -0,0 +1,12 @@ +Analysis & Synthesis Status : Successful - Thu Oct 29 17:12:32 2009 +Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version +Revision Name : vga_pll +Top-level Entity Name : vga_pll +Family : Stratix +Total logic elements : 143 +Total pins : 91 +Total virtual pins : 0 +Total memory bits : 0 +DSP block 9-bit elements : 0 +Total PLLs : 1 +Total DLLs : 0 diff --git a/bsp3/Designflow/ppr/download/vga_pll.pin b/bsp3/Designflow/ppr/download/vga_pll.pin new file mode 100644 index 0000000..ce42e13 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.pin @@ -0,0 +1,748 @@ + -- Copyright (C) 1991-2009 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- Bank 9: 3.3V + -- Bank 11: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), + -- connect each pin marked GND* either individually through a 10k Ohm resistor + -- to GND or tie all pins together and connect through a single 10k Ohm resistor + -- to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version +CHIP "vga_pll" ASSIGNED TO AN: EP1S25F672C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A2 : gnd : : : : +GND* : A3 : : : : 3 : +VCCIO3 : A4 : power : : 3.3V : 3 : +reset : A5 : input : 3.3-V LVTTL : : 3 : Y +GND* : A6 : : : : 3 : +GND* : A7 : : : : 3 : +GND* : A8 : : : : 3 : +GND* : A9 : : : : 3 : +GND* : A10 : : : : 3 : +VCCIO3 : A11 : power : : 3.3V : 3 : +GND* : A12 : : : : 3 : +GND : A13 : gnd : : : : +GND : A14 : gnd : : : : +GND+ : A15 : : : : 4 : +VCCIO4 : A16 : power : : 3.3V : 4 : +d_hsync_counter[6] : A17 : output : 3.3-V LVTTL : : 4 : N +GND* : A18 : : : : 4 : +GND* : A19 : : : : 4 : +GND* : A20 : : : : 4 : +GND* : A21 : : : : 4 : +GND* : A22 : : : : 4 : +VCCIO4 : A23 : power : : 3.3V : 4 : +GND* : A24 : : : : 4 : +GND : A25 : gnd : : : : +GND* : AA1 : : : : 1 : +GND* : AA2 : : : : 1 : +GND* : AA3 : : : : 1 : +GND* : AA4 : : : : 1 : +GND* : AA5 : : : : 1 : +GND* : AA6 : : : : 1 : +GND* : AA7 : : : : 8 : +GND* : AA8 : : : : 8 : +GND* : AA9 : : : : 8 : +GND* : AA10 : : : : 8 : +seven_seg_pin[12] : AA11 : output : 3.3-V LVTTL : : 8 : Y +GND* : AA12 : : : : 11 : +GND* : AA13 : : : : 11 : +d_vsync_counter[5] : AA14 : output : 3.3-V LVTTL : : 11 : N +nIO_PULLUP : AA15 : : : : 7 : +GND* : AA16 : : : : 7 : +d_hsync_counter[1] : AA17 : output : 3.3-V LVTTL : : 7 : N +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND* : AA21 : : : : 7 : +GND* : AA22 : : : : 6 : +GND* : AA23 : : : : 6 : +GND* : AA24 : : : : 6 : +GND* : AA25 : : : : 6 : +GND* : AA26 : : : : 6 : +GND* : AB1 : : : : 1 : +GND* : AB2 : : : : 1 : +GND* : AB3 : : : : 1 : +GND* : AB4 : : : : 1 : +GND* : AB5 : : : : 8 : +GND* : AB6 : : : : 8 : +GND* : AB7 : : : : 8 : +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +GND* : AB10 : : : : 8 : +GND* : AB11 : : : : 8 : +d_vsync_counter[4] : AB12 : output : 3.3-V LVTTL : : 11 : N +GND* : AB13 : : : : 11 : +GND* : AB14 : : : : 11 : +GND : AB15 : gnd : : : : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND : AB18 : gnd : : : : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +GND* : AB21 : : : : 7 : +GND* : AB22 : : : : 7 : +GND* : AB23 : : : : 6 : +GND* : AB24 : : : : 6 : +GND* : AB25 : : : : 6 : +GND* : AB26 : : : : 6 : +VCCIO1 : AC1 : power : : 3.3V : 1 : +GND* : AC2 : : : : 1 : +GND* : AC3 : : : : 1 : +GND* : AC4 : : : : 1 : +GND* : AC5 : : : : 8 : +GND* : AC6 : : : : 8 : +GND* : AC7 : : : : 8 : +GND* : AC8 : : : : 8 : +GND* : AC9 : : : : 8 : +GND* : AC10 : : : : 8 : +GND* : AC11 : : : : 8 : +GND+ : AC12 : : : : 8 : +GND : AC13 : gnd : : : : +GNDA_PLL6 : AC14 : gnd : : : : +GND* : AC15 : : : : 7 : +GND* : AC16 : : : : 7 : +GND* : AC17 : : : : 7 : +GND* : AC18 : : : : 7 : +GND* : AC19 : : : : 7 : +GND* : AC20 : : : : 7 : +GND* : AC21 : : : : 7 : +GND* : AC22 : : : : 7 : +GND* : AC23 : : : : 7 : +GND* : AC24 : : : : 6 : +GND* : AC25 : : : : 6 : +VCCIO6 : AC26 : power : : 3.3V : 6 : +GND* : AD1 : : : : 1 : +GND* : AD2 : : : : 8 : +GND* : AD3 : : : : 8 : +GND* : AD4 : : : : 8 : +GND* : AD5 : : : : 8 : +GND* : AD6 : : : : 8 : +GND* : AD7 : : : : 8 : +GND* : AD8 : : : : 8 : +GND* : AD9 : : : : 8 : +GND* : AD10 : : : : 8 : +GND* : AD11 : : : : 8 : +GND* : AD12 : : : : 8 : +VCCG_PLL6 : AD13 : power : : 1.5V : : +VCCA_PLL6 : AD14 : power : : 1.5V : : +GND* : AD15 : : : : 7 : +GND* : AD16 : : : : 7 : +GND* : AD17 : : : : 7 : +GND* : AD18 : : : : 7 : +GND* : AD19 : : : : 7 : +GND* : AD20 : : : : 7 : +GND : AD21 : gnd : : : : +GND* : AD22 : : : : 7 : +GND* : AD23 : : : : 7 : +GND* : AD24 : : : : 7 : +GND* : AD25 : : : : 6 : +GND* : AD26 : : : : 6 : +GND : AE1 : gnd : : : : +GND* : AE2 : : : : 8 : +GND* : AE3 : : : : 8 : +GND* : AE4 : : : : 8 : +GND : AE5 : gnd : : : : +GND* : AE6 : : : : 8 : +GND* : AE7 : : : : 8 : +GND* : AE8 : : : : 8 : +GND : AE9 : gnd : : : : +GND* : AE10 : : : : 8 : +GND* : AE11 : : : : 8 : +GND+ : AE12 : : : : 8 : +VCC_PLL6_OUTA : AE13 : power : : 3.3V : 11 : +GNDG_PLL6 : AE14 : gnd : : : : +GND+ : AE15 : : : : 7 : +d_hsync_counter[3] : AE16 : output : 3.3-V LVTTL : : 7 : N +GND* : AE17 : : : : 7 : +GND* : AE18 : : : : 7 : +GND* : AE19 : : : : 7 : +GND* : AE20 : : : : 7 : +GND* : AE21 : : : : 7 : +GND* : AE22 : : : : 7 : +GND* : AE23 : : : : 7 : +GND* : AE24 : : : : 7 : +GND* : AE25 : : : : 7 : +GND : AE26 : gnd : : : : +GND : AF2 : gnd : : : : +GND* : AF3 : : : : 8 : +VCCIO8 : AF4 : power : : 3.3V : 8 : +GND* : AF5 : : : : 8 : +GND* : AF6 : : : : 8 : +GND* : AF7 : : : : 8 : +GND* : AF8 : : : : 8 : +GND* : AF9 : : : : 8 : +GND* : AF10 : : : : 8 : +VCCIO8 : AF11 : power : : 3.3V : 8 : +GND* : AF12 : : : : 8 : +GND : AF13 : gnd : : : : +GND : AF14 : gnd : : : : +GND+ : AF15 : : : : 7 : +VCCIO7 : AF16 : power : : 3.3V : 7 : +GND* : AF17 : : : : 7 : +GND* : AF18 : : : : 7 : +GND* : AF19 : : : : 7 : +GND* : AF20 : : : : 7 : +GND* : AF21 : : : : 7 : +GND* : AF22 : : : : 7 : +VCCIO7 : AF23 : power : : 3.3V : 7 : +GND* : AF24 : : : : 7 : +GND : AF25 : gnd : : : : +GND : B1 : gnd : : : : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +GND* : B7 : : : : 3 : +GND* : B8 : : : : 3 : +GND* : B9 : : : : 3 : +GND* : B10 : : : : 3 : +GND* : B11 : : : : 3 : +GND+ : B12 : : : : 3 : +GNDG_PLL5 : B13 : gnd : : : : +GNDA_PLL5 : B14 : gnd : : : : +GND+ : B15 : : : : 4 : +GND* : B16 : : : : 4 : +GND* : B17 : : : : 4 : +GND* : B18 : : : : 4 : +GND* : B19 : : : : 4 : +GND* : B20 : : : : 4 : +GND* : B21 : : : : 4 : +GND* : B22 : : : : 4 : +GND* : B23 : : : : 4 : +GND* : B24 : : : : 4 : +GND* : B25 : : : : 4 : +GND : B26 : gnd : : : : +GND* : C1 : : : : 2 : +GND* : C2 : : : : 3 : +GND* : C3 : : : : 3 : +GND* : C4 : : : : 3 : +GND* : C5 : : : : 3 : +GND* : C6 : : : : 3 : +GND* : C7 : : : : 3 : +GND* : C8 : : : : 3 : +GND* : C9 : : : : 3 : +GND* : C10 : : : : 3 : +GND* : C11 : : : : 3 : +GND* : C12 : : : : 3 : +GND : C13 : gnd : : : : +VCCG_PLL5 : C14 : power : : 1.5V : : +GND* : C15 : : : : 4 : +GND* : C16 : : : : 4 : +GND* : C17 : : : : 4 : +GND* : C18 : : : : 4 : +GND* : C19 : : : : 4 : +GND* : C20 : : : : 4 : +GND* : C21 : : : : 4 : +GND* : C22 : : : : 4 : +GND* : C23 : : : : 4 : +GND* : C24 : : : : 4 : +GND* : C25 : : : : 5 : +GND* : C26 : : : : 5 : +VCCIO2 : D1 : power : : 3.3V : 2 : +GND* : D2 : : : : 2 : +GND* : D3 : : : : 3 : +GND* : D4 : : : : 3 : +GND* : D5 : : : : 3 : +GND* : D6 : : : : 3 : +GND : D7 : gnd : : : : +GND* : D8 : : : : 3 : +GND : D9 : gnd : : : : +GND* : D10 : : : : 3 : +GND* : D11 : : : : 3 : +GND+ : D12 : : : : 3 : +VCC_PLL5_OUTA : D13 : power : : 3.3V : 9 : +VCCA_PLL5 : D14 : power : : 1.5V : : +TRST : D15 : input : : : 4 : +GND* : D16 : : : : 4 : +d_hsync_counter[4] : D17 : output : 3.3-V LVTTL : : 4 : N +GND* : D18 : : : : 4 : +GND* : D19 : : : : 4 : +GND* : D20 : : : : 4 : +GND* : D21 : : : : 4 : +GND* : D22 : : : : 4 : +GND* : D23 : : : : 4 : +GND* : D24 : : : : 5 : +GND* : D25 : : : : 5 : +VCCIO5 : D26 : power : : 3.3V : 5 : +GND* : E1 : : : : 2 : +GND* : E2 : : : : 2 : +GND* : E3 : : : : 2 : +GND* : E4 : : : : 2 : +GND* : E5 : : : : 3 : +GND* : E6 : : : : 3 : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +GND* : E9 : : : : 3 : +GND* : E10 : : : : 3 : +GND* : E11 : : : : 3 : +d_vsync_counter[2] : E12 : output : 3.3-V LVTTL : : 9 : N +GND* : E13 : : : : 9 : +GND* : E14 : : : : 9 : +TMS : E15 : input : : : 4 : +GND* : E16 : : : : 4 : +GND* : E17 : : : : 4 : +GND* : E18 : : : : 4 : +GND* : E19 : : : : 4 : +GND* : E20 : : : : 4 : +GND* : E21 : : : : 4 : +r0_pin : E22 : output : 3.3-V LVTTL : : 4 : Y +g0_pin : E23 : output : 3.3-V LVTTL : : 5 : Y +b0_pin : E24 : output : 3.3-V LVTTL : : 5 : Y +GND* : E25 : : : : 5 : +GND* : E26 : : : : 5 : +hsync_pin : F1 : output : 3.3-V LVTTL : : 2 : Y +vsync_pin : F2 : output : 3.3-V LVTTL : : 2 : Y +d_vsync_state[2] : F3 : output : 3.3-V LVTTL : : 2 : Y +d_vsync_state[1] : F4 : output : 3.3-V LVTTL : : 2 : Y +d_vsync_state[0] : F5 : output : 3.3-V LVTTL : : 3 : Y +d_hsync_state[6] : F6 : output : 3.3-V LVTTL : : 3 : Y +GND* : F7 : : : : 3 : +GND : F8 : gnd : : : : +d_hsync_state[5] : F9 : output : 3.3-V LVTTL : : 3 : Y +d_hsync_state[4] : F10 : output : 3.3-V LVTTL : : 3 : Y +GND : F11 : gnd : : : : +GND* : F12 : : : : 9 : +GND* : F13 : : : : 9 : +d_vsync_counter[1] : F14 : output : 3.3-V LVTTL : : 9 : N +GND* : F15 : : : : 4 : +~DATA0~ / RESERVED_INPUT : F16 : input : 3.3-V LVTTL : : 4 : N +d_hsync_state[2] : F17 : output : 3.3-V LVTTL : : 4 : Y +GND : F18 : gnd : : : : +d_hsync_state[1] : F19 : output : 3.3-V LVTTL : : 4 : Y +GND* : F20 : : : : 4 : +d_set_line_counter : F21 : output : 3.3-V LVTTL : : 4 : Y +GND : F22 : gnd : : : : +GND* : F23 : : : : 5 : +d_set_vsync_counter : F24 : output : 3.3-V LVTTL : : 5 : Y +d_hsync_counter[5] : F25 : output : 3.3-V LVTTL : : 5 : N +d_set_hsync_counter : F26 : output : 3.3-V LVTTL : : 5 : Y +GND* : G1 : : : : 2 : +d_vsync_counter[9] : G2 : output : 3.3-V LVTTL : : 2 : Y +GND* : G3 : : : : 2 : +d_vsync_counter[8] : G4 : output : 3.3-V LVTTL : : 2 : Y +GND* : G5 : : : : 2 : +d_vsync_counter[7] : G6 : output : 3.3-V LVTTL : : 2 : Y +GND* : G7 : : : : 3 : +GND : G8 : gnd : : : : +d_vsync_counter[0] : G9 : output : 3.3-V LVTTL : : 3 : Y +GND* : G10 : : : : 3 : +GND* : G11 : : : : 3 : +DCLK : G12 : : : : 3 : +TEMPDIODEn : G13 : : : : : +TDO : G14 : output : : : 4 : +TCK : G15 : input : : : 4 : +GND : G16 : gnd : : : : +d_hsync_counter[2] : G17 : output : 3.3-V LVTTL : : 4 : N +d_hsync_counter[9] : G18 : output : 3.3-V LVTTL : : 4 : Y +GND* : G19 : : : : 4 : +GND* : G20 : : : : 4 : +GND* : G21 : : : : 5 : +d_hsync_counter[8] : G22 : output : 3.3-V LVTTL : : 5 : Y +GND* : G23 : : : : 5 : +GND* : G24 : : : : 5 : +d_hsync_counter[7] : G25 : output : 3.3-V LVTTL : : 5 : Y +GND* : G26 : : : : 5 : +GND* : H1 : : : : 2 : +GND* : H2 : : : : 2 : +GND* : H3 : : : : 2 : +d_hsync_counter[0] : H4 : output : 3.3-V LVTTL : : 2 : Y +GND* : H5 : : : : 2 : +GND* : H6 : : : : 2 : +GND* : H7 : : : : 2 : +GND : H8 : gnd : : : : +GND : H9 : gnd : : : : +GND* : H10 : : : : 3 : +CONF_DONE : H11 : : : : 3 : +nCONFIG : H12 : : : : 3 : +nSTATUS : H13 : : : : 3 : +TEMPDIODEp : H14 : : : : : +TDI : H15 : input : : : 4 : +GND* : H16 : : : : 4 : +GND : H17 : gnd : : : : +d_v_enable : H18 : output : 3.3-V LVTTL : : 4 : Y +GND* : H19 : : : : 5 : +GND* : H20 : : : : 5 : +GND* : H21 : : : : 5 : +GND* : H22 : : : : 5 : +GND* : H23 : : : : 5 : +GND* : H24 : : : : 5 : +GND* : H25 : : : : 5 : +GND* : H26 : : : : 5 : +GND* : J1 : : : : 2 : +GND* : J2 : : : : 2 : +GND* : J3 : : : : 2 : +GND* : J4 : : : : 2 : +GND* : J5 : : : : 2 : +GND* : J6 : : : : 2 : +GND* : J7 : : : : 2 : +GND* : J8 : : : : 2 : +GND : J9 : gnd : : : : +GND : J10 : gnd : : : : +VCCIO3 : J11 : power : : 3.3V : 3 : +VCCIO3 : J12 : power : : 3.3V : 3 : +GND : J13 : gnd : : : : +GND : J14 : gnd : : : : +VCCIO4 : J15 : power : : 3.3V : 4 : +VCCIO4 : J16 : power : : 3.3V : 4 : +GND : J17 : gnd : : : : +GND : J18 : gnd : : : : +GND* : J19 : : : : 5 : +GND* : J20 : : : : 5 : +d_h_enable : J21 : output : 3.3-V LVTTL : : 5 : Y +d_line_counter[2] : J22 : output : 3.3-V LVTTL : : 5 : Y +GND* : J23 : : : : 5 : +GND* : J24 : : : : 5 : +GND* : J25 : : : : 5 : +GND* : J26 : : : : 5 : +GND* : K1 : : : : 2 : +GND* : K2 : : : : 2 : +d_state_clk : K3 : output : 3.3-V LVTTL : : 2 : Y +d_line_counter[1] : K4 : output : 3.3-V LVTTL : : 2 : Y +d_column_counter[9] : K5 : output : 3.3-V LVTTL : : 2 : Y +d_line_counter[0] : K6 : output : 3.3-V LVTTL : : 2 : Y +d_vsync_counter[3] : K7 : output : 3.3-V LVTTL : : 2 : N +GND* : K8 : : : : 2 : +GND* : K9 : : : : 2 : +GND : K10 : gnd : : : : +VCCINT : K11 : power : : 1.5V : : +GND : K12 : gnd : : : : +VCCINT : K13 : power : : 1.5V : : +GND : K14 : gnd : : : : +VCCINT : K15 : power : : 1.5V : : +GND : K16 : gnd : : : : +VCCINT : K17 : power : : 1.5V : : +GND : K18 : gnd : : : : +d_column_counter[8] : K19 : output : 3.3-V LVTTL : : 5 : Y +d_b : K20 : output : 3.3-V LVTTL : : 5 : Y +d_vsync_counter[6] : K21 : output : 3.3-V LVTTL : : 5 : N +GND* : K22 : : : : 5 : +d_column_counter[7] : K23 : output : 3.3-V LVTTL : : 5 : Y +d_g : K24 : output : 3.3-V LVTTL : : 5 : Y +GND* : K25 : : : : 5 : +GND* : K26 : : : : 5 : +VCCIO2 : L1 : power : : 3.3V : 2 : +d_column_counter[6] : L2 : output : 3.3-V LVTTL : : 2 : Y +d_r : L3 : output : 3.3-V LVTTL : : 2 : Y +d_column_counter[5] : L4 : output : 3.3-V LVTTL : : 2 : Y +d_vsync : L5 : output : 3.3-V LVTTL : : 2 : Y +d_column_counter[4] : L6 : output : 3.3-V LVTTL : : 2 : Y +d_hsync : L7 : output : 3.3-V LVTTL : : 2 : Y +GND : L8 : gnd : : : : +VCCIO2 : L9 : power : : 3.3V : 2 : +VCCINT : L10 : power : : 1.5V : : +GND : L11 : gnd : : : : +VCCINT : L12 : power : : 1.5V : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.5V : : +GND : L15 : gnd : : : : +VCCINT : L16 : power : : 1.5V : : +GND : L17 : gnd : : : : +VCCIO5 : L18 : power : : 3.3V : 5 : +GND : L19 : gnd : : : : +d_column_counter[3] : L20 : output : 3.3-V LVTTL : : 5 : Y +d_column_counter[2] : L21 : output : 3.3-V LVTTL : : 5 : Y +d_column_counter[1] : L22 : output : 3.3-V LVTTL : : 5 : Y +d_column_counter[0] : L23 : output : 3.3-V LVTTL : : 5 : Y +d_line_counter[7] : L24 : output : 3.3-V LVTTL : : 5 : Y +d_line_counter[8] : L25 : output : 3.3-V LVTTL : : 5 : Y +VCCIO5 : L26 : power : : 3.3V : 5 : +GND+ : M1 : : : : 2 : +VCCG_PLL1 : M2 : power : : 1.5V : : +VCCA_PLL1 : M3 : power : : 1.5V : : +d_vsync_state[6] : M4 : output : 3.3-V LVTTL : : 2 : Y +d_line_counter[6] : M5 : output : 3.3-V LVTTL : : 2 : Y +d_line_counter[5] : M6 : output : 3.3-V LVTTL : : 2 : Y +d_vsync_state[5] : M7 : output : 3.3-V LVTTL : : 2 : Y +d_line_counter[4] : M8 : output : 3.3-V LVTTL : : 2 : Y +d_line_counter[3] : M9 : output : 3.3-V LVTTL : : 2 : Y +GND : M10 : gnd : : : : +VCCINT : M11 : power : : 1.5V : : +GND : M12 : gnd : : : : +VCCINT : M13 : power : : 1.5V : : +GND : M14 : gnd : : : : +VCCINT : M15 : power : : 1.5V : : +GND : M16 : gnd : : : : +VCCINT : M17 : power : : 1.5V : : +d_vsync_state[4] : M18 : output : 3.3-V LVTTL : : 5 : Y +d_vsync_state[3] : M19 : output : 3.3-V LVTTL : : 5 : Y +GND* : M20 : : : : 5 : +GND* : M21 : : : : 5 : +GND* : M22 : : : : 5 : +GND* : M23 : : : : 5 : +GND+ : M24 : : : : 5 : +GND+ : M25 : : : : 5 : +GND+ : M26 : : : : 5 : +GND : N1 : gnd : : : : +GND+ : N2 : : : : 2 : +board_clk : N3 : input : 3.3-V LVTTL : : 2 : Y +GNDG_PLL1 : N4 : gnd : : : : +GNDA_PLL1 : N5 : gnd : : : : +GND* : N6 : : : : 2 : +seven_seg_pin[8] : N7 : output : 3.3-V LVTTL : : 2 : Y +seven_seg_pin[9] : N8 : output : 3.3-V LVTTL : : 2 : Y +GND : N9 : gnd : : : : +VCCINT : N10 : power : : 1.5V : : +GND : N11 : gnd : : : : +VCCINT : N12 : power : : 1.5V : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.5V : : +GND : N15 : gnd : : : : +VCCINT : N16 : power : : 1.5V : : +GND : N17 : gnd : : : : +GND : N18 : gnd : : : : +GND* : N19 : : : : 6 : +GND* : N20 : : : : 5 : +GND* : N21 : : : : 5 : +GNDG_PLL4 : N22 : gnd : : : : +GNDA_PLL4 : N23 : gnd : : : : +VCCG_PLL4 : N24 : power : : 1.5V : : +VCCA_PLL4 : N25 : power : : 1.5V : : +GND : N26 : gnd : : : : +GND : P1 : gnd : : : : +GNDG_PLL2 : P2 : gnd : : : : +GNDA_PLL2 : P3 : gnd : : : : +VCCG_PLL2 : P4 : power : : 1.5V : : +VCCA_PLL2 : P5 : power : : 1.5V : : +GND* : P6 : : : : 1 : +GND* : P7 : : : : 1 : +GND* : P8 : : : : 2 : +GND : P9 : gnd : : : : +GND : P10 : gnd : : : : +VCCINT : P11 : power : : 1.5V : : +GND : P12 : gnd : : : : +VCCINT : P13 : power : : 1.5V : : +GND : P14 : gnd : : : : +VCCINT : P15 : power : : 1.5V : : +GND : P16 : gnd : : : : +VCCINT : P17 : power : : 1.5V : : +GND : P18 : gnd : : : : +GND* : P19 : : : : 6 : +GND* : P20 : : : : 6 : +GND* : P21 : : : : 6 : +VCCA_PLL3 : P22 : power : : 1.5V : : +VCCG_PLL3 : P23 : power : : 1.5V : : +GND+ : P24 : : : : 6 : +GND+ : P25 : : : : 6 : +GND : P26 : gnd : : : : +GND+ : R1 : : : : 1 : +GND+ : R2 : : : : 1 : +GND+ : R3 : : : : 1 : +seven_seg_pin[10] : R4 : output : 3.3-V LVTTL : : 1 : Y +GND* : R5 : : : : 1 : +seven_seg_pin[11] : R6 : output : 3.3-V LVTTL : : 1 : Y +GND* : R7 : : : : 1 : +seven_seg_pin[0] : R8 : output : 3.3-V LVTTL : : 1 : Y +seven_seg_pin[1] : R9 : output : 3.3-V LVTTL : : 1 : Y +VCCINT : R10 : power : : 1.5V : : +GND : R11 : gnd : : : : +VCCINT : R12 : power : : 1.5V : : +GND : R13 : gnd : : : : +VCCINT : R14 : power : : 1.5V : : +GND : R15 : gnd : : : : +VCCINT : R16 : power : : 1.5V : : +GND : R17 : gnd : : : : +GND : R18 : gnd : : : : +seven_seg_pin[2] : R19 : output : 3.3-V LVTTL : : 6 : Y +seven_seg_pin[3] : R20 : output : 3.3-V LVTTL : : 6 : Y +seven_seg_pin[4] : R21 : output : 3.3-V LVTTL : : 6 : Y +seven_seg_pin[5] : R22 : output : 3.3-V LVTTL : : 6 : Y +seven_seg_pin[6] : R23 : output : 3.3-V LVTTL : : 6 : Y +GNDA_PLL3 : R24 : gnd : : : : +GNDG_PLL3 : R25 : gnd : : : : +GND+ : R26 : : : : 6 : +VCCIO1 : T1 : power : : 3.3V : 1 : +seven_seg_pin[13] : T2 : output : 3.3-V LVTTL : : 1 : Y +GND* : T3 : : : : 1 : +r1_pin : T4 : output : 3.3-V LVTTL : : 1 : Y +g1_pin : T5 : output : 3.3-V LVTTL : : 1 : Y +b1_pin : T6 : output : 3.3-V LVTTL : : 1 : Y +r2_pin : T7 : output : 3.3-V LVTTL : : 1 : Y +GND : T8 : gnd : : : : +VCCIO1 : T9 : power : : 3.3V : 1 : +GND : T10 : gnd : : : : +VCCINT : T11 : power : : 1.5V : : +GND : T12 : gnd : : : : +VCCINT : T13 : power : : 1.5V : : +GND : T14 : gnd : : : : +VCCINT : T15 : power : : 1.5V : : +GND : T16 : gnd : : : : +VCCINT : T17 : power : : 1.5V : : +VCCIO6 : T18 : power : : 3.3V : 6 : +GND* : T19 : : : : 6 : +GND* : T20 : : : : 6 : +GND* : T21 : : : : 6 : +GND* : T22 : : : : 6 : +GND* : T23 : : : : 6 : +g2_pin : T24 : output : 3.3-V LVTTL : : 6 : Y +GND* : T25 : : : : 6 : +VCCIO6 : T26 : power : : 3.3V : 6 : +GND* : U1 : : : : 1 : +GND* : U2 : : : : 1 : +GND* : U3 : : : : 1 : +GND* : U4 : : : : 1 : +GND* : U5 : : : : 1 : +GND* : U6 : : : : 1 : +GND* : U7 : : : : 1 : +GND* : U8 : : : : 1 : +GND* : U9 : : : : 1 : +VCCINT : U10 : power : : 1.5V : : +GND : U11 : gnd : : : : +VCCINT : U12 : power : : 1.5V : : +GND : U13 : gnd : : : : +VCCINT : U14 : power : : 1.5V : : +GND : U15 : gnd : : : : +VCCINT : U16 : power : : 1.5V : : +GND : U17 : gnd : : : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +GND* : U21 : : : : 6 : +GND* : U22 : : : : 6 : +GND* : U23 : : : : 6 : +GND* : U24 : : : : 6 : +GND* : U25 : : : : 6 : +GND* : U26 : : : : 6 : +GND* : V1 : : : : 1 : +GND* : V2 : : : : 1 : +GND* : V3 : : : : 1 : +GND* : V4 : : : : 1 : +GND* : V5 : : : : 1 : +GND* : V6 : : : : 1 : +GND : V7 : gnd : : : : +GND* : V8 : : : : 1 : +GND : V9 : gnd : : : : +GND : V10 : gnd : : : : +VCCIO8 : V11 : power : : 3.3V : 8 : +VCCIO8 : V12 : power : : 3.3V : 8 : +GND : V13 : gnd : : : : +GND : V14 : gnd : : : : +VCCIO7 : V15 : power : : 3.3V : 7 : +VCCIO7 : V16 : power : : 3.3V : 7 : +GND : V17 : gnd : : : : +GND : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND : V20 : gnd : : : : +GND* : V21 : : : : 6 : +GND* : V22 : : : : 6 : +GND* : V23 : : : : 6 : +GND* : V24 : : : : 6 : +GND* : V25 : : : : 6 : +GND* : V26 : : : : 6 : +GND* : W1 : : : : 1 : +GND* : W2 : : : : 1 : +GND* : W3 : : : : 1 : +GND* : W4 : : : : 1 : +GND* : W5 : : : : 1 : +GND* : W6 : : : : 1 : +GND* : W7 : : : : 1 : +GND* : W8 : : : : 1 : +GND* : W9 : : : : 8 : +GND* : W10 : : : : 8 : +GND : W11 : gnd : : : : +PLL_ENA : W12 : : : : 8 : +MSEL2 : W13 : : : : 8 : +nCEO : W14 : : : : 7 : +GND* : W15 : : : : 7 : +PORSEL : W16 : : : : 7 : +GND* : W17 : : : : 7 : +GND* : W18 : : : : 7 : +GND* : W19 : : : : 6 : +GND* : W20 : : : : 6 : +GND* : W21 : : : : 6 : +GND* : W22 : : : : 6 : +GND* : W23 : : : : 6 : +GND* : W24 : : : : 6 : +GND* : W25 : : : : 6 : +GND* : W26 : : : : 6 : +GND* : Y1 : : : : 1 : +d_hsync_state[3] : Y2 : output : 3.3-V LVTTL : : 1 : Y +GND* : Y3 : : : : 1 : +GND* : Y4 : : : : 1 : +d_hsync_state[0] : Y5 : output : 3.3-V LVTTL : : 1 : Y +GND* : Y6 : : : : 1 : +GND : Y7 : gnd : : : : +GND* : Y8 : : : : 8 : +GND* : Y9 : : : : 8 : +GND* : Y10 : : : : 8 : +seven_seg_pin[7] : Y11 : output : 3.3-V LVTTL : : 8 : Y +MSEL0 : Y12 : : : : 8 : +MSEL1 : Y13 : : : : 8 : +nCE : Y14 : : : : 7 : +VCCSEL : Y15 : : : : 7 : +GND* : Y16 : : : : 7 : +GND* : Y17 : : : : 7 : +GND* : Y18 : : : : 7 : +GND* : Y19 : : : : 7 : +GND* : Y20 : : : : 7 : +GND : Y21 : gnd : : : : +GND* : Y22 : : : : 6 : +d_set_column_counter : Y23 : output : 3.3-V LVTTL : : 6 : Y +GND* : Y24 : : : : 6 : +GND* : Y25 : : : : 6 : +GND* : Y26 : : : : 6 : diff --git a/bsp3/Designflow/ppr/download/vga_pll.pof b/bsp3/Designflow/ppr/download/vga_pll.pof new file mode 100644 index 0000000000000000000000000000000000000000..a23d9e16cc35a4bc750a6a3ae205994f7425d32c GIT binary patch literal 1048717 zcmeFa4SW;FnLoaEl;CS=@XE3=#MqWCz~uj!3S5a&%bNs`V9}PU6X(7tXuNk4?nQFHNUuIPW~-(X3v>Bd(JJl+?v01 zVSeqyt5=HwnN&=&rlGo=xsLfOpu22M`vdK(SGF=NGoDEY2mb1W#IMqeB0v$K2v7tl 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partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 132 02/25/2009 SJ Full Version +# Date created = 17:11:00 October 29, 2009 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "17:11:00 October 29, 2009" + +# Revisions + +PROJECT_REVISION = "vga_pll" diff --git a/bsp3/Designflow/ppr/download/vga_pll.qsf b/bsp3/Designflow/ppr/download/vga_pll.qsf new file mode 100644 index 0000000..87bda1c --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.qsf @@ -0,0 +1,158 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 132 02/25/2009 SJ Full Version +# Date created = 17:11:00 October 29, 2009 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# vga_pll_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY Stratix +set_global_assignment -name DEVICE EP1S25F672C6 +set_global_assignment -name TOP_LEVEL_ENTITY vga_pll +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" +set_global_assignment -name LAST_QUARTUS_VERSION 6.0 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" +set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf +set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name BSF_FILE ../../src/vpll.bsf +set_global_assignment -name VHDL_FILE ../../src/vpll.vhd +set_location_assignment PIN_E24 -to b0_pin +set_location_assignment PIN_T6 -to b1_pin +set_location_assignment PIN_N3 -to board_clk +set_location_assignment PIN_E23 -to g0_pin +set_location_assignment PIN_T5 -to g1_pin +set_location_assignment PIN_T24 -to g2_pin +set_location_assignment PIN_F1 -to hsync_pin +set_location_assignment PIN_E22 -to r0_pin +set_location_assignment PIN_T4 -to r1_pin +set_location_assignment PIN_T7 -to r2_pin +set_location_assignment PIN_A5 -to reset +set_location_assignment PIN_F2 -to vsync_pin +set_location_assignment PIN_Y5 -to d_hsync_state[0] +set_location_assignment PIN_F19 -to d_hsync_state[1] +set_location_assignment PIN_F17 -to d_hsync_state[2] +set_location_assignment PIN_Y2 -to d_hsync_state[3] +set_location_assignment PIN_F10 -to d_hsync_state[4] +set_location_assignment PIN_F9 -to d_hsync_state[5] +set_location_assignment PIN_F6 -to d_hsync_state[6] +set_location_assignment PIN_H4 -to d_hsync_counter[0] +set_location_assignment PIN_G25 -to d_hsync_counter[7] +set_location_assignment PIN_G22 -to d_hsync_counter[8] +set_location_assignment PIN_G18 -to d_hsync_counter[9] +set_location_assignment PIN_F5 -to d_vsync_state[0] +set_location_assignment PIN_F4 -to d_vsync_state[1] +set_location_assignment PIN_F3 -to d_vsync_state[2] +set_location_assignment PIN_M19 -to d_vsync_state[3] +set_location_assignment PIN_M18 -to d_vsync_state[4] +set_location_assignment PIN_M7 -to d_vsync_state[5] +set_location_assignment PIN_M4 -to d_vsync_state[6] +set_location_assignment PIN_G9 -to d_vsync_counter[0] +set_location_assignment PIN_G6 -to d_vsync_counter[7] +set_location_assignment PIN_G4 -to d_vsync_counter[8] +set_location_assignment PIN_G2 -to d_vsync_counter[9] +set_location_assignment PIN_K6 -to d_line_counter[0] +set_location_assignment PIN_K4 -to d_line_counter[1] +set_location_assignment PIN_J22 -to d_line_counter[2] +set_location_assignment PIN_M9 -to d_line_counter[3] +set_location_assignment PIN_M8 -to d_line_counter[4] +set_location_assignment PIN_M6 -to d_line_counter[5] +set_location_assignment PIN_M5 -to d_line_counter[6] +set_location_assignment PIN_L24 -to d_line_counter[7] +set_location_assignment PIN_L25 -to d_line_counter[8] +set_location_assignment PIN_L23 -to d_column_counter[0] +set_location_assignment PIN_L22 -to d_column_counter[1] +set_location_assignment PIN_L21 -to d_column_counter[2] +set_location_assignment PIN_L20 -to d_column_counter[3] +set_location_assignment PIN_L6 -to d_column_counter[4] +set_location_assignment PIN_L4 -to d_column_counter[5] +set_location_assignment PIN_L2 -to d_column_counter[6] +set_location_assignment PIN_K23 -to d_column_counter[7] +set_location_assignment PIN_K19 -to d_column_counter[8] +set_location_assignment PIN_K5 -to d_column_counter[9] +set_location_assignment PIN_L7 -to d_hsync +set_location_assignment PIN_L5 -to d_vsync +set_location_assignment PIN_F26 -to d_set_hsync_counter +set_location_assignment PIN_F24 -to d_set_vsync_counter +set_location_assignment PIN_F21 -to d_set_line_counter +set_location_assignment PIN_Y23 -to d_set_column_counter +set_location_assignment PIN_L3 -to d_r +set_location_assignment PIN_K24 -to d_g +set_location_assignment PIN_K20 -to d_b +set_location_assignment PIN_H18 -to d_v_enable +set_location_assignment PIN_J21 -to d_h_enable +set_location_assignment PIN_R8 -to seven_seg_pin[0] +set_location_assignment PIN_R9 -to seven_seg_pin[1] +set_location_assignment PIN_R19 -to seven_seg_pin[2] +set_location_assignment PIN_R20 -to seven_seg_pin[3] +set_location_assignment PIN_R21 -to seven_seg_pin[4] +set_location_assignment PIN_R22 -to seven_seg_pin[5] +set_location_assignment PIN_R23 -to seven_seg_pin[6] +set_location_assignment PIN_Y11 -to seven_seg_pin[7] +set_location_assignment PIN_N7 -to seven_seg_pin[8] +set_location_assignment PIN_N8 -to seven_seg_pin[9] +set_location_assignment PIN_R4 -to seven_seg_pin[10] +set_location_assignment PIN_R6 -to seven_seg_pin[11] +set_location_assignment PIN_AA11 -to seven_seg_pin[12] +set_location_assignment PIN_T2 -to seven_seg_pin[13] +set_location_assignment PIN_K3 -to d_state_clk +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6] +set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state +set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin \ No newline at end of file diff --git a/bsp3/Designflow/ppr/download/vga_pll.qws b/bsp3/Designflow/ppr/download/vga_pll.qws new file mode 100644 index 0000000..270194c --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.qws @@ -0,0 +1,12 @@ + + +[ProjectWorkspace] +ptn_Child1=Frames + +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames + +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 \ No newline at end of file diff --git a/bsp3/Designflow/ppr/download/vga_pll.sof b/bsp3/Designflow/ppr/download/vga_pll.sof new file mode 100644 index 0000000000000000000000000000000000000000..0800d4af1bc01c17e60a7c801dea6064a0a6979d GIT binary patch literal 966463 zcmeFaU94@%aUQnLo;_D*NGjYjBp?G34x|JSl03+Y9~{5|js;;LAVI#nb=t7~grWkA1#^oYTLv>PHBF z{HuTE7k}xiexQ>Y(#_Sr9e?)yLg1ONKx-uQv) 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+--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Parallel Compilation + 6. Clock Setup: 'vpll:inst1|altpll:altpll_component|_clk0' + 7. Clock Hold: 'vpll:inst1|altpll:altpll_component|_clk0' + 8. tsu + 9. tco + 10. tpd + 11. th + 12. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++---------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------+-----------------------------------------------------+------------------------------------------+------------------------------------------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++---------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------+-----------------------------------------------------+------------------------------------------+------------------------------------------+--------------+ +; Worst-case tsu ; N/A ; None ; 11.030 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; -- ; board_clk ; 0 ; +; Worst-case tco ; N/A ; None ; 9.803 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[7] ; board_clk ; -- ; 0 ; +; Worst-case tpd ; N/A ; None ; 15.201 ns ; reset ; seven_seg_pin[7] ; -- ; -- ; 0 ; +; Worst-case th ; N/A ; None ; -5.484 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|v_sync ; -- ; board_clk ; 0 ; +; Clock Setup: 'vpll:inst1|altpll:altpll_component|_clk0' ; 29.381 ns ; 27.19 MHz ( period = 36.777 ns ) ; 135.21 MHz ( period = 7.396 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|b ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0 ; +; Clock Hold: 'vpll:inst1|altpll:altpll_component|_clk0' ; 0.737 ns ; 27.19 MHz ( period = 36.777 ns ) ; N/A ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; ++---------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------+-----------------------------------------------------+------------------------------------------+------------------------------------------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Device Name ; EP1S25F672C6 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; Off ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++------------------------------------------+--------------------+------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++------------------------------------------+--------------------+------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+ +; vpll:inst1|altpll:altpll_component|_clk0 ; ; PLL output ; 27.19 MHz ; 0.000 ns ; 0.000 ns ; board_clk ; 31 ; 38 ; -1.030 ns ; ; +; board_clk ; ; User Pin ; 33.33 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++------------------------------------------+--------------------+------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; 0.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'vpll:inst1|altpll:altpll_component|_clk0' ; ++-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 29.381 ns ; 135.21 MHz ( period = 7.396 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|b ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.604 ns ; 7.223 ns ; +; 29.583 ns ; 139.00 MHz ( period = 7.194 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.586 ns ; 7.003 ns ; +; 29.727 ns ; 141.84 MHz ( period = 7.050 ns ) ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; vga:inst|vga_control:vga_control_unit|b ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.585 ns ; 6.858 ns ; +; 29.816 ns ; 143.66 MHz ( period = 6.961 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.586 ns ; 6.770 ns ; +; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.724 ns ; +; 29.878 ns ; 144.95 MHz ( period = 6.899 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.586 ns ; 6.708 ns ; +; 29.887 ns ; 145.14 MHz ( period = 6.890 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.586 ns ; 6.699 ns ; +; 29.952 ns ; 146.52 MHz ( period = 6.825 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.597 ns ; 6.645 ns ; +; 29.955 ns ; 146.58 MHz ( period = 6.822 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.622 ns ; +; 29.998 ns ; 147.51 MHz ( period = 6.779 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.586 ns ; 6.588 ns ; +; 30.056 ns ; 148.79 MHz ( period = 6.721 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.521 ns ; +; 30.072 ns ; 149.14 MHz ( period = 6.705 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.597 ns ; 6.525 ns ; +; 30.078 ns ; 149.28 MHz ( period = 6.699 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.597 ns ; 6.519 ns ; +; 30.183 ns ; 151.65 MHz ( period = 6.594 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.604 ns ; 6.421 ns ; +; 30.225 ns ; 152.63 MHz ( period = 6.552 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.352 ns ; +; 30.262 ns ; 153.49 MHz ( period = 6.515 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.315 ns ; +; 30.309 ns ; 154.61 MHz ( period = 6.468 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.597 ns ; 6.288 ns ; +; 30.339 ns ; 155.33 MHz ( period = 6.438 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.238 ns ; +; 30.342 ns ; 155.40 MHz ( period = 6.435 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.235 ns ; +; 30.342 ns ; 155.40 MHz ( period = 6.435 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.235 ns ; +; 30.342 ns ; 155.40 MHz ( period = 6.435 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.235 ns ; +; 30.444 ns ; 157.90 MHz ( period = 6.333 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.133 ns ; +; 30.444 ns ; 157.90 MHz ( period = 6.333 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.133 ns ; +; 30.444 ns ; 157.90 MHz ( period = 6.333 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.133 ns ; +; 30.491 ns ; 159.08 MHz ( period = 6.286 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.086 ns ; +; 30.529 ns ; 160.05 MHz ( period = 6.248 ns ) ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.585 ns ; 6.056 ns ; +; 30.545 ns ; 160.46 MHz ( period = 6.232 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.032 ns ; +; 30.545 ns ; 160.46 MHz ( period = 6.232 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.032 ns ; +; 30.545 ns ; 160.46 MHz ( period = 6.232 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 6.032 ns ; +; 30.614 ns ; 162.26 MHz ( period = 6.163 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.963 ns ; +; 30.623 ns ; 162.50 MHz ( period = 6.154 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.954 ns ; +; 30.714 ns ; 164.93 MHz ( period = 6.063 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.863 ns ; +; 30.714 ns ; 164.93 MHz ( period = 6.063 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.863 ns ; +; 30.714 ns ; 164.93 MHz ( period = 6.063 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.863 ns ; +; 30.725 ns ; 165.23 MHz ( period = 6.052 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.852 ns ; +; 30.751 ns ; 165.95 MHz ( period = 6.026 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.826 ns ; +; 30.751 ns ; 165.95 MHz ( period = 6.026 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.826 ns ; +; 30.751 ns ; 165.95 MHz ( period = 6.026 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.826 ns ; +; 30.783 ns ; 166.83 MHz ( period = 5.994 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.794 ns ; +; 30.813 ns ; 167.67 MHz ( period = 5.964 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.538 ns ; 5.725 ns ; +; 30.826 ns ; 168.04 MHz ( period = 5.951 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.751 ns ; +; 30.828 ns ; 168.10 MHz ( period = 5.949 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.749 ns ; +; 30.828 ns ; 168.10 MHz ( period = 5.949 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.749 ns ; +; 30.828 ns ; 168.10 MHz ( period = 5.949 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.749 ns ; +; 30.871 ns ; 169.32 MHz ( period = 5.906 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.724 ns ; +; 30.871 ns ; 169.32 MHz ( period = 5.906 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.724 ns ; +; 30.878 ns ; 169.52 MHz ( period = 5.899 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|g ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.713 ns ; +; 30.889 ns ; 169.84 MHz ( period = 5.888 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.699 ns ; +; 30.891 ns ; 169.89 MHz ( period = 5.886 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.697 ns ; +; 30.892 ns ; 169.92 MHz ( period = 5.885 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.696 ns ; +; 30.893 ns ; 169.95 MHz ( period = 5.884 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.695 ns ; +; 30.893 ns ; 169.95 MHz ( period = 5.884 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.695 ns ; +; 30.896 ns ; 170.04 MHz ( period = 5.881 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.692 ns ; +; 30.898 ns ; 170.10 MHz ( period = 5.879 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.690 ns ; +; 30.901 ns ; 170.18 MHz ( period = 5.876 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.687 ns ; +; 30.903 ns ; 170.24 MHz ( period = 5.874 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.685 ns ; +; 30.904 ns ; 170.27 MHz ( period = 5.873 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.588 ns ; 5.684 ns ; +; 30.931 ns ; 171.06 MHz ( period = 5.846 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.525 ns ; 5.594 ns ; +; 30.931 ns ; 171.06 MHz ( period = 5.846 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.525 ns ; 5.594 ns ; +; 30.947 ns ; 171.53 MHz ( period = 5.830 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.525 ns ; 5.578 ns ; +; 30.947 ns ; 171.53 MHz ( period = 5.830 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.525 ns ; 5.578 ns ; +; 30.947 ns ; 171.53 MHz ( period = 5.830 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.525 ns ; 5.578 ns ; +; 30.947 ns ; 171.53 MHz ( period = 5.830 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.525 ns ; 5.578 ns ; +; 30.947 ns ; 171.53 MHz ( period = 5.830 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.525 ns ; 5.578 ns ; +; 30.947 ns ; 171.53 MHz ( period = 5.830 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.525 ns ; 5.578 ns ; +; 30.970 ns ; 172.21 MHz ( period = 5.807 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.625 ns ; +; 30.970 ns ; 172.21 MHz ( period = 5.807 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.625 ns ; +; 30.980 ns ; 172.50 MHz ( period = 5.797 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.597 ns ; +; 30.980 ns ; 172.50 MHz ( period = 5.797 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.597 ns ; +; 30.980 ns ; 172.50 MHz ( period = 5.797 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.597 ns ; +; 30.981 ns ; 172.53 MHz ( period = 5.796 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.614 ns ; +; 30.981 ns ; 172.53 MHz ( period = 5.796 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.614 ns ; +; 30.995 ns ; 172.95 MHz ( period = 5.782 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.582 ns ; +; 30.997 ns ; 173.01 MHz ( period = 5.780 ns ) ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; vga:inst|vga_control:vga_control_unit|b ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.538 ns ; 5.541 ns ; +; 31.013 ns ; 173.49 MHz ( period = 5.764 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.582 ns ; +; 31.013 ns ; 173.49 MHz ( period = 5.764 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.582 ns ; +; 31.032 ns ; 174.06 MHz ( period = 5.745 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.545 ns ; +; 31.064 ns ; 175.04 MHz ( period = 5.713 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.531 ns ; +; 31.064 ns ; 175.04 MHz ( period = 5.713 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.531 ns ; +; 31.075 ns ; 175.38 MHz ( period = 5.702 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.502 ns ; +; 31.103 ns ; 176.24 MHz ( period = 5.674 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.474 ns ; +; 31.103 ns ; 176.24 MHz ( period = 5.674 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.474 ns ; +; 31.103 ns ; 176.24 MHz ( period = 5.674 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.474 ns ; +; 31.109 ns ; 176.43 MHz ( period = 5.668 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.468 ns ; +; 31.145 ns ; 177.56 MHz ( period = 5.632 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.596 ns ; 5.451 ns ; +; 31.156 ns ; 177.90 MHz ( period = 5.621 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.439 ns ; +; 31.156 ns ; 177.90 MHz ( period = 5.621 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.439 ns ; +; 31.190 ns ; 178.99 MHz ( period = 5.587 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.405 ns ; +; 31.190 ns ; 178.99 MHz ( period = 5.587 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.405 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.194 ns ; 179.12 MHz ( period = 5.583 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.445 ns ; +; 31.224 ns ; 180.08 MHz ( period = 5.553 ns ) ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; vga:inst|vga_control:vga_control_unit|g ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.572 ns ; 5.348 ns ; +; 31.244 ns ; 180.73 MHz ( period = 5.533 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.643 ns ; 5.399 ns ; +; 31.244 ns ; 180.73 MHz ( period = 5.533 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.643 ns ; 5.399 ns ; +; 31.261 ns ; 181.29 MHz ( period = 5.516 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.316 ns ; +; 31.272 ns ; 181.65 MHz ( period = 5.505 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.305 ns ; +; 31.272 ns ; 181.65 MHz ( period = 5.505 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.305 ns ; +; 31.272 ns ; 181.65 MHz ( period = 5.505 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.305 ns ; +; 31.284 ns ; 182.05 MHz ( period = 5.493 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.596 ns ; 5.312 ns ; +; 31.318 ns ; 183.18 MHz ( period = 5.459 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.277 ns ; +; 31.318 ns ; 183.18 MHz ( period = 5.459 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.277 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.333 ns ; 183.69 MHz ( period = 5.444 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.306 ns ; +; 31.339 ns ; 183.89 MHz ( period = 5.438 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.525 ns ; 5.186 ns ; +; 31.339 ns ; 183.89 MHz ( period = 5.438 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.256 ns ; +; 31.339 ns ; 183.89 MHz ( period = 5.438 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.256 ns ; +; 31.366 ns ; 184.81 MHz ( period = 5.411 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.228 ns ; +; 31.366 ns ; 184.81 MHz ( period = 5.411 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.228 ns ; +; 31.366 ns ; 184.81 MHz ( period = 5.411 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.228 ns ; +; 31.383 ns ; 185.39 MHz ( period = 5.394 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.643 ns ; 5.260 ns ; +; 31.383 ns ; 185.39 MHz ( period = 5.394 ns ) ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.643 ns ; 5.260 ns ; +; 31.384 ns ; 185.43 MHz ( period = 5.393 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.193 ns ; +; 31.407 ns ; 186.22 MHz ( period = 5.370 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.188 ns ; +; 31.407 ns ; 186.22 MHz ( period = 5.370 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.595 ns ; 5.188 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.436 ns ; 187.23 MHz ( period = 5.341 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.639 ns ; 5.203 ns ; +; 31.465 ns ; 188.25 MHz ( period = 5.312 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.129 ns ; +; 31.465 ns ; 188.25 MHz ( period = 5.312 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.129 ns ; +; 31.465 ns ; 188.25 MHz ( period = 5.312 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.129 ns ; +; 31.476 ns ; 188.64 MHz ( period = 5.301 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.118 ns ; +; 31.476 ns ; 188.64 MHz ( period = 5.301 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.118 ns ; +; 31.476 ns ; 188.64 MHz ( period = 5.301 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.118 ns ; +; 31.508 ns ; 189.79 MHz ( period = 5.269 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.086 ns ; +; 31.508 ns ; 189.79 MHz ( period = 5.269 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.086 ns ; +; 31.508 ns ; 189.79 MHz ( period = 5.269 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.086 ns ; +; 31.553 ns ; 191.42 MHz ( period = 5.224 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.024 ns ; +; 31.559 ns ; 191.64 MHz ( period = 5.218 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.035 ns ; +; 31.559 ns ; 191.64 MHz ( period = 5.218 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.035 ns ; +; 31.559 ns ; 191.64 MHz ( period = 5.218 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.035 ns ; +; 31.563 ns ; 191.79 MHz ( period = 5.214 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 5.031 ns ; +; 31.564 ns ; 191.83 MHz ( period = 5.213 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.013 ns ; +; 31.564 ns ; 191.83 MHz ( period = 5.213 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.013 ns ; +; 31.564 ns ; 191.83 MHz ( period = 5.213 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.577 ns ; 5.013 ns ; +; 31.651 ns ; 195.08 MHz ( period = 5.126 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.943 ns ; +; 31.651 ns ; 195.08 MHz ( period = 5.126 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.943 ns ; +; 31.651 ns ; 195.08 MHz ( period = 5.126 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.943 ns ; +; 31.662 ns ; 195.50 MHz ( period = 5.115 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.932 ns ; +; 31.673 ns ; 195.92 MHz ( period = 5.104 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.921 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.684 ns ; 196.35 MHz ( period = 5.093 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.907 ns ; +; 31.685 ns ; 196.39 MHz ( period = 5.092 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.909 ns ; +; 31.685 ns ; 196.39 MHz ( period = 5.092 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.909 ns ; +; 31.685 ns ; 196.39 MHz ( period = 5.092 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.909 ns ; +; 31.705 ns ; 197.16 MHz ( period = 5.072 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.889 ns ; +; 31.739 ns ; 198.49 MHz ( period = 5.038 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.642 ns ; 4.903 ns ; +; 31.739 ns ; 198.49 MHz ( period = 5.038 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.642 ns ; 4.903 ns ; +; 31.739 ns ; 198.49 MHz ( period = 5.038 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.642 ns ; 4.903 ns ; +; 31.756 ns ; 199.16 MHz ( period = 5.021 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.838 ns ; +; 31.792 ns ; 200.60 MHz ( period = 4.985 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.637 ns ; 4.845 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.796 ns ; 200.76 MHz ( period = 4.981 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.795 ns ; +; 31.799 ns ; 200.88 MHz ( period = 4.978 ns ) ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.538 ns ; 4.739 ns ; +; 31.813 ns ; 201.45 MHz ( period = 4.964 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.781 ns ; +; 31.813 ns ; 201.45 MHz ( period = 4.964 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.781 ns ; +; 31.813 ns ; 201.45 MHz ( period = 4.964 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.594 ns ; 4.781 ns ; +; 31.827 ns ; 202.02 MHz ( period = 4.950 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.764 ns ; +; 31.827 ns ; 202.02 MHz ( period = 4.950 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.764 ns ; +; 31.827 ns ; 202.02 MHz ( period = 4.950 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.764 ns ; +; 31.827 ns ; 202.02 MHz ( period = 4.950 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.764 ns ; +; 31.827 ns ; 202.02 MHz ( period = 4.950 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 4.764 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'vpll:inst1|altpll:altpll_component|_clk0' ; ++-----------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------------------------------------+------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------------------------------------+------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.737 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.661 ns ; +; 0.743 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.667 ns ; +; 0.746 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.670 ns ; +; 0.747 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.671 ns ; +; 0.755 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.679 ns ; +; 0.767 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.691 ns ; +; 0.796 ns ; vga:inst|dly_counter[1] ; vga:inst|dly_counter[1] ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.720 ns ; +; 0.798 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.722 ns ; +; 0.798 ns ; vga:inst|dly_counter[1] ; vga:inst|dly_counter[0] ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.722 ns ; +; 0.891 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.815 ns ; +; 0.904 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.828 ns ; +; 0.935 ns ; vga:inst|dly_counter[0] ; vga:inst|dly_counter[0] ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.859 ns ; +; 0.938 ns ; vga:inst|dly_counter[0] ; vga:inst|dly_counter[1] ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.862 ns ; +; 0.940 ns ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.864 ns ; +; 0.971 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.895 ns ; +; 0.981 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.905 ns ; +; 0.984 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.908 ns ; +; 0.984 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.908 ns ; +; 0.985 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.909 ns ; +; 0.985 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.909 ns ; +; 0.987 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.911 ns ; +; 0.988 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.912 ns ; +; 0.990 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.914 ns ; +; 0.993 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.917 ns ; +; 1.095 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.019 ns ; +; 1.095 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.019 ns ; +; 1.096 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.020 ns ; +; 1.096 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.020 ns ; +; 1.103 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.027 ns ; +; 1.103 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.027 ns ; +; 1.104 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ; +; 1.104 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ; +; 1.104 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ; +; 1.104 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ; +; 1.128 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|b ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.052 ns ; +; 1.143 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.067 ns ; +; 1.155 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.079 ns ; +; 1.174 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.098 ns ; +; 1.181 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.105 ns ; +; 1.196 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.120 ns ; +; 1.282 ns ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.206 ns ; +; 1.350 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|g ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.274 ns ; +; 1.387 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.311 ns ; +; 1.407 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.331 ns ; +; 1.407 ns ; vga:inst|vga_driver:vga_driver_unit|h_sync ; vga:inst|vga_driver:vga_driver_unit|h_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.331 ns ; +; 1.410 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.334 ns ; +; 1.410 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.334 ns ; +; 1.411 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.335 ns ; +; 1.411 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.335 ns ; +; 1.411 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.335 ns ; +; 1.413 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.337 ns ; +; 1.414 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.338 ns ; +; 1.414 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.338 ns ; +; 1.421 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.345 ns ; +; 1.436 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.360 ns ; +; 1.437 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.361 ns ; +; 1.467 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.391 ns ; +; 1.468 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.062 ns ; 1.406 ns ; +; 1.470 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.394 ns ; +; 1.470 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.394 ns ; +; 1.471 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.395 ns ; +; 1.471 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.395 ns ; +; 1.473 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.397 ns ; +; 1.474 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.398 ns ; +; 1.526 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.450 ns ; +; 1.526 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.450 ns ; +; 1.527 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.451 ns ; +; 1.527 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.451 ns ; +; 1.527 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.451 ns ; +; 1.530 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.454 ns ; +; 1.530 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.454 ns ; +; 1.531 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.455 ns ; +; 1.531 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.455 ns ; +; 1.533 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.457 ns ; +; 1.534 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.458 ns ; +; 1.534 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.458 ns ; +; 1.534 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.458 ns ; +; 1.535 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.459 ns ; +; 1.535 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.459 ns ; +; 1.553 ns ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.477 ns ; +; 1.555 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.075 ns ; 1.480 ns ; +; 1.556 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.090 ns ; 1.466 ns ; +; 1.558 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.075 ns ; 1.483 ns ; +; 1.568 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.077 ns ; 1.491 ns ; +; 1.583 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.507 ns ; +; 1.586 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.510 ns ; +; 1.586 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.510 ns ; +; 1.589 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.513 ns ; +; 1.591 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.515 ns ; +; 1.591 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.515 ns ; +; 1.593 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.090 ns ; 1.503 ns ; +; 1.594 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.518 ns ; +; 1.594 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.518 ns ; +; 1.594 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.518 ns ; +; 1.609 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|g ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.533 ns ; +; 1.632 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.090 ns ; 1.542 ns ; +; 1.633 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.557 ns ; +; 1.634 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.558 ns ; +; 1.652 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.576 ns ; +; 1.653 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.577 ns ; +; 1.658 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.582 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ; +; 1.682 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.606 ns ; +; 1.688 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.612 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.690 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.614 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.694 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.618 ns ; +; 1.705 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.629 ns ; +; 1.718 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.642 ns ; +; 1.756 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.680 ns ; +; 1.756 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.680 ns ; +; 1.756 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.680 ns ; +; 1.756 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.680 ns ; +; 1.756 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.680 ns ; +; 1.760 ns ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.684 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.763 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.687 ns ; +; 1.777 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.090 ns ; 1.687 ns ; +; 1.780 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|g ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.704 ns ; +; 1.803 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.727 ns ; +; 1.804 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.728 ns ; +; 1.807 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.731 ns ; +; 1.813 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.737 ns ; +; 1.837 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.761 ns ; +; 1.843 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.090 ns ; 1.753 ns ; +; 1.856 ns ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|h_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.090 ns ; 1.766 ns ; +; 1.875 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.799 ns ; +; 1.878 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.802 ns ; +; 1.882 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.806 ns ; +; 1.883 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.807 ns ; +; 1.884 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.808 ns ; +; 1.897 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.821 ns ; +; 1.904 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.065 ns ; 1.839 ns ; +; 1.905 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.065 ns ; 1.840 ns ; +; 1.915 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.090 ns ; 1.825 ns ; +; 1.920 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.844 ns ; +; 1.920 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.072 ns ; 1.848 ns ; +; 1.921 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.845 ns ; +; 1.923 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.847 ns ; +; 1.951 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|b ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.063 ns ; 1.888 ns ; +; 1.957 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.881 ns ; +; 1.979 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.903 ns ; +; 1.979 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.903 ns ; +; 1.980 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.904 ns ; +; 1.982 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.906 ns ; +; 1.993 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.917 ns ; +; 1.996 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.920 ns ; +; 2.000 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.924 ns ; +; 2.001 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.925 ns ; +; 2.014 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.938 ns ; +; 2.015 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.939 ns ; +; 2.017 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.941 ns ; +; 2.021 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.072 ns ; 1.949 ns ; +; 2.024 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.948 ns ; +; 2.039 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.963 ns ; +; 2.046 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.072 ns ; 1.974 ns ; +; 2.061 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|h_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.090 ns ; 1.971 ns ; +; 2.067 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.991 ns ; +; 2.068 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.992 ns ; +; 2.077 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 2.001 ns ; +; 2.079 ns ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.090 ns ; 1.989 ns ; +; 2.083 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|g ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.089 ns ; 1.994 ns ; +; 2.084 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.063 ns ; 2.021 ns ; +; 2.089 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 2.013 ns ; +; 2.095 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 2.019 ns ; +; 2.101 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.065 ns ; 2.036 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------------------------------------+------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; tsu ; ++-------+--------------+------------+-------+----------------------------------------------------------+-----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-------+--------------+------------+-------+----------------------------------------------------------+-----------+ +; N/A ; None ; 11.030 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; board_clk ; +; N/A ; None ; 10.981 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; board_clk ; +; N/A ; None ; 10.931 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; board_clk ; +; N/A ; None ; 10.931 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; board_clk ; +; N/A ; None ; 10.436 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; board_clk ; +; N/A ; None ; 10.436 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; board_clk ; +; N/A ; None ; 10.436 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; board_clk ; +; N/A ; None ; 10.241 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; board_clk ; +; N/A ; None ; 10.239 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; board_clk ; +; N/A ; None ; 10.129 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; board_clk ; +; N/A ; None ; 10.077 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; board_clk ; +; N/A ; None ; 9.588 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; board_clk ; +; N/A ; None ; 9.588 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; board_clk ; +; N/A ; None ; 9.588 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; board_clk ; +; N/A ; None ; 9.318 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; board_clk ; +; N/A ; None ; 9.307 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; board_clk ; +; N/A ; None ; 9.200 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; board_clk ; +; N/A ; None ; 9.200 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; board_clk ; +; N/A ; None ; 9.184 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; board_clk ; +; N/A ; None ; 9.184 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; board_clk ; +; N/A ; None ; 9.184 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; board_clk ; +; N/A ; None ; 9.184 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; board_clk ; +; N/A ; None ; 9.184 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; board_clk ; +; N/A ; None ; 9.184 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; board_clk ; +; N/A ; None ; 9.130 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; board_clk ; +; N/A ; None ; 9.130 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; board_clk ; +; N/A ; None ; 8.928 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; board_clk ; +; N/A ; None ; 8.928 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; board_clk ; +; N/A ; None ; 8.901 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; board_clk ; +; N/A ; None ; 8.901 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; board_clk ; +; N/A ; None ; 8.901 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; board_clk ; +; N/A ; None ; 8.901 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; board_clk ; +; N/A ; None ; 8.792 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; board_clk ; +; N/A ; None ; 8.601 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; board_clk ; +; N/A ; None ; 7.061 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; board_clk ; +; N/A ; None ; 6.790 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; board_clk ; +; N/A ; None ; 6.428 ns ; reset ; vga:inst|dly_counter[0] ; board_clk ; +; N/A ; None ; 6.427 ns ; reset ; vga:inst|dly_counter[1] ; board_clk ; +; N/A ; None ; 6.421 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; board_clk ; +; N/A ; None ; 5.595 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|h_sync ; board_clk ; +; N/A ; None ; 5.594 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|v_sync ; board_clk ; ++-------+--------------+------------+-------+----------------------------------------------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; tco ; ++-------+--------------+------------+----------------------------------------------------------+----------------------+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++-------+--------------+------------+----------------------------------------------------------+----------------------+------------+ +; N/A ; None ; 9.803 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[7] ; board_clk ; +; N/A ; None ; 9.791 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[12] ; board_clk ; +; N/A ; None ; 9.672 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; d_hsync_state[0] ; board_clk ; +; N/A ; None ; 9.664 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[7] ; board_clk ; +; N/A ; None ; 9.652 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[12] ; board_clk ; +; N/A ; None ; 9.652 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; d_column_counter[9] ; board_clk ; +; N/A ; None ; 9.572 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; d_hsync_state[3] ; board_clk ; +; N/A ; None ; 9.541 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; d_hsync_counter[1] ; board_clk ; +; N/A ; None ; 9.278 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; d_vsync_counter[4] ; board_clk ; +; N/A ; None ; 9.201 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; d_set_hsync_counter ; board_clk ; +; N/A ; None ; 9.188 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[10] ; board_clk ; +; N/A ; None ; 9.176 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[1] ; board_clk ; +; N/A ; None ; 9.176 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[11] ; board_clk ; +; N/A ; None ; 9.125 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[2] ; board_clk ; +; N/A ; None ; 9.112 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; d_column_counter[4] ; board_clk ; +; N/A ; None ; 9.093 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[8] ; board_clk ; +; N/A ; None ; 9.049 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[10] ; board_clk ; +; N/A ; None ; 9.037 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[1] ; board_clk ; +; N/A ; None ; 9.037 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[11] ; board_clk ; +; N/A ; None ; 8.986 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[2] ; board_clk ; +; N/A ; None ; 8.954 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[8] ; board_clk ; +; N/A ; None ; 8.930 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; d_vsync_counter[9] ; board_clk ; +; N/A ; None ; 8.840 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[9] ; board_clk ; +; N/A ; None ; 8.701 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[9] ; board_clk ; +; N/A ; None ; 8.626 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; d_vsync_counter[6] ; board_clk ; +; N/A ; None ; 8.589 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; d_vsync_counter[5] ; board_clk ; +; N/A ; None ; 8.572 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; d_hsync_counter[3] ; board_clk ; +; N/A ; None ; 8.459 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; d_vsync_counter[7] ; board_clk ; +; N/A ; None ; 8.446 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; d_line_counter[5] ; board_clk ; +; N/A ; None ; 8.444 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; d_line_counter[3] ; board_clk ; +; N/A ; None ; 8.443 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; d_line_counter[0] ; board_clk ; +; N/A ; None ; 8.441 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; d_line_counter[4] ; board_clk ; +; N/A ; None ; 8.440 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; d_hsync_counter[0] ; board_clk ; +; N/A ; None ; 8.429 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; d_line_counter[1] ; board_clk ; +; N/A ; None ; 8.410 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; d_line_counter[6] ; board_clk ; +; N/A ; None ; 8.406 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; d_column_counter[5] ; board_clk ; +; N/A ; None ; 8.277 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; d_vsync_state[0] ; board_clk ; +; N/A ; None ; 8.185 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; d_vsync_counter[8] ; board_clk ; +; N/A ; None ; 8.170 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; d_vsync_state[6] ; board_clk ; +; N/A ; None ; 8.159 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; d_column_counter[6] ; board_clk ; +; N/A ; None ; 8.127 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; d_vsync_state[5] ; board_clk ; +; N/A ; None ; 8.123 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; d_vsync_state[4] ; board_clk ; +; N/A ; None ; 8.118 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; d_vsync_state[1] ; board_clk ; +; N/A ; None ; 8.082 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; d_hsync_state[5] ; board_clk ; +; N/A ; None ; 8.019 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; d_set_vsync_counter ; board_clk ; +; N/A ; None ; 7.961 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; d_vsync_state[2] ; board_clk ; +; N/A ; None ; 7.918 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; d_vsync_counter[3] ; board_clk ; +; N/A ; None ; 7.918 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; d_hsync_state[6] ; board_clk ; +; N/A ; None ; 7.890 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; d_vsync_counter[1] ; board_clk ; +; N/A ; None ; 7.872 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; d_vsync_counter[0] ; board_clk ; +; N/A ; None ; 7.861 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; d_hsync_counter[5] ; board_clk ; +; N/A ; None ; 7.795 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; d_hsync_state[4] ; board_clk ; +; N/A ; None ; 7.790 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; d_vsync_state[3] ; board_clk ; +; N/A ; None ; 7.784 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; d_line_counter[2] ; board_clk ; +; N/A ; None ; 7.719 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; d_set_vsync_counter ; board_clk ; +; N/A ; None ; 7.646 ns ; vga:inst|vga_control:vga_control_unit|g ; g1_pin ; board_clk ; +; N/A ; None ; 7.614 ns ; vga:inst|vga_control:vga_control_unit|r ; r1_pin ; board_clk ; +; N/A ; None ; 7.605 ns ; vga:inst|vga_control:vga_control_unit|r ; r2_pin ; board_clk ; +; N/A ; None ; 7.561 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; d_vsync_counter[2] ; board_clk ; +; N/A ; None ; 7.446 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; d_hsync_counter[8] ; board_clk ; +; N/A ; None ; 7.440 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; d_line_counter[8] ; board_clk ; +; N/A ; None ; 7.421 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; d_line_counter[7] ; board_clk ; +; N/A ; None ; 7.374 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; d_set_column_counter ; board_clk ; +; N/A ; None ; 7.310 ns ; vga:inst|vga_control:vga_control_unit|b ; b1_pin ; board_clk ; +; N/A ; None ; 7.215 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; d_hsync_counter[7] ; board_clk ; +; N/A ; None ; 7.169 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; d_hsync_counter[9] ; board_clk ; +; N/A ; None ; 7.163 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; d_set_line_counter ; board_clk ; +; N/A ; None ; 7.103 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; d_hsync_state[1] ; board_clk ; +; N/A ; None ; 7.032 ns ; vga:inst|vga_control:vga_control_unit|r ; d_r ; board_clk ; +; N/A ; None ; 6.992 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; d_set_hsync_counter ; board_clk ; +; N/A ; None ; 6.879 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; d_column_counter[0] ; board_clk ; +; N/A ; None ; 6.876 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; d_hsync_counter[2] ; board_clk ; +; N/A ; None ; 6.870 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; d_column_counter[1] ; board_clk ; +; N/A ; None ; 6.859 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; d_column_counter[2] ; board_clk ; +; N/A ; None ; 6.836 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; d_hsync_state[2] ; board_clk ; +; N/A ; None ; 6.836 ns ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vsync_pin ; board_clk ; +; N/A ; None ; 6.804 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; d_hsync_counter[6] ; board_clk ; +; N/A ; None ; 6.803 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; d_hsync_counter[4] ; board_clk ; +; N/A ; None ; 6.730 ns ; vga:inst|vga_driver:vga_driver_unit|h_sync ; hsync_pin ; board_clk ; +; N/A ; None ; 6.673 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; d_column_counter[7] ; board_clk ; +; N/A ; None ; 6.669 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; d_column_counter[8] ; board_clk ; +; N/A ; None ; 6.645 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; d_column_counter[3] ; board_clk ; +; N/A ; None ; 6.558 ns ; vga:inst|vga_driver:vga_driver_unit|h_sync ; d_hsync ; board_clk ; +; N/A ; None ; 6.544 ns ; vga:inst|vga_driver:vga_driver_unit|v_sync ; d_vsync ; board_clk ; +; N/A ; None ; 6.414 ns ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; d_h_enable ; board_clk ; +; N/A ; None ; 6.318 ns ; vga:inst|vga_control:vga_control_unit|r ; r0_pin ; board_clk ; +; N/A ; None ; 5.941 ns ; vga:inst|vga_control:vga_control_unit|g ; g2_pin ; board_clk ; +; N/A ; None ; 5.828 ns ; vga:inst|vga_control:vga_control_unit|g ; g0_pin ; board_clk ; +; N/A ; None ; 5.553 ns ; vga:inst|vga_control:vga_control_unit|b ; b0_pin ; board_clk ; +; N/A ; None ; 5.268 ns ; vga:inst|vga_control:vga_control_unit|g ; d_g ; board_clk ; +; N/A ; None ; 5.069 ns ; vga:inst|vga_control:vga_control_unit|b ; d_b ; board_clk ; +; N/A ; None ; 5.060 ns ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; d_v_enable ; board_clk ; +; N/A ; None ; 3.711 ns ; vpll:inst1|altpll:altpll_component|_clk0 ; d_state_clk ; board_clk ; ++-------+--------------+------------+----------------------------------------------------------+----------------------+------------+ + + ++-------------------------------------------------------------------------+ +; tpd ; ++-------+-------------------+-----------------+-------+-------------------+ +; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; ++-------+-------------------+-----------------+-------+-------------------+ +; N/A ; None ; 15.201 ns ; reset ; seven_seg_pin[7] ; +; N/A ; None ; 15.189 ns ; reset ; seven_seg_pin[12] ; +; N/A ; None ; 14.586 ns ; reset ; seven_seg_pin[10] ; +; N/A ; None ; 14.574 ns ; reset ; seven_seg_pin[1] ; +; N/A ; None ; 14.574 ns ; reset ; seven_seg_pin[11] ; +; N/A ; None ; 14.523 ns ; reset ; seven_seg_pin[2] ; +; N/A ; None ; 14.491 ns ; reset ; seven_seg_pin[8] ; +; N/A ; None ; 14.238 ns ; reset ; seven_seg_pin[9] ; ++-------+-------------------+-----------------+-------+-------------------+ + + ++------------------------------------------------------------------------------------------------------------------------+ +; th ; ++---------------+-------------+-----------+-------+----------------------------------------------------------+-----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++---------------+-------------+-----------+-------+----------------------------------------------------------+-----------+ +; N/A ; None ; -5.484 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|v_sync ; board_clk ; +; N/A ; None ; -5.485 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|h_sync ; board_clk ; +; N/A ; None ; -6.311 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; board_clk ; +; N/A ; None ; -6.317 ns ; reset ; vga:inst|dly_counter[1] ; board_clk ; +; N/A ; None ; -6.318 ns ; reset ; vga:inst|dly_counter[0] ; board_clk ; +; N/A ; None ; -6.626 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; board_clk ; +; N/A ; None ; -6.629 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; board_clk ; +; N/A ; None ; -6.632 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; board_clk ; +; N/A ; None ; -6.635 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; board_clk ; +; N/A ; None ; -6.637 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; board_clk ; +; N/A ; None ; -6.639 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; board_clk ; +; N/A ; None ; -6.640 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; board_clk ; +; N/A ; None ; -6.641 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; board_clk ; +; N/A ; None ; -6.643 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; board_clk ; +; N/A ; None ; -6.644 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; board_clk ; +; N/A ; None ; -6.680 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; board_clk ; +; N/A ; None ; -6.951 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; board_clk ; +; N/A ; None ; -8.491 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; board_clk ; +; N/A ; None ; -8.682 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; board_clk ; +; N/A ; None ; -8.701 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; board_clk ; +; N/A ; None ; -8.791 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; board_clk ; +; N/A ; None ; -8.791 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; board_clk ; +; N/A ; None ; -8.791 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; board_clk ; +; N/A ; None ; -8.791 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; board_clk ; +; N/A ; None ; -8.818 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; board_clk ; +; N/A ; None ; -8.818 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; board_clk ; +; N/A ; None ; -8.849 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; board_clk ; +; N/A ; None ; -8.849 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; board_clk ; +; N/A ; None ; -8.849 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; board_clk ; +; N/A ; None ; -8.850 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; board_clk ; +; N/A ; None ; -8.957 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; board_clk ; +; N/A ; None ; -8.958 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; board_clk ; +; N/A ; None ; -8.960 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; board_clk ; +; N/A ; None ; -8.963 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; board_clk ; +; N/A ; None ; -8.965 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; board_clk ; +; N/A ; None ; -8.968 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; board_clk ; +; N/A ; None ; -8.968 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; board_clk ; +; N/A ; None ; -8.969 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; board_clk ; +; N/A ; None ; -8.970 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; board_clk ; +; N/A ; None ; -8.972 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; board_clk ; +; N/A ; None ; -9.020 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; board_clk ; +; N/A ; None ; -9.020 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; board_clk ; +; N/A ; None ; -9.074 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; board_clk ; +; N/A ; None ; -9.074 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; board_clk ; +; N/A ; None ; -9.074 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; board_clk ; +; N/A ; None ; -9.074 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; board_clk ; +; N/A ; None ; -9.074 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; board_clk ; +; N/A ; None ; -9.074 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; board_clk ; +; N/A ; None ; -9.090 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; board_clk ; +; N/A ; None ; -9.090 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; board_clk ; +; N/A ; None ; -9.164 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; board_clk ; +; N/A ; None ; -9.208 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; board_clk ; +; N/A ; None ; -9.584 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; board_clk ; +; N/A ; None ; -9.584 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; board_clk ; +; N/A ; None ; -9.584 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; board_clk ; +; N/A ; None ; -9.595 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; board_clk ; +; N/A ; None ; -9.595 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; board_clk ; +; N/A ; None ; -9.595 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; board_clk ; +; N/A ; None ; -9.598 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; board_clk ; ++---------------+-------------+-----------+-------+----------------------------------------------------------+-----------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 17:13:27 2009 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled +Info: Found timing assignments -- calculating delays +Info: Slack time is 29.381 ns for clock "vpll:inst1|altpll:altpll_component|_clk0" between source register "vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9" and destination register "vga:inst|vga_control:vga_control_unit|b" + Info: Fmax is 135.21 MHz (period= 7.396 ns) + Info: + Largest register to register requirement is 36.604 ns + Info: + Setup relationship between source and destination is 36.777 ns + Info: + Latch edge is 35.747 ns + Info: Clock period of Destination clock "vpll:inst1|altpll:altpll_component|_clk0" is 36.777 ns with offset of -1.030 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is -1.030 ns + Info: Clock period of Source clock "vpll:inst1|altpll:altpll_component|_clk0" is 36.777 ns with offset of -1.030 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 0.013 ns + Info: + Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.053 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.493 ns) + CELL(0.560 ns) = 2.053 ns; Loc. = LC_X78_Y32_N4; Fanout = 3; REG Node = 'vga:inst|vga_control:vga_control_unit|b' + Info: Total cell delay = 0.560 ns ( 27.28 % ) + Info: Total interconnect delay = 1.493 ns ( 72.72 % ) + Info: - Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.040 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.480 ns) + CELL(0.560 ns) = 2.040 ns; Loc. = LC_X78_Y33_N0; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9' + Info: Total cell delay = 0.560 ns ( 27.45 % ) + Info: Total interconnect delay = 1.480 ns ( 72.55 % ) + Info: - Micro clock to output delay of source is 0.176 ns + Info: - Micro setup delay of destination is 0.010 ns + Info: - Longest register to register delay is 7.223 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X78_Y33_N0; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9' + Info: 2: + IC(2.360 ns) + CELL(0.087 ns) = 2.447 ns; Loc. = LC_X56_Y45_N5; Fanout = 3; COMB Node = 'vga:inst|vga_control:vga_control_unit|r_next_i_o7' + Info: 3: + IC(2.773 ns) + CELL(0.332 ns) = 5.552 ns; Loc. = LC_X76_Y33_N4; Fanout = 1; COMB Node = 'vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0' + Info: 4: + IC(1.307 ns) + CELL(0.364 ns) = 7.223 ns; Loc. = LC_X78_Y32_N4; Fanout = 3; REG Node = 'vga:inst|vga_control:vga_control_unit|b' + Info: Total cell delay = 0.783 ns ( 10.84 % ) + Info: Total interconnect delay = 6.440 ns ( 89.16 % ) +Info: No valid register-to-register data paths exist for clock "board_clk" +Info: Minimum slack time is 737 ps for clock "vpll:inst1|altpll:altpll_component|_clk0" between source register "vga:inst|vga_driver:vga_driver_unit|vsync_counter_9" and destination register "vga:inst|vga_driver:vga_driver_unit|vsync_counter_9" + Info: + Shortest register to register delay is 0.661 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst|vga_driver:vga_driver_unit|vsync_counter_9' + Info: 2: + IC(0.426 ns) + CELL(0.235 ns) = 0.661 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst|vga_driver:vga_driver_unit|vsync_counter_9' + Info: Total cell delay = 0.235 ns ( 35.55 % ) + Info: Total interconnect delay = 0.426 ns ( 64.45 % ) + Info: - Smallest register to register requirement is -0.076 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -1.030 ns + Info: Clock period of Destination clock "vpll:inst1|altpll:altpll_component|_clk0" is 36.777 ns with offset of -1.030 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -1.030 ns + Info: Clock period of Source clock "vpll:inst1|altpll:altpll_component|_clk0" is 36.777 ns with offset of -1.030 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.054 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst|vga_driver:vga_driver_unit|vsync_counter_9' + Info: Total cell delay = 0.560 ns ( 27.26 % ) + Info: Total interconnect delay = 1.494 ns ( 72.74 % ) + Info: - Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.054 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst|vga_driver:vga_driver_unit|vsync_counter_9' + Info: Total cell delay = 0.560 ns ( 27.26 % ) + Info: Total interconnect delay = 1.494 ns ( 72.74 % ) + Info: - Micro clock to output delay of source is 0.176 ns + Info: + Micro hold delay of destination is 0.100 ns +Info: tsu for register "vga:inst|vga_driver:vga_driver_unit|h_enable_sig" (data pin = "reset", clock pin = "board_clk") is 11.030 ns + Info: + Longest pin to register delay is 12.049 ns + Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset' + Info: 2: + IC(5.711 ns) + CELL(0.459 ns) = 7.311 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x' + Info: 3: + IC(1.863 ns) + CELL(0.332 ns) = 9.506 ns; Loc. = LC_X34_Y34_N6; Fanout = 1; COMB Node = 'vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4' + Info: 4: + IC(1.817 ns) + CELL(0.726 ns) = 12.049 ns; Loc. = LC_X52_Y35_N2; Fanout = 2; REG Node = 'vga:inst|vga_driver:vga_driver_unit|h_enable_sig' + Info: Total cell delay = 2.658 ns ( 22.06 % ) + Info: Total interconnect delay = 9.391 ns ( 77.94 % ) + Info: + Micro setup delay of destination is 0.010 ns + Info: - Offset between input clock "board_clk" and output clock "vpll:inst1|altpll:altpll_component|_clk0" is -1.030 ns + Info: - Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.059 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.499 ns) + CELL(0.560 ns) = 2.059 ns; Loc. = LC_X52_Y35_N2; Fanout = 2; REG Node = 'vga:inst|vga_driver:vga_driver_unit|h_enable_sig' + Info: Total cell delay = 0.560 ns ( 27.20 % ) + Info: Total interconnect delay = 1.499 ns ( 72.80 % ) +Info: tco from clock "board_clk" to destination pin "seven_seg_pin[7]" through register "vga:inst|dly_counter[0]" is 9.803 ns + Info: + Offset between input clock "board_clk" and output clock "vpll:inst1|altpll:altpll_component|_clk0" is -1.030 ns + Info: + Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.054 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X36_Y33_N3; Fanout = 10; REG Node = 'vga:inst|dly_counter[0]' + Info: Total cell delay = 0.560 ns ( 27.26 % ) + Info: Total interconnect delay = 1.494 ns ( 72.74 % ) + Info: + Micro clock to output delay of source is 0.176 ns + Info: + Longest register to pin delay is 8.603 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y33_N3; Fanout = 10; REG Node = 'vga:inst|dly_counter[0]' + Info: 2: + IC(0.500 ns) + CELL(0.213 ns) = 0.713 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x' + Info: 3: + IC(3.699 ns) + CELL(4.191 ns) = 8.603 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin[7]' + Info: Total cell delay = 4.404 ns ( 51.19 % ) + Info: Total interconnect delay = 4.199 ns ( 48.81 % ) +Info: Longest tpd from source pin "reset" to destination pin "seven_seg_pin[7]" is 15.201 ns + Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset' + Info: 2: + IC(5.711 ns) + CELL(0.459 ns) = 7.311 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x' + Info: 3: + IC(3.699 ns) + CELL(4.191 ns) = 15.201 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin[7]' + Info: Total cell delay = 5.791 ns ( 38.10 % ) + Info: Total interconnect delay = 9.410 ns ( 61.90 % ) +Info: th for register "vga:inst|vga_driver:vga_driver_unit|v_sync" (data pin = "reset", clock pin = "board_clk") is -5.484 ns + Info: + Offset between input clock "board_clk" and output clock "vpll:inst1|altpll:altpll_component|_clk0" is -1.030 ns + Info: + Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.040 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0' + Info: 2: + IC(1.480 ns) + CELL(0.560 ns) = 2.040 ns; Loc. = LC_X34_Y34_N7; Fanout = 3; REG Node = 'vga:inst|vga_driver:vga_driver_unit|v_sync' + Info: Total cell delay = 0.560 ns ( 27.45 % ) + Info: Total interconnect delay = 1.480 ns ( 72.55 % ) + Info: + Micro hold delay of destination is 0.100 ns + Info: - Shortest pin to register delay is 6.594 ns + Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset' + Info: 2: + IC(4.964 ns) + CELL(0.489 ns) = 6.594 ns; Loc. = LC_X34_Y34_N7; Fanout = 3; REG Node = 'vga:inst|vga_driver:vga_driver_unit|v_sync' + Info: Total cell delay = 1.630 ns ( 24.72 % ) + Info: Total interconnect delay = 4.964 ns ( 75.28 % ) +Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details. +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 141 megabytes + Info: Processing ended: Thu Oct 29 17:13:27 2009 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/bsp3/Designflow/ppr/download/vga_pll.tan.summary b/bsp3/Designflow/ppr/download/vga_pll.tan.summary new file mode 100644 index 0000000..f3e906f --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.tan.summary @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : N/A +Required Time : None +Actual Time : 11.030 ns +From : reset +To : vga:inst|vga_driver:vga_driver_unit|h_enable_sig +From Clock : -- +To Clock : board_clk +Failed Paths : 0 + +Type : Worst-case tco +Slack : N/A +Required Time : None +Actual Time : 9.803 ns +From : vga:inst|dly_counter[0] +To : seven_seg_pin[7] +From Clock : board_clk +To Clock : -- +Failed Paths : 0 + +Type : Worst-case tpd +Slack : N/A +Required Time : None +Actual Time : 15.201 ns +From : reset +To : seven_seg_pin[7] +From Clock : -- +To Clock : -- +Failed Paths : 0 + +Type : Worst-case th +Slack : N/A +Required Time : None +Actual Time : -5.484 ns +From : reset +To : vga:inst|vga_driver:vga_driver_unit|v_sync +From Clock : -- +To Clock : board_clk +Failed Paths : 0 + +Type : Clock Setup: 'vpll:inst1|altpll:altpll_component|_clk0' +Slack : 29.381 ns +Required Time : 27.19 MHz ( period = 36.777 ns ) +Actual Time : 135.21 MHz ( period = 7.396 ns ) +From : vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 +To : vga:inst|vga_control:vga_control_unit|b +From Clock : vpll:inst1|altpll:altpll_component|_clk0 +To Clock : vpll:inst1|altpll:altpll_component|_clk0 +Failed Paths : 0 + +Type : Clock Hold: 'vpll:inst1|altpll:altpll_component|_clk0' +Slack : 0.737 ns +Required Time : 27.19 MHz ( period = 36.777 ns ) +Actual Time : N/A +From : vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 +To : vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 +From Clock : vpll:inst1|altpll:altpll_component|_clk0 +To Clock : vpll:inst1|altpll:altpll_component|_clk0 +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 0 + +-------------------------------------------------------------------------------------- + diff --git a/bsp3/Designflow/ppr/download/vga_pll.tcl b/bsp3/Designflow/ppr/download/vga_pll.tcl new file mode 100755 index 0000000..aa73503 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll.tcl @@ -0,0 +1,172 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: vga_pll.tcl +# Generated on: Fri Sep 29 09:31:24 2006 + +# Load Quartus II Tcl Project package +package require ::quartus::project +package require ::quartus::flow + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "vga_pll"]} { + puts "Project vga_pll is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists vga_pll]} { + project_open -cmp vga_pll vga_pll + } else { + project_new -cmp vga_pll vga_pll + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + catch { set_global_assignment -name FAMILY Stratix } result + catch { set_global_assignment -name DEVICE EP1S25F672C6 } result + catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result + catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result + catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result + catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result + catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result + catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result + catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result + catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result + catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result + catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result + catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result + catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result + + set_location_assignment PIN_E24 -to b0_pin + set_location_assignment PIN_T6 -to b1_pin + set_location_assignment PIN_N3 -to board_clk + set_location_assignment PIN_E23 -to g0_pin + set_location_assignment PIN_T5 -to g1_pin + set_location_assignment PIN_T24 -to g2_pin + set_location_assignment PIN_F1 -to hsync_pin + set_location_assignment PIN_E22 -to r0_pin + set_location_assignment PIN_T4 -to r1_pin + set_location_assignment PIN_T7 -to r2_pin + set_location_assignment PIN_A5 -to reset + set_location_assignment PIN_F2 -to vsync_pin + set_location_assignment PIN_Y5 -to d_hsync_state[0] + set_location_assignment PIN_F19 -to d_hsync_state[1] + set_location_assignment PIN_F17 -to d_hsync_state[2] + set_location_assignment PIN_Y2 -to d_hsync_state[3] + set_location_assignment PIN_F10 -to d_hsync_state[4] + set_location_assignment PIN_F9 -to d_hsync_state[5] + set_location_assignment PIN_F6 -to d_hsync_state[6] + set_location_assignment PIN_H4 -to d_hsync_counter[0] + set_location_assignment PIN_G25 -to d_hsync_counter[7] + set_location_assignment PIN_G22 -to d_hsync_counter[8] + set_location_assignment PIN_G18 -to d_hsync_counter[9] + set_location_assignment PIN_F5 -to d_vsync_state[0] + set_location_assignment PIN_F4 -to d_vsync_state[1] + set_location_assignment PIN_F3 -to d_vsync_state[2] + set_location_assignment PIN_M19 -to d_vsync_state[3] + set_location_assignment PIN_M18 -to d_vsync_state[4] + set_location_assignment PIN_M7 -to d_vsync_state[5] + set_location_assignment PIN_M4 -to d_vsync_state[6] + set_location_assignment PIN_G9 -to d_vsync_counter[0] + set_location_assignment PIN_G6 -to d_vsync_counter[7] + set_location_assignment PIN_G4 -to d_vsync_counter[8] + set_location_assignment PIN_G2 -to d_vsync_counter[9] + set_location_assignment PIN_K6 -to d_line_counter[0] + set_location_assignment PIN_K4 -to d_line_counter[1] + set_location_assignment PIN_J22 -to d_line_counter[2] + set_location_assignment PIN_M9 -to d_line_counter[3] + set_location_assignment PIN_M8 -to d_line_counter[4] + set_location_assignment PIN_M6 -to d_line_counter[5] + set_location_assignment PIN_M5 -to d_line_counter[6] + set_location_assignment PIN_L24 -to d_line_counter[7] + set_location_assignment PIN_L25 -to d_line_counter[8] + set_location_assignment PIN_L23 -to d_column_counter[0] + set_location_assignment PIN_L22 -to d_column_counter[1] + set_location_assignment PIN_L21 -to d_column_counter[2] + set_location_assignment PIN_L20 -to d_column_counter[3] + set_location_assignment PIN_L6 -to d_column_counter[4] + set_location_assignment PIN_L4 -to d_column_counter[5] + set_location_assignment PIN_L2 -to d_column_counter[6] + set_location_assignment PIN_K23 -to d_column_counter[7] + set_location_assignment PIN_K19 -to d_column_counter[8] + set_location_assignment PIN_K5 -to d_column_counter[9] + set_location_assignment PIN_L7 -to d_hsync + set_location_assignment PIN_L5 -to d_vsync + set_location_assignment PIN_F26 -to d_set_hsync_counter + set_location_assignment PIN_F24 -to d_set_vsync_counter + set_location_assignment PIN_F21 -to d_set_line_counter + set_location_assignment PIN_Y23 -to d_set_column_counter + set_location_assignment PIN_L3 -to d_r + set_location_assignment PIN_K24 -to d_g + set_location_assignment PIN_K20 -to d_b + set_location_assignment PIN_H18 -to d_v_enable + set_location_assignment PIN_J21 -to d_h_enable + set_location_assignment PIN_R8 -to seven_seg_pin[0] + set_location_assignment PIN_R9 -to seven_seg_pin[1] + set_location_assignment PIN_R19 -to seven_seg_pin[2] + set_location_assignment PIN_R20 -to seven_seg_pin[3] + set_location_assignment PIN_R21 -to seven_seg_pin[4] + set_location_assignment PIN_R22 -to seven_seg_pin[5] + set_location_assignment PIN_R23 -to seven_seg_pin[6] + set_location_assignment PIN_Y11 -to seven_seg_pin[7] + set_location_assignment PIN_N7 -to seven_seg_pin[8] + set_location_assignment PIN_N8 -to seven_seg_pin[9] + set_location_assignment PIN_R4 -to seven_seg_pin[10] + set_location_assignment PIN_R6 -to seven_seg_pin[11] + set_location_assignment PIN_AA11 -to seven_seg_pin[12] + set_location_assignment PIN_T2 -to seven_seg_pin[13] + set_location_assignment PIN_K3 -to d_state_clk + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin + + + # Commit assignments + export_assignments + +execute_flow -compile + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/bsp3/Designflow/ppr/download/vga_pll_assignment_defaults.qdf b/bsp3/Designflow/ppr/download/vga_pll_assignment_defaults.qdf new file mode 100644 index 0000000..58d80a9 --- /dev/null +++ b/bsp3/Designflow/ppr/download/vga_pll_assignment_defaults.qdf @@ -0,0 +1,626 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 132 02/25/2009 SJ Full Version +# Date created = 17:12:29 October 29, 2009 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus II software and is used +# to preserve global assignments across Quartus II versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name SMART_RECOMPILE Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name IGNORE_CLOCK_SETTINGS Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off +set_global_assignment -name ENABLE_CLOCK_LATENCY Off +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family ACEX1K +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KA +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KE +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10K +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KC +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX6000 +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "APEX II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KE +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix +set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200 +set_global_assignment -name DO_MIN_ANALYSIS Off +set_global_assignment -name DO_MIN_TIMING Off +set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off +set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family ACEX1K +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KA +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10K +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KC +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX6000 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "APEX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family ACEX1K +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KA +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10K +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KC +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX6000 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "APEX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL93 +set_global_assignment -name FAMILY -value Stratix +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On +set_global_assignment -name PARALLEL_SYNTHESIS Off +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off +set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III" +set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III" +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off +set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS Off +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family ACEX1K +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KA +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10K +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KC +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX6000 +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "APEX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" +set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Stratix III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY -value ON +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION -value ON +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name INCREMENTAL_COMPILATION -value OFF +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name DUTY_CYCLE 50 -section_id ? +set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ? +set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name OPTIMIZE_SSN Off -entity ? -family "Cyclone III" +set_global_assignment -name OPTIMIZE_SSN Off -entity ? -family "Stratix III" +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? diff --git a/bsp3/Designflow/ppr/sim/db/vga.(0).cnf.cdb b/bsp3/Designflow/ppr/sim/db/vga.(0).cnf.cdb new file mode 100644 index 0000000000000000000000000000000000000000..61bacbc65bbe0d30bfaac23645522fd0153c2f13 GIT binary patch literal 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zKm?y~L&%e?BzmKnO5xiDUY&n@wL3veU^u{cv2jxwQvu$ghdBtFEGVPygyW90L!dZw z?a9VyAx}2gmJB^TJ-VK$(j(qg9PkOHLRn8^*Gh@@u+M>?E%dbR#Ii9FA}$?b=AZI5 z_^#~OLyoc~I`v`N!D$X_3%8%J9Z8%j{F7{=ic4f|VNpg7wcLQ??6oo1S#!`KZmj=x UZr>0a4cEj7&F9_z0{{U3|Alr5#sB~S literal 0 HcmV?d00001 diff --git a/bsp3/Designflow/ppr/sim/db/vga.cmp_merge.kpt b/bsp3/Designflow/ppr/sim/db/vga.cmp_merge.kpt new file mode 100644 index 0000000..e6722db --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga.cmp_merge.kpt @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/bsp3/Designflow/ppr/sim/db/vga.db_info b/bsp3/Designflow/ppr/sim/db/vga.db_info new file mode 100644 index 0000000..285ea14 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 9.0 Build 132 02/25/2009 SJ Full Version +Version_Index = 167805952 +Creation_Time = Thu Oct 29 16:59:28 2009 diff --git a/bsp3/Designflow/ppr/sim/db/vga.eco.cdb b/bsp3/Designflow/ppr/sim/db/vga.eco.cdb new file mode 100644 index 0000000000000000000000000000000000000000..8c94386ba2d0f63249cb2651a7af5ca398532096 GIT binary patch literal 161 zcmd;QU|?9w&B%}dgoZ$NSZYymW`3T6rJjL;Q)y;Sih`lBk%EDdzLBZEk%57wLa>*D zTWL;?0#u clk_pin_in.PADIO +reset_pin => reset_pin_in.PADIO +r0_pin <= r0_pin_out.PADIO +r1_pin <= r1_pin_out.PADIO +r2_pin <= r2_pin_out.PADIO +g0_pin <= g0_pin_out.PADIO +g1_pin <= g1_pin_out.PADIO +g2_pin <= g2_pin_out.PADIO +b0_pin <= b0_pin_out.PADIO +b1_pin <= b1_pin_out.PADIO +hsync_pin <= hsync_pin_out.PADIO +vsync_pin <= vsync_pin_out.PADIO +seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO +seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO +seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO +seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO +seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO +seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO +seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO +seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO +seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO +seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO +seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO +seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO +seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO +seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO +d_hsync <= d_hsync_out.PADIO +d_vsync <= d_vsync_out.PADIO +d_column_counter[0] <= d_column_counter_out_0_.PADIO +d_column_counter[1] <= d_column_counter_out_1_.PADIO +d_column_counter[2] <= d_column_counter_out_2_.PADIO +d_column_counter[3] <= d_column_counter_out_3_.PADIO +d_column_counter[4] <= d_column_counter_out_4_.PADIO +d_column_counter[5] <= d_column_counter_out_5_.PADIO +d_column_counter[6] <= d_column_counter_out_6_.PADIO +d_column_counter[7] <= d_column_counter_out_7_.PADIO +d_column_counter[8] <= d_column_counter_out_8_.PADIO +d_column_counter[9] <= d_column_counter_out_9_.PADIO +d_line_counter[0] <= d_line_counter_out_0_.PADIO +d_line_counter[1] <= d_line_counter_out_1_.PADIO +d_line_counter[2] <= d_line_counter_out_2_.PADIO +d_line_counter[3] <= d_line_counter_out_3_.PADIO +d_line_counter[4] <= d_line_counter_out_4_.PADIO +d_line_counter[5] <= d_line_counter_out_5_.PADIO +d_line_counter[6] <= d_line_counter_out_6_.PADIO +d_line_counter[7] <= d_line_counter_out_7_.PADIO +d_line_counter[8] <= d_line_counter_out_8_.PADIO +d_set_column_counter <= d_set_column_counter_out.PADIO +d_set_line_counter <= d_set_line_counter_out.PADIO +d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO +d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO +d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO +d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO +d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO +d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO +d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO +d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO +d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO +d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO +d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO +d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO +d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO +d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO +d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO +d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO +d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO +d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO +d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO +d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO +d_set_hsync_counter <= d_set_hsync_counter_out.PADIO +d_set_vsync_counter <= d_set_vsync_counter_out.PADIO +d_h_enable <= d_h_enable_out.PADIO +d_v_enable <= d_v_enable_out.PADIO +d_r <= d_r_out.PADIO +d_g <= d_g_out.PADIO +d_b <= d_b_out.PADIO +d_hsync_state[6] <= d_hsync_state_out_6_.PADIO +d_hsync_state[5] <= d_hsync_state_out_5_.PADIO +d_hsync_state[4] <= d_hsync_state_out_4_.PADIO +d_hsync_state[3] <= d_hsync_state_out_3_.PADIO +d_hsync_state[2] <= d_hsync_state_out_2_.PADIO +d_hsync_state[1] <= d_hsync_state_out_1_.PADIO +d_hsync_state[0] <= d_hsync_state_out_0_.PADIO +d_vsync_state[6] <= d_vsync_state_out_6_.PADIO +d_vsync_state[5] <= d_vsync_state_out_5_.PADIO +d_vsync_state[4] <= d_vsync_state_out_4_.PADIO +d_vsync_state[3] <= d_vsync_state_out_3_.PADIO +d_vsync_state[2] <= d_vsync_state_out_2_.PADIO +d_vsync_state[1] <= d_vsync_state_out_1_.PADIO +d_vsync_state[0] <= d_vsync_state_out_0_.PADIO +d_state_clk <= d_state_clk_out.PADIO + + +|vga|vga_driver:vga_driver_unit +line_counter_sig_0 <= line_counter_sig_0_.REGOUT +line_counter_sig_1 <= line_counter_sig_1_.REGOUT +line_counter_sig_2 <= line_counter_sig_2_.REGOUT +line_counter_sig_3 <= line_counter_sig_3_.REGOUT +line_counter_sig_4 <= line_counter_sig_4_.REGOUT +line_counter_sig_5 <= line_counter_sig_5_.REGOUT +line_counter_sig_6 <= line_counter_sig_6_.REGOUT +line_counter_sig_7 <= line_counter_sig_7_.REGOUT +line_counter_sig_8 <= line_counter_sig_8_.REGOUT +dly_counter_1 => vsync_state_6_.DATAC +dly_counter_1 => h_sync_Z.DATAC +dly_counter_1 => v_sync_Z.DATAC +dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC +dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC +dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC +dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC +dly_counter_0 => vsync_state_6_.DATAB +dly_counter_0 => h_sync_Z.DATAB +dly_counter_0 => v_sync_Z.DATAB +dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB +dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB +dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB +dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB +vsync_state_2 <= vsync_state_2_.REGOUT +vsync_state_5 <= vsync_state_5_.REGOUT +vsync_state_3 <= vsync_state_3_.REGOUT +vsync_state_6 <= vsync_state_6_.REGOUT +vsync_state_4 <= vsync_state_4_.REGOUT +vsync_state_1 <= vsync_state_1_.REGOUT +vsync_state_0 <= vsync_state_0_.REGOUT +hsync_state_2 <= hsync_state_2_.REGOUT +hsync_state_4 <= hsync_state_4_.REGOUT +hsync_state_0 <= hsync_state_0_.REGOUT +hsync_state_5 <= hsync_state_5_.REGOUT +hsync_state_1 <= hsync_state_1_.REGOUT +hsync_state_3 <= hsync_state_3_.REGOUT +hsync_state_6 <= hsync_state_6_.REGOUT +column_counter_sig_0 <= column_counter_sig_0_.REGOUT +column_counter_sig_1 <= column_counter_sig_1_.REGOUT +column_counter_sig_2 <= column_counter_sig_2_.REGOUT +column_counter_sig_3 <= column_counter_sig_3_.REGOUT +column_counter_sig_4 <= column_counter_sig_4_.REGOUT +column_counter_sig_5 <= column_counter_sig_5_.REGOUT +column_counter_sig_6 <= column_counter_sig_6_.REGOUT +column_counter_sig_7 <= column_counter_sig_7_.REGOUT +column_counter_sig_8 <= column_counter_sig_8_.REGOUT +column_counter_sig_9 <= column_counter_sig_9_.REGOUT +vsync_counter_9 <= vsync_counter_9_.REGOUT +vsync_counter_8 <= vsync_counter_8_.REGOUT +vsync_counter_7 <= vsync_counter_7_.REGOUT +vsync_counter_6 <= vsync_counter_6_.REGOUT +vsync_counter_5 <= vsync_counter_5_.REGOUT +vsync_counter_4 <= vsync_counter_4_.REGOUT +vsync_counter_3 <= vsync_counter_3_.REGOUT +vsync_counter_2 <= vsync_counter_2_.REGOUT +vsync_counter_1 <= vsync_counter_1_.REGOUT +vsync_counter_0 <= vsync_counter_0_.REGOUT +hsync_counter_9 <= hsync_counter_9_.REGOUT +hsync_counter_8 <= hsync_counter_8_.REGOUT +hsync_counter_7 <= hsync_counter_7_.REGOUT +hsync_counter_6 <= hsync_counter_6_.REGOUT +hsync_counter_5 <= hsync_counter_5_.REGOUT +hsync_counter_4 <= hsync_counter_4_.REGOUT +hsync_counter_3 <= hsync_counter_3_.REGOUT +hsync_counter_2 <= hsync_counter_2_.REGOUT +hsync_counter_1 <= hsync_counter_1_.REGOUT +hsync_counter_0 <= hsync_counter_0_.REGOUT +d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT +un10_column_counter_siglt6_1 <= COLUMN_COUNT_next_un10_column_counter_siglt6_1.COMBOUT +un10_column_counter_siglt6_3 <= COLUMN_COUNT_next_un10_column_counter_siglt6_3.COMBOUT +v_sync <= v_sync_Z.REGOUT +h_sync <= h_sync_Z.REGOUT +h_enable_sig <= h_enable_sig_Z.REGOUT +v_enable_sig <= v_enable_sig_Z.REGOUT +reset_pin_c => vsync_state_6_.DATAA +reset_pin_c => h_sync_Z.DATAA +reset_pin_c => v_sync_Z.DATAA +reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA +reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA +reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA +reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA +un6_dly_counter_0_x <= vsync_state_6_.COMBOUT +d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT +clk_pin_c => hsync_counter_0_.CLK +clk_pin_c => hsync_counter_1_.CLK +clk_pin_c => hsync_counter_2_.CLK +clk_pin_c => hsync_counter_3_.CLK +clk_pin_c => hsync_counter_4_.CLK +clk_pin_c => hsync_counter_5_.CLK +clk_pin_c => hsync_counter_6_.CLK +clk_pin_c => hsync_counter_7_.CLK +clk_pin_c => hsync_counter_8_.CLK +clk_pin_c => hsync_counter_9_.CLK +clk_pin_c => vsync_counter_0_.CLK +clk_pin_c => vsync_counter_1_.CLK +clk_pin_c => vsync_counter_2_.CLK +clk_pin_c => vsync_counter_3_.CLK +clk_pin_c => vsync_counter_4_.CLK +clk_pin_c => vsync_counter_5_.CLK +clk_pin_c => vsync_counter_6_.CLK +clk_pin_c => vsync_counter_7_.CLK +clk_pin_c => vsync_counter_8_.CLK +clk_pin_c => vsync_counter_9_.CLK +clk_pin_c => column_counter_sig_9_.CLK +clk_pin_c => column_counter_sig_8_.CLK +clk_pin_c => column_counter_sig_7_.CLK +clk_pin_c => column_counter_sig_6_.CLK +clk_pin_c => column_counter_sig_5_.CLK +clk_pin_c => column_counter_sig_4_.CLK +clk_pin_c => column_counter_sig_3_.CLK +clk_pin_c => column_counter_sig_2_.CLK +clk_pin_c => column_counter_sig_1_.CLK +clk_pin_c => column_counter_sig_0_.CLK +clk_pin_c => hsync_state_6_.CLK +clk_pin_c => vsync_state_0_.CLK +clk_pin_c => vsync_state_1_.CLK +clk_pin_c => vsync_state_6_.CLK +clk_pin_c => line_counter_sig_8_.CLK +clk_pin_c => line_counter_sig_7_.CLK +clk_pin_c => line_counter_sig_6_.CLK +clk_pin_c => line_counter_sig_5_.CLK +clk_pin_c => line_counter_sig_4_.CLK +clk_pin_c => line_counter_sig_3_.CLK +clk_pin_c => line_counter_sig_2_.CLK +clk_pin_c => line_counter_sig_1_.CLK +clk_pin_c => line_counter_sig_0_.CLK +clk_pin_c => v_enable_sig_Z.CLK +clk_pin_c => h_enable_sig_Z.CLK +clk_pin_c => h_sync_Z.CLK +clk_pin_c => v_sync_Z.CLK +clk_pin_c => vsync_state_5_.CLK +clk_pin_c => vsync_state_4_.CLK +clk_pin_c => vsync_state_3_.CLK +clk_pin_c => vsync_state_2_.CLK +clk_pin_c => hsync_state_5_.CLK +clk_pin_c => hsync_state_4_.CLK +clk_pin_c => hsync_state_3_.CLK +clk_pin_c => hsync_state_2_.CLK +clk_pin_c => hsync_state_1_.CLK +clk_pin_c => hsync_state_0_.CLK + + +|vga|vga_control:vga_control_unit +column_counter_sig_1 => g_next_i_o3_cZ.DATAB +column_counter_sig_7 => r_next_i_o7_cZ.DATAA +column_counter_sig_2 => b_next_i_o3_0_cZ.DATAC +column_counter_sig_2 => g_next_i_o3_cZ.DATAA +column_counter_sig_0 => b_next_i_a7_1_cZ.DATAC +column_counter_sig_4 => N_23_i_0_g0_a_cZ.DATAB +column_counter_sig_4 => b_next_i_o3_0_cZ.DATAB +column_counter_sig_3 => N_23_i_0_g0_a_cZ.DATAA +column_counter_sig_3 => b_next_i_o3_0_cZ.DATAA +column_counter_sig_5 => g_Z.DATAB +column_counter_sig_5 => N_4_i_0_g0_1_cZ.DATAA +column_counter_sig_5 => N_6_i_0_g0_0_cZ.DATAA +column_counter_sig_5 => b_next_i_a7_1_cZ.DATAA +column_counter_sig_5 => b_next_i_o3_0_cZ.DATAD +column_counter_sig_6 => b_Z.DATAA +column_counter_sig_6 => r_Z.DATAA +column_counter_sig_6 => g_Z.DATAA +column_counter_sig_6 => N_4_i_0_g0_1_cZ.DATAB +column_counter_sig_6 => N_6_i_0_g0_0_cZ.DATAB +column_counter_sig_6 => b_next_i_a7_1_cZ.DATAB +h_enable_sig => r_next_i_o7_cZ.DATAC +v_enable_sig => r_next_i_o7_cZ.DATAB +un10_column_counter_siglt6_1 => N_23_i_0_g0_a_cZ.DATAD +g <= g_Z.REGOUT +un10_column_counter_siglt6_3 => r_Z.DATAB +un10_column_counter_siglt6_3 => N_6_i_0_g0_0_cZ.DATAC +r <= r_Z.REGOUT +un6_dly_counter_0_x => b_Z.ACLR +un6_dly_counter_0_x => r_Z.ACLR +un6_dly_counter_0_x => g_Z.ACLR +clk_pin_c => b_Z.CLK +clk_pin_c => r_Z.CLK +clk_pin_c => g_Z.CLK +b <= b_Z.REGOUT + + diff --git a/bsp3/Designflow/ppr/sim/db/vga.hif b/bsp3/Designflow/ppr/sim/db/vga.hif new file mode 100644 index 0000000..84411e2 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga.hif @@ -0,0 +1,79 @@ +Version 9.0 Build 132 02/25/2009 SJ Full Version +45 +3235 +OFF +OFF +OFF +ON +ON +ON +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +synplcty.lmf +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +vga +# storage +db|vga.(0).cnf +db|vga.(0).cnf +# case_sensitive +# source_file +..|..|syn|rev_1|vga.vqm +75b23e99ee7fd7794044e77b9ba64bf9 +28 +# hierarchies { +| +} +# lmf +|opt|quartus|quartus|lmf|synplcty.lmf +3057712873b497a38b70a3917f30cc38 +# macro_sequence + +# end +# entity +vga_driver +# storage +db|vga.(1).cnf +db|vga.(1).cnf +# case_sensitive +# source_file +..|..|syn|rev_1|vga.vqm +75b23e99ee7fd7794044e77b9ba64bf9 +28 +# hierarchies { +vga_driver:vga_driver_unit +} +# lmf +|opt|quartus|quartus|lmf|synplcty.lmf +3057712873b497a38b70a3917f30cc38 +# macro_sequence + +# end +# entity +vga_control +# storage +db|vga.(2).cnf +db|vga.(2).cnf +# case_sensitive +# source_file +..|..|syn|rev_1|vga.vqm +75b23e99ee7fd7794044e77b9ba64bf9 +28 +# hierarchies { +vga_control:vga_control_unit +} +# lmf +|opt|quartus|quartus|lmf|synplcty.lmf +3057712873b497a38b70a3917f30cc38 +# macro_sequence + +# end +# complete + \ No newline at end of file diff --git a/bsp3/Designflow/ppr/sim/db/vga.lpc.html b/bsp3/Designflow/ppr/sim/db/vga.lpc.html new file mode 100644 index 0000000..fa19f6d --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga.lpc.html @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
vga_control_unit14000300000000
vga_driver_unit40006200000000
diff --git a/bsp3/Designflow/ppr/sim/db/vga.lpc.rdb b/bsp3/Designflow/ppr/sim/db/vga.lpc.rdb new file mode 100644 index 0000000000000000000000000000000000000000..beca4931e94fdbd973efe91fcd422feac0bbd99d GIT binary patch literal 456 zcmd;QU|?9w&B%}dgoZ$NSZYymW`3T6rJjL;Q)y;Sih`lBk%EDdzLBZEk%57wLa>*D zTWL;?0#xBkCZHxD2w{ZKDzotj^6u`n_9S0!F( zGJWE;GP6%kev_iUyV#EOwDYoh-HGXpna?LaSKpCv=-c-NA@lp=cdYi%?A-n#Vv^&f ziMEEn53VXP6I>Z3c26K--i?Nvs}^lOwPNL@1vb%BJUw3NS#f&JvW(#Pf63*Vhww@6 zcnkNda^1~+U#7mC|3q}!quM;P=zfu!jVlFq+=eP$5MFPq(ns^s=spOnM= zCbnbWqw>>XMzuaxzvcmb|Nnmlqfk;Z1CyG97}FyK@#Q}R+|}i;SA@%l$A|BqaK8TE zoD{Z|2@e=1^YC1Am?hoe==FE*o|w7LCg<1XB{QBr*RYCFlKs#mhaLkX3zZX>&&#H5 m%IvAM5N_rRVC5I!UbLcRhV=gf2f8OV3TkX->i`Ax|Nj6AEw*L= literal 0 HcmV?d00001 diff --git a/bsp3/Designflow/ppr/sim/db/vga.lpc.txt b/bsp3/Designflow/ppr/sim/db/vga.lpc.txt new file mode 100644 index 0000000..9f94739 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga.lpc.txt @@ -0,0 +1,8 @@ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; vga_control_unit ; 14 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; vga_driver_unit ; 4 ; 0 ; 0 ; 0 ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/bsp3/Designflow/ppr/sim/db/vga.map.bpm b/bsp3/Designflow/ppr/sim/db/vga.map.bpm new file mode 100644 index 0000000000000000000000000000000000000000..140de78bdd1b16806221093dc32f3278468f253e GIT binary patch literal 1080 zcmV-81jqXi000233jqLN0AK(y00011WpZV>fD*ylh0002K0{{R30001^000000000u1ONa40001Z z0qj`GiW5;3jRWF<8;6CuZ~ze$ySnCbDYS?pvNYaY<0pcI{1Ac+M z64&BFLBXYh3Sv7TI3VIwzFWEXbP?i0=}qE&@TjWO=bk&%y)Q}Ud7dv;DwSX6s#|L? zEcn()@;o40 zAoJmypEK}Av%Nsj>x_hTiD<8-U=6JCB#)tzB`6B0t_=5<;Xqts>wBQ})_-LK|hC?!l_%Txg2uCavAaVM3 zNj+!7)k8*HSZ!x38&@P#QJjHILvG8g9|UY2Jh zNCwS*i**qmeMlDJp#eii92iOG1n_j2IW}I^J&6wyOS6Zt62w6cXk;Lcct;KoL>Uoo zWsVD9A2}_!dMQSDR|muhGGCb!KxQX%LZnXZUz7*o$mtazbviE#4!p|&;z36mH-OGA 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vga_driver_unit/line_counter_sig_0_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_2_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_4_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_1_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_8_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_4_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_5_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_9_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_3_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_5_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_2_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_7_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_8_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_4_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_1_ + stratix_lcell + le + + + vga_control_unit/b_Z + stratix_lcell + le + + + vga_driver_unit/vsync_counter_1_ + stratix_lcell + le + + + vga_driver_unit/h_sync_Z + stratix_lcell + le + + + vga_driver_unit/vsync_state_2_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_6_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_0_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_0_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_6_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_4_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_6_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_2_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_1_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_5_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_9_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_7_ + stratix_lcell + le + + + vga_driver_unit/v_enable_sig_Z + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_3_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_7_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_0_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_5_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_3_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_3_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_6_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_6_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_2_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_0_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_3_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_2_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_7_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_4_ + stratix_lcell + le + + + vga_control_unit/g_Z + stratix_lcell + le + + + vga_driver_unit/hsync_counter_4_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_8_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_8_ + stratix_lcell + le + + + dly_counter_0_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_1_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_1_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_0_ + stratix_lcell + le + + + dly_counter_1_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_6_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_5_ + stratix_lcell + le + + + vga_driver_unit/v_sync_Z + stratix_lcell + le + + + vga_driver_unit/h_enable_sig_Z + stratix_lcell + le + + + vga_driver_unit/vsync_state_5_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_3_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_9_ + stratix_lcell + le + + + + + + + vga_driver:vga_driver_unit|vsync_counter_8 + + + vga_driver:vga_driver_unit|vsync_state_3 + + + vga_driver:vga_driver_unit|vsync_counter_9 + + + vga_driver:vga_driver_unit|vsync_state_2 + + + vga_driver:vga_driver_unit|vsync_state_1 + + + vga_driver:vga_driver_unit|vsync_state_0 + + + vga_driver:vga_driver_unit|vsync_state_6 + + + vga_driver:vga_driver_unit|vsync_state_5 + + + vga_driver:vga_driver_unit|vsync_state_4 + + + vga_driver:vga_driver_unit|line_counter_sig_8 + + + vga_driver:vga_driver_unit|line_counter_sig_6 + + + vga_driver:vga_driver_unit|line_counter_sig_7 + + + vga_driver:vga_driver_unit|line_counter_sig_0 + + + vga_driver:vga_driver_unit|line_counter_sig_1 + + + vga_driver:vga_driver_unit|line_counter_sig_4 + + + vga_driver:vga_driver_unit|line_counter_sig_5 + + + vga_driver:vga_driver_unit|line_counter_sig_2 + + + vga_driver:vga_driver_unit|line_counter_sig_3 + + + vga_driver:vga_driver_unit|v_enable_sig + + + vga_driver:vga_driver_unit|hsync_counter_8 + + + vga_driver:vga_driver_unit|hsync_counter_7 + + + vga_driver:vga_driver_unit|hsync_counter_9 + + + dly_counter[0] + + + vga_control:vga_control_unit|r + + + vga_driver:vga_driver_unit|v_sync + + + dly_counter[1] + + + vga_driver:vga_driver_unit|column_counter_sig_4 + + + vga_driver:vga_driver_unit|column_counter_sig_3 + + + vga_driver:vga_driver_unit|hsync_state_2 + + + vga_driver:vga_driver_unit|column_counter_sig_2 + + + vga_driver:vga_driver_unit|hsync_state_3 + + + vga_driver:vga_driver_unit|column_counter_sig_1 + + + vga_driver:vga_driver_unit|hsync_state_0 + + + vga_driver:vga_driver_unit|column_counter_sig_0 + + + vga_driver:vga_driver_unit|hsync_state_1 + + + vga_driver:vga_driver_unit|hsync_state_6 + + + vga_driver:vga_driver_unit|hsync_state_4 + + + vga_control:vga_control_unit|b + + + vga_driver:vga_driver_unit|hsync_state_5 + + + vga_control:vga_control_unit|g + + + vga_driver:vga_driver_unit|h_enable_sig + + + vga_driver:vga_driver_unit|column_counter_sig_9 + + + vga_driver:vga_driver_unit|column_counter_sig_8 + + + vga_driver:vga_driver_unit|column_counter_sig_7 + + + vga_driver:vga_driver_unit|hsync_counter_4 + + + vga_driver:vga_driver_unit|column_counter_sig_6 + + + vga_driver:vga_driver_unit|hsync_counter_3 + + + vga_driver:vga_driver_unit|column_counter_sig_5 + + + vga_driver:vga_driver_unit|hsync_counter_6 + + + vga_driver:vga_driver_unit|hsync_counter_5 + + + vga_driver:vga_driver_unit|hsync_counter_0 + + + vga_driver:vga_driver_unit|hsync_counter_2 + + + vga_driver:vga_driver_unit|hsync_counter_1 + + + vga_driver:vga_driver_unit|vsync_counter_0 + + + vga_driver:vga_driver_unit|h_sync + + + vga_driver:vga_driver_unit|vsync_counter_1 + + + vga_driver:vga_driver_unit|vsync_counter_2 + + + vga_driver:vga_driver_unit|vsync_counter_3 + + + vga_driver:vga_driver_unit|vsync_counter_4 + + + vga_driver:vga_driver_unit|vsync_counter_5 + + + vga_driver:vga_driver_unit|vsync_counter_6 + + + vga_driver:vga_driver_unit|vsync_counter_7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp3/Designflow/ppr/sim/db/vga.map.logdb b/bsp3/Designflow/ppr/sim/db/vga.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/bsp3/Designflow/ppr/sim/db/vga.map.qmsg b/bsp3/Designflow/ppr/sim/db/vga.map.qmsg new file mode 100644 index 0000000..4dcf2d7 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga.map.qmsg @@ -0,0 +1,9 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 16:59:47 2009 " "Info: Processing started: Thu Oct 29 16:59:47 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga -c vga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../syn/rev_1/vga.vqm 3 3 " "Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm" { { "Info" "ISGN_ENTITY_NAME" "1 vga_driver " "Info: Found entity 1: vga_driver" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 25 18 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 vga_control " "Info: Found entity 2: vga_control" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3149 19 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 vga " "Info: Found entity 3: vga" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3424 11 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "vga " "Info: Elaborating entity \"vga\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_driver vga_driver:vga_driver_unit " "Info: Elaborating entity \"vga_driver\" for hierarchy \"vga_driver:vga_driver_unit\"" { } { { "../../syn/rev_1/vga.vqm" "vga_driver_unit" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4836 3 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_control vga_control:vga_control_unit " "Info: Elaborating entity \"vga_control\" for hierarchy \"vga_control:vga_control_unit\"" { } { { "../../syn/rev_1/vga.vqm" "vga_control_unit" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4856 3 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "234 " "Info: Implemented 234 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "89 " "Info: Implemented 89 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "143 " "Info: Implemented 143 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 16:59:53 2009 " "Info: Processing ended: Thu Oct 29 16:59:53 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was 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a/bsp3/Designflow/sim/post/modelsim.ini b/bsp3/Designflow/sim/post/modelsim.ini new file mode 100644 index 0000000..0a48df5 --- /dev/null +++ b/bsp3/Designflow/sim/post/modelsim.ini @@ -0,0 +1,1305 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0-in compiler on the VHDL source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverageSub = 0 + +; Automatically exclude VHDL case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn off detection of FSMs having single bit current state variable. +; FsmSingle = 0 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/report/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect ; +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal +; to or greater than 1M are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Run the 0-in compiler on the Verilog source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a Verilog condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + + +; Turn on code coverage in VLOG `celldefine modules and modules included +; using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 1 to 4, with the following +; meanings (the default is 3): +; 1 -- Turn off all optimizations that affect coverage reports. +; 2 -- Allow optimizations that allow large performance improvements +; by invoking sequential processes only when the data changes. +; This may make major reductions in coverage counts. +; 3 -- In addition, allow optimizations that may change expressions or +; remove some statements. Allow constant propagation. Allow VHDL +; subprogram inlining and VHDL FF recognition. +; 4 -- In addition, allow optimizations that may remove major regions of +; code by changing assignments to built-ins or removing unused +; signals. Change Verilog gates to continuous assignments. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "merge_instances" option for +; the Covergroup Type. This is a compile time option which forces +; "merge_instances" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupMergeInstancesDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiOvm mtiUPF + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn off detection of FSMs having single bit current state variable. +; FsmSingle = 0 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SVFileExtensions = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2001 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "package_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a vopt condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; vopt automatic SDF +; If automatic design optimization is on, enables automatic compilation +; of SDF files. +; Default is on, uncomment to turn off. +; VoptAutoSDFCompile = 0 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Stop the simulator after a VHDL/Verilog immediate assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; VHDL assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %i - Instance pathname with process +; %O - Process name +; %K - Kind of object path is to return: Instance, Signal, Process or Unknown +; %P - Instance or Region path without leaf process +; %F - File +; %L - Line number of assertion or, if assertion is in a subprogram, line +; from which the call is made +; %% - Print '%' character +; If specific format for assertion level is defined, use its format. +; If specific format is not defined for assertion level: +; - and if failure occurs during elaboration, use MessageFormatBreakLine; +; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion +; level), use MessageFormatBreak; +; - otherwise, use MessageFormat. +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops do to a breakpoint or fatal error. +; Example w/function name: # Break in Process ctr at counter.vhd line 44 +; Example wo/function name: # Break at counter.vhd line 44 +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable System Verilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be indexed during +; simulation. If set to 0, the WLF file will not be indexed. +; The default is 1, indexed the WLF file. +; WLFIndex = 0 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 256M per open WLF file. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: these ini variables can be overriden by the vsim command +; line switch "-onfinish ". +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result at the end of simulation before shutdown. +; If this is enabled, the simstats result will be printed out before shutdown. +; The default is off. +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA concurrent assertion pass enable. +; For SVA, Default is on when the assertion has a pass action block, or +; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active. +; For PSL, Default is on only when vsim switch "-assertdebug" is used +; and the vopt "+acc=a" flag is active. +; AssertionPassEnable = 0 + +; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on. +; AssertionFailEnable = 0 + +; Set PSL/SVA concurrent assertion pass limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionPassLimit = 1 + +; Set PSL/SVA concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionFailLimit = 1 + +; Turn on/off PSL concurrent assertion pass log. Default is off. +; The flag does not affect SVA +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that +; are included for toggle coverage. This leads to a longer simulation time with bigger +; arrays covered with toggle coverage. Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable is 1 +; SVCovergroup63Compatibility = 1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0in runtime tool. +; Default value set to "". +; ZeroInOptions = "" + +; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog). +; Sv_Seed = 0 + +; Maximum size of dynamic arrays that are resized during randomize(). +; The default is 1000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 1000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; The default is 0 (no error). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures (SystemVerilog). +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; When SolveFailDebug is enabled, this value specifies the algorithm used to +; discover conflicts between constraints for randomize() failures. +; The default is "many". +; +; Valid schemes are: +; "many" = best for determining conflicts due to many related constraints +; "few" = best for determining conflicts due to few related constraints +; +; SolveFailDebugScheme = many + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum number of constraint subsets that will be tested for +; conflicts. +; The default is 0 (no limit). +; SolveFailDebugLimit = 0 + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum size of constraint subsets that will be tested for +; conflicts. +; The default value is 0 (no limit). +; SolveFailDebugMaxSet = 0 + +; Maximum size of the solution graph that may be generated during randomize(). +; This value can be used to force randomize() to abort if the memory +; requirements of the constraint scenario exceeds the specified limit. This +; value is specified in 1000s of nodes. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Maximum number of evaluations that may be performed on the solution graph +; generated during randomize(). This value can be used to force randomize() to +; abort if the complexity of the constraint scenario (in time) exceeds the +; specified limit. This value is specified in 10000s of evaluations. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of +; the constraint solver for others. +; The default value is "" (no options). +; +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints +; n = disable bit interleaving for all constraints +; r = reverse bit interleaving +; +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; Note: To achieve the same random sequences, solver optimizations and/or +; bug fixes introduced since the specified release may be disabled - +; yielding the performance / behavior of the prior release. +; Default value set to "" (random compatibility not required). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +; MvcHome = $MODEL_TECH/... + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; suppress = 3009,CNNODP,3043,TFMPC +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear in the transcript and recorded in the wlf +; file (messages that are recorded in the wlf file can be viewed +; in the MsgViewer). The other settings are to send messages +; only to the transcript or only to the wlf file. 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0000000000000000000000000000000000000000..711751054aa1f2ac2260bd6665e0034601d5eeba GIT binary patch literal 154 zcmd;QU|?9w&B%}dgoZ$NSZYymW`3T6rJjL;Q)y;Sih`lBk%EDdzLBZEk%57wLa>*D zTWL;?0#u;@P!9;?LnsC#C_M{GS1|ti|NnnIn+k~k|9=IeP;xQ@lbgabwnqu+=PSgo bC-|4|4;FN@c38y2qm?kJv60h@8LSilJ$@#@ literal 0 HcmV?d00001 diff --git a/bsp3/Designflow/ppr/sim/db/vga.syn_hier_info b/bsp3/Designflow/ppr/sim/db/vga.syn_hier_info new file mode 100644 index 0000000..e69de29 diff --git a/bsp3/Designflow/ppr/sim/db/vga.tan.qmsg b/bsp3/Designflow/ppr/sim/db/vga.tan.qmsg new file mode 100644 index 0000000..17cabd8 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga.tan.qmsg @@ -0,0 +1,11 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:00:51 2009 " "Info: Processing started: Thu Oct 29 17:00:51 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_pin " "Info: Assuming node \"clk_pin\" is an undefined clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "clk_pin" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_pin register vga_driver:vga_driver_unit\|vsync_counter_4 register vga_driver:vga_driver_unit\|vsync_state_3 191.53 MHz 5.221 ns Internal " "Info: Clock \"clk_pin\" has Internal fmax of 191.53 MHz between source register \"vga_driver:vga_driver_unit\|vsync_counter_4\" and destination register \"vga_driver:vga_driver_unit\|vsync_state_3\" (period= 5.221 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.035 ns + Longest register register " "Info: + Longest register to register delay is 5.035 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_driver:vga_driver_unit\|vsync_counter_4 1 REG LC_X37_Y35_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X37_Y35_N4; Fanout = 6; REG Node = 'vga_driver:vga_driver_unit\|vsync_counter_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 134 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.459 ns) 1.492 ns vga_driver:vga_driver_unit\|un12_vsync_counter_7 2 COMB LC_X38_Y35_N7 3 " "Info: 2: + IC(1.033 ns) + CELL(0.459 ns) = 1.492 ns; Loc. = LC_X38_Y35_N7; Fanout = 3; COMB Node = 'vga_driver:vga_driver_unit\|un12_vsync_counter_7'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.492 ns" { vga_driver:vga_driver_unit|vsync_counter_4 vga_driver:vga_driver_unit|un12_vsync_counter_7 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 243 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.087 ns) 2.433 ns vga_driver:vga_driver_unit\|un14_vsync_counter_8 3 COMB LC_X36_Y35_N1 4 " "Info: 3: + IC(0.854 ns) + CELL(0.087 ns) = 2.433 ns; Loc. = LC_X36_Y35_N1; Fanout = 4; COMB Node = 'vga_driver:vga_driver_unit\|un14_vsync_counter_8'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.941 ns" { vga_driver:vga_driver_unit|un12_vsync_counter_7 vga_driver:vga_driver_unit|un14_vsync_counter_8 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 251 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.087 ns) 3.085 ns vga_driver:vga_driver_unit\|vsync_state_next_1_sqmuxa_3 4 COMB LC_X35_Y35_N6 1 " "Info: 4: + IC(0.565 ns) + CELL(0.087 ns) = 3.085 ns; Loc. = LC_X35_Y35_N6; Fanout = 1; COMB Node = 'vga_driver:vga_driver_unit\|vsync_state_next_1_sqmuxa_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.652 ns" { vga_driver:vga_driver_unit|un14_vsync_counter_8 vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 261 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.087 ns) 3.736 ns vga_driver:vga_driver_unit\|vsync_state_next_2_sqmuxa 5 COMB LC_X36_Y35_N7 5 " "Info: 5: + IC(0.564 ns) + CELL(0.087 ns) = 3.736 ns; Loc. = LC_X36_Y35_N7; Fanout = 5; COMB Node = 'vga_driver:vga_driver_unit\|vsync_state_next_2_sqmuxa'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.651 ns" { vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 242 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.726 ns) 5.035 ns vga_driver:vga_driver_unit\|vsync_state_3 6 REG LC_X35_Y35_N6 5 " "Info: 6: + IC(0.573 ns) + CELL(0.726 ns) = 5.035 ns; Loc. = LC_X35_Y35_N6; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.299 ns" { vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.446 ns ( 28.72 % ) " "Info: Total cell delay = 1.446 ns ( 28.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.589 ns ( 71.28 % ) " "Info: Total interconnect delay = 3.589 ns ( 71.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.035 ns" { vga_driver:vga_driver_unit|vsync_counter_4 vga_driver:vga_driver_unit|un12_vsync_counter_7 vga_driver:vga_driver_unit|un14_vsync_counter_8 vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.035 ns" { vga_driver:vga_driver_unit|vsync_counter_4 {} vga_driver:vga_driver_unit|un12_vsync_counter_7 {} vga_driver:vga_driver_unit|un14_vsync_counter_8 {} vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 {} vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 1.033ns 0.854ns 0.565ns 0.564ns 0.573ns } { 0.000ns 0.459ns 0.087ns 0.087ns 0.087ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.191 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_pin\" to destination register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.560 ns) 3.191 ns vga_driver:vga_driver_unit\|vsync_state_3 2 REG LC_X35_Y35_N6 5 " "Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X35_Y35_N6; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.323 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.75 % ) " "Info: Total cell delay = 1.428 ns ( 44.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.763 ns ( 55.25 % ) " "Info: Total interconnect delay = 1.763 ns ( 55.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.191 ns - Longest register " "Info: - Longest clock path from clock \"clk_pin\" to source register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.560 ns) 3.191 ns vga_driver:vga_driver_unit\|vsync_counter_4 2 REG LC_X37_Y35_N4 6 " "Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X37_Y35_N4; Fanout = 6; REG Node = 'vga_driver:vga_driver_unit\|vsync_counter_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.323 ns" { clk_pin vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 134 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.75 % ) " "Info: Total cell delay = 1.428 ns ( 44.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.763 ns ( 55.25 % ) " "Info: Total interconnect delay = 1.763 ns ( 55.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_counter_4 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_counter_4 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 134 25 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.035 ns" { vga_driver:vga_driver_unit|vsync_counter_4 vga_driver:vga_driver_unit|un12_vsync_counter_7 vga_driver:vga_driver_unit|un14_vsync_counter_8 vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.035 ns" { vga_driver:vga_driver_unit|vsync_counter_4 {} vga_driver:vga_driver_unit|un12_vsync_counter_7 {} vga_driver:vga_driver_unit|un14_vsync_counter_8 {} vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 {} vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 1.033ns 0.854ns 0.565ns 0.564ns 0.573ns } { 0.000ns 0.459ns 0.087ns 0.087ns 0.087ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_counter_4 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1} +{ "Info" "ITDB_TSU_RESULT" "vga_driver:vga_driver_unit\|hsync_state_3 reset_pin clk_pin 6.710 ns register " "Info: tsu for register \"vga_driver:vga_driver_unit\|hsync_state_3\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is 6.710 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.916 ns + Longest pin register " "Info: + Longest pin to register delay is 9.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns reset_pin 1 PIN PIN_K2 10 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3459 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.777 ns) + CELL(0.459 ns) 6.531 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X35_Y35_N2 32 " "Info: 2: + IC(4.777 ns) + CELL(0.459 ns) = 6.531 ns; Loc. = LC_X35_Y35_N2; Fanout = 32; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.236 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.669 ns) + CELL(0.459 ns) 8.659 ns vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0 3 COMB LC_X29_Y33_N4 6 " "Info: 3: + IC(1.669 ns) + CELL(0.459 ns) = 8.659 ns; Loc. = LC_X29_Y33_N4; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.128 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 252 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.531 ns) + CELL(0.726 ns) 9.916 ns vga_driver:vga_driver_unit\|hsync_state_3 4 REG LC_X28_Y33_N3 5 " "Info: 4: + IC(0.531 ns) + CELL(0.726 ns) = 9.916 ns; Loc. = LC_X28_Y33_N3; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.257 ns" { vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 117 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.939 ns ( 29.64 % ) " "Info: Total cell delay = 2.939 ns ( 29.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.977 ns ( 70.36 % ) " "Info: Total interconnect delay = 6.977 ns ( 70.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.916 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "9.916 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_3 {} } { 0.000ns 0.000ns 4.777ns 1.669ns 0.531ns } { 0.000ns 1.295ns 0.459ns 0.459ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 117 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.216 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_pin\" to destination register is 3.216 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.788 ns) + CELL(0.560 ns) 3.216 ns vga_driver:vga_driver_unit\|hsync_state_3 2 REG LC_X28_Y33_N3 5 " "Info: 2: + IC(1.788 ns) + CELL(0.560 ns) = 3.216 ns; Loc. = LC_X28_Y33_N3; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.348 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 117 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.40 % ) " "Info: Total cell delay = 1.428 ns ( 44.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.788 ns ( 55.60 % ) " "Info: Total interconnect delay = 1.788 ns ( 55.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.216 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.216 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_3 {} } { 0.000ns 0.000ns 1.788ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.916 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "9.916 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_3 {} } { 0.000ns 0.000ns 4.777ns 1.669ns 0.531ns } { 0.000ns 1.295ns 0.459ns 0.459ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.216 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.216 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_3 {} } { 0.000ns 0.000ns 1.788ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TCO_RESULT" "clk_pin seven_seg_pin\[1\] dly_counter\[0\] 10.979 ns register " "Info: tco from clock \"clk_pin\" to destination pin \"seven_seg_pin\[1\]\" through register \"dly_counter\[0\]\" is 10.979 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.191 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to source register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.560 ns) 3.191 ns dly_counter\[0\] 2 REG LC_X35_Y35_N5 10 " "Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X35_Y35_N5; Fanout = 10; REG Node = 'dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.323 ns" { clk_pin dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.75 % ) " "Info: Total cell delay = 1.428 ns ( 44.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.763 ns ( 55.25 % ) " "Info: Total interconnect delay = 1.763 ns ( 55.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} dly_counter[0] {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.612 ns + Longest register pin " "Info: + Longest register to pin delay is 7.612 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dly_counter\[0\] 1 REG LC_X35_Y35_N5 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y35_N5; Fanout = 10; REG Node = 'dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.476 ns) + CELL(0.332 ns) 0.808 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X35_Y35_N2 32 " "Info: 2: + IC(0.476 ns) + CELL(0.332 ns) = 0.808 ns; Loc. = LC_X35_Y35_N2; Fanout = 32; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.808 ns" { dly_counter[0] vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.309 ns) + CELL(2.495 ns) 7.612 ns seven_seg_pin\[1\] 3 PIN PIN_M9 0 " "Info: 3: + IC(4.309 ns) + CELL(2.495 ns) = 7.612 ns; Loc. = PIN_M9; Fanout = 0; PIN Node = 'seven_seg_pin\[1\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.804 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3470 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.827 ns ( 37.14 % ) " "Info: Total cell delay = 2.827 ns ( 37.14 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.785 ns ( 62.86 % ) " "Info: Total interconnect delay = 4.785 ns ( 62.86 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.612 ns" { dly_counter[0] vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.612 ns" { dly_counter[0] {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[1] {} } { 0.000ns 0.476ns 4.309ns } { 0.000ns 0.332ns 2.495ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} dly_counter[0] {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.612 ns" { dly_counter[0] vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.612 ns" { dly_counter[0] {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[1] {} } { 0.000ns 0.476ns 4.309ns } { 0.000ns 0.332ns 2.495ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TPD_RESULT" "reset_pin seven_seg_pin\[1\] 13.335 ns Longest " "Info: Longest tpd from source pin \"reset_pin\" to destination pin \"seven_seg_pin\[1\]\" is 13.335 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns reset_pin 1 PIN PIN_K2 10 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3459 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.777 ns) + CELL(0.459 ns) 6.531 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X35_Y35_N2 32 " "Info: 2: + IC(4.777 ns) + CELL(0.459 ns) = 6.531 ns; Loc. = LC_X35_Y35_N2; Fanout = 32; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.236 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.309 ns) + CELL(2.495 ns) 13.335 ns seven_seg_pin\[1\] 3 PIN PIN_M9 0 " "Info: 3: + IC(4.309 ns) + CELL(2.495 ns) = 13.335 ns; Loc. = PIN_M9; Fanout = 0; PIN Node = 'seven_seg_pin\[1\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.804 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3470 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.249 ns ( 31.86 % ) " "Info: Total cell delay = 4.249 ns ( 31.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.086 ns ( 68.14 % ) " "Info: Total interconnect delay = 9.086 ns ( 68.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "13.335 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "13.335 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[1] {} } { 0.000ns 0.000ns 4.777ns 4.309ns } { 0.000ns 1.295ns 0.459ns 2.495ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_TH_RESULT" "vga_driver:vga_driver_unit\|h_sync reset_pin clk_pin -3.134 ns register " "Info: th for register \"vga_driver:vga_driver_unit\|h_sync\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is -3.134 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.191 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to destination register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.560 ns) 3.191 ns vga_driver:vga_driver_unit\|h_sync 2 REG LC_X34_Y35_N2 3 " "Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X34_Y35_N2; Fanout = 3; REG Node = 'vga_driver:vga_driver_unit\|h_sync'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.323 ns" { clk_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 153 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.75 % ) " "Info: Total cell delay = 1.428 ns ( 44.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.763 ns ( 55.25 % ) " "Info: Total interconnect delay = 1.763 ns ( 55.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|h_sync {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 153 16 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.425 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.425 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns reset_pin 1 PIN PIN_K2 10 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3459 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.641 ns) + CELL(0.489 ns) 6.425 ns vga_driver:vga_driver_unit\|h_sync 2 REG LC_X34_Y35_N2 3 " "Info: 2: + IC(4.641 ns) + CELL(0.489 ns) = 6.425 ns; Loc. = LC_X34_Y35_N2; Fanout = 3; REG Node = 'vga_driver:vga_driver_unit\|h_sync'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.130 ns" { reset_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 153 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns ( 27.77 % ) " "Info: Total cell delay = 1.784 ns ( 27.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.641 ns ( 72.23 % ) " "Info: Total interconnect delay = 4.641 ns ( 72.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.425 ns" { reset_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.425 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|h_sync {} } { 0.000ns 0.000ns 4.641ns } { 0.000ns 1.295ns 0.489ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|h_sync {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.425 ns" { reset_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.425 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|h_sync {} } { 0.000ns 0.000ns 4.641ns } { 0.000ns 1.295ns 0.489ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Peak virtual memory: 140 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 17:00:52 2009 " "Info: Processing ended: Thu Oct 29 17:00:52 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/bsp3/Designflow/ppr/sim/db/vga.tis_db_list.ddb b/bsp3/Designflow/ppr/sim/db/vga.tis_db_list.ddb new file mode 100644 index 0000000000000000000000000000000000000000..7a45114581bb8ff3e53543d803e264030a96c865 GIT binary patch literal 178 zcmd;QU|?9w&B%}dgoZ$NSZYymW`3T6rJjL;Q)y;Sih`lBk%EDdzLBZEk%57wLa>*D zTWL;?0#utZ?_Pd=!4HP(3lh#h5D4Etp~BzZyuNmu?tKR>Nr{RBD$LBnQ`o@T0n5=c AP5=M^ literal 0 HcmV?d00001 diff --git a/bsp3/Designflow/ppr/sim/db/vga.tmw_info b/bsp3/Designflow/ppr/sim/db/vga.tmw_info new file mode 100644 index 0000000..b4d9e79 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga.tmw_info @@ -0,0 +1,7 @@ +start_full_compilation:s:00:01:14 +start_analysis_synthesis:s:00:00:10-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:34-start_full_compilation +start_assembler:s:00:00:22-start_full_compilation +start_timing_analyzer:s:00:00:03-start_full_compilation +start_eda_netlist_writer:s:00:00:05-start_full_compilation diff --git a/bsp3/Designflow/ppr/sim/db/vga_global_asgn_op.abo b/bsp3/Designflow/ppr/sim/db/vga_global_asgn_op.abo new file mode 100644 index 0000000..d15cf42 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/db/vga_global_asgn_op.abo @@ -0,0 +1,11949 @@ +Version: + 9.0 Build 132 02/25/2009 SJ Full Version + +Chip Device Options: + Device Name: EP1S25F672C6 + Device JTAG code: ffffffff + Programming_mode: Passive Serial + NWS_NRS_NCS: UNRESERVED + RDYNBUSY: UNRESERVED + DATA 7 to 1: UNRESERVED + nCEO: UNRESERVED + UNUSED PINS: RESERVED_GND + Default IO Standard:: 3.3-V LVTTL + User Start-up Clock: 0 + Auto Restart on Error: 1 + Release Clears Before Tristates: 0 + Device Clear: 0 + Test And Scan: 0 + Device OE: 0 + Enable Lock Output: 0 + Enable Init Done: 0 + Enable JTAG BST: 0 + Enable Vref A: 0 + Enable Vref B: 0 + + + +**************************** +******Individual Atoms****** +**************************** + +- ATOM ------------------------ + ATOM_NAME: r0_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 0 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] r0_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: r1_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 1 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] r1_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: r2_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 2 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] r2_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: g0_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 3 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|g LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] g0_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: g1_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 4 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|g LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] g1_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: g2_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 5 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|g LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] g2_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: b0_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 6 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] b0_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: b1_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 7 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] b1_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: hsync_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 8 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] hsync_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vsync_pin_out -- UNIQUE + Atom Hier Name: + Atom Id: 9 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] vsync_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_tri_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 10 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 11 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 12 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_tri_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 13 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_tri_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 14 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_tri_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 15 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_tri_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 16 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 17 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 18 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_out_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 19 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[9] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_out_10_ -- UNIQUE + Atom Hier Name: + Atom Id: 20 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[10] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_out_11_ -- UNIQUE + Atom Hier Name: + Atom Id: 21 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[11] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_out_12_ -- UNIQUE + Atom Hier Name: + Atom Id: 22 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[12] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: seven_seg_pin_tri_13_ -- UNIQUE + Atom Hier Name: + Atom Id: 23 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] seven_seg_pin[13] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_out -- UNIQUE + Atom Hier Name: + Atom Id: 24 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_out -- UNIQUE + Atom Hier Name: + Atom Id: 25 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 26 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 27 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 28 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 29 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 30 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 31 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 32 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 33 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 34 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_column_counter_out_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 35 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_column_counter[9] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_line_counter_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 36 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_line_counter_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 37 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_line_counter_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 38 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_line_counter_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 39 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_line_counter_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 40 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_line_counter_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 41 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_line_counter_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 42 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_line_counter_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 43 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_line_counter_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 44 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_line_counter[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_set_column_counter_out -- UNIQUE + Atom Hier Name: + Atom Id: 45 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_set_column_counter LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_set_line_counter_out -- UNIQUE + Atom Hier Name: + Atom Id: 46 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_set_line_counter LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 47 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 48 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 49 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 50 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 51 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 52 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 53 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 54 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 55 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_counter_out_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 56 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_counter[9] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 57 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 58 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 59 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 60 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 61 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 62 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 63 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 64 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[7] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 65 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[8] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_counter_out_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 66 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_counter[9] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_set_hsync_counter_out -- UNIQUE + Atom Hier Name: + Atom Id: 67 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_set_hsync_counter LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_set_vsync_counter_out -- UNIQUE + Atom Hier Name: + Atom Id: 68 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_set_vsync_counter LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_h_enable_out -- UNIQUE + Atom Hier Name: + Atom Id: 69 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_h_enable LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_v_enable_out -- UNIQUE + Atom Hier Name: + Atom Id: 70 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_v_enable LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_r_out -- UNIQUE + Atom Hier Name: + Atom Id: 71 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_r LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_g_out -- UNIQUE + Atom Hier Name: + Atom Id: 72 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|g LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_g LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_b_out -- UNIQUE + Atom Hier Name: + Atom Id: 73 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_b LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_state_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 74 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_state_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 75 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_state_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 76 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_state_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 77 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_state_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 78 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_state_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 79 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_hsync_state_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 80 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_hsync_state[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_state_out_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 81 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[6] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_state_out_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 82 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[5] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_state_out_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 83 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[4] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_state_out_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 84 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[3] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_state_out_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 85 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[2] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_state_out_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 86 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[1] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_vsync_state_out_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 87 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_vsync_state[0] LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: d_state_clk_out -- UNIQUE + Atom Hier Name: + Atom Id: 88 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: [DATAIN] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] d_state_clk LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = output + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|r_Z -- UNIQUE + Atom Hier Name: + Atom Id: 89 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglt6_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_control:vga_control_unit|b_next_i_o3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_control:vga_control_unit|N_4_i_0_g0_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_control:vga_control_unit|r LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 1b00 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|g_Z -- UNIQUE + Atom Hier Name: + Atom Id: 90 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_control:vga_control_unit|r_next_i_o7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_control:vga_control_unit|N_23_i_0_g0_a LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_control:vga_control_unit|g LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0400 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|b_Z -- UNIQUE + Atom Hier Name: + Atom Id: 91 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_control:vga_control_unit|b_next_i_o3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_control:vga_control_unit|b_next_i_a7_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_control:vga_control_unit|N_6_i_0_g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_control:vga_control_unit|b LIT INDEX 0 FANOUTS 3 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0700 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|h_sync_Z -- UNIQUE + Atom Hier Name: + Atom Id: 92 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|h_sync LIT INDEX 0 FANOUTS 3 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff7f + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|v_sync_Z -- UNIQUE + Atom Hier Name: + Atom Id: 93 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|v_sync LIT INDEX 0 FANOUTS 3 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff7f + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 94 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 FANOUTS 32 + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7f7f + output_mode = reg_and_comb + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 95 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7777 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 96 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 97 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 98 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 99 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 100 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 101 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 102 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 FANOUTS 9 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 103 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 FANOUTS 10 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 104 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 105 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bbbb + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 106 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 107 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 108 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 109 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 110 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 111 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 112 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 113 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 FANOUTS 3 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = dddd + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 114 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 115 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 116 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[0] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 55aa + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 117 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 118 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[2] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 119 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[3] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 120 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 FANOUTS 7 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[4] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 121 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[5] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 122 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 FANOUTS 7 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[6] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 123 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 FANOUTS 7 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[7] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 124 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 FANOUTS 6 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[8] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 125 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 FANOUTS 6 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 126 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 FANOUTS 9 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[0] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 6688 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 127 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 128 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[2] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 129 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[3] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 130 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[4] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 131 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[5] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 132 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[6] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 133 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[7] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5f + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 134 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 FANOUTS 5 REGED POS + 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[8] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a50a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 135 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 9: [ENA] DISCONNECTED + 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 FANOUTS 9 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a5a + cin_used = true + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|d_set_hsync_counter_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 136 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 FANOUTS 5 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|d_set_vsync_counter_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 137 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|h_enable_sig_Z -- UNIQUE + Atom Hier Name: + Atom Id: 138 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 FANOUTS 2 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|v_enable_sig_Z -- UNIQUE + Atom Hier Name: + Atom Id: 139 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 FANOUTS 2 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 140 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: [DATAD] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff00 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 141 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 142 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 143 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = aaaa + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 144 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8888 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 145 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8888 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 146 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 147 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 2000 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 148 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = aaaa + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 149 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 8: NO ITERM + 9: [ENA] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 FANOUTS 4 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = on + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 150 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 FANOUTS 5 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 30ba + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: clk_pin_in -- UNIQUE + Atom Hier Name: + Atom Id: 151 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: NO ITERM + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [PADIO] DISCONNECTED + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] clk_pin LIT INDEX 0 FANOUTS 63 + 1: NONE + 2: NONE + 3: [PADIO] clk_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = input + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 -- UNIQUE + Atom Hier Name: + Atom Id: 152 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_column_counter_siglt6_3 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7777 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|b_next_i_o3_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 153 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_control:vga_control_unit|b_next_i_o3_0 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff80 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|N_4_i_0_g0_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 154 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_control:vga_control_unit|g_next_i_o3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_control:vga_control_unit|r_next_i_o7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_control:vga_control_unit|N_4_i_0_g0_1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 00ec + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|r_next_i_o7_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 155 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_control:vga_control_unit|r_next_i_o7 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = bfbf + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|N_23_i_0_g0_a_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 156 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_control:vga_control_unit|g_next_i_o3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un10_column_counter_siglt6_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_control:vga_control_unit|N_23_i_0_g0_a LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 6c6e + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|b_next_i_a7_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 157 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_control:vga_control_unit|g_next_i_o3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_control:vga_control_unit|b_next_i_a7_1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0001 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|N_6_i_0_g0_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 158 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un10_column_counter_siglt6_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_control:vga_control_unit|r_next_i_o7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_control:vga_control_unit|N_6_i_0_g0_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 00ef + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: reset_pin_in -- UNIQUE + Atom Hier Name: + Atom Id: 159 + Atom Type: stratix_io (WYSIWYG) + + INPUTS (Driven By): + 0: NO ITERM + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [PADIO] DISCONNECTED + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] reset_pin LIT INDEX 0 FANOUTS 9 + 1: NONE + 2: NONE + 3: [PADIO] reset_pin LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = input + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + +- ATOM ------------------------ + ATOM_NAME: dly_counter_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 160 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] dly_counter[0] LIT INDEX 0 FANOUTS 9 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = a2a2 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: dly_counter_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 161 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: [ENA] DISCONNECTED + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: [REGOUT] dly_counter[1] LIT INDEX 0 FANOUTS 9 REGED POS + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = a8a8 + output_mode = reg_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 162 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un1_hsync_state_3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ccd8 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 163 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un1_vsync_state_2_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ccd8 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 -- UNIQUE + Atom Hier Name: + Atom Id: 164 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un10_column_counter_siglt6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 1f0f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 165 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 166 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[1] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 6688 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 167 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[2] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[2] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 168 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[3] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[3] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 6c7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 169 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[4] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[4] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a508 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 170 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[5] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[5] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = c608 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 171 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[6] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[6] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 172 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[7] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[7] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 6c7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 173 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[8] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a5a5 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 174 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[9] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = c6c6 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 175 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[1] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 6688 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 -- UNIQUE + Atom Hier Name: + Atom Id: 176 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un10_line_counter_siglto5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 FANOUTS 9 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff7f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 177 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 LIT INDEX 0 FANOUTS 9 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_2_ -- UNIQUE + Atom Hier Name: + Atom Id: 178 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_a_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[2] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[2] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_3_ -- UNIQUE + Atom Hier Name: + Atom Id: 179 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[3] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 6c7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_4_ -- UNIQUE + Atom Hier Name: + Atom Id: 180 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[4] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[4] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a508 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_5_ -- UNIQUE + Atom Hier Name: + Atom Id: 181 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[5] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[5] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = c608 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_6_ -- UNIQUE + Atom Hier Name: + Atom Id: 182 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[6] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[6] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 5a7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_7_ -- UNIQUE + Atom Hier Name: + Atom Id: 183 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[7] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[7] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = 6c7f + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_8_ -- UNIQUE + Atom Hier Name: + Atom Id: 184 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[8] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = a5a5 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_9_ -- UNIQUE + Atom Hier Name: + Atom Id: 185 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[9] LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = cin + lut_mask = c6c6 + cin_used = true + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 -- UNIQUE + Atom Hier Name: + Atom Id: 186 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0808 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 -- UNIQUE + Atom Hier Name: + Atom Id: 187 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 FANOUTS 4 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0101 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 188 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0008 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 189 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 FANOUTS 6 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = f0f1 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 -- UNIQUE + Atom Hier Name: + Atom Id: 190 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0001 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 -- UNIQUE + Atom Hier Name: + Atom Id: 191 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un13_vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 192 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|G_2 -- UNIQUE + Atom Hier Name: + Atom Id: 193 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un9_hsync_counterlt9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|G_2_i LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0f1f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 -- UNIQUE + Atom Hier Name: + Atom Id: 194 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un9_hsync_counterlt9_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un9_hsync_counterlt9 LIT INDEX 0 FANOUTS 11 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = f7ff + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 195 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|G_16 -- UNIQUE + Atom Hier Name: + Atom Id: 196 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un9_vsync_counterlt9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|G_16_i LIT INDEX 0 FANOUTS 10 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0f1f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 -- UNIQUE + Atom Hier Name: + Atom Id: 197 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un9_vsync_counterlt9_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un9_vsync_counterlt9_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un9_vsync_counterlt9 LIT INDEX 0 FANOUTS 11 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = fff7 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 198 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = f1f1 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 199 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = f1f1 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 200 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0101 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 -- UNIQUE + Atom Hier Name: + Atom Id: 201 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter -- UNIQUE + Atom Hier Name: + Atom Id: 202 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un12_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un12_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter -- UNIQUE + Atom Hier Name: + Atom Id: 203 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un13_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 1000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 204 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 FANOUTS 5 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = aaab + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 -- UNIQUE + Atom Hier Name: + Atom Id: 205 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 FANOUTS 4 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8888 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 206 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_control:vga_control_unit|g_next_i_o3_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 207 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_control:vga_control_unit|g_next_i_o3 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 -- UNIQUE + Atom Hier Name: + Atom Id: 208 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_column_counter_siglt6_1 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7f7f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_hsync_state_3_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 209 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_hsync_state_3_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_vsync_state_2_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 210 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_vsync_state_2_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = eeee + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 -- UNIQUE + Atom Hier Name: + Atom Id: 211 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un10_column_counter_siglt6_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un10_column_counter_siglt6_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_column_counter_siglt6 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = fff7 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_0_ -- UNIQUE + Atom Hier Name: + Atom Id: 212 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_0_~COMBOUT LIT INDEX 0 FANOUTS 0 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[0] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff88 + output_mode = none + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 -- UNIQUE + Atom Hier Name: + Atom Id: 213 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un10_line_counter_siglt4_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_line_counter_siglto5 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0f07 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_a_1_ -- UNIQUE + Atom Hier Name: + Atom Id: 214 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT LIT INDEX 0 FANOUTS 0 + 1: NONE + 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_a_cout[1] LIT INDEX 0 FANOUTS 1 + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = arithmetic + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff88 + output_mode = none + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 215 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 2aaa + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 216 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 2aaa + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 217 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0ace + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 218 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un13_vsync_counter_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0001 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 -- UNIQUE + Atom Hier Name: + Atom Id: 219 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un9_hsync_counterlt9_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7fff + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 -- UNIQUE + Atom Hier Name: + Atom Id: 220 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 8000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 -- UNIQUE + Atom Hier Name: + Atom Id: 221 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un9_vsync_counterlt9_5 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7fff + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 -- UNIQUE + Atom Hier Name: + Atom Id: 222 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un9_vsync_counterlt9_6 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7fff + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 223 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un12_hsync_counter_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0020 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 -- UNIQUE + Atom Hier Name: + Atom Id: 224 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un12_hsync_counter_4 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0010 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 -- UNIQUE + Atom Hier Name: + Atom Id: 225 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un13_hsync_counter_2 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0080 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 226 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = d0f0 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 227 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 70f0 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 228 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = ff2a + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 -- UNIQUE + Atom Hier Name: + Atom Id: 229 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 FANOUTS 3 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0001 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 -- UNIQUE + Atom Hier Name: + Atom Id: 230 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un15_vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 FANOUTS 2 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 1010 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 -- UNIQUE + Atom Hier Name: + Atom Id: 231 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un10_line_counter_siglt4_2 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 7f7f + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ -- UNIQUE + Atom Hier Name: + Atom Id: 232 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 2a2a + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 -- UNIQUE + Atom Hier Name: + Atom Id: 233 + Atom Type: stratix_lcell (WYSIWYG) + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] vga_driver:vga_driver_unit|un15_vsync_counter_3 LIT INDEX 0 FANOUTS 1 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0008 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: ~STRATIX_FITTER_CREATED_GND~I -- NON-UNIQUE + Atom Hier Name: + Atom Id: 234 + Atom Type: stratix_lcell + + Assembler Lutmask : I very much like HEX numbers. + power up = low + + INPUTS (Driven By): + 0: NO ITERM + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + 11: NO ITERM + 12: NO ITERM + 13: NO ITERM + 14: NO ITERM + OUTPUTS (Int. Connections): + 0: [COMBOUT] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 FANOUTS 6 + 1: NONE + 2: NONE + 3: NONE + 4: NONE + + PARAMETER LIST: + operation_mode = normal + synch_mode = off + register_cascade_mode = off + sum_lutc_input = datac + lut_mask = 0000 + output_mode = comb_only + + +- ATOM ------------------------ + ATOM_NAME: ~DATA0~ -- NON-UNIQUE + Atom Hier Name: + Atom Id: 235 + Atom Type: stratix_io + + INPUTS (Driven By): + 0: NO ITERM + 1: NO ITERM + 2: NO ITERM + 3: NO ITERM + 4: NO ITERM + 5: NO ITERM + 6: NO ITERM + 7: NO ITERM + 8: NO ITERM + 9: NO ITERM + 10: NO ITERM + OUTPUTS (Int. Connections): + 0: NONE + 1: NONE + 2: NONE + 3: [PADIO] ~DATA0~ LIT INDEX 0 FANOUTS 0 + 4: NONE + 5: NONE + 6: NONE + 7: NONE + + PARAMETER LIST: + operation_mode = input + ddio_mode = none + input_register_mode = none + output_register_mode = none + oe_register_mode = none + input_async_reset = none + output_async_reset = none + oe_async_reset = none + input_sync_reset = none + output_sync_reset = none + oe_sync_reset = none + input_power_up = low + output_power_up = low + oe_power_up = low + + DELAY CHAINS: + PAD TO CORE 0: OFF + PAD TO CORE 1: OFF + TCO CHAIN: OFF + TCOE CHAIN: OFF + PAD TO INPUT REG: OFF + CORE TO OUTPUT REG: OFF + ZBT: OFF + CE TO INPUT_REG: OFF + CE TO OUTPUT_REG: OFF + CE TO OE_REG: OFF + + IO STANDARD: 3.3-V LVTTL + CURRENT STRENGTH: DEFAULT + PCI DIODE: OFF + TERMINATION: OFF + DQS INFORMATION: + Not a DQS atom. + DQS system clock: False + PLL COMPENSATED: False + diff --git a/bsp3/Designflow/ppr/sim/incremental_db/README b/bsp3/Designflow/ppr/sim/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/bsp3/Designflow/ppr/sim/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.cmp.atm b/bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.cmp.atm new file mode 100644 index 0000000000000000000000000000000000000000..f6de86d672d59bbcafa8d67d3464bcf4ce884bf6 GIT binary patch literal 37849 zcmZ^~1yEc~)FvF^a@1`*d9@&>-IZ`SHj&{%-3`AdztPwET*#+1dILqn_vH*wU+mpN_Ig{2z}xHZtCgp8h356whspYEexC>4 zCntBlr)$uD_}jkS?bXfNc-YF)OR)mU+3TmL``>-zPfN@OcIz6<>*Hn39$%iWj(@&X zFJzm$XZyCkb=eCT^r?U_<^=3d&&900~YHgsZt`=3t3)UuwSbh7JvC%`YVTP=|)4_56QiL{nszwhuxE>C+6(6+0Li^ODHw0 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vga_driver_unit/vsync_counter_3_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_5_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_2_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_7_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_8_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_4_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_1_ + stratix_lcell + le + + + vga_control_unit/b_Z + stratix_lcell + le + + + vga_driver_unit/vsync_counter_1_ + stratix_lcell + le + + + vga_driver_unit/h_sync_Z + stratix_lcell + le + + + vga_driver_unit/vsync_state_2_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_6_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_0_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_0_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_6_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_4_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_6_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_2_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_1_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_5_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_9_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_7_ + stratix_lcell + le + + + vga_driver_unit/v_enable_sig_Z + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_3_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_7_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_0_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_5_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_3_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_3_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_6_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_6_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_2_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_0_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_3_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_2_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_7_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_4_ + stratix_lcell + le + + + vga_control_unit/g_Z + stratix_lcell + le + + + vga_driver_unit/hsync_counter_4_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_8_ + stratix_lcell + le + + + vga_driver_unit/vsync_counter_8_ + stratix_lcell + le + + + dly_counter_0_ + stratix_lcell + le + + + vga_driver_unit/vsync_state_1_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_1_ + stratix_lcell + le + + + vga_driver_unit/hsync_state_0_ + stratix_lcell + le + + + dly_counter_1_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_6_ + stratix_lcell + le + + + vga_driver_unit/line_counter_sig_5_ + stratix_lcell + le + + + vga_driver_unit/v_sync_Z + stratix_lcell + le + + + vga_driver_unit/h_enable_sig_Z + stratix_lcell + le + + + vga_driver_unit/vsync_state_5_ + stratix_lcell + le + + + vga_driver_unit/hsync_counter_3_ + stratix_lcell + le + + + vga_driver_unit/column_counter_sig_9_ + stratix_lcell + le + + + + + + + vga_driver:vga_driver_unit|vsync_counter_8 + + + vga_driver:vga_driver_unit|vsync_state_3 + + + vga_driver:vga_driver_unit|vsync_counter_9 + + + vga_driver:vga_driver_unit|vsync_state_2 + + + vga_driver:vga_driver_unit|vsync_state_1 + + + vga_driver:vga_driver_unit|vsync_state_0 + + + vga_driver:vga_driver_unit|vsync_state_6 + + + vga_driver:vga_driver_unit|vsync_state_5 + + + vga_driver:vga_driver_unit|vsync_state_4 + + + vga_driver:vga_driver_unit|line_counter_sig_8 + + + vga_driver:vga_driver_unit|line_counter_sig_6 + + + vga_driver:vga_driver_unit|line_counter_sig_7 + + + vga_driver:vga_driver_unit|line_counter_sig_0 + + + vga_driver:vga_driver_unit|line_counter_sig_1 + + + vga_driver:vga_driver_unit|line_counter_sig_4 + + + vga_driver:vga_driver_unit|line_counter_sig_5 + + + vga_driver:vga_driver_unit|line_counter_sig_2 + + + vga_driver:vga_driver_unit|line_counter_sig_3 + + + vga_driver:vga_driver_unit|v_enable_sig + + + vga_driver:vga_driver_unit|hsync_counter_8 + + + vga_driver:vga_driver_unit|hsync_counter_7 + + + vga_driver:vga_driver_unit|hsync_counter_9 + + + dly_counter[0] + + + vga_control:vga_control_unit|r + + + vga_driver:vga_driver_unit|v_sync + + + dly_counter[1] + + + vga_driver:vga_driver_unit|column_counter_sig_4 + + + vga_driver:vga_driver_unit|column_counter_sig_3 + + + vga_driver:vga_driver_unit|hsync_state_2 + + + vga_driver:vga_driver_unit|column_counter_sig_2 + + + vga_driver:vga_driver_unit|hsync_state_3 + + + vga_driver:vga_driver_unit|column_counter_sig_1 + + + vga_driver:vga_driver_unit|hsync_state_0 + + + vga_driver:vga_driver_unit|column_counter_sig_0 + + + vga_driver:vga_driver_unit|hsync_state_1 + + + vga_driver:vga_driver_unit|hsync_state_6 + + + vga_driver:vga_driver_unit|hsync_state_4 + + + vga_control:vga_control_unit|b + + + vga_driver:vga_driver_unit|hsync_state_5 + + + vga_control:vga_control_unit|g + + + vga_driver:vga_driver_unit|h_enable_sig + + + vga_driver:vga_driver_unit|column_counter_sig_9 + + + vga_driver:vga_driver_unit|column_counter_sig_8 + + + vga_driver:vga_driver_unit|column_counter_sig_7 + + + vga_driver:vga_driver_unit|hsync_counter_4 + + + vga_driver:vga_driver_unit|column_counter_sig_6 + + + vga_driver:vga_driver_unit|hsync_counter_3 + + + vga_driver:vga_driver_unit|column_counter_sig_5 + + + vga_driver:vga_driver_unit|hsync_counter_6 + + + vga_driver:vga_driver_unit|hsync_counter_5 + + + vga_driver:vga_driver_unit|hsync_counter_0 + + + vga_driver:vga_driver_unit|hsync_counter_2 + + + vga_driver:vga_driver_unit|hsync_counter_1 + + + vga_driver:vga_driver_unit|vsync_counter_0 + + + vga_driver:vga_driver_unit|h_sync + + + vga_driver:vga_driver_unit|vsync_counter_1 + + + vga_driver:vga_driver_unit|vsync_counter_2 + + + vga_driver:vga_driver_unit|vsync_counter_3 + + + vga_driver:vga_driver_unit|vsync_counter_4 + + + vga_driver:vga_driver_unit|vsync_counter_5 + + + vga_driver:vga_driver_unit|vsync_counter_6 + + + vga_driver:vga_driver_unit|vsync_counter_7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft new file mode 100644 index 0000000..d306a9b --- /dev/null +++ b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft @@ -0,0 +1,4 @@ +set tool_name "ModelSim-Altera (VHDL)" +set corner_file_list { + {{"Slow Model"} {vga.vho vga_vhd.sdo}} +} diff --git a/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho new file mode 100644 index 0000000..2421f7c --- /dev/null +++ b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho @@ -0,0 +1,6160 @@ +-- Copyright (C) 1991-2009 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II" +-- VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version" + +-- DATE "10/29/2009 17:00:56" + +-- +-- Device: Altera EP1S25F672C6 Package FBGA672 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY IEEE, stratix; +USE IEEE.std_logic_1164.all; +USE stratix.stratix_components.all; + +ENTITY vga IS + PORT ( + clk_pin : IN std_logic; + reset_pin : IN std_logic; + r0_pin : OUT std_logic; + r1_pin : OUT std_logic; + r2_pin : OUT std_logic; + g0_pin : OUT std_logic; + g1_pin : OUT std_logic; + g2_pin : OUT std_logic; + b0_pin : OUT std_logic; + b1_pin : OUT std_logic; + hsync_pin : OUT std_logic; + vsync_pin : OUT std_logic; + seven_seg_pin : OUT std_logic_vector(13 DOWNTO 0); + d_hsync : OUT std_logic; + d_vsync : OUT std_logic; + d_column_counter : OUT std_logic_vector(9 DOWNTO 0); + d_line_counter : OUT std_logic_vector(8 DOWNTO 0); + d_set_column_counter : OUT std_logic; + d_set_line_counter : OUT std_logic; + d_hsync_counter : OUT std_logic_vector(9 DOWNTO 0); + d_vsync_counter : OUT std_logic_vector(9 DOWNTO 0); + d_set_hsync_counter : OUT std_logic; + d_set_vsync_counter : OUT std_logic; + d_h_enable : OUT std_logic; + d_v_enable : OUT std_logic; + d_r : OUT std_logic; + d_g : OUT std_logic; + d_b : OUT std_logic; + d_hsync_state : OUT std_logic_vector(0 TO 6); + d_vsync_state : OUT std_logic_vector(0 TO 6); + d_state_clk : OUT std_logic + ); +END vga; + +ARCHITECTURE structure OF vga IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_clk_pin : std_logic; +SIGNAL ww_reset_pin : std_logic; +SIGNAL ww_r0_pin : std_logic; +SIGNAL ww_r1_pin : std_logic; +SIGNAL ww_r2_pin : std_logic; +SIGNAL ww_g0_pin : std_logic; +SIGNAL ww_g1_pin : std_logic; +SIGNAL ww_g2_pin : std_logic; +SIGNAL ww_b0_pin : std_logic; +SIGNAL ww_b1_pin : std_logic; +SIGNAL ww_hsync_pin : std_logic; +SIGNAL ww_vsync_pin : std_logic; +SIGNAL ww_seven_seg_pin : std_logic_vector(13 DOWNTO 0); +SIGNAL ww_d_hsync : std_logic; +SIGNAL ww_d_vsync : std_logic; +SIGNAL ww_d_column_counter : std_logic_vector(9 DOWNTO 0); +SIGNAL ww_d_line_counter : std_logic_vector(8 DOWNTO 0); +SIGNAL ww_d_set_column_counter : std_logic; +SIGNAL ww_d_set_line_counter : std_logic; +SIGNAL ww_d_hsync_counter : std_logic_vector(9 DOWNTO 0); +SIGNAL ww_d_vsync_counter : std_logic_vector(9 DOWNTO 0); +SIGNAL ww_d_set_hsync_counter : std_logic; +SIGNAL ww_d_set_vsync_counter : std_logic; +SIGNAL ww_d_h_enable : std_logic; +SIGNAL ww_d_v_enable : std_logic; +SIGNAL ww_d_r : std_logic; +SIGNAL ww_d_g : std_logic; +SIGNAL ww_d_b : std_logic; +SIGNAL ww_d_hsync_state : std_logic_vector(0 TO 6); +SIGNAL ww_d_vsync_state : std_logic_vector(0 TO 6); +SIGNAL ww_d_state_clk : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\ : std_logic; +SIGNAL \clk_pin~combout\ : std_logic; +SIGNAL \reset_pin~combout\ : std_logic; +SIGNAL \vga_driver_unit|un6_dly_counter_0_x\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_6\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_0\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_1\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_5\ : std_logic; +SIGNAL \vga_driver_unit|un13_hsync_counter_7\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_6\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_8\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_9\ : std_logic; +SIGNAL \vga_driver_unit|un9_hsync_counterlt9_3\ : std_logic; +SIGNAL \vga_driver_unit|un9_hsync_counterlt9\ : std_logic; +SIGNAL \vga_driver_unit|G_2_i\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_7\ : std_logic; +SIGNAL \vga_driver_unit|un13_hsync_counter_2\ : std_logic; +SIGNAL \vga_driver_unit|un13_hsync_counter\ : std_logic; +SIGNAL \vga_driver_unit|un12_hsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|un12_hsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|un12_hsync_counter\ : std_logic; +SIGNAL \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ : std_logic; +SIGNAL \vga_driver_unit|un10_hsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_5\ : std_logic; +SIGNAL \vga_driver_unit|un10_hsync_counter_1\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ : std_logic; +SIGNAL \vga_driver_unit|un11_hsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|un11_hsync_counter_2\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_3\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_2\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_0\ : std_logic; +SIGNAL \vga_driver_unit|d_set_hsync_counter\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_next_1_sqmuxa\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_2\ : std_logic; +SIGNAL \vga_driver_unit|un10_hsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_4\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_1\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_0\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_1\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_3\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_2\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_4\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_5\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_7\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_8\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_9\ : std_logic; +SIGNAL \vga_driver_unit|un10_column_counter_siglt6_1\ : std_logic; +SIGNAL \vga_driver_unit|un10_column_counter_siglt6\ : std_logic; +SIGNAL \vga_driver_unit|un10_column_counter_siglto9\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_6\ : std_logic; +SIGNAL \vga_driver_unit|un10_column_counter_siglt6_3\ : std_logic; +SIGNAL \vga_control_unit|b_next_i_o3_0\ : std_logic; +SIGNAL \vga_control_unit|g_next_i_o3\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_6\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_0\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_1\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_2\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_5\ : std_logic; +SIGNAL \vga_driver_unit|un9_vsync_counterlt9_6\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_6\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_8\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_9\ : std_logic; +SIGNAL \vga_driver_unit|un9_vsync_counterlt9_5\ : std_logic; +SIGNAL \vga_driver_unit|un9_vsync_counterlt9\ : std_logic; +SIGNAL \vga_driver_unit|G_16_i\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_7\ : std_logic; +SIGNAL \vga_driver_unit|un12_vsync_counter_6\ : std_logic; +SIGNAL \vga_driver_unit|un15_vsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|un15_vsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|un14_vsync_counter_8\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_5\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_4\ : std_logic; +SIGNAL \vga_driver_unit|un13_vsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|un13_vsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ : std_logic; +SIGNAL \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_next_2_sqmuxa\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_3\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_2\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_0\ : std_logic; +SIGNAL \vga_driver_unit|d_set_vsync_counter\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_next_1_sqmuxa\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|un12_vsync_counter_7\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_1\ : std_logic; +SIGNAL \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ : std_logic; +SIGNAL \vga_driver_unit|h_enable_sig\ : std_logic; +SIGNAL \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ : std_logic; +SIGNAL \vga_driver_unit|v_enable_sig\ : std_logic; +SIGNAL \vga_control_unit|r_next_i_o7\ : std_logic; +SIGNAL \vga_control_unit|N_4_i_0_g0_1\ : std_logic; +SIGNAL \vga_control_unit|r\ : std_logic; +SIGNAL \vga_control_unit|N_23_i_0_g0_a\ : std_logic; +SIGNAL \vga_control_unit|g\ : std_logic; +SIGNAL \vga_control_unit|b_next_i_a7_1\ : std_logic; +SIGNAL \vga_control_unit|N_6_i_0_g0_0\ : std_logic; +SIGNAL \vga_control_unit|b\ : std_logic; +SIGNAL \vga_driver_unit|un1_hsync_state_3_0\ : std_logic; +SIGNAL \vga_driver_unit|h_sync_1_0_0_0_g1\ : std_logic; +SIGNAL \vga_driver_unit|h_sync\ : std_logic; +SIGNAL \vga_driver_unit|un1_vsync_state_2_0\ : std_logic; +SIGNAL \vga_driver_unit|v_sync_1_0_0_0_g1\ : std_logic; +SIGNAL \vga_driver_unit|v_sync\ : std_logic; +SIGNAL \~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_1\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_2\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_3\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_4\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_5\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_6\ : std_logic; +SIGNAL \vga_driver_unit|un10_line_counter_siglt4_2\ : std_logic; +SIGNAL \vga_driver_unit|un10_line_counter_siglto5\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_7\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_8\ : std_logic; +SIGNAL \vga_driver_unit|un10_line_counter_siglto8\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_0\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout\ : std_logic_vector(8 DOWNTO 0); +SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout\ : std_logic_vector(1 DOWNTO 1); +SIGNAL \vga_driver_unit|un1_line_counter_sig_combout\ : std_logic_vector(9 DOWNTO 1); +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout\ : std_logic_vector(7 DOWNTO 1); +SIGNAL \vga_driver_unit|un2_column_counter_next_combout\ : std_logic_vector(9 DOWNTO 1); +SIGNAL \vga_driver_unit|un2_column_counter_next_cout\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \vga_driver_unit|vsync_counter_cout\ : std_logic_vector(8 DOWNTO 0); +SIGNAL dly_counter : std_logic_vector(1 DOWNTO 0); +SIGNAL \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_G_2_i\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_G_16_i\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ : std_logic; +SIGNAL \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic; + +BEGIN + +ww_clk_pin <= clk_pin; +ww_reset_pin <= reset_pin; +r0_pin <= ww_r0_pin; +r1_pin <= ww_r1_pin; +r2_pin <= ww_r2_pin; +g0_pin <= ww_g0_pin; +g1_pin <= ww_g1_pin; +g2_pin <= ww_g2_pin; +b0_pin <= ww_b0_pin; +b1_pin <= ww_b1_pin; +hsync_pin <= ww_hsync_pin; +vsync_pin <= ww_vsync_pin; +seven_seg_pin <= ww_seven_seg_pin; +d_hsync <= ww_d_hsync; +d_vsync <= ww_d_vsync; +d_column_counter <= ww_d_column_counter; +d_line_counter <= ww_d_line_counter; +d_set_column_counter <= ww_d_set_column_counter; +d_set_line_counter <= ww_d_set_line_counter; +d_hsync_counter <= ww_d_hsync_counter; +d_vsync_counter <= ww_d_vsync_counter; +d_set_hsync_counter <= ww_d_set_hsync_counter; +d_set_vsync_counter <= ww_d_set_vsync_counter; +d_h_enable <= ww_d_h_enable; +d_v_enable <= ww_d_v_enable; +d_r <= ww_d_r; +d_g <= ww_d_g; +d_b <= ww_d_b; +d_hsync_state <= ww_d_hsync_state; +d_vsync_state <= ww_d_vsync_state; +d_state_clk <= ww_d_state_clk; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +\vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\; +\vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\; +\vga_driver_unit|ALT_INV_G_2_i\ <= NOT \vga_driver_unit|G_2_i\; +\vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ <= NOT \vga_driver_unit|un9_hsync_counterlt9\; +\vga_driver_unit|ALT_INV_G_16_i\ <= NOT \vga_driver_unit|G_16_i\; +\vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ <= NOT \vga_driver_unit|un9_vsync_counterlt9\; +\ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ <= NOT \~STRATIX_FITTER_CREATED_GND~I_combout\; + +clk_pin_in : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_clk_pin, + combout => \clk_pin~combout\); + +reset_pin_in : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_reset_pin, + combout => \reset_pin~combout\); + +\dly_counter_1_\ : stratix_lcell +-- Equation(s): +-- dly_counter(1) = DFFEAS(\reset_pin~combout\ & (dly_counter(0) # dly_counter(1)), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a8a8", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => dly_counter(1)); + +\dly_counter_0_\ : stratix_lcell +-- Equation(s): +-- dly_counter(0) = DFFEAS(\reset_pin~combout\ & (dly_counter(1) # !dly_counter(0)), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a2a2", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => dly_counter(0)); + +\vga_driver_unit|vsync_state_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un6_dly_counter_0_x\ = !dly_counter(1) # !dly_counter(0) # !\reset_pin~combout\ +-- \vga_driver_unit|vsync_state_6\ = DFFEAS(\vga_driver_unit|un6_dly_counter_0_x\, GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "7f7f", + operation_mode => "normal", + output_mode => "reg_and_comb", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un6_dly_counter_0_x\, + regout => \vga_driver_unit|vsync_state_6\); + +\vga_driver_unit|hsync_state_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|d_set_hsync_counter\ = C1_hsync_state_6 # \vga_driver_unit|hsync_state_0\ +-- \vga_driver_unit|hsync_state_6\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|un6_dly_counter_0_x\, , , VCC) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fff0", + operation_mode => "normal", + output_mode => "reg_and_comb", + register_cascade_mode => "off", + sum_lutc_input => "qfbk", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un6_dly_counter_0_x\, + datad => \vga_driver_unit|hsync_state_0\, + aclr => GND, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|d_set_hsync_counter\, + regout => \vga_driver_unit|hsync_state_6\); + +\vga_driver_unit|hsync_counter_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_0\ = DFFEAS(!\vga_driver_unit|hsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(0) = CARRY(\vga_driver_unit|hsync_counter_0\) +-- \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|hsync_counter_0\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "33cc", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_counter_0\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_0\, + cout0 => \vga_driver_unit|hsync_counter_cout\(0), + cout1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\); + +\vga_driver_unit|hsync_counter_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_1\ = DFFEAS(\vga_driver_unit|hsync_counter_1\ $ \vga_driver_unit|hsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(1) = CARRY(!\vga_driver_unit|hsync_counter_cout\(0) # !\vga_driver_unit|hsync_counter_1\) +-- \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|hsync_counter_1\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "3c3f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_counter_1\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin0 => \vga_driver_unit|hsync_counter_cout\(0), + cin1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_1\, + cout0 => \vga_driver_unit|hsync_counter_cout\(1), + cout1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\); + +\vga_driver_unit|hsync_counter_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_2\ = DFFEAS(\vga_driver_unit|hsync_counter_2\ $ (!\vga_driver_unit|hsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(2) = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout\(1))) +-- \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout[1]~COUT1_12\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_2\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin0 => \vga_driver_unit|hsync_counter_cout\(1), + cin1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_2\, + cout0 => \vga_driver_unit|hsync_counter_cout\(2), + cout1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\); + +\vga_driver_unit|hsync_counter_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_3\ = DFFEAS(\vga_driver_unit|hsync_counter_3\ $ (\vga_driver_unit|hsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(3) = CARRY(!\vga_driver_unit|hsync_counter_cout\(2) # !\vga_driver_unit|hsync_counter_3\) +-- \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|hsync_counter_3\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "5a5f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_3\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin0 => \vga_driver_unit|hsync_counter_cout\(2), + cin1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_3\, + cout0 => \vga_driver_unit|hsync_counter_cout\(3), + cout1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\); + +\vga_driver_unit|hsync_counter_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_4\ = DFFEAS(\vga_driver_unit|hsync_counter_4\ $ (!\vga_driver_unit|hsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(4) = CARRY(\vga_driver_unit|hsync_counter_4\ & (!\vga_driver_unit|hsync_counter_cout[3]~COUT1_16\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_4\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin0 => \vga_driver_unit|hsync_counter_cout\(3), + cin1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_4\, + cout => \vga_driver_unit|hsync_counter_cout\(4)); + +\vga_driver_unit|hsync_counter_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_5\ = DFFEAS(\vga_driver_unit|hsync_counter_5\ $ \vga_driver_unit|hsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(5) = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\) +-- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\) + +-- pragma translate_off +GENERIC MAP ( + cin_used => "true", + lut_mask => "3c3f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_counter_5\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_5\, + cout0 => \vga_driver_unit|hsync_counter_cout\(5), + cout1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\); + +\vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_hsync_counter_7\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_2\ & \vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_1\, + datab => \vga_driver_unit|hsync_counter_2\, + datac => \vga_driver_unit|hsync_counter_3\, + datad => \vga_driver_unit|hsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_hsync_counter_7\); + +\vga_driver_unit|hsync_counter_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_6\ = DFFEAS(\vga_driver_unit|hsync_counter_6\ $ !(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(5)) # (\vga_driver_unit|hsync_counter_cout\(4) & +-- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(6) = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout\(5)) +-- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout[5]~COUT1_18\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "c30c", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_counter_6\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + cin0 => \vga_driver_unit|hsync_counter_cout\(5), + cin1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_6\, + cout0 => \vga_driver_unit|hsync_counter_cout\(6), + cout1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\); + +\vga_driver_unit|hsync_counter_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_7\ = DFFEAS(\vga_driver_unit|hsync_counter_7\ $ ((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(6)) # (\vga_driver_unit|hsync_counter_cout\(4) & +-- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(7) = CARRY(!\vga_driver_unit|hsync_counter_cout\(6) # !\vga_driver_unit|hsync_counter_7\) +-- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|hsync_counter_7\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "5a5f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_7\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + cin0 => \vga_driver_unit|hsync_counter_cout\(6), + cin1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_7\, + cout0 => \vga_driver_unit|hsync_counter_cout\(7), + cout1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\); + +\vga_driver_unit|hsync_counter_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_8\ = DFFEAS(\vga_driver_unit|hsync_counter_8\ $ (!(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(7)) # (\vga_driver_unit|hsync_counter_cout\(4) & +-- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(8) = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout\(7))) +-- \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout[7]~COUT1_22\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_8\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + cin0 => \vga_driver_unit|hsync_counter_cout\(7), + cin1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_8\, + cout0 => \vga_driver_unit|hsync_counter_cout\(8), + cout1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\); + +\vga_driver_unit|hsync_counter_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_9\ = DFFEAS((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(8)) # (\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\) $ +-- \vga_driver_unit|hsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "0ff0", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + datad => \vga_driver_unit|hsync_counter_9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + cin0 => \vga_driver_unit|hsync_counter_cout\(8), + cin1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_9\); + +\vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_hsync_counterlt9_3\ = !\vga_driver_unit|hsync_counter_6\ # !\vga_driver_unit|hsync_counter_8\ # !\vga_driver_unit|hsync_counter_9\ # !\vga_driver_unit|hsync_counter_7\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "7fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_7\, + datab => \vga_driver_unit|hsync_counter_9\, + datac => \vga_driver_unit|hsync_counter_8\, + datad => \vga_driver_unit|hsync_counter_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_hsync_counterlt9_3\); + +\vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_hsync_counterlt9\ = \vga_driver_unit|un9_hsync_counterlt9_3\ # !\vga_driver_unit|un13_hsync_counter_7\ # !\vga_driver_unit|hsync_counter_4\ # !\vga_driver_unit|hsync_counter_5\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff7f", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_5\, + datab => \vga_driver_unit|hsync_counter_4\, + datac => \vga_driver_unit|un13_hsync_counter_7\, + datad => \vga_driver_unit|un9_hsync_counterlt9_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_hsync_counterlt9\); + +\vga_driver_unit|G_2\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|G_2_i\ = !\vga_driver_unit|hsync_state_6\ & !\vga_driver_unit|hsync_state_0\ & !\vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un9_hsync_counterlt9\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "3337", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_state_6\, + datab => \vga_driver_unit|un9_hsync_counterlt9\, + datac => \vga_driver_unit|hsync_state_0\, + datad => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|G_2_i\); + +\vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_hsync_counter_2\ = !\vga_driver_unit|hsync_counter_5\ & \vga_driver_unit|hsync_counter_9\ & \vga_driver_unit|hsync_counter_8\ & \vga_driver_unit|hsync_counter_4\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "4000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_5\, + datab => \vga_driver_unit|hsync_counter_9\, + datac => \vga_driver_unit|hsync_counter_8\, + datad => \vga_driver_unit|hsync_counter_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_hsync_counter_2\); + +\vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_hsync_counter\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|un13_hsync_counter_7\ & \vga_driver_unit|un13_hsync_counter_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_7\, + datab => \vga_driver_unit|hsync_counter_6\, + datac => \vga_driver_unit|un13_hsync_counter_7\, + datad => \vga_driver_unit|un13_hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_hsync_counter\); + +\vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_hsync_counter_4\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_6\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_7\, + datab => \vga_driver_unit|hsync_counter_4\, + datac => \vga_driver_unit|hsync_counter_8\, + datad => \vga_driver_unit|hsync_counter_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_hsync_counter_4\); + +\vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_5\ & \vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0400", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_5\, + datab => \vga_driver_unit|hsync_counter_9\, + datac => \vga_driver_unit|hsync_counter_3\, + datad => \vga_driver_unit|hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_hsync_counter_3\); + +\vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_hsync_counter\ = \vga_driver_unit|hsync_counter_0\ & \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|un12_hsync_counter_4\ & \vga_driver_unit|un12_hsync_counter_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_0\, + datab => \vga_driver_unit|hsync_counter_1\, + datac => \vga_driver_unit|un12_hsync_counter_4\, + datad => \vga_driver_unit|un12_hsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_hsync_counter\); + +\vga_driver_unit|hsync_state_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|hsync_state_2\ & (C1_hsync_state_3 & !\vga_driver_unit|un12_hsync_counter\ # !\vga_driver_unit|un13_hsync_counter\) # !\vga_driver_unit|hsync_state_2\ & (C1_hsync_state_3 & +-- !\vga_driver_unit|un12_hsync_counter\) +-- \vga_driver_unit|hsync_state_3\ = DFFEAS(\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, \vga_driver_unit|hsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "22f2", + operation_mode => "normal", + output_mode => "reg_and_comb", + register_cascade_mode => "off", + sum_lutc_input => "qfbk", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_state_2\, + datab => \vga_driver_unit|un13_hsync_counter\, + datac => \vga_driver_unit|hsync_state_1\, + datad => \vga_driver_unit|un12_hsync_counter\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + sload => VCC, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, + regout => \vga_driver_unit|hsync_state_3\); + +\vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_hsync_counter_4\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_1\, + datab => \vga_driver_unit|hsync_counter_6\, + datac => \vga_driver_unit|hsync_counter_4\, + datad => \vga_driver_unit|hsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_hsync_counter_4\); + +\vga_driver_unit|hsync_state_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_5\ = DFFEAS(\vga_driver_unit|hsync_state_0\ # \vga_driver_unit|hsync_state_6\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fcfc", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_state_0\, + datac => \vga_driver_unit|hsync_state_6\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_5\); + +\vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_hsync_counter_1\ = !\vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_5\ & (!\vga_driver_unit|hsync_counter_8\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_9\, + datab => \vga_driver_unit|hsync_counter_5\, + datad => \vga_driver_unit|hsync_counter_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_hsync_counter_1\); + +\vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|hsync_state_5\ & (!\vga_driver_unit|un10_hsync_counter_1\ # !\vga_driver_unit|un10_hsync_counter_4\ # !\vga_driver_unit|un10_hsync_counter_3\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "70f0", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un10_hsync_counter_3\, + datab => \vga_driver_unit|un10_hsync_counter_4\, + datac => \vga_driver_unit|hsync_state_5\, + datad => \vga_driver_unit|un10_hsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\); + +\vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un11_hsync_counter_3\ = \vga_driver_unit|hsync_counter_1\ & !\vga_driver_unit|hsync_counter_4\ & !\vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0200", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_1\, + datab => \vga_driver_unit|hsync_counter_4\, + datac => \vga_driver_unit|hsync_counter_3\, + datad => \vga_driver_unit|hsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un11_hsync_counter_3\); + +\vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un11_hsync_counter_2\ = !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_7\ & \vga_driver_unit|hsync_counter_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "3000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|hsync_counter_6\, + datac => \vga_driver_unit|hsync_counter_7\, + datad => \vga_driver_unit|hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un11_hsync_counter_2\); + +\vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|hsync_state_4\ & (!\vga_driver_unit|un11_hsync_counter_2\ # !\vga_driver_unit|un11_hsync_counter_3\ # !\vga_driver_unit|un10_hsync_counter_1\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "2aaa", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_state_4\, + datab => \vga_driver_unit|un10_hsync_counter_1\, + datac => \vga_driver_unit|un11_hsync_counter_3\, + datad => \vga_driver_unit|un11_hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\); + +\vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "aaab", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un6_dly_counter_0_x\, + datab => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, + datac => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\, + datad => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\); + +\vga_driver_unit|hsync_state_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_2\ = DFFEAS(\vga_driver_unit|hsync_state_3\ & (\vga_driver_unit|un12_hsync_counter\), GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "cc00", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_state_3\, + datad => \vga_driver_unit|un12_hsync_counter\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_2\); + +\vga_driver_unit|hsync_state_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_0\ = DFFEAS(\vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|un13_hsync_counter\), GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a0a0", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_state_2\, + datac => \vga_driver_unit|un13_hsync_counter\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_0\); + +\vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_next_1_sqmuxa\ = \reset_pin~combout\ & dly_counter(0) & !\vga_driver_unit|d_set_hsync_counter\ & dly_counter(1) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0800", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => \vga_driver_unit|d_set_hsync_counter\, + datad => dly_counter(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|hsync_counter_next_1_sqmuxa\); + +\vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_2\ & !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0003", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|hsync_counter_2\, + datac => \vga_driver_unit|hsync_counter_7\, + datad => \vga_driver_unit|hsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_hsync_counter_3\); + +\vga_driver_unit|hsync_state_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_4\ = DFFEAS(\vga_driver_unit|un10_hsync_counter_3\ & \vga_driver_unit|un10_hsync_counter_4\ & \vga_driver_unit|hsync_state_5\ & \vga_driver_unit|un10_hsync_counter_1\, GLOBAL(\clk_pin~combout\), VCC, , +-- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un10_hsync_counter_3\, + datab => \vga_driver_unit|un10_hsync_counter_4\, + datac => \vga_driver_unit|hsync_state_5\, + datad => \vga_driver_unit|un10_hsync_counter_1\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_4\); + +\vga_driver_unit|hsync_state_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_1\ = DFFEAS(\vga_driver_unit|hsync_state_4\ & \vga_driver_unit|un10_hsync_counter_1\ & \vga_driver_unit|un11_hsync_counter_3\ & \vga_driver_unit|un11_hsync_counter_2\, GLOBAL(\clk_pin~combout\), VCC, , +-- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_state_4\, + datab => \vga_driver_unit|un10_hsync_counter_1\, + datac => \vga_driver_unit|un11_hsync_counter_3\, + datad => \vga_driver_unit|un11_hsync_counter_2\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_1\); + +\vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ = \reset_pin~combout\ & dly_counter(0) & dly_counter(1) & !\vga_driver_unit|hsync_state_1\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0080", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + datad => \vga_driver_unit|hsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\); + +\vga_driver_unit|column_counter_sig_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_0\ = DFFEAS(!\vga_driver_unit|un10_column_counter_siglto9\ # !\vga_driver_unit|column_counter_sig_0\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "3f3f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|column_counter_sig_0\, + datac => \vga_driver_unit|un10_column_counter_siglto9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_0\); + +\vga_driver_unit|un2_column_counter_next_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(1) = \vga_driver_unit|column_counter_sig_0\ $ \vga_driver_unit|column_counter_sig_1\ +-- \vga_driver_unit|un2_column_counter_next_cout\(1) = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\) +-- \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "6688", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_0\, + datab => \vga_driver_unit|column_counter_sig_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(1), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(1), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\); + +\vga_driver_unit|column_counter_sig_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_1\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(1) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "cfcf", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un2_column_counter_next_combout\(1), + datac => \vga_driver_unit|un10_column_counter_siglto9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_1\); + +\vga_driver_unit|un2_column_counter_next_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(3) = \vga_driver_unit|column_counter_sig_3\ $ (\vga_driver_unit|column_counter_sig_2\ & \vga_driver_unit|un2_column_counter_next_cout\(1)) +-- \vga_driver_unit|un2_column_counter_next_cout\(3) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(1) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\) +-- \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "6c7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_2\, + datab => \vga_driver_unit|column_counter_sig_3\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(1), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(3), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(3), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\); + +\vga_driver_unit|column_counter_sig_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_3\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(3) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_column_counter_siglto9\, + datad => \vga_driver_unit|un2_column_counter_next_combout\(3), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_3\); + +\vga_driver_unit|un2_column_counter_next_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_cout\(0) = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\) +-- \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff88", + operation_mode => "arithmetic", + output_mode => "none", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_0\, + datab => \vga_driver_unit|column_counter_sig_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\, + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(0), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\); + +\vga_driver_unit|un2_column_counter_next_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(2) = \vga_driver_unit|column_counter_sig_2\ $ (\vga_driver_unit|un2_column_counter_next_cout\(0)) +-- \vga_driver_unit|un2_column_counter_next_cout\(2) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(0) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\) +-- \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "5a7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_2\, + datab => \vga_driver_unit|column_counter_sig_3\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(0), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(2), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(2), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\); + +\vga_driver_unit|column_counter_sig_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_2\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(2) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f5f5", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un10_column_counter_siglto9\, + datac => \vga_driver_unit|un2_column_counter_next_combout\(2), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_2\); + +\vga_driver_unit|un2_column_counter_next_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(4) = \vga_driver_unit|column_counter_sig_4\ $ !\vga_driver_unit|un2_column_counter_next_cout\(2) +-- \vga_driver_unit|un2_column_counter_next_cout\(4) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(2)) +-- \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "c308", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_5\, + datab => \vga_driver_unit|column_counter_sig_4\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(2), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(4), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(4), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\); + +\vga_driver_unit|column_counter_sig_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_4\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(4) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f3f3", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_column_counter_siglto9\, + datac => \vga_driver_unit|un2_column_counter_next_combout\(4), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_4\); + +\vga_driver_unit|un2_column_counter_next_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(5) = \vga_driver_unit|column_counter_sig_5\ $ (\vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3)) +-- \vga_driver_unit|un2_column_counter_next_cout\(5) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3)) +-- \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a608", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_5\, + datab => \vga_driver_unit|column_counter_sig_4\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(3), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(5), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(5), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\); + +\vga_driver_unit|column_counter_sig_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_5\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(5) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "afaf", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un2_column_counter_next_combout\(5), + datac => \vga_driver_unit|un10_column_counter_siglto9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_5\); + +\vga_driver_unit|un2_column_counter_next_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(7) = \vga_driver_unit|column_counter_sig_7\ $ (\vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|un2_column_counter_next_cout\(5)) +-- \vga_driver_unit|un2_column_counter_next_cout\(7) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(5) # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\) +-- \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "6a7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_7\, + datab => \vga_driver_unit|column_counter_sig_6\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(5), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(7), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(7), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\); + +\vga_driver_unit|column_counter_sig_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_7\ = DFFEAS(\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ & (\vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|un2_column_counter_next_combout\(7)), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, + datac => \vga_driver_unit|un10_column_counter_siglto9\, + datad => \vga_driver_unit|un2_column_counter_next_combout\(7), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_7\); + +\vga_driver_unit|un2_column_counter_next_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(6) = \vga_driver_unit|column_counter_sig_6\ $ \vga_driver_unit|un2_column_counter_next_cout\(4) +-- \vga_driver_unit|un2_column_counter_next_cout\(6) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(4) # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\) +-- \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "3c7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_7\, + datab => \vga_driver_unit|column_counter_sig_6\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(4), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(6), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(6), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\); + +\vga_driver_unit|un2_column_counter_next_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(8) = \vga_driver_unit|un2_column_counter_next_cout\(6) $ !\vga_driver_unit|column_counter_sig_8\ + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "f00f", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datad => \vga_driver_unit|column_counter_sig_8\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(6), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(8)); + +\vga_driver_unit|column_counter_sig_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_8\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(8) & (\vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un2_column_counter_next_combout\(8), + datac => \vga_driver_unit|un10_column_counter_siglto9\, + datad => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_8\); + +\vga_driver_unit|un2_column_counter_next_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(9) = \vga_driver_unit|column_counter_sig_9\ $ (\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|un2_column_counter_next_cout\(7)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "f30c", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|column_counter_sig_8\, + datad => \vga_driver_unit|column_counter_sig_9\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(7), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(9)); + +\vga_driver_unit|column_counter_sig_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_9\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(9) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_column_counter_siglto9\, + datad => \vga_driver_unit|un2_column_counter_next_combout\(9), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_9\); + +\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_column_counter_siglt6_1\ = !\vga_driver_unit|column_counter_sig_2\ # !\vga_driver_unit|column_counter_sig_1\ # !\vga_driver_unit|column_counter_sig_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "3fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|column_counter_sig_0\, + datac => \vga_driver_unit|column_counter_sig_1\, + datad => \vga_driver_unit|column_counter_sig_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_column_counter_siglt6_1\); + +\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_column_counter_siglt6\ = \vga_driver_unit|un10_column_counter_siglt6_3\ # \vga_driver_unit|un10_column_counter_siglt6_1\ # !\vga_driver_unit|column_counter_sig_4\ # !\vga_driver_unit|column_counter_sig_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fdff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_3\, + datab => \vga_driver_unit|un10_column_counter_siglt6_3\, + datac => \vga_driver_unit|un10_column_counter_siglt6_1\, + datad => \vga_driver_unit|column_counter_sig_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_column_counter_siglt6\); + +\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_column_counter_siglto9\ = !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\ & \vga_driver_unit|un10_column_counter_siglt6\ # !\vga_driver_unit|column_counter_sig_9\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1f0f", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_8\, + datab => \vga_driver_unit|column_counter_sig_7\, + datac => \vga_driver_unit|column_counter_sig_9\, + datad => \vga_driver_unit|un10_column_counter_siglt6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_column_counter_siglto9\); + +\vga_driver_unit|column_counter_sig_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_6\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(6) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f3f3", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_column_counter_siglto9\, + datac => \vga_driver_unit|un2_column_counter_next_combout\(6), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_6\); + +\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_column_counter_siglt6_3\ = !\vga_driver_unit|column_counter_sig_5\ # !\vga_driver_unit|column_counter_sig_6\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datac => \vga_driver_unit|column_counter_sig_6\, + datad => \vga_driver_unit|column_counter_sig_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_column_counter_siglt6_3\); + +\vga_control_unit|b_next_i_o3_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|b_next_i_o3_0\ = \vga_driver_unit|column_counter_sig_7\ # \vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|column_counter_sig_4\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f8f0", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_5\, + datab => \vga_driver_unit|column_counter_sig_6\, + datac => \vga_driver_unit|column_counter_sig_7\, + datad => \vga_driver_unit|column_counter_sig_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|b_next_i_o3_0\); + +\vga_control_unit|g_next_i_o3_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|g_next_i_o3\ = \vga_driver_unit|column_counter_sig_4\ # \vga_driver_unit|column_counter_sig_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ffaa", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_4\, + datad => \vga_driver_unit|column_counter_sig_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|g_next_i_o3\); + +\vga_driver_unit|vsync_counter_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_0\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\ $ \vga_driver_unit|vsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(0) = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|vsync_counter_0\) +-- \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|vsync_counter_0\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "6688", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|d_set_hsync_counter\, + datab => \vga_driver_unit|vsync_counter_0\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_0\, + cout0 => \vga_driver_unit|vsync_counter_cout\(0), + cout1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\); + +\vga_driver_unit|vsync_counter_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_1\ = DFFEAS(\vga_driver_unit|vsync_counter_1\ $ \vga_driver_unit|vsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(1) = CARRY(!\vga_driver_unit|vsync_counter_cout\(0) # !\vga_driver_unit|vsync_counter_1\) +-- \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|vsync_counter_1\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "3c3f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|vsync_counter_1\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin0 => \vga_driver_unit|vsync_counter_cout\(0), + cin1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_1\, + cout0 => \vga_driver_unit|vsync_counter_cout\(1), + cout1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\); + +\vga_driver_unit|vsync_counter_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_2\ = DFFEAS(\vga_driver_unit|vsync_counter_2\ $ (!\vga_driver_unit|vsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(2) = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout\(1))) +-- \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout[1]~COUT1_12\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_2\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin0 => \vga_driver_unit|vsync_counter_cout\(1), + cin1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_2\, + cout0 => \vga_driver_unit|vsync_counter_cout\(2), + cout1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\); + +\vga_driver_unit|vsync_counter_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_3\ = DFFEAS(\vga_driver_unit|vsync_counter_3\ $ (\vga_driver_unit|vsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(3) = CARRY(!\vga_driver_unit|vsync_counter_cout\(2) # !\vga_driver_unit|vsync_counter_3\) +-- \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|vsync_counter_3\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "5a5f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_3\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin0 => \vga_driver_unit|vsync_counter_cout\(2), + cin1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_3\, + cout0 => \vga_driver_unit|vsync_counter_cout\(3), + cout1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\); + +\vga_driver_unit|vsync_counter_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_4\ = DFFEAS(\vga_driver_unit|vsync_counter_4\ $ (!\vga_driver_unit|vsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(4) = CARRY(\vga_driver_unit|vsync_counter_4\ & (!\vga_driver_unit|vsync_counter_cout[3]~COUT1_16\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_4\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin0 => \vga_driver_unit|vsync_counter_cout\(3), + cin1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_4\, + cout => \vga_driver_unit|vsync_counter_cout\(4)); + +\vga_driver_unit|vsync_counter_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_5\ = DFFEAS(\vga_driver_unit|vsync_counter_5\ $ \vga_driver_unit|vsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(5) = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\) +-- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\) + +-- pragma translate_off +GENERIC MAP ( + cin_used => "true", + lut_mask => "3c3f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|vsync_counter_5\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_5\, + cout0 => \vga_driver_unit|vsync_counter_cout\(5), + cout1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\); + +\vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_vsync_counterlt9_6\ = !\vga_driver_unit|vsync_counter_1\ # !\vga_driver_unit|vsync_counter_2\ # !\vga_driver_unit|vsync_counter_3\ # !\vga_driver_unit|vsync_counter_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "7fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_0\, + datab => \vga_driver_unit|vsync_counter_3\, + datac => \vga_driver_unit|vsync_counter_2\, + datad => \vga_driver_unit|vsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_vsync_counterlt9_6\); + +\vga_driver_unit|vsync_counter_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_6\ = DFFEAS(\vga_driver_unit|vsync_counter_6\ $ !(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(5)) # (\vga_driver_unit|vsync_counter_cout\(4) & +-- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(6) = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout\(5)) +-- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout[5]~COUT1_18\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "c30c", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|vsync_counter_6\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + cin0 => \vga_driver_unit|vsync_counter_cout\(5), + cin1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_6\, + cout0 => \vga_driver_unit|vsync_counter_cout\(6), + cout1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\); + +\vga_driver_unit|vsync_counter_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_7\ = DFFEAS(\vga_driver_unit|vsync_counter_7\ $ ((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(6)) # (\vga_driver_unit|vsync_counter_cout\(4) & +-- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(7) = CARRY(!\vga_driver_unit|vsync_counter_cout\(6) # !\vga_driver_unit|vsync_counter_7\) +-- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|vsync_counter_7\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "5a5f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_7\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + cin0 => \vga_driver_unit|vsync_counter_cout\(6), + cin1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_7\, + cout0 => \vga_driver_unit|vsync_counter_cout\(7), + cout1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\); + +\vga_driver_unit|vsync_counter_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_8\ = DFFEAS(\vga_driver_unit|vsync_counter_8\ $ (!(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(7)) # (\vga_driver_unit|vsync_counter_cout\(4) & +-- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(8) = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout\(7))) +-- \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout[7]~COUT1_22\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_8\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + cin0 => \vga_driver_unit|vsync_counter_cout\(7), + cin1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_8\, + cout0 => \vga_driver_unit|vsync_counter_cout\(8), + cout1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\); + +\vga_driver_unit|vsync_counter_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_9\ = DFFEAS((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(8)) # (\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\) $ +-- \vga_driver_unit|vsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "0ff0", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + datad => \vga_driver_unit|vsync_counter_9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + cin0 => \vga_driver_unit|vsync_counter_cout\(8), + cin1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_9\); + +\vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_vsync_counterlt9_5\ = !\vga_driver_unit|vsync_counter_7\ # !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_6\ # !\vga_driver_unit|vsync_counter_8\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "7fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_8\, + datab => \vga_driver_unit|vsync_counter_6\, + datac => \vga_driver_unit|vsync_counter_9\, + datad => \vga_driver_unit|vsync_counter_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_vsync_counterlt9_5\); + +\vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_vsync_counterlt9\ = \vga_driver_unit|un9_vsync_counterlt9_6\ # \vga_driver_unit|un9_vsync_counterlt9_5\ # !\vga_driver_unit|vsync_counter_4\ # !\vga_driver_unit|vsync_counter_5\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ffdf", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_5\, + datab => \vga_driver_unit|un9_vsync_counterlt9_6\, + datac => \vga_driver_unit|vsync_counter_4\, + datad => \vga_driver_unit|un9_vsync_counterlt9_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_vsync_counterlt9\); + +\vga_driver_unit|G_16\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|G_16_i\ = !\vga_driver_unit|un6_dly_counter_0_x\ & !\vga_driver_unit|vsync_state_6\ & !\vga_driver_unit|vsync_state_0\ # !\vga_driver_unit|un9_vsync_counterlt9\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "01ff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un6_dly_counter_0_x\, + datab => \vga_driver_unit|vsync_state_6\, + datac => \vga_driver_unit|vsync_state_0\, + datad => \vga_driver_unit|un9_vsync_counterlt9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|G_16_i\); + +\vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_vsync_counter_6\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_5\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_7\, + datab => \vga_driver_unit|vsync_counter_8\, + datac => \vga_driver_unit|vsync_counter_6\, + datad => \vga_driver_unit|vsync_counter_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_vsync_counter_6\); + +\vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un15_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|vsync_counter_3\ & \vga_driver_unit|vsync_counter_9\ & !\vga_driver_unit|vsync_counter_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0040", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_0\, + datab => \vga_driver_unit|vsync_counter_3\, + datac => \vga_driver_unit|vsync_counter_9\, + datad => \vga_driver_unit|vsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un15_vsync_counter_3\); + +\vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un15_vsync_counter_4\ = !\vga_driver_unit|vsync_counter_4\ & !\vga_driver_unit|vsync_counter_1\ & \vga_driver_unit|un15_vsync_counter_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0300", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|vsync_counter_4\, + datac => \vga_driver_unit|vsync_counter_1\, + datad => \vga_driver_unit|un15_vsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un15_vsync_counter_4\); + +\vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un14_vsync_counter_8\ = \vga_driver_unit|un12_vsync_counter_6\ & \vga_driver_unit|un12_vsync_counter_7\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datac => \vga_driver_unit|un12_vsync_counter_6\, + datad => \vga_driver_unit|un12_vsync_counter_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un14_vsync_counter_8\); + +\vga_driver_unit|vsync_state_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_5\ = DFFEAS(\vga_driver_unit|vsync_state_0\ # \vga_driver_unit|vsync_state_6\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fff0", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|vsync_state_0\, + datad => \vga_driver_unit|vsync_state_6\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_5\); + +\vga_driver_unit|vsync_state_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_4\ = DFFEAS(\vga_driver_unit|vsync_counter_0\ & !\vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|un14_vsync_counter_8\ & \vga_driver_unit|vsync_state_5\, GLOBAL(\clk_pin~combout\), VCC, , +-- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "2000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_0\, + datab => \vga_driver_unit|vsync_counter_9\, + datac => \vga_driver_unit|un14_vsync_counter_8\, + datad => \vga_driver_unit|vsync_state_5\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_4\); + +\vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_9\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_7\, + datab => \vga_driver_unit|vsync_counter_6\, + datac => \vga_driver_unit|vsync_counter_8\, + datad => \vga_driver_unit|vsync_counter_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_vsync_counter_3\); + +\vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_vsync_counter_4\ = \vga_driver_unit|vsync_counter_5\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un13_vsync_counter_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "c000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|vsync_counter_5\, + datac => \vga_driver_unit|vsync_counter_0\, + datad => \vga_driver_unit|un13_vsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_vsync_counter_4\); + +\vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|vsync_state_4\ & (!\vga_driver_unit|un13_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_7\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0ccc", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|vsync_state_4\, + datac => \vga_driver_unit|un12_vsync_counter_7\, + datad => \vga_driver_unit|un13_vsync_counter_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\); + +\vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ # \vga_driver_unit|vsync_state_2\ & (!\vga_driver_unit|un15_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_6\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff2a", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_state_2\, + datab => \vga_driver_unit|un12_vsync_counter_6\, + datac => \vga_driver_unit|un15_vsync_counter_4\, + datad => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\); + +\vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|vsync_state_5\ & (\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_0\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8ccc", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_9\, + datab => \vga_driver_unit|vsync_state_5\, + datac => \vga_driver_unit|vsync_counter_0\, + datad => \vga_driver_unit|un14_vsync_counter_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\); + +\vga_driver_unit|vsync_state_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ = C1_vsync_state_3 & (!\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_0\) +-- \vga_driver_unit|vsync_state_3\ = DFFEAS(\vga_driver_unit|vsync_state_next_1_sqmuxa_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, \vga_driver_unit|vsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "70f0", + operation_mode => "normal", + output_mode => "reg_and_comb", + register_cascade_mode => "off", + sum_lutc_input => "qfbk", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_0\, + datab => \vga_driver_unit|vsync_counter_9\, + datac => \vga_driver_unit|vsync_state_1\, + datad => \vga_driver_unit|un14_vsync_counter_8\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + sload => VCC, + ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\, + regout => \vga_driver_unit|vsync_state_3\); + +\vga_driver_unit|vsync_state_next_2_sqmuxa_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_next_2_sqmuxa\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ & !\vga_driver_unit|vsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|vsync_state_next_1_sqmuxa_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "aaab", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un6_dly_counter_0_x\, + datab => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\, + datac => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\, + datad => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_next_2_sqmuxa\); + +\vga_driver_unit|vsync_state_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_2\ = DFFEAS(\vga_driver_unit|un14_vsync_counter_8\ & \vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|vsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , +-- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un14_vsync_counter_8\, + datab => \vga_driver_unit|vsync_counter_9\, + datac => \vga_driver_unit|vsync_counter_0\, + datad => \vga_driver_unit|vsync_state_3\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_2\); + +\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ = \vga_driver_unit|un12_vsync_counter_6\ & \vga_driver_unit|un15_vsync_counter_4\ & \vga_driver_unit|vsync_state_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "c000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|un12_vsync_counter_6\, + datac => \vga_driver_unit|un15_vsync_counter_4\, + datad => \vga_driver_unit|vsync_state_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\); + +\vga_driver_unit|vsync_state_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_0\ = DFFEAS(\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ & (\vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\ # !\vga_driver_unit|un6_dly_counter_0_x\) # +-- !\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ & (\vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "22f2", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\, + datab => \vga_driver_unit|un6_dly_counter_0_x\, + datac => \vga_driver_unit|vsync_state_0\, + datad => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_0\); + +\vga_driver_unit|d_set_vsync_counter_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|d_set_vsync_counter\ = \vga_driver_unit|vsync_state_6\ # \vga_driver_unit|vsync_state_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ffcc", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|vsync_state_6\, + datad => \vga_driver_unit|vsync_state_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|d_set_vsync_counter\); + +\vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_next_1_sqmuxa\ = dly_counter(1) & \reset_pin~combout\ & !\vga_driver_unit|d_set_vsync_counter\ & dly_counter(0) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0800", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => dly_counter(1), + datab => \reset_pin~combout\, + datac => \vga_driver_unit|d_set_vsync_counter\, + datad => dly_counter(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_counter_next_1_sqmuxa\); + +\vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_vsync_counter_7\ = !\vga_driver_unit|vsync_counter_4\ & !\vga_driver_unit|vsync_counter_2\ & !\vga_driver_unit|vsync_counter_3\ & !\vga_driver_unit|vsync_counter_1\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_4\, + datab => \vga_driver_unit|vsync_counter_2\, + datac => \vga_driver_unit|vsync_counter_3\, + datad => \vga_driver_unit|vsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_vsync_counter_7\); + +\vga_driver_unit|vsync_state_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_1\ = DFFEAS(\vga_driver_unit|un12_vsync_counter_7\ & !\vga_driver_unit|un6_dly_counter_0_x\ & \vga_driver_unit|un13_vsync_counter_4\ & \vga_driver_unit|vsync_state_4\, GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "2000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un12_vsync_counter_7\, + datab => \vga_driver_unit|un6_dly_counter_0_x\, + datac => \vga_driver_unit|un13_vsync_counter_4\, + datad => \vga_driver_unit|vsync_state_4\, + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_1\); + +\vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|vsync_state_4\ & (!\vga_driver_unit|vsync_state_5\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ccdd", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_state_4\, + datab => \vga_driver_unit|un6_dly_counter_0_x\, + datad => \vga_driver_unit|vsync_state_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\); + +\vga_driver_unit|h_enable_sig_Z\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|h_enable_sig\ = DFFEAS(\vga_driver_unit|vsync_state_1\ # \vga_driver_unit|vsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ffcc", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|vsync_state_1\, + datad => \vga_driver_unit|vsync_state_3\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|h_enable_sig\); + +\vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|hsync_state_5\ & !\vga_driver_unit|hsync_state_4\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "aaaf", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un6_dly_counter_0_x\, + datac => \vga_driver_unit|hsync_state_5\, + datad => \vga_driver_unit|hsync_state_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\); + +\vga_driver_unit|v_enable_sig_Z\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|v_enable_sig\ = DFFEAS(\vga_driver_unit|hsync_state_1\ # \vga_driver_unit|hsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fcfc", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_state_1\, + datac => \vga_driver_unit|hsync_state_3\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|v_enable_sig\); + +\vga_control_unit|r_next_i_o7_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|r_next_i_o7\ = \vga_driver_unit|column_counter_sig_9\ # !\vga_driver_unit|v_enable_sig\ # !\vga_driver_unit|h_enable_sig\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f3ff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|h_enable_sig\, + datac => \vga_driver_unit|column_counter_sig_9\, + datad => \vga_driver_unit|v_enable_sig\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|r_next_i_o7\); + +\vga_control_unit|N_4_i_0_g0_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|N_4_i_0_g0_1\ = !\vga_control_unit|r_next_i_o7\ & (\vga_driver_unit|column_counter_sig_8\ # \vga_control_unit|g_next_i_o3\ & \vga_driver_unit|column_counter_sig_7\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "00f8", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_control_unit|g_next_i_o3\, + datab => \vga_driver_unit|column_counter_sig_7\, + datac => \vga_driver_unit|column_counter_sig_8\, + datad => \vga_control_unit|r_next_i_o7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|N_4_i_0_g0_1\); + +\vga_control_unit|r_Z\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|r\ = DFFEAS(\vga_control_unit|N_4_i_0_g0_1\ & (\vga_driver_unit|column_counter_sig_8\ & (!\vga_control_unit|b_next_i_o3_0\) # !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|un10_column_counter_siglt6_3\), +-- GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1d00", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un10_column_counter_siglt6_3\, + datab => \vga_driver_unit|column_counter_sig_8\, + datac => \vga_control_unit|b_next_i_o3_0\, + datad => \vga_control_unit|N_4_i_0_g0_1\, + aclr => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_control_unit|r\); + +\vga_control_unit|N_23_i_0_g0_a_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|N_23_i_0_g0_a\ = \vga_driver_unit|column_counter_sig_5\ & (\vga_driver_unit|column_counter_sig_6\ & (!\vga_control_unit|g_next_i_o3\) # !\vga_driver_unit|column_counter_sig_6\ & (\vga_control_unit|g_next_i_o3\ # +-- !\vga_driver_unit|un10_column_counter_siglt6_1\)) # !\vga_driver_unit|column_counter_sig_5\ & (\vga_driver_unit|column_counter_sig_6\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "5af2", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_5\, + datab => \vga_driver_unit|un10_column_counter_siglt6_1\, + datac => \vga_driver_unit|column_counter_sig_6\, + datad => \vga_control_unit|g_next_i_o3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|N_23_i_0_g0_a\); + +\vga_control_unit|g_Z\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|g\ = DFFEAS(\vga_driver_unit|column_counter_sig_7\ & !\vga_driver_unit|column_counter_sig_8\ & \vga_control_unit|N_23_i_0_g0_a\ & !\vga_control_unit|r_next_i_o7\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), +-- , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0020", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|column_counter_sig_7\, + datab => \vga_driver_unit|column_counter_sig_8\, + datac => \vga_control_unit|N_23_i_0_g0_a\, + datad => \vga_control_unit|r_next_i_o7\, + aclr => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_control_unit|g\); + +\vga_control_unit|b_next_i_a7_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|b_next_i_a7_1\ = !\vga_driver_unit|column_counter_sig_2\ & !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\ & !\vga_control_unit|g_next_i_o3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_2\, + datab => \vga_driver_unit|column_counter_sig_8\, + datac => \vga_driver_unit|column_counter_sig_7\, + datad => \vga_control_unit|g_next_i_o3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|b_next_i_a7_1\); + +\vga_control_unit|N_6_i_0_g0_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|N_6_i_0_g0_0\ = !\vga_control_unit|r_next_i_o7\ & (\vga_driver_unit|column_counter_sig_7\ # \vga_driver_unit|column_counter_sig_8\ # !\vga_driver_unit|un10_column_counter_siglt6_3\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "00ef", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_7\, + datab => \vga_driver_unit|column_counter_sig_8\, + datac => \vga_driver_unit|un10_column_counter_siglt6_3\, + datad => \vga_control_unit|r_next_i_o7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|N_6_i_0_g0_0\); + +\vga_control_unit|b_Z\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|b\ = DFFEAS(!\vga_control_unit|b_next_i_a7_1\ & \vga_control_unit|N_6_i_0_g0_0\ & (!\vga_driver_unit|column_counter_sig_8\ # !\vga_control_unit|b_next_i_o3_0\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , +-- , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1050", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_control_unit|b_next_i_a7_1\, + datab => \vga_control_unit|b_next_i_o3_0\, + datac => \vga_control_unit|N_6_i_0_g0_0\, + datad => \vga_driver_unit|column_counter_sig_8\, + aclr => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_control_unit|b\); + +\vga_driver_unit|un1_hsync_state_3_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_hsync_state_3_0\ = \vga_driver_unit|hsync_state_1\ # \vga_driver_unit|hsync_state_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fcfc", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|hsync_state_1\, + datac => \vga_driver_unit|hsync_state_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_hsync_state_3_0\); + +\vga_driver_unit|h_sync_1_0_0_0_g1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|h_sync_1_0_0_0_g1\ = \vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|hsync_state_2\ & +-- \vga_driver_unit|hsync_state_4\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fe02", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_state_4\, + datab => \vga_driver_unit|un1_hsync_state_3_0\, + datac => \vga_driver_unit|hsync_state_2\, + datad => \vga_driver_unit|h_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|h_sync_1_0_0_0_g1\); + +\vga_driver_unit|h_sync_Z\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|h_sync\ = DFFEAS(\vga_driver_unit|h_sync_1_0_0_0_g1\ # !dly_counter(0) # !dly_counter(1) # !\reset_pin~combout\, GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "bfff", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|h_sync_1_0_0_0_g1\, + datab => \reset_pin~combout\, + datac => dly_counter(1), + datad => dly_counter(0), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|h_sync\); + +\vga_driver_unit|un1_vsync_state_2_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_vsync_state_2_0\ = \vga_driver_unit|vsync_state_1\ # \vga_driver_unit|vsync_state_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fff0", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datac => \vga_driver_unit|vsync_state_1\, + datad => \vga_driver_unit|vsync_state_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_vsync_state_2_0\); + +\vga_driver_unit|v_sync_1_0_0_0_g1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|v_sync_1_0_0_0_g1\ = \vga_driver_unit|vsync_state_2\ & \vga_driver_unit|v_sync\ # !\vga_driver_unit|vsync_state_2\ & (\vga_driver_unit|un1_vsync_state_2_0\ & \vga_driver_unit|v_sync\ # !\vga_driver_unit|un1_vsync_state_2_0\ & +-- (\vga_driver_unit|vsync_state_4\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "aba8", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|v_sync\, + datab => \vga_driver_unit|vsync_state_2\, + datac => \vga_driver_unit|un1_vsync_state_2_0\, + datad => \vga_driver_unit|vsync_state_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|v_sync_1_0_0_0_g1\); + +\vga_driver_unit|v_sync_Z\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|v_sync\ = DFFEAS(\vga_driver_unit|v_sync_1_0_0_0_g1\ # !dly_counter(1) # !dly_counter(0) # !\reset_pin~combout\, GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff7f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + datad => \vga_driver_unit|v_sync_1_0_0_0_g1\, + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|v_sync\); + +\~STRATIX_FITTER_CREATED_GND~I\ : stratix_lcell +-- Equation(s): +-- \~STRATIX_FITTER_CREATED_GND~I_combout\ = GND + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \~STRATIX_FITTER_CREATED_GND~I_combout\); + +\vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ = \reset_pin~combout\ & !\vga_driver_unit|vsync_state_1\ & dly_counter(1) & dly_counter(0) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "2000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \reset_pin~combout\, + datab => \vga_driver_unit|vsync_state_1\, + datac => dly_counter(1), + datad => dly_counter(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\); + +\vga_driver_unit|un1_line_counter_sig_a_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_a_cout\(1) = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\) +-- \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff88", + operation_mode => "arithmetic", + output_mode => "none", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_0\, + datab => \vga_driver_unit|d_set_hsync_counter\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\, + cout0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1), + cout1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\); + +\vga_driver_unit|un1_line_counter_sig_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(2) = \vga_driver_unit|line_counter_sig_1\ $ \vga_driver_unit|un1_line_counter_sig_a_cout\(1) +-- \vga_driver_unit|un1_line_counter_sig_cout\(2) = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout\(1) # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\) +-- \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "3c7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_2\, + datab => \vga_driver_unit|line_counter_sig_1\, + cin0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1), + cin1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(2), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(2), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\); + +\vga_driver_unit|line_counter_sig_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_1\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(2) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(2), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_1\); + +\vga_driver_unit|un1_line_counter_sig_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(1) = \vga_driver_unit|line_counter_sig_0\ $ \vga_driver_unit|d_set_hsync_counter\ +-- \vga_driver_unit|un1_line_counter_sig_cout\(1) = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\) +-- \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "6688", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_0\, + datab => \vga_driver_unit|d_set_hsync_counter\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(1), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(1), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\); + +\vga_driver_unit|un1_line_counter_sig_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(3) = \vga_driver_unit|line_counter_sig_2\ $ (\vga_driver_unit|line_counter_sig_1\ & \vga_driver_unit|un1_line_counter_sig_cout\(1)) +-- \vga_driver_unit|un1_line_counter_sig_cout\(3) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(1) # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\) +-- \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "6c7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_1\, + datab => \vga_driver_unit|line_counter_sig_2\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(1), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(3), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(3), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\); + +\vga_driver_unit|line_counter_sig_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_2\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(3) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(3), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_2\); + +\vga_driver_unit|un1_line_counter_sig_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(4) = \vga_driver_unit|line_counter_sig_3\ $ !\vga_driver_unit|un1_line_counter_sig_cout\(2) +-- \vga_driver_unit|un1_line_counter_sig_cout\(4) = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(2)) +-- \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "c308", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_4\, + datab => \vga_driver_unit|line_counter_sig_3\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(2), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(4), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(4), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\); + +\vga_driver_unit|line_counter_sig_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_3\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(4) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f3f3", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_line_counter_siglto8\, + datac => \vga_driver_unit|un1_line_counter_sig_combout\(4), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_3\); + +\vga_driver_unit|un1_line_counter_sig_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(5) = \vga_driver_unit|line_counter_sig_4\ $ (\vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3)) +-- \vga_driver_unit|un1_line_counter_sig_cout\(5) = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3)) +-- \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a608", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_4\, + datab => \vga_driver_unit|line_counter_sig_3\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(3), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(5), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(5), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\); + +\vga_driver_unit|line_counter_sig_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_4\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(5) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(5), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_4\); + +\vga_driver_unit|un1_line_counter_sig_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(6) = \vga_driver_unit|line_counter_sig_5\ $ (\vga_driver_unit|un1_line_counter_sig_cout\(4)) +-- \vga_driver_unit|un1_line_counter_sig_cout\(6) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(4) # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\) +-- \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "5a7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_5\, + datab => \vga_driver_unit|line_counter_sig_6\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(4), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(6), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(6), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\); + +\vga_driver_unit|line_counter_sig_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_5\ = DFFEAS(\vga_driver_unit|un10_line_counter_siglto8\ & (\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ & \vga_driver_unit|un1_line_counter_sig_combout\(6)), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un10_line_counter_siglto8\, + datac => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(6), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_5\); + +\vga_driver_unit|un1_line_counter_sig_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(7) = \vga_driver_unit|line_counter_sig_6\ $ (\vga_driver_unit|line_counter_sig_5\ & \vga_driver_unit|un1_line_counter_sig_cout\(5)) +-- \vga_driver_unit|un1_line_counter_sig_cout\(7) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(5) # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\) +-- \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "6a7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_6\, + datab => \vga_driver_unit|line_counter_sig_5\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(5), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(7), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(7), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\); + +\vga_driver_unit|line_counter_sig_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_6\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(7) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f0ff", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un1_line_counter_sig_combout\(7), + datad => \vga_driver_unit|un10_line_counter_siglto8\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_6\); + +\vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_line_counter_siglt4_2\ = !\vga_driver_unit|line_counter_sig_0\ # !\vga_driver_unit|line_counter_sig_3\ # !\vga_driver_unit|line_counter_sig_4\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "77ff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_4\, + datab => \vga_driver_unit|line_counter_sig_3\, + datad => \vga_driver_unit|line_counter_sig_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_line_counter_siglt4_2\); + +\vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_line_counter_siglto5\ = !\vga_driver_unit|line_counter_sig_5\ & (\vga_driver_unit|un10_line_counter_siglt4_2\ # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0f07", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_1\, + datab => \vga_driver_unit|line_counter_sig_2\, + datac => \vga_driver_unit|line_counter_sig_5\, + datad => \vga_driver_unit|un10_line_counter_siglt4_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_line_counter_siglto5\); + +\vga_driver_unit|un1_line_counter_sig_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(8) = \vga_driver_unit|line_counter_sig_7\ $ (!\vga_driver_unit|un1_line_counter_sig_cout\(6)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a5a5", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_7\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(6), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(8)); + +\vga_driver_unit|line_counter_sig_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_7\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(8) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(8), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_7\); + +\vga_driver_unit|un1_line_counter_sig_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(9) = \vga_driver_unit|line_counter_sig_8\ $ (\vga_driver_unit|line_counter_sig_7\ & !\vga_driver_unit|un1_line_counter_sig_cout\(7)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "f30c", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|line_counter_sig_7\, + datad => \vga_driver_unit|line_counter_sig_8\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(7), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(9)); + +\vga_driver_unit|line_counter_sig_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_8\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(9) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff33", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(9), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_8\); + +\vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_line_counter_siglto8\ = \vga_driver_unit|un10_line_counter_siglto5\ # !\vga_driver_unit|line_counter_sig_8\ # !\vga_driver_unit|line_counter_sig_7\ # !\vga_driver_unit|line_counter_sig_6\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "dfff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_6\, + datab => \vga_driver_unit|un10_line_counter_siglto5\, + datac => \vga_driver_unit|line_counter_sig_7\, + datad => \vga_driver_unit|line_counter_sig_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_line_counter_siglto8\); + +\vga_driver_unit|line_counter_sig_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_0\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(1) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff33", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(1), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_0\); + +r0_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|r\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_r0_pin); + +r1_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|r\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_r1_pin); + +r2_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|r\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_r2_pin); + +g0_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|g\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_g0_pin); + +g1_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|g\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_g1_pin); + +g2_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|g\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_g2_pin); + +b0_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|b\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_b0_pin); + +b1_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|b\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_b1_pin); + +hsync_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|h_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_hsync_pin); + +vsync_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|v_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_vsync_pin); + +\seven_seg_pin_tri_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(0)); + +\seven_seg_pin_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(1)); + +\seven_seg_pin_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(2)); + +\seven_seg_pin_tri_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(3)); + +\seven_seg_pin_tri_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(4)); + +\seven_seg_pin_tri_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(5)); + +\seven_seg_pin_tri_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(6)); + +\seven_seg_pin_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(7)); + +\seven_seg_pin_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(8)); + +\seven_seg_pin_out_9_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(9)); + +\seven_seg_pin_out_10_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(10)); + +\seven_seg_pin_out_11_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(11)); + +\seven_seg_pin_out_12_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(12)); + +\seven_seg_pin_tri_13_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(13)); + +d_hsync_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|h_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync); + +d_vsync_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|v_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync); + +\d_column_counter_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(0)); + +\d_column_counter_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(1)); + +\d_column_counter_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(2)); + +\d_column_counter_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(3)); + +\d_column_counter_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(4)); + +\d_column_counter_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(5)); + +\d_column_counter_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(6)); + +\d_column_counter_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(7)); + +\d_column_counter_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(8)); + +\d_column_counter_out_9_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(9)); + +\d_line_counter_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(0)); + +\d_line_counter_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(1)); + +\d_line_counter_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(2)); + +\d_line_counter_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(3)); + +\d_line_counter_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(4)); + +\d_line_counter_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(5)); + +\d_line_counter_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(6)); + +\d_line_counter_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(7)); + +\d_line_counter_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(8)); + +d_set_column_counter_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_set_column_counter); + +d_set_line_counter_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_set_line_counter); + +\d_hsync_counter_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(0)); + +\d_hsync_counter_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(1)); + +\d_hsync_counter_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(2)); + +\d_hsync_counter_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(3)); + +\d_hsync_counter_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(4)); + +\d_hsync_counter_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(5)); + +\d_hsync_counter_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(6)); + +\d_hsync_counter_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(7)); + +\d_hsync_counter_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(8)); + +\d_hsync_counter_out_9_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(9)); + +\d_vsync_counter_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(0)); + +\d_vsync_counter_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(1)); + +\d_vsync_counter_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(2)); + +\d_vsync_counter_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(3)); + +\d_vsync_counter_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(4)); + +\d_vsync_counter_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(5)); + +\d_vsync_counter_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(6)); + +\d_vsync_counter_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(7)); + +\d_vsync_counter_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(8)); + +\d_vsync_counter_out_9_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(9)); + +d_set_hsync_counter_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|d_set_hsync_counter\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_set_hsync_counter); + +d_set_vsync_counter_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|d_set_vsync_counter\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_set_vsync_counter); + +d_h_enable_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|h_enable_sig\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_h_enable); + +d_v_enable_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|v_enable_sig\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_v_enable); + +d_r_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|r\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_r); + +d_g_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|g\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_g); + +d_b_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|b\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_b); + +\d_hsync_state_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(6)); + +\d_hsync_state_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(5)); + +\d_hsync_state_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(4)); + +\d_hsync_state_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(3)); + +\d_hsync_state_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(2)); + +\d_hsync_state_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(1)); + +\d_hsync_state_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(0)); + +\d_vsync_state_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(6)); + +\d_vsync_state_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(5)); + +\d_vsync_state_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(4)); + +\d_vsync_state_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(3)); + +\d_vsync_state_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(2)); + +\d_vsync_state_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(1)); + +\d_vsync_state_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(0)); + +d_state_clk_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \clk_pin~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_state_clk); +END structure; + + diff --git a/bsp3/Designflow/ppr/sim/simulation/modelsim/vga_modelsim.xrf b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga_modelsim.xrf new file mode 100644 index 0000000..3829bd3 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga_modelsim.xrf @@ -0,0 +1,212 @@ +vendor_name = ModelSim +source_file = 1, /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm +source_file = 1, /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/db/vga.cbx.xml +design_name = vga +instance = comp, \dly_counter_1_\, dly_counter_1_, vga, 1 +instance = comp, \dly_counter_0_\, dly_counter_0_, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_6_\, vga_driver_unit|vsync_state_6_, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_6_\, vga_driver_unit|hsync_state_6_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_0_\, vga_driver_unit|hsync_counter_0_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_1_\, vga_driver_unit|hsync_counter_1_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_2_\, vga_driver_unit|hsync_counter_2_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_3_\, vga_driver_unit|hsync_counter_3_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_4_\, vga_driver_unit|hsync_counter_4_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_5_\, vga_driver_unit|hsync_counter_5_, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7\, vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_6_\, vga_driver_unit|hsync_counter_6_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_7_\, vga_driver_unit|hsync_counter_7_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_8_\, vga_driver_unit|hsync_counter_8_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_9_\, vga_driver_unit|hsync_counter_9_, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3\, vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9\, vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9, vga, 1 +instance = comp, \vga_driver_unit|G_2\, vga_driver_unit|G_2, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2\, vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter\, vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4\, vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3\, vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter\, vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_3_\, vga_driver_unit|hsync_state_3_, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4\, vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_5_\, vga_driver_unit|hsync_state_5_, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1\, vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ\, vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3\, vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2\, vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ\, vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ\, vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_2_\, vga_driver_unit|hsync_state_2_, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_0_\, vga_driver_unit|hsync_state_0_, vga, 1 +instance = comp, \vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ\, vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ, vga, 1 +instance = comp, \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3\, vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_4_\, vga_driver_unit|hsync_state_4_, vga, 1 +instance = comp, \vga_driver_unit|hsync_state_1_\, vga_driver_unit|hsync_state_1_, vga, 1 +instance = comp, \vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ\, vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_0_\, vga_driver_unit|column_counter_sig_0_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_1_\, vga_driver_unit|un2_column_counter_next_1_, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_1_\, vga_driver_unit|column_counter_sig_1_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_3_\, vga_driver_unit|un2_column_counter_next_3_, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_3_\, vga_driver_unit|column_counter_sig_3_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_0_\, vga_driver_unit|un2_column_counter_next_0_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_2_\, vga_driver_unit|un2_column_counter_next_2_, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_2_\, vga_driver_unit|column_counter_sig_2_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_4_\, vga_driver_unit|un2_column_counter_next_4_, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_4_\, vga_driver_unit|column_counter_sig_4_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_5_\, vga_driver_unit|un2_column_counter_next_5_, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_5_\, vga_driver_unit|column_counter_sig_5_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_7_\, vga_driver_unit|un2_column_counter_next_7_, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_7_\, vga_driver_unit|column_counter_sig_7_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_6_\, vga_driver_unit|un2_column_counter_next_6_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_8_\, vga_driver_unit|un2_column_counter_next_8_, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_8_\, vga_driver_unit|column_counter_sig_8_, vga, 1 +instance = comp, \vga_driver_unit|un2_column_counter_next_9_\, vga_driver_unit|un2_column_counter_next_9_, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_9_\, vga_driver_unit|column_counter_sig_9_, vga, 1 +instance = comp, \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1\, vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1, vga, 1 +instance = comp, \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6\, vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6, vga, 1 +instance = comp, \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9\, vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9, vga, 1 +instance = comp, \vga_driver_unit|column_counter_sig_6_\, vga_driver_unit|column_counter_sig_6_, vga, 1 +instance = comp, \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3\, vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3, vga, 1 +instance = comp, \vga_control_unit|b_next_i_o3_0_cZ\, vga_control_unit|b_next_i_o3_0_cZ, vga, 1 +instance = comp, \vga_control_unit|g_next_i_o3_cZ\, vga_control_unit|g_next_i_o3_cZ, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_0_\, vga_driver_unit|vsync_counter_0_, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_1_\, vga_driver_unit|vsync_counter_1_, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_2_\, vga_driver_unit|vsync_counter_2_, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_3_\, vga_driver_unit|vsync_counter_3_, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_4_\, vga_driver_unit|vsync_counter_4_, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_5_\, vga_driver_unit|vsync_counter_5_, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6\, vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_6_\, vga_driver_unit|vsync_counter_6_, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_7_\, vga_driver_unit|vsync_counter_7_, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_8_\, vga_driver_unit|vsync_counter_8_, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_9_\, vga_driver_unit|vsync_counter_9_, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5\, vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9\, vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9, vga, 1 +instance = comp, \vga_driver_unit|G_16\, vga_driver_unit|G_16, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6\, vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3\, vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4\, vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8\, vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_5_\, vga_driver_unit|vsync_state_5_, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_4_\, vga_driver_unit|vsync_state_4_, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3\, vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4\, vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ\, vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ, vga, 1 +instance = comp, \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ\, vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ\, vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_3_\, vga_driver_unit|vsync_state_3_, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_next_2_sqmuxa_cZ\, vga_driver_unit|vsync_state_next_2_sqmuxa_cZ, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_2_\, vga_driver_unit|vsync_state_2_, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\, vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_0_\, vga_driver_unit|vsync_state_0_, vga, 1 +instance = comp, \vga_driver_unit|d_set_vsync_counter_cZ\, vga_driver_unit|d_set_vsync_counter_cZ, vga, 1 +instance = comp, \vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ\, vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ, vga, 1 +instance = comp, \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7\, vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7, vga, 1 +instance = comp, \vga_driver_unit|vsync_state_1_\, vga_driver_unit|vsync_state_1_, vga, 1 +instance = comp, \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ\, vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ, vga, 1 +instance = comp, \vga_driver_unit|h_enable_sig_Z\, vga_driver_unit|h_enable_sig_Z, vga, 1 +instance = comp, \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ\, vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ, vga, 1 +instance = comp, \vga_driver_unit|v_enable_sig_Z\, vga_driver_unit|v_enable_sig_Z, vga, 1 +instance = comp, \vga_control_unit|r_next_i_o7_cZ\, vga_control_unit|r_next_i_o7_cZ, vga, 1 +instance = comp, \vga_control_unit|N_4_i_0_g0_1_cZ\, vga_control_unit|N_4_i_0_g0_1_cZ, vga, 1 +instance = comp, \vga_control_unit|r_Z\, vga_control_unit|r_Z, vga, 1 +instance = comp, \vga_control_unit|N_23_i_0_g0_a_cZ\, vga_control_unit|N_23_i_0_g0_a_cZ, vga, 1 +instance = comp, \vga_control_unit|g_Z\, vga_control_unit|g_Z, vga, 1 +instance = comp, \vga_control_unit|b_next_i_a7_1_cZ\, vga_control_unit|b_next_i_a7_1_cZ, vga, 1 +instance = comp, \vga_control_unit|N_6_i_0_g0_0_cZ\, vga_control_unit|N_6_i_0_g0_0_cZ, vga, 1 +instance = comp, \vga_control_unit|b_Z\, vga_control_unit|b_Z, vga, 1 +instance = comp, \vga_driver_unit|un1_hsync_state_3_0_cZ\, vga_driver_unit|un1_hsync_state_3_0_cZ, vga, 1 +instance = comp, \vga_driver_unit|h_sync_1_0_0_0_g1_cZ\, vga_driver_unit|h_sync_1_0_0_0_g1_cZ, vga, 1 +instance = comp, \vga_driver_unit|h_sync_Z\, vga_driver_unit|h_sync_Z, vga, 1 +instance = comp, \vga_driver_unit|un1_vsync_state_2_0_cZ\, vga_driver_unit|un1_vsync_state_2_0_cZ, vga, 1 +instance = comp, \vga_driver_unit|v_sync_1_0_0_0_g1_cZ\, vga_driver_unit|v_sync_1_0_0_0_g1_cZ, vga, 1 +instance = comp, \vga_driver_unit|v_sync_Z\, vga_driver_unit|v_sync_Z, vga, 1 +instance = comp, \~STRATIX_FITTER_CREATED_GND~I\, ~STRATIX_FITTER_CREATED_GND~I, vga, 1 +instance = comp, \vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ\, vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_a_1_\, vga_driver_unit|un1_line_counter_sig_a_1_, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_2_\, vga_driver_unit|un1_line_counter_sig_2_, vga, 1 +instance = comp, \vga_driver_unit|line_counter_sig_1_\, vga_driver_unit|line_counter_sig_1_, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_1_\, vga_driver_unit|un1_line_counter_sig_1_, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_3_\, vga_driver_unit|un1_line_counter_sig_3_, vga, 1 +instance = comp, \vga_driver_unit|line_counter_sig_2_\, vga_driver_unit|line_counter_sig_2_, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_4_\, vga_driver_unit|un1_line_counter_sig_4_, vga, 1 +instance = comp, \vga_driver_unit|line_counter_sig_3_\, vga_driver_unit|line_counter_sig_3_, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_5_\, vga_driver_unit|un1_line_counter_sig_5_, vga, 1 +instance = comp, \vga_driver_unit|line_counter_sig_4_\, vga_driver_unit|line_counter_sig_4_, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_6_\, vga_driver_unit|un1_line_counter_sig_6_, vga, 1 +instance = comp, \vga_driver_unit|line_counter_sig_5_\, vga_driver_unit|line_counter_sig_5_, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_7_\, vga_driver_unit|un1_line_counter_sig_7_, vga, 1 +instance = comp, \vga_driver_unit|line_counter_sig_6_\, vga_driver_unit|line_counter_sig_6_, vga, 1 +instance = comp, \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2\, vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2, vga, 1 +instance = comp, \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5\, vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_8_\, vga_driver_unit|un1_line_counter_sig_8_, vga, 1 +instance = comp, \vga_driver_unit|line_counter_sig_7_\, vga_driver_unit|line_counter_sig_7_, vga, 1 +instance = comp, \vga_driver_unit|un1_line_counter_sig_9_\, vga_driver_unit|un1_line_counter_sig_9_, vga, 1 +instance = comp, \vga_driver_unit|line_counter_sig_8_\, vga_driver_unit|line_counter_sig_8_, vga, 1 +instance = comp, \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8\, vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8, vga, 1 +instance = comp, \vga_driver_unit|line_counter_sig_0_\, vga_driver_unit|line_counter_sig_0_, vga, 1 +instance = comp, \seven_seg_pin_tri_0_\, seven_seg_pin_tri_0_, vga, 1 +instance = comp, \seven_seg_pin_out_1_\, seven_seg_pin_out_1_, vga, 1 +instance = comp, \seven_seg_pin_out_2_\, seven_seg_pin_out_2_, vga, 1 +instance = comp, \seven_seg_pin_tri_3_\, seven_seg_pin_tri_3_, vga, 1 +instance = comp, \seven_seg_pin_tri_4_\, seven_seg_pin_tri_4_, vga, 1 +instance = comp, \seven_seg_pin_tri_5_\, seven_seg_pin_tri_5_, vga, 1 +instance = comp, \seven_seg_pin_tri_6_\, seven_seg_pin_tri_6_, vga, 1 +instance = comp, \seven_seg_pin_out_7_\, seven_seg_pin_out_7_, vga, 1 +instance = comp, \seven_seg_pin_out_8_\, seven_seg_pin_out_8_, vga, 1 +instance = comp, \seven_seg_pin_out_9_\, seven_seg_pin_out_9_, vga, 1 +instance = comp, \seven_seg_pin_out_10_\, seven_seg_pin_out_10_, vga, 1 +instance = comp, \seven_seg_pin_out_11_\, seven_seg_pin_out_11_, vga, 1 +instance = comp, \seven_seg_pin_out_12_\, seven_seg_pin_out_12_, vga, 1 +instance = comp, \seven_seg_pin_tri_13_\, seven_seg_pin_tri_13_, vga, 1 +instance = comp, \d_column_counter_out_0_\, d_column_counter_out_0_, vga, 1 +instance = comp, \d_column_counter_out_1_\, d_column_counter_out_1_, vga, 1 +instance = comp, \d_column_counter_out_2_\, d_column_counter_out_2_, vga, 1 +instance = comp, \d_column_counter_out_3_\, d_column_counter_out_3_, vga, 1 +instance = comp, \d_column_counter_out_4_\, d_column_counter_out_4_, vga, 1 +instance = comp, \d_column_counter_out_5_\, d_column_counter_out_5_, vga, 1 +instance = comp, \d_column_counter_out_6_\, d_column_counter_out_6_, vga, 1 +instance = comp, \d_column_counter_out_7_\, d_column_counter_out_7_, vga, 1 +instance = comp, \d_column_counter_out_8_\, d_column_counter_out_8_, vga, 1 +instance = comp, \d_column_counter_out_9_\, d_column_counter_out_9_, vga, 1 +instance = comp, \d_line_counter_out_0_\, d_line_counter_out_0_, vga, 1 +instance = comp, \d_line_counter_out_1_\, d_line_counter_out_1_, vga, 1 +instance = comp, \d_line_counter_out_2_\, d_line_counter_out_2_, vga, 1 +instance = comp, \d_line_counter_out_3_\, d_line_counter_out_3_, vga, 1 +instance = comp, \d_line_counter_out_4_\, d_line_counter_out_4_, vga, 1 +instance = comp, \d_line_counter_out_5_\, d_line_counter_out_5_, vga, 1 +instance = comp, \d_line_counter_out_6_\, d_line_counter_out_6_, vga, 1 +instance = comp, \d_line_counter_out_7_\, d_line_counter_out_7_, vga, 1 +instance = comp, \d_line_counter_out_8_\, d_line_counter_out_8_, vga, 1 +instance = comp, \d_hsync_counter_out_0_\, d_hsync_counter_out_0_, vga, 1 +instance = comp, \d_hsync_counter_out_1_\, d_hsync_counter_out_1_, vga, 1 +instance = comp, \d_hsync_counter_out_2_\, d_hsync_counter_out_2_, vga, 1 +instance = comp, \d_hsync_counter_out_3_\, d_hsync_counter_out_3_, vga, 1 +instance = comp, \d_hsync_counter_out_4_\, d_hsync_counter_out_4_, vga, 1 +instance = comp, \d_hsync_counter_out_5_\, d_hsync_counter_out_5_, vga, 1 +instance = comp, \d_hsync_counter_out_6_\, d_hsync_counter_out_6_, vga, 1 +instance = comp, \d_hsync_counter_out_7_\, d_hsync_counter_out_7_, vga, 1 +instance = comp, \d_hsync_counter_out_8_\, d_hsync_counter_out_8_, vga, 1 +instance = comp, \d_hsync_counter_out_9_\, d_hsync_counter_out_9_, vga, 1 +instance = comp, \d_vsync_counter_out_0_\, d_vsync_counter_out_0_, vga, 1 +instance = comp, \d_vsync_counter_out_1_\, d_vsync_counter_out_1_, vga, 1 +instance = comp, \d_vsync_counter_out_2_\, d_vsync_counter_out_2_, vga, 1 +instance = comp, \d_vsync_counter_out_3_\, d_vsync_counter_out_3_, vga, 1 +instance = comp, \d_vsync_counter_out_4_\, d_vsync_counter_out_4_, vga, 1 +instance = comp, \d_vsync_counter_out_5_\, d_vsync_counter_out_5_, vga, 1 +instance = comp, \d_vsync_counter_out_6_\, d_vsync_counter_out_6_, vga, 1 +instance = comp, \d_vsync_counter_out_7_\, d_vsync_counter_out_7_, vga, 1 +instance = comp, \d_vsync_counter_out_8_\, d_vsync_counter_out_8_, vga, 1 +instance = comp, \d_vsync_counter_out_9_\, d_vsync_counter_out_9_, vga, 1 +instance = comp, \d_hsync_state_out_6_\, d_hsync_state_out_6_, vga, 1 +instance = comp, \d_hsync_state_out_5_\, d_hsync_state_out_5_, vga, 1 +instance = comp, \d_hsync_state_out_4_\, d_hsync_state_out_4_, vga, 1 +instance = comp, \d_hsync_state_out_3_\, d_hsync_state_out_3_, vga, 1 +instance = comp, \d_hsync_state_out_2_\, d_hsync_state_out_2_, vga, 1 +instance = comp, \d_hsync_state_out_1_\, d_hsync_state_out_1_, vga, 1 +instance = comp, \d_hsync_state_out_0_\, d_hsync_state_out_0_, vga, 1 +instance = comp, \d_vsync_state_out_6_\, d_vsync_state_out_6_, vga, 1 +instance = comp, \d_vsync_state_out_5_\, d_vsync_state_out_5_, vga, 1 +instance = comp, \d_vsync_state_out_4_\, d_vsync_state_out_4_, vga, 1 +instance = comp, \d_vsync_state_out_3_\, d_vsync_state_out_3_, vga, 1 +instance = comp, \d_vsync_state_out_2_\, d_vsync_state_out_2_, vga, 1 +instance = comp, \d_vsync_state_out_1_\, d_vsync_state_out_1_, vga, 1 +instance = comp, \d_vsync_state_out_0_\, d_vsync_state_out_0_, vga, 1 diff --git a/bsp3/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo new file mode 100644 index 0000000..acbb6c4 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo @@ -0,0 +1,4380 @@ +// Copyright (C) 1991-2009 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP1S25F672C6 Package FBGA672 +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga") + (DATE "10/29/2009 17:00:56") + (VENDOR "Altera") + (PROGRAM "Quartus II") + (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE clk_pin_in.inst1) + (DELAY + (ABSOLUTE + (IOPATH padio combout (868:868:868) (868:868:868)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE reset_pin_in.inst1) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1295:1295:1295) (1295:1295:1295)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\dly_counter_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (4768:4768:4768) (4768:4768:4768)) + (PORT datab (469:469:469) (469:469:469)) + (PORT datac (486:486:486) (486:486:486)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\dly_counter_1_\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\dly_counter_0_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (4768:4768:4768) (4768:4768:4768)) + (PORT datab (465:465:465) (465:465:465)) + (PORT datac (485:485:485) (485:485:485)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\dly_counter_0_\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (4777:4777:4777) (4777:4777:4777)) + (PORT datab (476:476:476) (476:476:476)) + (PORT datac (490:490:490) (490:490:490)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (2355:2355:2355) (2355:2355:2355)) + (PORT datad (1131:1131:1131) (1131:1131:1131)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH qfbkin combout (291:291:291) (291:291:291)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lereg) + (DELAY + (ABSOLUTE + (PORT datac (2445:2445:2445) (2445:2445:2445)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (423:423:423) (423:423:423)) + (PORT datac (1704:1704:1704) (1704:1704:1704)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1794:1794:1794) (1794:1794:1794)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (419:419:419)) + (PORT datac (1707:1707:1707) (1707:1707:1707)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1797:1797:1797) (1797:1797:1797)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (444:444:444)) + (PORT datac (1709:1709:1709) (1709:1709:1709)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1799:1799:1799) (1799:1799:1799)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (437:437:437)) + (PORT datac (1712:1712:1712) (1712:1712:1712)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1802:1802:1802) (1802:1802:1802)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (445:445:445)) + (PORT datac (1715:1715:1715) (1715:1715:1715)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout (551:551:551) (551:551:551)) + (IOPATH cin0 cout (135:135:135) (135:135:135)) + (IOPATH cin1 cout (123:123:123) (123:123:123)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1805:1805:1805) (1805:1805:1805)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (420:420:420)) + (PORT datac (1722:1722:1722) (1722:1722:1722)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1812:1812:1812) (1812:1812:1812)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (665:665:665)) + (PORT datab (628:628:628) (628:628:628)) + (PORT datac (650:650:650) (650:650:650)) + (PORT datad (644:644:644) (644:644:644)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (422:422:422) (422:422:422)) + (PORT datac (1721:1721:1721) (1721:1721:1721)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1811:1811:1811) (1811:1811:1811)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (436:436:436)) + (PORT datac (1719:1719:1719) (1719:1719:1719)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1809:1809:1809) (1809:1809:1809)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (445:445:445)) + (PORT datac (1718:1718:1718) (1718:1718:1718)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1808:1808:1808) (1808:1808:1808)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (1717:1717:1717) (1717:1717:1717)) + (PORT datad (432:432:432) (432:432:432)) + (IOPATH datad regin (235:235:235) (235:235:235)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1759:1759:1759) (1759:1759:1759)) + (PORT datac (1807:1807:1807) (1807:1807:1807)) + (PORT sclr (1308:1308:1308) (1308:1308:1308)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (663:663:663)) + (PORT datab (609:609:609) (609:609:609)) + (PORT datac (1034:1034:1034) (1034:1034:1034)) + (PORT datad (636:636:636) (636:636:636)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (963:963:963)) + (PORT datab (934:934:934) (934:934:934)) + (PORT datac (374:374:374) (374:374:374)) + (PORT datad (351:351:351) (351:351:351)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|G_2\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1446:1446:1446) (1446:1446:1446)) + (PORT datab (344:344:344) (344:344:344)) + (PORT datac (626:626:626) (626:626:626)) + (PORT datad (1675:1675:1675) (1675:1675:1675)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (640:640:640)) + (PORT datab (610:610:610) (610:610:610)) + (PORT datac (1035:1035:1035) (1035:1035:1035)) + (PORT datad (652:652:652) (652:652:652)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (924:924:924)) + (PORT datab (627:627:627) (627:627:627)) + (PORT datac (371:371:371) (371:371:371)) + (PORT datad (350:350:350) (350:350:350)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (665:665:665)) + (PORT datab (649:649:649) (649:649:649)) + (PORT datac (1030:1030:1030) (1030:1030:1030)) + (PORT datad (636:636:636) (636:636:636)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (637:637:637)) + (PORT datab (604:604:604) (604:604:604)) + (PORT datac (650:650:650) (650:650:650)) + (PORT datad (637:637:637) (637:637:637)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (656:656:656)) + (PORT datab (929:929:929) (929:929:929)) + (PORT datac (364:364:364) (364:364:364)) + (PORT datad (353:353:353) (353:353:353)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (706:706:706)) + (PORT datab (346:346:346) (346:346:346)) + (PORT datac (926:926:926) (926:926:926)) + (PORT datad (351:351:351) (351:351:351)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH qfbkin combout (291:291:291) (291:291:291)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lereg) + (DELAY + (ABSOLUTE + (PORT datac (1016:1016:1016) (1016:1016:1016)) + (PORT sclr (2456:2456:2456) (2456:2456:2456)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (PORT ena (1257:1257:1257) (1257:1257:1257)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (960:960:960)) + (PORT datab (903:903:903) (903:903:903)) + (PORT datac (959:959:959) (959:959:959)) + (PORT datad (943:943:943) (943:943:943)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (439:439:439) (439:439:439)) + (PORT datac (1416:1416:1416) (1416:1416:1416)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2436:2436:2436) (2436:2436:2436)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (PORT ena (1086:1086:1086) (1086:1086:1086)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (927:927:927)) + (PORT datab (928:928:928) (928:928:928)) + (PORT datad (996:996:996) (996:996:996)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (592:592:592)) + (PORT datab (368:368:368) (368:368:368)) + (PORT datac (462:462:462) (462:462:462)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (956:956:956)) + (PORT datab (909:909:909) (909:909:909)) + (PORT datac (910:910:910) (910:910:910)) + (PORT datad (921:921:921) (921:921:921)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (903:903:903) (903:903:903)) + (PORT datac (951:951:951) (951:951:951)) + (PORT datad (962:962:962) (962:962:962)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (448:448:448)) + (PORT datab (377:377:377) (377:377:377)) + (PORT datac (556:556:556) (556:556:556)) + (PORT datad (568:568:568) (568:568:568)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1669:1669:1669) (1669:1669:1669)) + (PORT datab (554:554:554) (554:554:554)) + (PORT datac (374:374:374) (374:374:374)) + (PORT datad (346:346:346) (346:346:346)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (987:987:987) (987:987:987)) + (PORT datad (558:558:558) (558:558:558)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2436:2436:2436) (2436:2436:2436)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (PORT ena (1086:1086:1086) (1086:1086:1086)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (445:445:445)) + (PORT datac (553:553:553) (553:553:553)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2436:2436:2436) (2436:2436:2436)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (PORT ena (1086:1086:1086) (1086:1086:1086)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (4777:4777:4777) (4777:4777:4777)) + (PORT datab (477:477:477) (477:477:477)) + (PORT datac (969:969:969) (969:969:969)) + (PORT datad (896:896:896) (896:896:896)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (946:946:946) (946:946:946)) + (PORT datac (955:955:955) (955:955:955)) + (PORT datad (921:921:921) (921:921:921)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (878:878:878)) + (PORT datab (367:367:367) (367:367:367)) + (PORT datac (456:456:456) (456:456:456)) + (PORT datad (385:385:385) (385:385:385)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2436:2436:2436) (2436:2436:2436)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (PORT ena (1086:1086:1086) (1086:1086:1086)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (449:449:449)) + (PORT datab (371:371:371) (371:371:371)) + (PORT datac (862:862:862) (862:862:862)) + (PORT datad (571:571:571) (571:571:571)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2436:2436:2436) (2436:2436:2436)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2348:2348:2348) (2348:2348:2348)) + (PORT ena (1086:1086:1086) (1086:1086:1086)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (4774:4774:4774) (4774:4774:4774)) + (PORT datab (475:475:475) (475:475:475)) + (PORT datac (489:489:489) (489:489:489)) + (PORT datad (1416:1416:1416) (1416:1416:1416)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (419:419:419)) + (PORT datac (940:940:940) (940:940:940)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2229:2229:2229) (2229:2229:2229)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (988:988:988)) + (PORT datab (929:929:929) (929:929:929)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (344:344:344)) + (PORT datac (937:937:937) (937:937:937)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2229:2229:2229) (2229:2229:2229)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_3_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (936:936:936)) + (PORT datab (700:700:700) (700:700:700)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (910:910:910) (910:910:910)) + (PORT datad (535:535:535) (535:535:535)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2199:2199:2199) (2199:2199:2199)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_0_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (993:993:993)) + (PORT datab (963:963:963) (963:963:963)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_2_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (451:451:451) (451:451:451)) + (PORT datab (1009:1009:1009) (1009:1009:1009)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (576:576:576)) + (PORT datac (365:365:365) (365:365:365)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2244:2244:2244) (2244:2244:2244)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_4_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (1010:1010:1010)) + (PORT datab (980:980:980) (980:980:980)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (890:890:890) (890:890:890)) + (PORT datac (858:858:858) (858:858:858)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2199:2199:2199) (2199:2199:2199)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_5_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (438:438:438)) + (PORT datab (960:960:960) (960:960:960)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (360:360:360)) + (PORT datac (938:938:938) (938:938:938)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2229:2229:2229) (2229:2229:2229)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_7_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (439:439:439)) + (PORT datab (647:647:647) (647:647:647)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1462:1462:1462)) + (PORT datac (939:939:939) (939:939:939)) + (PORT datad (348:348:348) (348:348:348)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_6_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1054:1054:1054) (1054:1054:1054)) + (PORT datab (917:917:917) (917:917:917)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_8_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datad (439:439:439) (439:439:439)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (366:366:366)) + (PORT datac (572:572:572) (572:572:572)) + (PORT datad (1463:1463:1463) (1463:1463:1463)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un2_column_counter_next_9_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (924:924:924) (924:924:924)) + (PORT datad (426:426:426) (426:426:426)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (941:941:941) (941:941:941)) + (PORT datad (347:347:347) (347:347:347)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2229:2229:2229) (2229:2229:2229)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_1\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (966:966:966) (966:966:966)) + (PORT datac (620:620:620) (620:620:620)) + (PORT datad (619:619:619) (619:619:619)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1013:1013:1013) (1013:1013:1013)) + (PORT datab (350:350:350) (350:350:350)) + (PORT datac (373:373:373) (373:373:373)) + (PORT datad (1014:1014:1014) (1014:1014:1014)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (954:954:954)) + (PORT datab (651:651:651) (651:651:651)) + (PORT datac (933:933:933) (933:933:933)) + (PORT datad (347:347:347) (347:347:347)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (890:890:890) (890:890:890)) + (PORT datac (881:881:881) (881:881:881)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2199:2199:2199) (2199:2199:2199)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_3\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (933:933:933) (933:933:933)) + (PORT datad (685:685:685) (685:685:685)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|b_next_i_o3_0_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1016:1016:1016) (1016:1016:1016)) + (PORT datab (917:917:917) (917:917:917)) + (PORT datac (1056:1056:1056) (1056:1056:1056)) + (PORT datad (992:992:992) (992:992:992)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|g_next_i_o3_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (439:439:439)) + (PORT datad (429:429:429) (429:429:429)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1046:1046:1046)) + (PORT datab (423:423:423) (423:423:423)) + (PORT datac (1004:1004:1004) (1004:1004:1004)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1094:1094:1094) (1094:1094:1094)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (419:419:419)) + (PORT datac (1004:1004:1004) (1004:1004:1004)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1094:1094:1094) (1094:1094:1094)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (444:444:444)) + (PORT datac (1003:1003:1003) (1003:1003:1003)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1093:1093:1093) (1093:1093:1093)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (437:437:437)) + (PORT datac (1002:1002:1002) (1002:1002:1002)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1092:1092:1092) (1092:1092:1092)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (445:445:445)) + (PORT datac (1001:1001:1001) (1001:1001:1001)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout (551:551:551) (551:551:551)) + (IOPATH cin0 cout (135:135:135) (135:135:135)) + (IOPATH cin1 cout (123:123:123) (123:123:123)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1091:1091:1091) (1091:1091:1091)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (420:420:420)) + (PORT datac (1002:1002:1002) (1002:1002:1002)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1092:1092:1092) (1092:1092:1092)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (634:634:634)) + (PORT datab (647:647:647) (647:647:647)) + (PORT datac (940:940:940) (940:940:940)) + (PORT datad (976:976:976) (976:976:976)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (422:422:422) (422:422:422)) + (PORT datac (1002:1002:1002) (1002:1002:1002)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1092:1092:1092) (1092:1092:1092)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (436:436:436)) + (PORT datac (1001:1001:1001) (1001:1001:1001)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1091:1091:1091) (1091:1091:1091)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (445:445:445)) + (PORT datac (1001:1001:1001) (1001:1001:1001)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1091:1091:1091) (1091:1091:1091)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (999:999:999) (999:999:999)) + (PORT datad (432:432:432) (432:432:432)) + (IOPATH datad regin (235:235:235) (235:235:235)) + (IOPATH cin regin (607:607:607) (607:607:607)) + (IOPATH cin0 regin (571:571:571) (571:571:571)) + (IOPATH cin1 regin (587:587:587) (587:587:587)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sload (1429:1429:1429) (1429:1429:1429)) + (PORT datac (1089:1089:1089) (1089:1089:1089)) + (PORT sclr (1316:1316:1316) (1316:1316:1316)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP sload (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD sload (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (996:996:996)) + (PORT datab (971:971:971) (971:971:971)) + (PORT datac (652:652:652) (652:652:652)) + (PORT datad (996:996:996) (996:996:996)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1000:1000:1000)) + (PORT datab (345:345:345) (345:345:345)) + (PORT datac (1071:1071:1071) (1071:1071:1071)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|G_16\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1066:1066:1066)) + (PORT datab (1052:1052:1052) (1052:1052:1052)) + (PORT datac (456:456:456) (456:456:456)) + (PORT datad (354:354:354) (354:354:354)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (624:624:624)) + (PORT datab (584:584:584) (584:584:584)) + (PORT datac (960:960:960) (960:960:960)) + (PORT datad (622:622:622) (622:622:622)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (629:629:629)) + (PORT datab (639:639:639) (639:639:639)) + (PORT datac (656:656:656) (656:656:656)) + (PORT datad (619:619:619) (619:619:619)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (1053:1053:1053) (1053:1053:1053)) + (PORT datac (979:979:979) (979:979:979)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (886:886:886) (886:886:886)) + (PORT datad (854:854:854) (854:854:854)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (947:947:947) (947:947:947)) + (PORT datad (699:699:699) (699:699:699)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1803:1803:1803) (1803:1803:1803)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (PORT ena (1081:1081:1081) (1081:1081:1081)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (969:969:969)) + (PORT datab (673:673:673) (673:673:673)) + (PORT datac (364:364:364) (364:364:364)) + (PORT datad (444:444:444) (444:444:444)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1803:1803:1803) (1803:1803:1803)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (PORT ena (1081:1081:1081) (1081:1081:1081)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (674:674:674)) + (PORT datab (610:610:610) (610:610:610)) + (PORT datac (657:657:657) (657:657:657)) + (PORT datad (683:683:683) (683:683:683)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (924:924:924) (924:924:924)) + (PORT datac (701:701:701) (701:701:701)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (431:431:431) (431:431:431)) + (PORT datac (877:877:877) (877:877:877)) + (PORT datad (253:253:253) (253:253:253)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (433:433:433)) + (PORT datab (871:871:871) (871:871:871)) + (PORT datac (863:863:863) (863:863:863)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (968:968:968)) + (PORT datab (435:435:435) (435:435:435)) + (PORT datac (700:700:700) (700:700:700)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (972:972:972)) + (PORT datab (894:894:894) (894:894:894)) + (PORT datac (1516:1516:1516) (1516:1516:1516)) + (PORT datad (565:565:565) (565:565:565)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH qfbkin combout (291:291:291) (291:291:291)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lereg) + (DELAY + (ABSOLUTE + (PORT datac (1606:1606:1606) (1606:1606:1606)) + (PORT sclr (1138:1138:1138) (1138:1138:1138)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (PORT ena (1299:1299:1299) (1299:1299:1299)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datac (posedge clk) (10:10:10)) + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datac (posedge clk) (100:100:100)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1038:1038:1038)) + (PORT datab (351:351:351) (351:351:351)) + (PORT datac (582:582:582) (582:582:582)) + (PORT datad (564:564:564) (564:564:564)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (888:888:888)) + (PORT datab (671:671:671) (671:671:671)) + (PORT datac (703:703:703) (703:703:703)) + (PORT datad (960:960:960) (960:960:960)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1803:1803:1803) (1803:1803:1803)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (PORT ena (1081:1081:1081) (1081:1081:1081)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (346:346:346)) + (PORT datac (359:359:359) (359:359:359)) + (PORT datad (992:992:992) (992:992:992)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (354:354:354)) + (PORT datab (1046:1046:1046) (1046:1046:1046)) + (PORT datac (451:451:451) (451:451:451)) + (PORT datad (944:944:944) (944:944:944)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|d_set_vsync_counter_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (991:991:991) (991:991:991)) + (PORT datad (946:946:946) (946:946:946)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (636:636:636)) + (PORT datab (4638:4638:4638) (4638:4638:4638)) + (PORT datac (363:363:363) (363:363:363)) + (PORT datad (613:613:613) (613:613:613)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1033:1033:1033) (1033:1033:1033)) + (PORT datab (610:610:610) (610:610:610)) + (PORT datac (662:662:662) (662:662:662)) + (PORT datad (613:613:613) (613:613:613)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1612:1612:1612)) + (PORT datab (1692:1692:1692) (1692:1692:1692)) + (PORT datac (1412:1412:1412) (1412:1412:1412)) + (PORT datad (1529:1529:1529) (1529:1529:1529)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1537:1537:1537)) + (PORT datab (1691:1691:1691) (1691:1691:1691)) + (PORT datad (1518:1518:1518) (1518:1518:1518)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (428:428:428) (428:428:428)) + (PORT datad (1520:1520:1520) (1520:1520:1520)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (2477:2477:2477) (2477:2477:2477)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (PORT ena (1086:1086:1086) (1086:1086:1086)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (968:968:968)) + (PORT datac (1401:1401:1401) (1401:1401:1401)) + (PORT datad (1404:1404:1404) (1404:1404:1404)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (1628:1628:1628) (1628:1628:1628)) + (PORT datac (1512:1512:1512) (1512:1512:1512)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1737:1737:1737) (1737:1737:1737)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (PORT ena (1092:1092:1092) (1092:1092:1092)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (SETUP ena (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + (HOLD ena (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|r_next_i_o7_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (427:427:427) (427:427:427)) + (PORT datac (930:930:930) (930:930:930)) + (PORT datad (1453:1453:1453) (1453:1453:1453)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|N_4_i_0_g0_1_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (895:895:895)) + (PORT datab (648:648:648) (648:648:648)) + (PORT datac (650:650:650) (650:650:650)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|r_Z\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (891:891:891)) + (PORT datab (618:618:618) (618:618:618)) + (PORT datac (551:551:551) (551:551:551)) + (PORT datad (852:852:852) (852:852:852)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_control_unit\|r_Z\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (5163:5163:5163) (5163:5163:5163)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|N_23_i_0_g0_a_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (698:698:698)) + (PORT datab (349:349:349) (349:349:349)) + (PORT datac (934:934:934) (934:934:934)) + (PORT datad (879:879:879) (879:879:879)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|g_Z\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (990:990:990)) + (PORT datab (621:621:621) (621:621:621)) + (PORT datac (860:860:860) (860:860:860)) + (PORT datad (899:899:899) (899:899:899)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_control_unit\|g_Z\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (5163:5163:5163) (5163:5163:5163)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|b_next_i_a7_1_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (449:449:449)) + (PORT datab (436:436:436) (436:436:436)) + (PORT datac (1056:1056:1056) (1056:1056:1056)) + (PORT datad (868:868:868) (868:868:868)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|N_6_i_0_g0_0_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1060:1060:1060) (1060:1060:1060)) + (PORT datab (435:435:435) (435:435:435)) + (PORT datac (557:557:557) (557:557:557)) + (PORT datad (587:587:587) (587:587:587)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_control_unit\|b_Z\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (546:546:546)) + (PORT datab (535:535:535) (535:535:535)) + (PORT datac (559:559:559) (559:559:559)) + (PORT datad (631:631:631) (631:631:631)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_control_unit\|b_Z\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (5163:5163:5163) (5163:5163:5163)) + (PORT clk (2359:2359:2359) (2359:2359:2359)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_hsync_state_3_0_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (1628:1628:1628) (1628:1628:1628)) + (PORT datac (1512:1512:1512) (1512:1512:1512)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|h_sync_1_0_0_0_g1_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1415:1415:1415)) + (PORT datab (335:335:335) (335:335:335)) + (PORT datac (1460:1460:1460) (1460:1460:1460)) + (PORT datad (431:431:431) (431:431:431)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (364:364:364)) + (PORT datab (4641:4641:4641) (4641:4641:4641)) + (PORT datac (635:635:635) (635:635:635)) + (PORT datad (616:616:616) (616:616:616)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_vsync_state_2_0_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (1513:1513:1513) (1513:1513:1513)) + (PORT datad (421:421:421) (421:421:421)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|v_sync_1_0_0_0_g1_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (610:610:610)) + (PORT datab (634:634:634) (634:634:634)) + (PORT datac (403:403:403) (403:403:403)) + (PORT datad (649:649:649) (649:649:649)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (4772:4772:4772) (4772:4772:4772)) + (PORT datab (473:473:473) (473:473:473)) + (PORT datac (488:488:488) (488:488:488)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (4776:4776:4776) (4776:4776:4776)) + (PORT datab (1496:1496:1496) (1496:1496:1496)) + (PORT datac (490:490:490) (490:490:490)) + (PORT datad (660:660:660) (660:660:660)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_a_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1009:1009:1009)) + (PORT datab (556:556:556) (556:556:556)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_2_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (434:434:434)) + (PORT datab (426:426:426) (426:426:426)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (614:614:614) (614:614:614)) + (PORT datad (355:355:355) (355:355:355)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1696:1696:1696) (1696:1696:1696)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_1_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (747:747:747)) + (PORT datab (342:342:342) (342:342:342)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_3_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (664:664:664)) + (PORT datab (695:695:695) (695:695:695)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (610:610:610) (610:610:610)) + (PORT datad (542:542:542) (542:542:542)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1696:1696:1696) (1696:1696:1696)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_4_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (646:646:646)) + (PORT datab (631:631:631) (631:631:631)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (596:596:596) (596:596:596)) + (PORT datac (368:368:368) (368:368:368)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datac regin (364:364:364) (364:364:364)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1696:1696:1696) (1696:1696:1696)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_5_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (678:678:678)) + (PORT datab (679:679:679) (679:679:679)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (613:613:613) (613:613:613)) + (PORT datad (541:541:541) (541:541:541)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1696:1696:1696) (1696:1696:1696)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_6_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (646:646:646)) + (PORT datab (942:942:942) (942:942:942)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (353:353:353)) + (PORT datac (928:928:928) (928:928:928)) + (PORT datad (837:837:837) (837:837:837)) + (IOPATH dataa regin (583:583:583) (583:583:583)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lereg) + (DELAY + (ABSOLUTE + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_7_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (671:671:671)) + (PORT datab (588:588:588) (588:588:588)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + (IOPATH dataa cout0 (443:443:443) (443:443:443)) + (IOPATH datab cout0 (344:344:344) (344:344:344)) + (IOPATH cin0 cout0 (60:60:60) (60:60:60)) + (IOPATH dataa cout1 (451:451:451) (451:451:451)) + (IOPATH datab cout1 (341:341:341) (341:341:341)) + (IOPATH cin1 cout1 (62:62:62) (62:62:62)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (540:540:540) (540:540:540)) + (PORT datad (572:572:572) (572:572:572)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1689:1689:1689) (1689:1689:1689)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (682:682:682)) + (PORT datab (681:681:681) (681:681:681)) + (PORT datad (999:999:999) (999:999:999)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (668:668:668)) + (PORT datab (702:702:702) (702:702:702)) + (PORT datac (437:437:437) (437:437:437)) + (PORT datad (139:139:139) (139:139:139)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_8_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (436:436:436)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datac (611:611:611) (611:611:611)) + (PORT datad (352:352:352) (352:352:352)) + (IOPATH datac regin (364:364:364) (364:364:364)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1696:1696:1696) (1696:1696:1696)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_9_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (636:636:636) (636:636:636)) + (PORT datad (660:660:660) (660:660:660)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datad combout (87:87:87) (87:87:87)) + (IOPATH cin0 combout (432:432:432) (432:432:432)) + (IOPATH cin1 combout (449:449:449) (449:449:449)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (565:565:565) (565:565:565)) + (PORT datad (538:538:538) (538:538:538)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1689:1689:1689) (1689:1689:1689)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8\\.lecomb) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (674:674:674)) + (PORT datab (341:341:341) (341:341:341)) + (PORT datac (653:653:653) (653:653:653)) + (PORT datad (662:662:662) (662:662:662)) + (IOPATH dataa combout (459:459:459) (459:459:459)) + (IOPATH datab combout (332:332:332) (332:332:332)) + (IOPATH datac combout (213:213:213) (213:213:213)) + (IOPATH datad combout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_lcell") + (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lecomb) + (DELAY + (ABSOLUTE + (PORT datab (557:557:557) (557:557:557)) + (PORT datad (533:533:533) (533:533:533)) + (IOPATH datab regin (489:489:489) (489:489:489)) + (IOPATH datad regin (235:235:235) (235:235:235)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_lcell_register") + (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lereg) + (DELAY + (ABSOLUTE + (PORT sclr (1689:1689:1689) (1689:1689:1689)) + (PORT aclr (668:668:668) (668:668:668)) + (PORT clk (2323:2323:2323) (2323:2323:2323)) + (IOPATH (posedge clk) regout (176:176:176) (176:176:176)) + (IOPATH (posedge aclr) regout (212:212:212) (212:212:212)) + ) + ) + (TIMINGCHECK + (SETUP datain (posedge clk) (10:10:10)) + (SETUP sclr (posedge clk) (10:10:10)) + (HOLD datain (posedge clk) (100:100:100)) + (HOLD sclr (posedge clk) (100:100:100)) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE r0_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (4282:4282:4282) (4282:4282:4282)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE r1_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (4282:4282:4282) (4282:4282:4282)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE r2_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (4282:4282:4282) (4282:4282:4282)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE g0_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2951:2951:2951) (2951:2951:2951)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE g1_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2951:2951:2951) (2951:2951:2951)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE g2_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2951:2951:2951) (2951:2951:2951)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE b0_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2828:2828:2828) (2828:2828:2828)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE b1_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2828:2828:2828) (2828:2828:2828)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE hsync_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2955:2955:2955) (2955:2955:2955)) + (IOPATH datain padio (2801:2801:2801) (2801:2801:2801)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE vsync_pin_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2606:2606:2606) (2606:2606:2606)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_tri_0_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1363:1363:1363) (1363:1363:1363)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_out_1_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (4309:4309:4309) (4309:4309:4309)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_out_2_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3697:3697:3697) (3697:3697:3697)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_tri_3_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1273:1273:1273) (1273:1273:1273)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_tri_4_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1273:1273:1273) (1273:1273:1273)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_tri_5_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1363:1363:1363) (1363:1363:1363)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_tri_6_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1363:1363:1363) (1363:1363:1363)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_out_7_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3254:3254:3254) (3254:3254:3254)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_out_8_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3254:3254:3254) (3254:3254:3254)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_out_9_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3697:3697:3697) (3697:3697:3697)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_out_10_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3842:3842:3842) (3842:3842:3842)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_out_11_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3830:3830:3830) (3830:3830:3830)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_out_12_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3254:3254:3254) (3254:3254:3254)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\seven_seg_pin_tri_13_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1363:1363:1363) (1363:1363:1363)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_hsync_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2955:2955:2955) (2955:2955:2955)) + (IOPATH datain padio (2801:2801:2801) (2801:2801:2801)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_vsync_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2606:2606:2606) (2606:2606:2606)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_0_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2176:2176:2176) (2176:2176:2176)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_1_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1905:1905:1905) (1905:1905:1905)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_2_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2327:2327:2327) (2327:2327:2327)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_3_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2207:2207:2207) (2207:2207:2207)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_4_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2378:2378:2378) (2378:2378:2378)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_5_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3095:3095:3095) (3095:3095:3095)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_6_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1888:1888:1888) (1888:1888:1888)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_7_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3062:3062:3062) (3062:3062:3062)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_8_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1984:1984:1984) (1984:1984:1984)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_column_counter_out_9_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2982:2982:2982) (2982:2982:2982)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_line_counter_out_0_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2120:2120:2120) (2120:2120:2120)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_line_counter_out_1_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1873:1873:1873) (1873:1873:1873)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_line_counter_out_2_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2469:2469:2469) (2469:2469:2469)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_line_counter_out_3_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2149:2149:2149) (2149:2149:2149)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_line_counter_out_4_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1892:1892:1892) (1892:1892:1892)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_line_counter_out_5_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2139:2139:2139) (2139:2139:2139)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_line_counter_out_6_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2130:2130:2130) (2130:2130:2130)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_line_counter_out_7_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2400:2400:2400) (2400:2400:2400)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_line_counter_out_8_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2376:2376:2376) (2376:2376:2376)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_set_column_counter_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3450:3450:3450) (3450:3450:3450)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_set_line_counter_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2524:2524:2524) (2524:2524:2524)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_0_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2189:2189:2189) (2189:2189:2189)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_1_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2078:2078:2078) (2078:2078:2078)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_2_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2133:2133:2133) (2133:2133:2133)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_3_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2126:2126:2126) (2126:2126:2126)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_4_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2313:2313:2313) (2313:2313:2313)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_5_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2116:2116:2116) (2116:2116:2116)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_6_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2128:2128:2128) (2128:2128:2128)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_7_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2167:2167:2167) (2167:2167:2167)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_8_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2171:2171:2171) (2171:2171:2171)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_counter_out_9_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2340:2340:2340) (2340:2340:2340)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_0_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2402:2402:2402) (2402:2402:2402)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_1_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2446:2446:2446) (2446:2446:2446)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_2_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2471:2471:2471) (2471:2471:2471)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_3_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2446:2446:2446) (2446:2446:2446)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_4_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2469:2469:2469) (2469:2469:2469)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_5_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (1665:1665:1665) (1665:1665:1665)) + (IOPATH datain padio (2801:2801:2801) (2801:2801:2801)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_6_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2212:2212:2212) (2212:2212:2212)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_7_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2397:2397:2397) (2397:2397:2397)) + (IOPATH datain padio (2801:2801:2801) (2801:2801:2801)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_8_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2401:2401:2401) (2401:2401:2401)) + (IOPATH datain padio (2801:2801:2801) (2801:2801:2801)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_counter_out_9_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2394:2394:2394) (2394:2394:2394)) + (IOPATH datain padio (2801:2801:2801) (2801:2801:2801)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_set_hsync_counter_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2047:2047:2047) (2047:2047:2047)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_set_vsync_counter_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2911:2911:2911) (2911:2911:2911)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_h_enable_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2355:2355:2355) (2355:2355:2355)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_v_enable_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2730:2730:2730) (2730:2730:2730)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_r_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (4250:4250:4250) (4250:4250:4250)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_g_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2951:2951:2951) (2951:2951:2951)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_b_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2828:2828:2828) (2828:2828:2828)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_state_out_6_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3434:3434:3434) (3434:3434:3434)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_state_out_5_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2465:2465:2465) (2465:2465:2465)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_state_out_4_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2351:2351:2351) (2351:2351:2351)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_state_out_3_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2196:2196:2196) (2196:2196:2196)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_state_out_2_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2188:2188:2188) (2188:2188:2188)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_state_out_1_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3450:3450:3450) (3450:3450:3450)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_hsync_state_out_0_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2303:2303:2303) (2303:2303:2303)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_state_out_6_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2148:2148:2148) (2148:2148:2148)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_state_out_5_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2482:2482:2482) (2482:2482:2482)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_state_out_4_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2399:2399:2399) (2399:2399:2399)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_state_out_3_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3927:3927:3927) (3927:3927:3927)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_state_out_2_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2404:2404:2404) (2404:2404:2404)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_state_out_1_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2524:2524:2524) (2524:2524:2524)) + (IOPATH datain padio (2504:2504:2504) (2504:2504:2504)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE \\d_vsync_state_out_0_\\.inst1) + (DELAY + (ABSOLUTE + (PORT datain (3107:3107:3107) (3107:3107:3107)) + (IOPATH datain padio (2801:2801:2801) (2801:2801:2801)) + ) + ) + ) + (CELL + (CELLTYPE "stratix_asynch_io") + (INSTANCE d_state_clk_out.inst1) + (DELAY + (ABSOLUTE + (PORT datain (2588:2588:2588) (2588:2588:2588)) + (IOPATH datain padio (2495:2495:2495) (2495:2495:2495)) + ) + ) + ) +) diff --git a/bsp3/Designflow/ppr/sim/vga.asm.rpt b/bsp3/Designflow/ppr/sim/vga.asm.rpt new file mode 100644 index 0000000..63929eb --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.asm.rpt @@ -0,0 +1,128 @@ +Assembler report for vga +Thu Oct 29 17:00:48 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: vga.sof + 6. Assembler Device Options: vga.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Oct 29 17:00:48 2009 ; +; Revision Name ; vga ; +; Top-level Entity Name ; vga ; +; Family ; Stratix ; +; Device ; EP1S25F672C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Auto-increment JTAG user code for multiple configuration devices ; On ; On ; +; Disable CONF_DONE and nSTATUS pull-ups on configuration device ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Use Checkered Pattern as Uninitialized RAM Content ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++---------------------------+ +; Assembler Generated Files ; ++---------------------------+ +; File Name ; ++---------------------------+ +; vga.sof ; +; vga.pof ; ++---------------------------+ + + ++-----------------------------------+ +; Assembler Device Options: vga.sof ; ++----------------+------------------+ +; Option ; Setting ; ++----------------+------------------+ +; Device ; EP1S25F672C6 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x002DADB7 ; ++----------------+------------------+ + + ++-----------------------------------+ +; Assembler Device Options: vga.pof ; ++--------------------+--------------+ +; Option ; Setting ; ++--------------------+--------------+ +; Device ; EPC8 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x0BFDD53B ; +; Compression Ratio ; 1 ; ++--------------------+--------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 17:00:30 2009 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off vga -c vga +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 269 megabytes + Info: Processing ended: Thu Oct 29 17:00:48 2009 + Info: Elapsed time: 00:00:18 + Info: Total CPU time (on all processors): 00:00:18 + + diff --git a/bsp3/Designflow/ppr/sim/vga.done b/bsp3/Designflow/ppr/sim/vga.done new file mode 100644 index 0000000..a7e1459 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.done @@ -0,0 +1 @@ +Thu Oct 29 17:00:58 2009 diff --git a/bsp3/Designflow/ppr/sim/vga.eda.rpt b/bsp3/Designflow/ppr/sim/vga.eda.rpt new file mode 100644 index 0000000..cb19c18 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.eda.rpt @@ -0,0 +1,94 @@ +EDA Netlist Writer report for vga +Thu Oct 29 17:00:56 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Oct 29 17:00:56 2009 ; +; Revision Name ; vga ; +; Top-level Entity Name ; vga ; +; Family ; Stratix ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Tool Name ; ModelSim-Altera (VHDL) ; +; Generate netlist for functional simulation only ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+------------------------+ + + ++--------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++--------------------------------------------------------------------------------------+ +; Generated Files ; ++--------------------------------------------------------------------------------------+ +; /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho ; +; /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo ; ++--------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II EDA Netlist Writer + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 17:00:55 2009 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vga -c vga +Info: Generated files "vga.vho" and "vga_vhd.sdo" in directory "/homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/simulation/modelsim/" for EDA simulation tool +Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 163 megabytes + Info: Processing ended: Thu Oct 29 17:00:56 2009 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/bsp3/Designflow/ppr/sim/vga.fit.rpt b/bsp3/Designflow/ppr/sim/vga.fit.rpt new file mode 100644 index 0000000..e771696 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.fit.rpt @@ -0,0 +1,1683 @@ +Fitter report for vga +Thu Oct 29 17:00:26 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Input Pins + 11. Output Pins + 12. I/O Bank Usage + 13. All Package Pins + 14. Output Pin Default Load For Reported TCO + 15. Fitter Resource Utilization by Entity + 16. Delay Chain Summary + 17. Pad To Core Delay Chain Fanout + 18. Control Signals + 19. Global & Other Fast Signals + 20. Non-Global High Fan-Out Signals + 21. Interconnect Usage Summary + 22. LAB Logic Elements + 23. LAB-wide Signals + 24. LAB Signals Sourced + 25. LAB Signals Sourced Out + 26. LAB Distinct Inputs + 27. Fitter Device Options + 28. Estimated Delay Added for Hold Timing + 29. Fitter Messages + 30. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------+ +; Fitter Summary ; ++--------------------------+------------------------------------------+ +; Fitter Status ; Successful - Thu Oct 29 17:00:26 2009 ; +; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; +; Revision Name ; vga ; +; Top-level Entity Name ; vga ; +; Family ; Stratix ; +; Device ; EP1S25F672C6 ; +; Timing Models ; Final ; +; Total logic elements ; 141 / 25,660 ( < 1 % ) ; +; Total pins ; 91 / 474 ( 19 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,944,576 ( 0 % ) ; +; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 2 ( 0 % ) ; ++--------------------------+------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP1S25F672C6 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Slow Slew Rate ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.13 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; 6.9% ; ++----------------------------+-------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+--------------------+ +; Type ; Value ; ++-------------------------+--------------------+ +; Placement ; ; +; -- Requested ; 0 / 234 ( 0.00 % ) ; +; -- Achieved ; 0 / 234 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 234 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/vga.pin. + + ++-----------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-------------------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------------------------------------------+ +; Total logic elements ; 141 / 25,660 ( < 1 % ) ; +; -- Combinational with no register ; 79 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 62 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 53 ; +; -- 3 input functions ; 32 ; +; -- 2 input functions ; 54 ; +; -- 1 input functions ; 1 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 107 ; +; -- arithmetic mode ; 34 ; +; -- qfbk mode ; 3 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 49 ; +; -- asynchronous clear/load mode ; 3 ; +; ; ; +; Total registers ; 62 / 28,424 ( < 1 % ) ; +; Total LABs ; 18 / 2,566 ( < 1 % ) ; +; Logic elements in carry chains ; 40 ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 91 / 474 ( 19 % ) ; +; -- Clock pins ; 1 / 16 ( 6 % ) ; +; Global signals ; 2 ; +; M512s ; 0 / 224 ( 0 % ) ; +; M4Ks ; 0 / 138 ( 0 % ) ; +; M-RAMs ; 0 / 2 ( 0 % ) ; +; Total memory bits ; 0 / 1,944,576 ( 0 % ) ; +; Total RAM block bits ; 0 / 1,944,576 ( 0 % ) ; +; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ; +; PLLs ; 0 / 6 ( 0 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; Regional clocks ; 0 / 16 ( 0 % ) ; +; Fast regional clocks ; 0 / 8 ( 0 % ) ; +; SERDES transmitters ; 0 / 78 ( 0 % ) ; +; SERDES receivers ; 0 / 78 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 1% / 1% / 1% ; +; Maximum fan-out node ; clk_pin ; +; Maximum fan-out ; 63 ; +; Highest non-global fan-out signal ; vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; +; Highest non-global fan-out ; 11 ; +; Total fan-out ; 677 ; +; Average fan-out ; 2.91 ; ++---------------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; clk_pin ; R3 ; 1 ; 0 ; 21 ; 0 ; 63 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; reset_pin ; K2 ; 2 ; 0 ; 35 ; 2 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; ++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ +; b0_pin ; B8 ; 3 ; 14 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; b1_pin ; A7 ; 3 ; 14 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_b ; F7 ; 3 ; 14 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[0] ; L6 ; 2 ; 0 ; 32 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[1] ; L7 ; 2 ; 0 ; 32 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[2] ; L4 ; 2 ; 0 ; 33 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[3] ; C11 ; 3 ; 25 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[4] ; Y11 ; 8 ; 29 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[5] ; AD11 ; 8 ; 29 ; 0 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[6] ; E11 ; 3 ; 31 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[7] ; AB11 ; 8 ; 25 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[8] ; F10 ; 3 ; 23 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_column_counter[9] ; A8 ; 3 ; 17 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_g ; W10 ; 8 ; 23 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_h_enable ; M6 ; 2 ; 0 ; 31 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync ; AB13 ; 11 ; 37 ; 0 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[0] ; C10 ; 3 ; 21 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[1] ; L2 ; 2 ; 0 ; 33 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[2] ; K8 ; 2 ; 0 ; 34 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[3] ; L5 ; 2 ; 0 ; 33 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[4] ; AC11 ; 8 ; 27 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[5] ; L3 ; 2 ; 0 ; 33 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[6] ; H10 ; 3 ; 27 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[7] ; A10 ; 3 ; 23 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[8] ; D11 ; 3 ; 25 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_counter[9] ; B10 ; 3 ; 21 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_state[0] ; K5 ; 2 ; 0 ; 34 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_state[1] ; AF12 ; 8 ; 33 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_state[2] ; G10 ; 3 ; 23 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_state[3] ; E10 ; 3 ; 23 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_state[4] ; K6 ; 2 ; 0 ; 34 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_state[5] ; G7 ; 3 ; 17 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_hsync_state[6] ; AE11 ; 8 ; 25 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_line_counter[0] ; G11 ; 3 ; 29 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_line_counter[1] ; K1 ; 2 ; 0 ; 35 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_line_counter[2] ; A9 ; 3 ; 21 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_line_counter[3] ; J8 ; 2 ; 0 ; 35 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_line_counter[4] ; K9 ; 2 ; 0 ; 35 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_line_counter[5] ; D10 ; 3 ; 21 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_line_counter[6] ; G9 ; 3 ; 23 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_line_counter[7] ; F9 ; 3 ; 21 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_line_counter[8] ; AA11 ; 8 ; 31 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_r ; AB10 ; 8 ; 23 ; 0 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_set_column_counter ; AD12 ; 8 ; 33 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_set_hsync_counter ; A12 ; 3 ; 33 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_set_line_counter ; B9 ; 3 ; 17 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_set_vsync_counter ; K25 ; 5 ; 79 ; 35 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_state_clk ; N8 ; 2 ; 0 ; 28 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_v_enable ; C9 ; 3 ; 17 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync ; J19 ; 5 ; 79 ; 35 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[0] ; E12 ; 9 ; 37 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[1] ; C15 ; 4 ; 50 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[2] ; D16 ; 4 ; 54 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[3] ; B16 ; 4 ; 52 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[4] ; H16 ; 4 ; 50 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[5] ; F14 ; 9 ; 37 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[6] ; F15 ; 4 ; 46 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[7] ; F13 ; 9 ; 37 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[8] ; E13 ; 9 ; 37 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_counter[9] ; E14 ; 9 ; 37 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_state[0] ; AA13 ; 11 ; 37 ; 0 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_state[1] ; E9 ; 3 ; 17 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_state[2] ; F12 ; 9 ; 37 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_state[3] ; AA12 ; 11 ; 37 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_state[4] ; B11 ; 3 ; 29 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_state[5] ; K7 ; 2 ; 0 ; 34 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; d_vsync_state[6] ; C12 ; 3 ; 33 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; g0_pin ; AA10 ; 8 ; 23 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; g1_pin ; AF10 ; 8 ; 23 ; 0 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; g2_pin ; Y10 ; 8 ; 23 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; hsync_pin ; AB14 ; 11 ; 37 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; r0_pin ; AF9 ; 8 ; 21 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; r1_pin ; AA9 ; 8 ; 21 ; 0 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; r2_pin ; AD10 ; 8 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[0] ; D18 ; 4 ; 65 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[10] ; M4 ; 2 ; 0 ; 30 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[11] ; M7 ; 2 ; 0 ; 31 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[12] ; J1 ; 2 ; 0 ; 38 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[13] ; C18 ; 4 ; 65 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[1] ; M9 ; 2 ; 0 ; 29 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[2] ; K4 ; 2 ; 0 ; 37 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[3] ; B19 ; 4 ; 67 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[4] ; C19 ; 4 ; 67 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[5] ; B18 ; 4 ; 65 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[6] ; F20 ; 4 ; 65 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[7] ; J6 ; 2 ; 0 ; 38 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[8] ; J2 ; 2 ; 0 ; 38 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; seven_seg_pin[9] ; K3 ; 2 ; 0 ; 37 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; +; vsync_pin ; J20 ; 5 ; 79 ; 35 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ; ++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 1 / 61 ( 2 % ) ; 3.3V ; -- ; +; 2 ; 24 / 59 ( 41 % ) ; 3.3V ; -- ; +; 3 ; 26 / 54 ( 48 % ) ; 3.3V ; -- ; +; 4 ; 12 / 56 ( 21 % ) ; 3.3V ; -- ; +; 5 ; 3 / 59 ( 5 % ) ; 3.3V ; -- ; +; 6 ; 0 / 61 ( 0 % ) ; 3.3V ; -- ; +; 7 ; 0 / 57 ( 0 % ) ; 3.3V ; -- ; +; 8 ; 16 / 54 ( 30 % ) ; 3.3V ; -- ; +; 9 ; 6 / 6 ( 100 % ) ; 3.3V ; -- ; +; 11 ; 4 / 6 ( 67 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; Termination ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+ +; A2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; A3 ; 733 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A4 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; A5 ; 725 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A6 ; 717 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A7 ; 703 ; 3 ; b1_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; A8 ; 702 ; 3 ; d_column_counter[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; A9 ; 695 ; 3 ; d_line_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; A10 ; 684 ; 3 ; d_hsync_counter[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; A11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; A12 ; 656 ; 3 ; d_set_hsync_counter ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; A13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; A14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; A15 ; 640 ; 4 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; A16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; A17 ; 602 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A18 ; 589 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A19 ; 579 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A20 ; 571 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A21 ; 564 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A22 ; 554 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; A24 ; 552 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; A25 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AA1 ; 158 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA2 ; 157 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA3 ; 160 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA4 ; 159 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA5 ; 155 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA6 ; 154 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA7 ; 195 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA8 ; 214 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA9 ; 223 ; 8 ; r1_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AA10 ; 227 ; 8 ; g0_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AA11 ; 251 ; 8 ; d_line_counter[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AA12 ; 269 ; 11 ; d_vsync_state[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AA13 ; 273 ; 11 ; d_vsync_state[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AA14 ; 271 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA15 ; 283 ; 7 ; ^nIO_PULLUP ; ; ; ; -- ; -- ; ; -- ; -- ; +; AA16 ; 304 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA17 ; 316 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA18 ; 324 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA19 ; 334 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA20 ; 344 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA21 ; 350 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AA22 ; 386 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA23 ; 382 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA24 ; 381 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA25 ; 384 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AA26 ; 383 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB1 ; 162 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB2 ; 161 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB3 ; 164 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB4 ; 163 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB5 ; 181 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB6 ; 184 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB7 ; 191 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB8 ; 203 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB9 ; 217 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB10 ; 229 ; 8 ; d_r ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AB11 ; 231 ; 8 ; d_column_counter[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AB12 ; 268 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB13 ; 272 ; 11 ; d_hsync ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AB14 ; 270 ; 11 ; hsync_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AB15 ; 292 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AB16 ; 309 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB17 ; 322 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB18 ; 323 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AB19 ; 336 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB20 ; 346 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB21 ; 351 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB22 ; 365 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AB23 ; 378 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB24 ; 377 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB25 ; 380 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AB26 ; 379 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AC2 ; 165 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC3 ; 168 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC4 ; 167 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC5 ; 171 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC6 ; 185 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC7 ; 186 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC8 ; 201 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC9 ; 215 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC10 ; 224 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC11 ; 239 ; 8 ; d_hsync_counter[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AC12 ; 257 ; 8 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; AC13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AC14 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AC15 ; 293 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC16 ; 307 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC17 ; 328 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC18 ; 338 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC19 ; 339 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC20 ; 349 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC21 ; 355 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC22 ; 369 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC23 ; 368 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AC24 ; 374 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC25 ; 376 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AC26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AD1 ; 166 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AD2 ; 172 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD3 ; 174 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD4 ; 178 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD5 ; 170 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD6 ; 188 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD7 ; 192 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD8 ; 204 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD9 ; 216 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD10 ; 220 ; 8 ; r2_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AD11 ; 247 ; 8 ; d_column_counter[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AD12 ; 256 ; 8 ; d_set_column_counter ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AD13 ; ; ; VCCG_PLL6 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; AD14 ; ; ; VCCA_PLL6 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; AD15 ; 302 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD16 ; 310 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD17 ; 329 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD18 ; 335 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD19 ; 337 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD20 ; 353 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD21 ; 354 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AD22 ; 370 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD23 ; 364 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD24 ; 367 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AD25 ; 373 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AD26 ; 375 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AE2 ; 173 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE3 ; 179 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE4 ; 176 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE5 ; 187 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AE6 ; 194 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE7 ; 189 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE8 ; 206 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE9 ; 218 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; AE10 ; 222 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE11 ; 232 ; 8 ; d_hsync_state[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AE12 ; 259 ; 8 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; AE13 ; ; 11 ; VCC_PLL6_OUTA ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AE14 ; ; ; GNDG_PLL6 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AE15 ; 274 ; 7 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; AE16 ; 313 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE17 ; 319 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE18 ; 330 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE19 ; 340 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE20 ; 343 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE21 ; 352 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE22 ; 363 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE23 ; 366 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE24 ; 371 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE25 ; 358 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AE26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AF3 ; 183 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF4 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AF5 ; 190 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF6 ; 198 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF7 ; 197 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF8 ; 207 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF9 ; 219 ; 8 ; r0_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AF10 ; 230 ; 8 ; g1_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AF11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AF12 ; 258 ; 8 ; d_hsync_state[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; AF13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AF14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; AF15 ; 276 ; 7 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; AF16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AF17 ; 315 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF18 ; 327 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF19 ; 331 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF20 ; 342 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF21 ; 347 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF22 ; 360 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF23 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; AF24 ; 362 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; AF25 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B3 ; 740 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B4 ; 736 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B5 ; 730 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B6 ; 716 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B7 ; 709 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B8 ; 704 ; 3 ; b0_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; B9 ; 698 ; 3 ; d_set_line_counter ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; B10 ; 694 ; 3 ; d_hsync_counter[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; B11 ; 667 ; 3 ; d_vsync_state[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; B12 ; 655 ; 3 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; B13 ; ; ; GNDG_PLL5 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B14 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; B15 ; 638 ; 4 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; B16 ; 610 ; 4 ; d_vsync_counter[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; B17 ; 596 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B18 ; 582 ; 4 ; seven_seg_pin[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; B19 ; 577 ; 4 ; seven_seg_pin[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; B20 ; 567 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B21 ; 563 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B22 ; 551 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B23 ; 548 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B24 ; 543 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B25 ; 544 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; B26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; C1 ; 0 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; C2 ; 738 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C3 ; 731 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C4 ; 742 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C5 ; 743 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C6 ; 729 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C7 ; 728 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C8 ; 710 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C9 ; 699 ; 3 ; d_v_enable ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; C10 ; 692 ; 3 ; d_hsync_counter[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; C11 ; 682 ; 3 ; d_column_counter[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; C12 ; 658 ; 3 ; d_vsync_state[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; C13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; C14 ; ; ; VCCG_PLL5 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; C15 ; 617 ; 4 ; d_vsync_counter[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; C16 ; 605 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C17 ; 592 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C18 ; 581 ; 4 ; seven_seg_pin[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; C19 ; 573 ; 4 ; seven_seg_pin[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; C20 ; 559 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C21 ; 566 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C22 ; 556 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C23 ; 550 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C24 ; 547 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; C25 ; 539 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; C26 ; 541 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; D1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; D2 ; 1 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; D3 ; 744 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D4 ; 741 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D5 ; 735 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D6 ; 722 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D7 ; 727 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; D8 ; 712 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D9 ; 696 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; D10 ; 691 ; 3 ; d_line_counter[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; D11 ; 683 ; 3 ; d_hsync_counter[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; D12 ; 657 ; 3 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ; +; D13 ; ; 9 ; VCC_PLL5_OUTA ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; D14 ; ; ; VCCA_PLL5 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; D15 ; 630 ; 4 ; #TRST ; input ; ; ; -- ; -- ; ; -- ; -- ; +; D16 ; 604 ; 4 ; d_vsync_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; D17 ; 600 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D18 ; 583 ; 4 ; seven_seg_pin[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; D19 ; 575 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D20 ; 562 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D21 ; 561 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D22 ; 546 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D23 ; 545 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; D24 ; 538 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; D25 ; 540 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; D26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; E1 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E2 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E5 ; 726 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E6 ; 723 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E7 ; 713 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E8 ; 706 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E9 ; 697 ; 3 ; d_vsync_state[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; E10 ; 685 ; 3 ; d_hsync_state[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; E11 ; 662 ; 3 ; d_column_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; E12 ; 646 ; 9 ; d_vsync_counter[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; E13 ; 642 ; 9 ; d_vsync_counter[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; E14 ; 644 ; 9 ; d_vsync_counter[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; E15 ; 629 ; 4 ; #TMS ; input ; ; ; -- ; -- ; ; -- ; -- ; +; E16 ; 607 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E17 ; 597 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E18 ; 586 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E19 ; 578 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E20 ; 576 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E21 ; 569 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E22 ; 549 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; E23 ; 534 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E24 ; 535 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E25 ; 536 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; E26 ; 537 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F1 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F2 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F3 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F4 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F5 ; 720 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F6 ; 719 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F7 ; 707 ; 3 ; d_b ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F8 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; F9 ; 690 ; 3 ; d_line_counter[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F10 ; 687 ; 3 ; d_column_counter[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F11 ; 659 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; F12 ; 645 ; 9 ; d_vsync_state[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F13 ; 641 ; 9 ; d_vsync_counter[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F14 ; 643 ; 9 ; d_vsync_counter[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F15 ; 632 ; 4 ; d_vsync_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F16 ; 612 ; 4 ; ~DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F17 ; 599 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F18 ; 591 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; F19 ; 590 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F20 ; 584 ; 4 ; seven_seg_pin[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; F21 ; 572 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; F22 ; 560 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; F23 ; 530 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F24 ; 531 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F25 ; 532 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; F26 ; 533 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G1 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G2 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G3 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G4 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G5 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G6 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G7 ; 700 ; 3 ; d_hsync_state[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; G9 ; 688 ; 3 ; d_line_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; G10 ; 686 ; 3 ; d_hsync_state[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; G11 ; 670 ; 3 ; d_line_counter[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; G12 ; 653 ; 3 ; ^DCLK ; ; ; ; -- ; -- ; ; -- ; -- ; +; G13 ; ; ; TEMPDIODEn ; ; ; ; -- ; -- ; ; -- ; -- ; +; G14 ; 636 ; 4 ; #TDO ; output ; ; ; -- ; -- ; ; -- ; -- ; +; G15 ; 631 ; 4 ; #TCK ; input ; ; ; -- ; -- ; ; -- ; -- ; +; G16 ; 622 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; G17 ; 601 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; G18 ; 594 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; G19 ; 585 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; G20 ; 587 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; G21 ; 522 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G22 ; 523 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G23 ; 526 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G24 ; 527 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G25 ; 528 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; G26 ; 529 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H1 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H2 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H3 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H4 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H5 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H6 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H7 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H8 ; 20 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; H9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; H10 ; 675 ; 3 ; d_hsync_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; H11 ; 654 ; 3 ; ^CONF_DONE ; ; ; ; -- ; -- ; ; -- ; -- ; +; H12 ; 652 ; 3 ; ^nCONFIG ; ; ; ; -- ; -- ; ; -- ; -- ; +; H13 ; 651 ; 3 ; ^nSTATUS ; ; ; ; -- ; -- ; ; -- ; -- ; +; H14 ; ; ; TEMPDIODEp ; ; ; ; -- ; -- ; ; -- ; -- ; +; H15 ; 635 ; 4 ; #TDI ; input ; ; ; -- ; -- ; ; -- ; -- ; +; H16 ; 621 ; 4 ; d_vsync_counter[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; H17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; H18 ; 603 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; H19 ; 506 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H20 ; 505 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H21 ; 514 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H22 ; 513 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H23 ; 518 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H24 ; 517 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H25 ; 524 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; H26 ; 525 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J1 ; 34 ; 2 ; seven_seg_pin[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; J2 ; 33 ; 2 ; seven_seg_pin[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; J3 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J4 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J5 ; 36 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J6 ; 35 ; 2 ; seven_seg_pin[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; J7 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J8 ; 48 ; 2 ; d_line_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; J12 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; J13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J15 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; J16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; J17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; J18 ; 521 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; J19 ; 494 ; 5 ; d_vsync ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; J20 ; 493 ; 5 ; vsync_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; J21 ; 504 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J22 ; 503 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J23 ; 512 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J24 ; 511 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J25 ; 508 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; J26 ; 507 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K1 ; 46 ; 2 ; d_line_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K2 ; 45 ; 2 ; reset_pin ; input ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K3 ; 38 ; 2 ; seven_seg_pin[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K4 ; 37 ; 2 ; seven_seg_pin[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K5 ; 50 ; 2 ; d_hsync_state[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K6 ; 49 ; 2 ; d_hsync_state[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K7 ; 52 ; 2 ; d_vsync_state[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K8 ; 51 ; 2 ; d_hsync_counter[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K9 ; 47 ; 2 ; d_line_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; K14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; K18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; K19 ; 486 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K20 ; 485 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K21 ; 490 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K22 ; 489 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K23 ; 492 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K24 ; 491 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; K25 ; 496 ; 5 ; d_set_vsync_counter ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; K26 ; 495 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; L1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; L2 ; 54 ; 2 ; d_hsync_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; L3 ; 53 ; 2 ; d_hsync_counter[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; L4 ; 56 ; 2 ; d_column_counter[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; L5 ; 55 ; 2 ; d_hsync_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; L6 ; 60 ; 2 ; d_column_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; L7 ; 59 ; 2 ; d_column_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; L8 ; 61 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; L9 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; L10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; L12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; L16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; L18 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; L19 ; 480 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; L20 ; 482 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; L21 ; 481 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; L22 ; 478 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; L23 ; 479 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; L24 ; 488 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; L25 ; 487 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; L26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; M1 ; 81 ; 2 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; M2 ; ; ; VCCG_PLL1 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M3 ; ; ; VCCA_PLL1 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M4 ; 66 ; 2 ; seven_seg_pin[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; M5 ; 67 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M6 ; 62 ; 2 ; d_h_enable ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; M7 ; 63 ; 2 ; seven_seg_pin[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; M8 ; 72 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M9 ; 73 ; 2 ; seven_seg_pin[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; M11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; M13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; M15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; M17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; M18 ; 468 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M19 ; 469 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M20 ; 470 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M21 ; 471 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M22 ; 474 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M23 ; 475 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; M24 ; 462 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; M25 ; 463 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; M26 ; 460 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N2 ; 78 ; 2 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; N3 ; 79 ; 2 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; N4 ; ; ; GNDG_PLL1 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N5 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N6 ; 70 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; N7 ; 71 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; N8 ; 77 ; 2 ; d_state_clk ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; N9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N19 ; 453 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; N20 ; 464 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; N21 ; 465 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; N22 ; ; ; GNDG_PLL4 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N23 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; N24 ; ; ; VCCG_PLL4 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N25 ; ; ; VCCA_PLL4 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; N26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P2 ; ; ; GNDG_PLL2 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P3 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P4 ; ; ; VCCG_PLL2 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P5 ; ; ; VCCA_PLL2 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P6 ; 88 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P7 ; 89 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P8 ; 76 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; P19 ; 452 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P20 ; 448 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P21 ; 449 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; P22 ; ; ; VCCA_PLL3 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P23 ; ; ; VCCG_PLL3 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; P24 ; 457 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; P25 ; 458 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; P26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R1 ; 82 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; R2 ; 83 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; R3 ; 84 ; 1 ; clk_pin ; input ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ; +; R4 ; 94 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R5 ; 95 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R6 ; 90 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R7 ; 91 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R8 ; 92 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R9 ; 93 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; R17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R18 ; 443 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; R19 ; 436 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R20 ; 450 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R21 ; 451 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R22 ; 446 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R23 ; 447 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; R24 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R25 ; ; ; GNDG_PLL3 ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; R26 ; 459 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ; +; T1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; T2 ; 100 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T3 ; 99 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T4 ; 108 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T5 ; 107 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T6 ; 106 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T7 ; 105 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T8 ; 98 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; T9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; T11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; T12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; T13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; T15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; T17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; T18 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; T19 ; 435 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T20 ; 432 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T21 ; 431 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T22 ; 442 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T23 ; 441 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T24 ; 434 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T25 ; 433 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; T26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; U1 ; 112 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U2 ; 111 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U3 ; 116 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U4 ; 115 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U5 ; 110 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U6 ; 109 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U7 ; 114 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U8 ; 113 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U9 ; 117 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; U11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; U12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; U14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; U15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; U16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ; +; U17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; U18 ; 428 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U19 ; 427 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U20 ; 424 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U21 ; 430 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U22 ; 429 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U23 ; 418 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U24 ; 417 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U25 ; 426 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; U26 ; 425 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V1 ; 132 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V2 ; 133 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V3 ; 136 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V4 ; 137 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V5 ; 124 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V6 ; 123 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V7 ; 127 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; V8 ; 118 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; V12 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; V13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V15 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; V16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ; +; V17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ; +; V19 ; 423 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V20 ; 414 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; V21 ; 406 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V22 ; 407 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V23 ; 404 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V24 ; 405 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V25 ; 408 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; V26 ; 409 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W1 ; 140 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W2 ; 141 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W3 ; 148 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W4 ; 149 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W5 ; 134 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W6 ; 135 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W7 ; 138 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W8 ; 139 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W9 ; 212 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; W10 ; 228 ; 8 ; d_g ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; W11 ; 255 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; W12 ; 260 ; 8 ; PLL_ENA ; ; ; ; -- ; -- ; ; -- ; -- ; +; W13 ; 263 ; 8 ; ^MSEL2 ; ; ; ; -- ; -- ; ; -- ; -- ; +; W14 ; 279 ; 7 ; ^nCEO ; ; ; ; -- ; -- ; ; -- ; -- ; +; W15 ; 282 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; W16 ; 285 ; 7 ; ^PORSEL ; ; ; ; -- ; -- ; ; -- ; -- ; +; W17 ; 311 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; W18 ; 321 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; W19 ; 402 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W20 ; 403 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W21 ; 394 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W22 ; 395 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W23 ; 392 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W24 ; 393 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W25 ; 400 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; W26 ; 401 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y1 ; 153 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y2 ; 152 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y3 ; 146 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y4 ; 147 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y5 ; 151 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y6 ; 150 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y7 ; 156 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; Y8 ; 210 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y9 ; 209 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y10 ; 226 ; 8 ; g2_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; Y11 ; 244 ; 8 ; d_column_counter[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ; +; Y12 ; 261 ; 8 ; ^MSEL0 ; ; ; ; -- ; -- ; ; -- ; -- ; +; Y13 ; 262 ; 8 ; ^MSEL1 ; ; ; ; -- ; -- ; ; -- ; -- ; +; Y14 ; 278 ; 7 ; ^nCE ; ; ; ; -- ; -- ; ; -- ; -- ; +; Y15 ; 284 ; 7 ; ^VCCSEL ; ; ; ; -- ; -- ; ; -- ; -- ; +; Y16 ; 297 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y17 ; 314 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y18 ; 317 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y19 ; 325 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y20 ; 333 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ; +; Y21 ; 385 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ; +; Y22 ; 387 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y23 ; 391 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y24 ; 390 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y25 ; 389 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; +; Y26 ; 388 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ; ++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 10 pF ; Not Available ; +; 3.3-V LVCMOS ; 10 pF ; Not Available ; +; 2.5 V ; 10 pF ; Not Available ; +; 1.8 V ; 10 pF ; Not Available ; +; 1.5 V ; 10 pF ; Not Available ; +; GTL ; 30 pF ; 25 Ohm (Parallel) ; +; GTL+ ; 30 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 8 pF ; 25 Ohm (Parallel) ; +; Compact PCI ; 10 pF ; 25 Ohm (Parallel) ; +; AGP 1X ; 10 pF ; Not Available ; +; AGP 2X ; 10 pF ; Not Available ; +; CTT ; 30 pF ; 50 Ohm (Parallel) ; +; SSTL-3 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-3 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 20 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 20 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 20 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 20 pF ; 25 Ohm (Parallel) ; +; LVDS ; 4 pF ; 100 Ohm (Differential) ; +; Differential LVPECL ; 4 pF ; 100 Ohm (Differential) ; +; 3.3-V PCML ; 4 pF ; 50 Ohm (Parallel) ; +; HyperTransport ; 4 pF ; 100 Ohm (Differential) ; +; Differential 1.5-V HSTL Class I ; 20 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.8-V HSTL Class I ; 20 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 20 pF ; (See 1.8-V HSTL Class II) ; +; Differential SSTL-2 ; 30 pF ; (See SSTL-2) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++-----------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++-----------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+ +; |vga ; 141 (3) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 91 ; 0 ; 79 (1) ; 0 (0) ; 62 (2) ; 40 (0) ; 3 (0) ; |vga ; work ; +; |vga_control:vga_control_unit| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |vga|vga_control:vga_control_unit ; work ; +; |vga_driver:vga_driver_unit| ; 128 (128) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 71 (71) ; 0 (0) ; 57 (57) ; 40 (40) ; 3 (3) ; |vga|vga_driver:vga_driver_unit ; work ; ++-----------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; Core to Output Register ; Clock Enable to Output Enable Register ; Clock Enable to Output Register ; Clock Enable to Input Register ; TCO ; TCOE ; Falling Edge Output Enable ; ++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+ +; r0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; r1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; r2_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; g0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; g1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; g2_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; b0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; b1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; hsync_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; vsync_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[10] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[11] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[12] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; seven_seg_pin[13] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_column_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_line_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_set_column_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_set_line_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_set_hsync_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_set_vsync_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_h_enable ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_v_enable ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_r ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_g ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_b ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_hsync_state[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_vsync_state[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; d_state_clk ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ; +; clk_pin ; Input ; ON ; ON ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; reset_pin ; Input ; ON ; ON ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------------------------------+-------------------+---------+ +; clk_pin_in ; ; ; +; reset_pin_in ; ; ; +; - vga_driver:vga_driver_unit|vsync_state_6_ ; 0 ; ON ; +; - vga_driver:vga_driver_unit|h_sync_Z ; 0 ; ON ; +; - vga_driver:vga_driver_unit|v_sync_Z ; 0 ; ON ; +; - dly_counter_0_ ; 0 ; ON ; +; - dly_counter_1_ ; 0 ; ON ; +; - vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ ; 0 ; ON ; +; - vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ ; 0 ; ON ; +; - vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ ; 0 ; ON ; +; - vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ ; 0 ; ON ; ++-----------------------------------------------------------------------+-------------------+---------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++-------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+ +; clk_pin ; PIN_R3 ; 63 ; Clock ; yes ; Global Clock ; GCLK3 ; +; vga_driver:vga_driver_unit|G_16_i ; LC_X38_Y35_N5 ; 10 ; Sync. clear ; no ; -- ; -- ; +; vga_driver:vga_driver_unit|G_2_i ; LC_X28_Y33_N1 ; 10 ; Sync. clear ; no ; -- ; -- ; +; vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; LC_X35_Y35_N4 ; 10 ; Sync. clear ; no ; -- ; -- ; +; vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ; LC_X29_Y32_N8 ; 1 ; Clock enable ; no ; -- ; -- ; +; vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; LC_X29_Y33_N4 ; 6 ; Clock enable ; no ; -- ; -- ; +; vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; LC_X35_Y35_N3 ; 9 ; Sync. clear ; no ; -- ; -- ; +; vga_driver:vga_driver_unit|un6_dly_counter_0_x ; LC_X35_Y35_N2 ; 32 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK12 ; +; vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; LC_X28_Y33_N0 ; 11 ; Sync. load ; no ; -- ; -- ; +; vga_driver:vga_driver_unit|un9_vsync_counterlt9 ; LC_X38_Y35_N9 ; 11 ; Sync. load ; no ; -- ; -- ; +; vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ; LC_X34_Y35_N8 ; 1 ; Clock enable ; no ; -- ; -- ; +; vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa ; LC_X36_Y35_N7 ; 5 ; Clock enable ; no ; -- ; -- ; ++-------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++------------------------------------------------+---------------+---------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; ++------------------------------------------------+---------------+---------+----------------------+------------------+ +; clk_pin ; PIN_R3 ; 63 ; Global Clock ; GCLK3 ; +; vga_driver:vga_driver_unit|un6_dly_counter_0_x ; LC_X35_Y35_N2 ; 32 ; Global Clock ; GCLK12 ; ++------------------------------------------------+---------------+---------+----------------------+------------------+ + + ++-----------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-------------------------------------------------------------+---------+ +; vga_driver:vga_driver_unit|un9_vsync_counterlt9 ; 11 ; +; vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; 11 ; +; vga_driver:vga_driver_unit|G_16_i ; 10 ; +; vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa ; 10 ; +; vga_driver:vga_driver_unit|G_2_i ; 10 ; +; vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa ; 10 ; +; vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; 10 ; +; vga_driver:vga_driver_unit|un10_column_counter_siglto9 ; 10 ; +; vga_driver:vga_driver_unit|column_counter_sig_8 ; 10 ; +; vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; 9 ; +; vga_driver:vga_driver_unit|un10_line_counter_siglto8 ; 9 ; +; dly_counter[1] ; 9 ; +; dly_counter[0] ; 9 ; +; reset_pin ; 9 ; +; vga_driver:vga_driver_unit|vsync_counter_9 ; 9 ; +; vga_driver:vga_driver_unit|vsync_counter_0 ; 9 ; +; vga_driver:vga_driver_unit|column_counter_sig_7 ; 9 ; +; vga_driver:vga_driver_unit|hsync_counter_7 ; 7 ; +; vga_driver:vga_driver_unit|hsync_counter_6 ; 7 ; +; vga_driver:vga_driver_unit|hsync_counter_4 ; 7 ; +; ~STRATIX_FITTER_CREATED_GND~I ; 6 ; +; vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; 6 ; +; vga_driver:vga_driver_unit|hsync_counter_9 ; 6 ; +; vga_driver:vga_driver_unit|hsync_counter_8 ; 6 ; +; vga_driver:vga_driver_unit|hsync_counter_5 ; 6 ; +; vga_driver:vga_driver_unit|hsync_counter_3 ; 6 ; +; vga_driver:vga_driver_unit|hsync_counter_2 ; 6 ; +; vga_driver:vga_driver_unit|hsync_counter_1 ; 6 ; +; vga_driver:vga_driver_unit|hsync_counter_0 ; 6 ; +; vga_driver:vga_driver_unit|vsync_state_1 ; 6 ; +; vga_driver:vga_driver_unit|hsync_state_1 ; 6 ; +; vga_driver:vga_driver_unit|column_counter_sig_6 ; 6 ; +; vga_driver:vga_driver_unit|column_counter_sig_5 ; 6 ; +; vga_driver:vga_driver_unit|column_counter_sig_4 ; 6 ; +; vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa ; 5 ; +; vga_driver:vga_driver_unit|vsync_state_0 ; 5 ; +; vga_driver:vga_driver_unit|vsync_state_4 ; 5 ; +; vga_driver:vga_driver_unit|hsync_state_4 ; 5 ; +; vga_driver:vga_driver_unit|d_set_hsync_counter ; 5 ; +; vga_driver:vga_driver_unit|vsync_counter_8 ; 5 ; +; vga_driver:vga_driver_unit|vsync_counter_7 ; 5 ; +; vga_driver:vga_driver_unit|vsync_counter_6 ; 5 ; +; vga_driver:vga_driver_unit|vsync_counter_5 ; 5 ; +; vga_driver:vga_driver_unit|vsync_counter_cout[4] ; 5 ; +; vga_driver:vga_driver_unit|vsync_counter_4 ; 5 ; +; vga_driver:vga_driver_unit|vsync_counter_3 ; 5 ; +; vga_driver:vga_driver_unit|vsync_counter_2 ; 5 ; +; vga_driver:vga_driver_unit|vsync_counter_1 ; 5 ; +; vga_driver:vga_driver_unit|hsync_counter_cout[4] ; 5 ; +; vga_driver:vga_driver_unit|column_counter_sig_3 ; 5 ; ++-------------------------------------------------------------+---------+ + + ++-------------------------------------------------------+ +; Interconnect Usage Summary ; ++-----------------------------+-------------------------+ +; Interconnect Resource Type ; Usage ; ++-----------------------------+-------------------------+ +; C16 interconnects ; 27 / 4,620 ( < 1 % ) ; +; C4 interconnects ; 51 / 69,840 ( < 1 % ) ; +; C8 interconnects ; 69 / 15,568 ( < 1 % ) ; +; DIFFIOCLKs ; 0 / 16 ( 0 % ) ; +; DQS bus muxes ; 0 / 102 ( 0 % ) ; +; DQS-16 I/O buses ; 0 / 8 ( 0 % ) ; +; DQS-32 I/O buses ; 0 / 4 ( 0 % ) ; +; DQS-8 I/O buses ; 0 / 20 ( 0 % ) ; +; Direct links ; 80 / 104,060 ( < 1 % ) ; +; Fast regional clocks ; 0 / 8 ( 0 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; I/O buses ; 3 / 320 ( < 1 % ) ; +; LUT chains ; 10 / 23,094 ( < 1 % ) ; +; Local routing interconnects ; 89 / 25,660 ( < 1 % ) ; +; R24 interconnects ; 22 / 4,692 ( < 1 % ) ; +; R4 interconnects ; 132 / 141,520 ( < 1 % ) ; +; R8 interconnects ; 55 / 22,956 ( < 1 % ) ; +; Regional clocks ; 0 / 16 ( 0 % ) ; ++-----------------------------+-------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 7.83) ; Number of LABs (Total = 18) ; ++--------------------------------------------+------------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 3 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 12 ; ++--------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 1.72) ; Number of LABs (Total = 18) ; ++------------------------------------+------------------------------+ +; 1 Async. clear ; 1 ; +; 1 Clock ; 16 ; +; 1 Clock enable ; 2 ; +; 1 Sync. clear ; 10 ; +; 1 Sync. load ; 2 ; ++------------------------------------+------------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 7.94) ; Number of LABs (Total = 18) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 3 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 7 ; +; 11 ; 2 ; +; 12 ; 1 ; ++---------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 5.94) ; Number of LABs (Total = 18) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 3 ; +; 4 ; 2 ; +; 5 ; 0 ; +; 6 ; 6 ; +; 7 ; 2 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 3 ; ++-------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 10.44) ; Number of LABs (Total = 18) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 1 ; +; 6 ; 2 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 2 ; +; 12 ; 1 ; +; 13 ; 2 ; +; 14 ; 0 ; +; 15 ; 2 ; +; 16 ; 0 ; +; 17 ; 2 ; +; 18 ; 0 ; +; 19 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Error detection CRC ; Off ; +; nWS, nRS, nCS, CS ; Unreserved ; +; RDYnBUSY ; Unreserved ; +; Data[7..1] ; Unreserved ; +; Data[0] ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 16:59:56 2009 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Info: Selected device EP1S25F672C6 for design "vga" +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP1S10F672C6 is compatible + Info: Device EP1S20F672C6 is compatible + Info: Device EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE is compatible +Info: Fitter converted 1 user pins into dedicated programming pins + Info: Pin ~DATA0~ is reserved at location F16 +Warning: No exact pin location assignment(s) for 91 pins of 91 total pins + Info: Pin r0_pin not assigned to an exact location on the device + Info: Pin r1_pin not assigned to an exact location on the device + Info: Pin r2_pin not assigned to an exact location on the device + Info: Pin g0_pin not assigned to an exact location on the device + Info: Pin g1_pin not assigned to an exact location on the device + Info: Pin g2_pin not assigned to an exact location on the device + Info: Pin b0_pin not assigned to an exact location on the device + Info: Pin b1_pin not assigned to an exact location on the device + Info: Pin hsync_pin not assigned to an exact location on the device + Info: Pin vsync_pin not assigned to an exact location on the device + Info: Pin seven_seg_pin[0] not assigned to an exact location on the device + Info: Pin seven_seg_pin[1] not assigned to an exact location on the device + Info: Pin seven_seg_pin[2] not assigned to an exact location on the device + Info: Pin seven_seg_pin[3] not assigned to an exact location on the device + Info: Pin seven_seg_pin[4] not assigned to an exact location on the device + Info: Pin seven_seg_pin[5] not assigned to an exact location on the device + Info: Pin seven_seg_pin[6] not assigned to an exact location on the device + Info: Pin seven_seg_pin[7] not assigned to an exact location on the device + Info: Pin seven_seg_pin[8] not assigned to an exact location on the device + Info: Pin seven_seg_pin[9] not assigned to an exact location on the device + Info: Pin seven_seg_pin[10] not assigned to an exact location on the device + Info: Pin seven_seg_pin[11] not assigned to an exact location on the device + Info: Pin seven_seg_pin[12] not assigned to an exact location on the device + Info: Pin seven_seg_pin[13] not assigned to an exact location on the device + Info: Pin d_hsync not assigned to an exact location on the device + Info: Pin d_vsync not assigned to an exact location on the device + Info: Pin d_column_counter[0] not assigned to an exact location on the device + Info: Pin d_column_counter[1] not assigned to an exact location on the device + Info: Pin d_column_counter[2] not assigned to an exact location on the device + Info: Pin d_column_counter[3] not assigned to an exact location on the device + Info: Pin d_column_counter[4] not assigned to an exact location on the device + Info: Pin d_column_counter[5] not assigned to an exact location on the device + Info: Pin d_column_counter[6] not assigned to an exact location on the device + Info: Pin d_column_counter[7] not assigned to an exact location on the device + Info: Pin d_column_counter[8] not assigned to an exact location on the device + Info: Pin d_column_counter[9] not assigned to an exact location on the device + Info: Pin d_line_counter[0] not assigned to an exact location on the device + Info: Pin d_line_counter[1] not assigned to an exact location on the device + Info: Pin d_line_counter[2] not assigned to an exact location on the device + Info: Pin d_line_counter[3] not assigned to an exact location on the device + Info: Pin d_line_counter[4] not assigned to an exact location on the device + Info: Pin d_line_counter[5] not assigned to an exact location on the device + Info: Pin d_line_counter[6] not assigned to an exact location on the device + Info: Pin d_line_counter[7] not assigned to an exact location on the device + Info: Pin d_line_counter[8] not assigned to an exact location on the device + Info: Pin d_set_column_counter not assigned to an exact location on the device + Info: Pin d_set_line_counter not assigned to an exact location on the device + Info: Pin d_hsync_counter[0] not assigned to an exact location on the device + Info: Pin d_hsync_counter[1] not assigned to an exact location on the device + Info: Pin d_hsync_counter[2] not assigned to an exact location on the device + Info: Pin d_hsync_counter[3] not assigned to an exact location on the device + Info: Pin d_hsync_counter[4] not assigned to an exact location on the device + Info: Pin d_hsync_counter[5] not assigned to an exact location on the device + Info: Pin d_hsync_counter[6] not assigned to an exact location on the device + Info: Pin d_hsync_counter[7] not assigned to an exact location on the device + Info: Pin d_hsync_counter[8] not assigned to an exact location on the device + Info: Pin d_hsync_counter[9] not assigned to an exact location on the device + Info: Pin d_vsync_counter[0] not assigned to an exact location on the device + Info: Pin d_vsync_counter[1] not assigned to an exact location on the device + Info: Pin d_vsync_counter[2] not assigned to an exact location on the device + Info: Pin d_vsync_counter[3] not assigned to an exact location on the device + Info: Pin d_vsync_counter[4] not assigned to an exact location on the device + Info: Pin d_vsync_counter[5] not assigned to an exact location on the device + Info: Pin d_vsync_counter[6] not assigned to an exact location on the device + Info: Pin d_vsync_counter[7] not assigned to an exact location on the device + Info: Pin d_vsync_counter[8] not assigned to an exact location on the device + Info: Pin d_vsync_counter[9] not assigned to an exact location on the device + Info: Pin d_set_hsync_counter not assigned to an exact location on the device + Info: Pin d_set_vsync_counter not assigned to an exact location on the device + Info: Pin d_h_enable not assigned to an exact location on the device + Info: Pin d_v_enable not assigned to an exact location on the device + Info: Pin d_r not assigned to an exact location on the device + Info: Pin d_g not assigned to an exact location on the device + Info: Pin d_b not assigned to an exact location on the device + Info: Pin d_hsync_state[6] not assigned to an exact location on the device + Info: Pin d_hsync_state[5] not assigned to an exact location on the device + Info: Pin d_hsync_state[4] not assigned to an exact location on the device + Info: Pin d_hsync_state[3] not assigned to an exact location on the device + Info: Pin d_hsync_state[2] not assigned to an exact location on the device + Info: Pin d_hsync_state[1] not assigned to an exact location on the device + Info: Pin d_hsync_state[0] not assigned to an exact location on the device + Info: Pin d_vsync_state[6] not assigned to an exact location on the device + Info: Pin d_vsync_state[5] not assigned to an exact location on the device + Info: Pin d_vsync_state[4] not assigned to an exact location on the device + Info: Pin d_vsync_state[3] not assigned to an exact location on the device + Info: Pin d_vsync_state[2] not assigned to an exact location on the device + Info: Pin d_vsync_state[1] not assigned to an exact location on the device + Info: Pin d_vsync_state[0] not assigned to an exact location on the device + Info: Pin d_state_clk not assigned to an exact location on the device + Info: Pin clk_pin not assigned to an exact location on the device + Info: Pin reset_pin not assigned to an exact location on the device +Info: Fitter is using the Classic Timing Analyzer +Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. +Info: Completed User Assigned Global Signals Promotion Operation +Info: Automatically promoted some destinations of signal "clk_pin" to use Global clock in PIN R3 + Info: Destination "d_state_clk_out" may be non-global or may not use global clock +Info: Automatically promoted some destinations of signal "vga_driver:vga_driver_unit|un6_dly_counter_0_x" to use Global clock + Info: Destination "seven_seg_pin_out_12_" may be non-global or may not use global clock + Info: Destination "seven_seg_pin_out_11_" may be non-global or may not use global clock + Info: Destination "seven_seg_pin_out_10_" may be non-global or may not use global clock + Info: Destination "seven_seg_pin_out_9_" may be non-global or may not use global clock + Info: Destination "seven_seg_pin_out_8_" may be non-global or may not use global clock + Info: Destination "seven_seg_pin_out_7_" may be non-global or may not use global clock + Info: Destination "seven_seg_pin_out_2_" may be non-global or may not use global clock + Info: Destination "seven_seg_pin_out_1_" may be non-global or may not use global clock + Info: Destination "vga_driver:vga_driver_unit|hsync_state_1_" may be non-global or may not use global clock + Info: Destination "vga_driver:vga_driver_unit|vsync_state_1_" may be non-global or may not use global clock + Info: Limited to 10 non-global destinations +Info: Completed Auto Global Promotion Operation +Info: Starting register packing +Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option +Info: Finished register packing +Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info: Number of I/O pins in group: 90 (unused VREF, 3.3V VCCIO, 1 input, 89 output, 0 bidirectional) + Info: I/O standards used: 3.3-V LVTTL. +Info: I/O bank details before I/O pin placement + Info: Statistics of I/O banks + Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 60 pins available + Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 59 pins available + Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 54 pins available + Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 55 pins available + Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 59 pins available + Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 61 pins available + Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 57 pins available + Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 54 pins available + Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available + Info: I/O bank number 11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available +Info: Fitter preparation operations ending: elapsed time is 00:00:03 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:04 +Info: Slack time is -3.661 ns between source register "vga_driver:vga_driver_unit|vsync_counter_2" and destination register "vga_driver:vga_driver_unit|vsync_state_3" + Info: + Largest register to register requirement is 0.814 ns + Info: Shortest clock path from clock "clk_pin" to destination register is 3.707 ns + Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 63; CLK Node = 'clk_pin' + Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|vsync_state_3' + Info: Total cell delay = 1.701 ns ( 45.89 % ) + Info: Total interconnect delay = 2.006 ns ( 54.11 % ) + Info: Longest clock path from clock "clk_pin" to destination register is 3.707 ns + Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 63; CLK Node = 'clk_pin' + Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|vsync_state_3' + Info: Total cell delay = 1.701 ns ( 45.89 % ) + Info: Total interconnect delay = 2.006 ns ( 54.11 % ) + Info: Shortest clock path from clock "clk_pin" to source register is 3.707 ns + Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 63; CLK Node = 'clk_pin' + Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 7; REG Node = 'vga_driver:vga_driver_unit|vsync_counter_2' + Info: Total cell delay = 1.701 ns ( 45.89 % ) + Info: Total interconnect delay = 2.006 ns ( 54.11 % ) + Info: Longest clock path from clock "clk_pin" to source register is 3.707 ns + Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 63; CLK Node = 'clk_pin' + Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 7; REG Node = 'vga_driver:vga_driver_unit|vsync_counter_2' + Info: Total cell delay = 1.701 ns ( 45.89 % ) + Info: Total interconnect delay = 2.006 ns ( 54.11 % ) + Info: Micro clock to output delay of source is 0.176 ns + Info: Micro setup delay of destination is 0.010 ns + Info: - Longest register to register delay is 4.475 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 7; REG Node = 'vga_driver:vga_driver_unit|vsync_counter_2' + Info: 2: + IC(0.678 ns) + CELL(0.087 ns) = 0.765 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'vga_driver:vga_driver_unit|un12_vsync_counter_7' + Info: 3: + IC(0.683 ns) + CELL(0.332 ns) = 1.780 ns; Loc. = Unassigned; Fanout = 4; COMB Node = 'vga_driver:vga_driver_unit|un14_vsync_counter_8' + Info: 4: + IC(0.655 ns) + CELL(0.087 ns) = 2.522 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3' + Info: 5: + IC(0.487 ns) + CELL(0.213 ns) = 3.222 ns; Loc. = Unassigned; Fanout = 5; COMB Node = 'vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa' + Info: 6: + IC(0.527 ns) + CELL(0.726 ns) = 4.475 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|vsync_state_3' + Info: Total cell delay = 1.445 ns ( 32.29 % ) + Info: Total interconnect delay = 3.030 ns ( 67.71 % ) +Info: Estimated most critical path is register to register delay of 4.475 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X37_Y35; Fanout = 7; REG Node = 'vga_driver:vga_driver_unit|vsync_counter_2' + Info: 2: + IC(0.678 ns) + CELL(0.087 ns) = 0.765 ns; Loc. = LAB_X38_Y35; Fanout = 3; COMB Node = 'vga_driver:vga_driver_unit|un12_vsync_counter_7' + Info: 3: + IC(0.683 ns) + CELL(0.332 ns) = 1.780 ns; Loc. = LAB_X36_Y35; Fanout = 4; COMB Node = 'vga_driver:vga_driver_unit|un14_vsync_counter_8' + Info: 4: + IC(0.655 ns) + CELL(0.087 ns) = 2.522 ns; Loc. = LAB_X35_Y35; Fanout = 1; COMB Node = 'vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3' + Info: 5: + IC(0.487 ns) + CELL(0.213 ns) = 3.222 ns; Loc. = LAB_X36_Y35; Fanout = 5; COMB Node = 'vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa' + Info: 6: + IC(0.527 ns) + CELL(0.726 ns) = 4.475 ns; Loc. = LAB_X35_Y35; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|vsync_state_3' + Info: Total cell delay = 1.445 ns ( 32.29 % ) + Info: Total interconnect delay = 3.030 ns ( 67.71 % ) +Info: Fitter routing operations beginning +Info: Average interconnect usage is 0% of the available device resources + Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X22_Y24 to location X33_Y35 +Info: Fitter routing operations ending: elapsed time is 00:00:01 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Completed Fixed Delay Chain Operation +Info: Started post-fitting delay annotation +Info: Delay annotation completed successfully +Info: Completed Auto Delay Chain Operation +Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results + Info: Pin seven_seg_pin[0] has GND driving its datain port + Info: Pin seven_seg_pin[3] has GND driving its datain port + Info: Pin seven_seg_pin[4] has GND driving its datain port + Info: Pin seven_seg_pin[5] has GND driving its datain port + Info: Pin seven_seg_pin[6] has GND driving its datain port + Info: Pin seven_seg_pin[13] has GND driving its datain port +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Generated suppressed messages file /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/vga.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 319 megabytes + Info: Processing ended: Thu Oct 29 17:00:27 2009 + Info: Elapsed time: 00:00:31 + Info: Total CPU time (on all processors): 00:00:29 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/vga.fit.smsg. + + diff --git a/bsp3/Designflow/ppr/sim/vga.fit.smsg b/bsp3/Designflow/ppr/sim/vga.fit.smsg new file mode 100644 index 0000000..38de4e4 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.fit.smsg @@ -0,0 +1,8 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Start inferring scan chains for DSP blocks +Extra Info: Inferring scan chains for DSP blocks is complete +Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density +Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks diff --git a/bsp3/Designflow/ppr/sim/vga.fit.summary b/bsp3/Designflow/ppr/sim/vga.fit.summary new file mode 100644 index 0000000..327f27c --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.fit.summary @@ -0,0 +1,14 @@ +Fitter Status : Successful - Thu Oct 29 17:00:26 2009 +Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version +Revision Name : vga +Top-level Entity Name : vga +Family : Stratix +Device : EP1S25F672C6 +Timing Models : Final +Total logic elements : 141 / 25,660 ( < 1 % ) +Total pins : 91 / 474 ( 19 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,944,576 ( 0 % ) +DSP block 9-bit elements : 0 / 80 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) diff --git a/bsp3/Designflow/ppr/sim/vga.flow.rpt b/bsp3/Designflow/ppr/sim/vga.flow.rpt new file mode 100644 index 0000000..0c3ec8e --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.flow.rpt @@ -0,0 +1,126 @@ +Flow report for vga +Thu Oct 29 17:00:56 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------+ +; Flow Summary ; ++--------------------------+------------------------------------------+ +; Flow Status ; Successful - Thu Oct 29 17:00:56 2009 ; +; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; +; Revision Name ; vga ; +; Top-level Entity Name ; vga ; +; Family ; Stratix ; +; Device ; EP1S25F672C6 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 141 / 25,660 ( < 1 % ) ; +; Total pins ; 91 / 474 ( 19 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,944,576 ( 0 % ) ; +; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 2 ( 0 % ) ; ++--------------------------+------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 10/29/2009 16:59:51 ; +; Main task ; Compilation ; +; Revision Name ; vga ; ++-------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+-----------------------------+---------------+-------------+----------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+-----------------------------+---------------+-------------+----------------------+ +; COMPILER_SIGNATURE_ID ; 91815334056.125683199105130 ; -- ; -- ; -- ; +; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Synplify Pro ; ; -- ; -- ; +; EDA_INPUT_DATA_FORMAT ; Vqm ; -- ; -- ; eda_design_synthesis ; +; EDA_LMF_FILE ; synplcty.lmf ; -- ; -- ; eda_design_synthesis ; +; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; ++------------------------------------+-----------------------------+---------------+-------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; -- ; 00:00:01 ; +; Fitter ; 00:00:30 ; 1.1 ; -- ; 00:00:28 ; +; Assembler ; 00:00:18 ; 1.0 ; -- ; 00:00:18 ; +; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; -- ; 00:00:00 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; -- ; 00:00:01 ; +; Total ; 00:00:55 ; -- ; -- ; 00:00:48 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------+------------+----------------+ +; Analysis & Synthesis ; ti14 ; Red Hat ; 5 ; x86_64 ; +; Fitter ; ti14 ; Red Hat ; 5 ; x86_64 ; +; Assembler ; ti14 ; Red Hat ; 5 ; x86_64 ; +; Classic Timing Analyzer ; ti14 ; Red Hat ; 5 ; x86_64 ; +; EDA Netlist Writer ; ti14 ; Red Hat ; 5 ; x86_64 ; ++-------------------------+------------------+---------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off vga -c vga +quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga +quartus_asm --read_settings_files=off --write_settings_files=off vga -c vga +quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only +quartus_eda --read_settings_files=off --write_settings_files=off vga -c vga + + + diff --git a/bsp3/Designflow/ppr/sim/vga.map.rpt b/bsp3/Designflow/ppr/sim/vga.map.rpt new file mode 100644 index 0000000..76ca7e8 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.map.rpt @@ -0,0 +1,230 @@ +Analysis & Synthesis report for vga +Thu Oct 29 16:59:53 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. General Register Statistics + 8. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Oct 29 16:59:53 2009 ; +; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; +; Revision Name ; vga ; +; Top-level Entity Name ; vga ; +; Family ; Stratix ; +; Total logic elements ; 143 ; +; Total pins ; 91 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; DSP block 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++-----------------------------+------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP1S25F672C6 ; ; +; Top-level entity name ; vga ; vga ; +; Family name ; Stratix ; Stratix II ; +; Type of Retiming Performed During Resynthesis ; Full ; ; +; Resynthesis Optimization Effort ; Normal ; ; +; Physical Synthesis Level for Resynthesis ; Normal ; ; +; Use Generated Physical Constraints File ; On ; ; +; Use smart compilation ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++----------------------------------------------------------------+--------------------+--------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+ +; ../../syn/rev_1/vga.vqm ; yes ; User Verilog Quartus Mapping File ; /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm ; ++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+ + + ++-------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+---------+ +; Resource ; Usage ; ++---------------------------------------------+---------+ +; Total logic elements ; 143 ; +; -- Combinational with no register ; 81 ; +; -- Register only ; 3 ; +; -- Combinational with a register ; 59 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 53 ; +; -- 3 input functions ; 32 ; +; -- 2 input functions ; 54 ; +; -- 1 input functions ; 1 ; +; -- 0 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 109 ; +; -- arithmetic mode ; 34 ; +; -- qfbk mode ; 0 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 48 ; +; -- asynchronous clear/load mode ; 3 ; +; ; ; +; Total registers ; 62 ; +; Total logic cells in carry chains ; 40 ; +; I/O pins ; 91 ; +; Maximum fan-out node ; clk_pin ; +; Maximum fan-out ; 63 ; +; Total fan-out ; 666 ; +; Average fan-out ; 2.85 ; ++---------------------------------------------+---------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+ +; |vga ; 143 (2) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 91 ; 0 ; 81 (0) ; 3 (0) ; 59 (2) ; 40 (0) ; 0 (0) ; |vga ; work ; +; |vga_control:vga_control_unit| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |vga|vga_control:vga_control_unit ; work ; +; |vga_driver:vga_driver_unit| ; 131 (131) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 (74) ; 3 (3) ; 54 (54) ; 40 (40) ; 0 (0) ; |vga|vga_driver:vga_driver_unit ; work ; ++-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 62 ; +; Number of registers using Synchronous Clear ; 48 ; +; Number of registers using Synchronous Load ; 20 ; +; Number of registers using Asynchronous Clear ; 3 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 12 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 16:59:47 2009 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga +Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm + Info: Found entity 1: vga_driver + Info: Found entity 2: vga_control + Info: Found entity 3: vga +Info: Elaborating entity "vga" for the top level hierarchy +Info: Elaborating entity "vga_driver" for hierarchy "vga_driver:vga_driver_unit" +Info: Elaborating entity "vga_control" for hierarchy "vga_control:vga_control_unit" +Info: Implemented 234 device resources after synthesis - the final resource count might be different + Info: Implemented 2 input pins + Info: Implemented 89 output pins + Info: Implemented 143 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 185 megabytes + Info: Processing ended: Thu Oct 29 16:59:53 2009 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/bsp3/Designflow/ppr/sim/vga.map.summary b/bsp3/Designflow/ppr/sim/vga.map.summary new file mode 100644 index 0000000..b6cb501 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.map.summary @@ -0,0 +1,12 @@ +Analysis & Synthesis Status : Successful - Thu Oct 29 16:59:53 2009 +Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version +Revision Name : vga +Top-level Entity Name : vga +Family : Stratix +Total logic elements : 143 +Total pins : 91 +Total virtual pins : 0 +Total memory bits : 0 +DSP block 9-bit elements : 0 +Total PLLs : 0 +Total DLLs : 0 diff --git a/bsp3/Designflow/ppr/sim/vga.pin b/bsp3/Designflow/ppr/sim/vga.pin new file mode 100644 index 0000000..b015813 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.pin @@ -0,0 +1,748 @@ + -- Copyright (C) 1991-2009 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- Bank 9: 3.3V + -- Bank 11: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), + -- connect each pin marked GND* either individually through a 10k Ohm resistor + -- to GND or tie all pins together and connect through a single 10k Ohm resistor + -- to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version +CHIP "vga" ASSIGNED TO AN: EP1S25F672C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A2 : gnd : : : : +GND* : A3 : : : : 3 : +VCCIO3 : A4 : power : : 3.3V : 3 : +GND* : A5 : : : : 3 : +GND* : A6 : : : : 3 : +b1_pin : A7 : output : 3.3-V LVTTL : : 3 : N +d_column_counter[9] : A8 : output : 3.3-V LVTTL : : 3 : N +d_line_counter[2] : A9 : output : 3.3-V LVTTL : : 3 : N +d_hsync_counter[7] : A10 : output : 3.3-V LVTTL : : 3 : N +VCCIO3 : A11 : power : : 3.3V : 3 : +d_set_hsync_counter : A12 : output : 3.3-V LVTTL : : 3 : N +GND : A13 : gnd : : : : +GND : A14 : gnd : : : : +GND+ : A15 : : : : 4 : +VCCIO4 : A16 : power : : 3.3V : 4 : +GND* : A17 : : : : 4 : +GND* : A18 : : : : 4 : +GND* : A19 : : : : 4 : +GND* : A20 : : : : 4 : +GND* : A21 : : : : 4 : +GND* : A22 : : : : 4 : +VCCIO4 : A23 : power : : 3.3V : 4 : +GND* : A24 : : : : 4 : +GND : A25 : gnd : : : : +GND* : AA1 : : : : 1 : +GND* : AA2 : : : : 1 : +GND* : AA3 : : : : 1 : +GND* : AA4 : : : : 1 : +GND* : AA5 : : : : 1 : +GND* : AA6 : : : : 1 : +GND* : AA7 : : : : 8 : +GND* : AA8 : : : : 8 : +r1_pin : AA9 : output : 3.3-V LVTTL : : 8 : N +g0_pin : AA10 : output : 3.3-V LVTTL : : 8 : N +d_line_counter[8] : AA11 : output : 3.3-V LVTTL : : 8 : N +d_vsync_state[3] : AA12 : output : 3.3-V LVTTL : : 11 : N +d_vsync_state[0] : AA13 : output : 3.3-V LVTTL : : 11 : N +GND* : AA14 : : : : 11 : +nIO_PULLUP : AA15 : : : : 7 : +GND* : AA16 : : : : 7 : +GND* : AA17 : : : : 7 : +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND* : AA21 : : : : 7 : +GND* : AA22 : : : : 6 : +GND* : AA23 : : : : 6 : +GND* : AA24 : : : : 6 : +GND* : AA25 : : : : 6 : +GND* : AA26 : : : : 6 : +GND* : AB1 : : : : 1 : +GND* : AB2 : : : : 1 : +GND* : AB3 : : : : 1 : +GND* : AB4 : : : : 1 : +GND* : AB5 : : : : 8 : +GND* : AB6 : : : : 8 : +GND* : AB7 : : : : 8 : +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +d_r : AB10 : output : 3.3-V LVTTL : : 8 : N +d_column_counter[7] : AB11 : output : 3.3-V LVTTL : : 8 : N +GND* : AB12 : : : : 11 : +d_hsync : AB13 : output : 3.3-V LVTTL : : 11 : N +hsync_pin : AB14 : output : 3.3-V LVTTL : : 11 : N +GND : AB15 : gnd : : : : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND : AB18 : gnd : : : : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +GND* : AB21 : : : : 7 : +GND* : AB22 : : : : 7 : +GND* : AB23 : : : : 6 : +GND* : AB24 : : : : 6 : +GND* : AB25 : : : : 6 : +GND* : AB26 : : : : 6 : +VCCIO1 : AC1 : power : : 3.3V : 1 : +GND* : AC2 : : : : 1 : +GND* : AC3 : : : : 1 : +GND* : AC4 : : : : 1 : +GND* : AC5 : : : : 8 : +GND* : AC6 : : : : 8 : +GND* : AC7 : : : : 8 : +GND* : AC8 : : : : 8 : +GND* : AC9 : : : : 8 : +GND* : AC10 : : : : 8 : +d_hsync_counter[4] : AC11 : output : 3.3-V LVTTL : : 8 : N +GND+ : AC12 : : : : 8 : +GND : AC13 : gnd : : : : +GNDA_PLL6 : AC14 : gnd : : : : +GND* : AC15 : : : : 7 : +GND* : AC16 : : : : 7 : +GND* : AC17 : : : : 7 : +GND* : AC18 : : : : 7 : +GND* : AC19 : : : : 7 : +GND* : AC20 : : : : 7 : +GND* : AC21 : : : : 7 : +GND* : AC22 : : : : 7 : +GND* : AC23 : : : : 7 : +GND* : AC24 : : : : 6 : +GND* : AC25 : : : : 6 : +VCCIO6 : AC26 : power : : 3.3V : 6 : +GND* : AD1 : : : : 1 : +GND* : AD2 : : : : 8 : +GND* : AD3 : : : : 8 : +GND* : AD4 : : : : 8 : +GND* : AD5 : : : : 8 : +GND* : AD6 : : : : 8 : +GND* : AD7 : : : : 8 : +GND* : AD8 : : : : 8 : +GND* : AD9 : : : : 8 : +r2_pin : AD10 : output : 3.3-V LVTTL : : 8 : N +d_column_counter[5] : AD11 : output : 3.3-V LVTTL : : 8 : N +d_set_column_counter : AD12 : output : 3.3-V LVTTL : : 8 : N +VCCG_PLL6 : AD13 : power : : 1.5V : : +VCCA_PLL6 : AD14 : power : : 1.5V : : +GND* : AD15 : : : : 7 : +GND* : AD16 : : : : 7 : +GND* : AD17 : : : : 7 : +GND* : AD18 : : : : 7 : +GND* : AD19 : : : : 7 : +GND* : AD20 : : : : 7 : +GND : AD21 : gnd : : : : +GND* : AD22 : : : : 7 : +GND* : AD23 : : : : 7 : +GND* : AD24 : : : : 7 : +GND* : AD25 : : : : 6 : +GND* : AD26 : : : : 6 : +GND : AE1 : gnd : : : : +GND* : AE2 : : : : 8 : +GND* : AE3 : : : : 8 : +GND* : AE4 : : : : 8 : +GND : AE5 : gnd : : : : +GND* : AE6 : : : : 8 : +GND* : AE7 : : : : 8 : +GND* : AE8 : : : : 8 : +GND : AE9 : gnd : : : : +GND* : AE10 : : : : 8 : +d_hsync_state[6] : AE11 : output : 3.3-V LVTTL : : 8 : N +GND+ : AE12 : : : : 8 : +VCC_PLL6_OUTA : AE13 : power : : 3.3V : 11 : +GNDG_PLL6 : AE14 : gnd : : : : +GND+ : AE15 : : : : 7 : +GND* : AE16 : : : : 7 : +GND* : AE17 : : : : 7 : +GND* : AE18 : : : : 7 : +GND* : AE19 : : : : 7 : +GND* : AE20 : : : : 7 : +GND* : AE21 : : : : 7 : +GND* : AE22 : : : : 7 : +GND* : AE23 : : : : 7 : +GND* : AE24 : : : : 7 : +GND* : AE25 : : : : 7 : +GND : AE26 : gnd : : : : +GND : AF2 : gnd : : : : +GND* : AF3 : : : : 8 : +VCCIO8 : AF4 : power : : 3.3V : 8 : +GND* : AF5 : : : : 8 : +GND* : AF6 : : : : 8 : +GND* : AF7 : : : : 8 : +GND* : AF8 : : : : 8 : +r0_pin : AF9 : output : 3.3-V LVTTL : : 8 : N +g1_pin : AF10 : output : 3.3-V LVTTL : : 8 : N +VCCIO8 : AF11 : power : : 3.3V : 8 : +d_hsync_state[1] : AF12 : output : 3.3-V LVTTL : : 8 : N +GND : AF13 : gnd : : : : +GND : AF14 : gnd : : : : +GND+ : AF15 : : : : 7 : +VCCIO7 : AF16 : power : : 3.3V : 7 : +GND* : AF17 : : : : 7 : +GND* : AF18 : : : : 7 : +GND* : AF19 : : : : 7 : +GND* : AF20 : : : : 7 : +GND* : AF21 : : : : 7 : +GND* : AF22 : : : : 7 : +VCCIO7 : AF23 : power : : 3.3V : 7 : +GND* : AF24 : : : : 7 : +GND : AF25 : gnd : : : : +GND : B1 : gnd : : : : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +GND* : B7 : : : : 3 : +b0_pin : B8 : output : 3.3-V LVTTL : : 3 : N +d_set_line_counter : B9 : output : 3.3-V LVTTL : : 3 : N +d_hsync_counter[9] : B10 : output : 3.3-V LVTTL : : 3 : N +d_vsync_state[4] : B11 : output : 3.3-V LVTTL : : 3 : N +GND+ : B12 : : : : 3 : +GNDG_PLL5 : B13 : gnd : : : : +GNDA_PLL5 : B14 : gnd : : : : +GND+ : B15 : : : : 4 : +d_vsync_counter[3] : B16 : output : 3.3-V LVTTL : : 4 : N +GND* : B17 : : : : 4 : +seven_seg_pin[5] : B18 : output : 3.3-V LVTTL : : 4 : N +seven_seg_pin[3] : B19 : output : 3.3-V LVTTL : : 4 : N +GND* : B20 : : : : 4 : +GND* : B21 : : : : 4 : +GND* : B22 : : : : 4 : +GND* : B23 : : : : 4 : +GND* : B24 : : : : 4 : +GND* : B25 : : : : 4 : +GND : B26 : gnd : : : : +GND* : C1 : : : : 2 : +GND* : C2 : : : : 3 : +GND* : C3 : : : : 3 : +GND* : C4 : : : : 3 : +GND* : C5 : : : : 3 : +GND* : C6 : : : : 3 : +GND* : C7 : : : : 3 : +GND* : C8 : : : : 3 : +d_v_enable : C9 : output : 3.3-V LVTTL : : 3 : N +d_hsync_counter[0] : C10 : output : 3.3-V LVTTL : : 3 : N +d_column_counter[3] : C11 : output : 3.3-V LVTTL : : 3 : N +d_vsync_state[6] : C12 : output : 3.3-V LVTTL : : 3 : N +GND : C13 : gnd : : : : +VCCG_PLL5 : C14 : power : : 1.5V : : +d_vsync_counter[1] : C15 : output : 3.3-V LVTTL : : 4 : N +GND* : C16 : : : : 4 : +GND* : C17 : : : : 4 : +seven_seg_pin[13] : C18 : output : 3.3-V LVTTL : : 4 : N +seven_seg_pin[4] : C19 : output : 3.3-V LVTTL : : 4 : N +GND* : C20 : : : : 4 : +GND* : C21 : : : : 4 : +GND* : C22 : : : : 4 : +GND* : C23 : : : : 4 : +GND* : C24 : : : : 4 : +GND* : C25 : : : : 5 : +GND* : C26 : : : : 5 : +VCCIO2 : D1 : power : : 3.3V : 2 : +GND* : D2 : : : : 2 : +GND* : D3 : : : : 3 : +GND* : D4 : : : : 3 : +GND* : D5 : : : : 3 : +GND* : D6 : : : : 3 : +GND : D7 : gnd : : : : +GND* : D8 : : : : 3 : +GND : D9 : gnd : : : : +d_line_counter[5] : D10 : output : 3.3-V LVTTL : : 3 : N +d_hsync_counter[8] : D11 : output : 3.3-V LVTTL : : 3 : N +GND+ : D12 : : : : 3 : +VCC_PLL5_OUTA : D13 : power : : 3.3V : 9 : +VCCA_PLL5 : D14 : power : : 1.5V : : +TRST : D15 : input : : : 4 : +d_vsync_counter[2] : D16 : output : 3.3-V LVTTL : : 4 : N +GND* : D17 : : : : 4 : +seven_seg_pin[0] : D18 : output : 3.3-V LVTTL : : 4 : N +GND* : D19 : : : : 4 : +GND* : D20 : : : : 4 : +GND* : D21 : : : : 4 : +GND* : D22 : : : : 4 : +GND* : D23 : : : : 4 : +GND* : D24 : : : : 5 : +GND* : D25 : : : : 5 : +VCCIO5 : D26 : power : : 3.3V : 5 : +GND* : E1 : : : : 2 : +GND* : E2 : : : : 2 : +GND* : E3 : : : : 2 : +GND* : E4 : : : : 2 : +GND* : E5 : : : : 3 : +GND* : E6 : : : : 3 : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +d_vsync_state[1] : E9 : output : 3.3-V LVTTL : : 3 : N +d_hsync_state[3] : E10 : output : 3.3-V LVTTL : : 3 : N +d_column_counter[6] : E11 : output : 3.3-V LVTTL : : 3 : N +d_vsync_counter[0] : E12 : output : 3.3-V LVTTL : : 9 : N +d_vsync_counter[8] : E13 : output : 3.3-V LVTTL : : 9 : N +d_vsync_counter[9] : E14 : output : 3.3-V LVTTL : : 9 : N +TMS : E15 : input : : : 4 : +GND* : E16 : : : : 4 : +GND* : E17 : : : : 4 : +GND* : E18 : : : : 4 : +GND* : E19 : : : : 4 : +GND* : E20 : : : : 4 : +GND* : E21 : : : : 4 : +GND* : E22 : : : : 4 : +GND* : E23 : : : : 5 : +GND* : E24 : : : : 5 : +GND* : E25 : : : : 5 : +GND* : E26 : : : : 5 : +GND* : F1 : : : : 2 : +GND* : F2 : : : : 2 : +GND* : F3 : : : : 2 : +GND* : F4 : : : : 2 : +GND* : F5 : : : : 3 : +GND* : F6 : : : : 3 : +d_b : F7 : output : 3.3-V LVTTL : : 3 : N +GND : F8 : gnd : : : : +d_line_counter[7] : F9 : output : 3.3-V LVTTL : : 3 : N +d_column_counter[8] : F10 : output : 3.3-V LVTTL : : 3 : N +GND : F11 : gnd : : : : +d_vsync_state[2] : F12 : output : 3.3-V LVTTL : : 9 : N +d_vsync_counter[7] : F13 : output : 3.3-V LVTTL : : 9 : N +d_vsync_counter[5] : F14 : output : 3.3-V LVTTL : : 9 : N +d_vsync_counter[6] : F15 : output : 3.3-V LVTTL : : 4 : N +~DATA0~ / RESERVED_INPUT : F16 : input : 3.3-V LVTTL : : 4 : N +GND* : F17 : : : : 4 : +GND : F18 : gnd : : : : +GND* : F19 : : : : 4 : +seven_seg_pin[6] : F20 : output : 3.3-V LVTTL : : 4 : N +GND* : F21 : : : : 4 : +GND : F22 : gnd : : : : +GND* : F23 : : : : 5 : +GND* : F24 : : : : 5 : +GND* : F25 : : : : 5 : +GND* : F26 : : : : 5 : +GND* : G1 : : : : 2 : +GND* : G2 : : : : 2 : +GND* : G3 : : : : 2 : +GND* : G4 : : : : 2 : +GND* : G5 : : : : 2 : +GND* : G6 : : : : 2 : +d_hsync_state[5] : G7 : output : 3.3-V LVTTL : : 3 : N +GND : G8 : gnd : : : : +d_line_counter[6] : G9 : output : 3.3-V LVTTL : : 3 : N +d_hsync_state[2] : G10 : output : 3.3-V LVTTL : : 3 : N +d_line_counter[0] : G11 : output : 3.3-V LVTTL : : 3 : N +DCLK : G12 : : : : 3 : +TEMPDIODEn : G13 : : : : : +TDO : G14 : output : : : 4 : +TCK : G15 : input : : : 4 : +GND : G16 : gnd : : : : +GND* : G17 : : : : 4 : +GND* : G18 : : : : 4 : +GND* : G19 : : : : 4 : +GND* : G20 : : : : 4 : +GND* : G21 : : : : 5 : +GND* : G22 : : : : 5 : +GND* : G23 : : : : 5 : +GND* : G24 : : : : 5 : +GND* : G25 : : : : 5 : +GND* : G26 : : : : 5 : +GND* : H1 : : : : 2 : +GND* : H2 : : : : 2 : +GND* : H3 : : : : 2 : +GND* : H4 : : : : 2 : +GND* : H5 : : : : 2 : +GND* : H6 : : : : 2 : +GND* : H7 : : : : 2 : +GND : H8 : gnd : : : : +GND : H9 : gnd : : : : +d_hsync_counter[6] : H10 : output : 3.3-V LVTTL : : 3 : N +CONF_DONE : H11 : : : : 3 : +nCONFIG : H12 : : : : 3 : +nSTATUS : H13 : : : : 3 : +TEMPDIODEp : H14 : : : : : +TDI : H15 : input : : : 4 : +d_vsync_counter[4] : H16 : output : 3.3-V LVTTL : : 4 : N +GND : H17 : gnd : : : : +GND* : H18 : : : : 4 : +GND* : H19 : : : : 5 : +GND* : H20 : : : : 5 : +GND* : H21 : : : : 5 : +GND* : H22 : : : : 5 : +GND* : H23 : : : : 5 : +GND* : H24 : : : : 5 : +GND* : H25 : : : : 5 : +GND* : H26 : : : : 5 : +seven_seg_pin[12] : J1 : output : 3.3-V LVTTL : : 2 : N +seven_seg_pin[8] : J2 : output : 3.3-V LVTTL : : 2 : N +GND* : J3 : : : : 2 : +GND* : J4 : : : : 2 : +GND* : J5 : : : : 2 : +seven_seg_pin[7] : J6 : output : 3.3-V LVTTL : : 2 : N +GND* : J7 : : : : 2 : +d_line_counter[3] : J8 : output : 3.3-V LVTTL : : 2 : N +GND : J9 : gnd : : : : +GND : J10 : gnd : : : : +VCCIO3 : J11 : power : : 3.3V : 3 : +VCCIO3 : J12 : power : : 3.3V : 3 : +GND : J13 : gnd : : : : +GND : J14 : gnd : : : : +VCCIO4 : J15 : power : : 3.3V : 4 : +VCCIO4 : J16 : power : : 3.3V : 4 : +GND : J17 : gnd : : : : +GND : J18 : gnd : : : : +d_vsync : J19 : output : 3.3-V LVTTL : : 5 : N +vsync_pin : J20 : output : 3.3-V LVTTL : : 5 : N +GND* : J21 : : : : 5 : +GND* : J22 : : : : 5 : +GND* : J23 : : : : 5 : +GND* : J24 : : : : 5 : +GND* : J25 : : : : 5 : +GND* : J26 : : : : 5 : +d_line_counter[1] : K1 : output : 3.3-V LVTTL : : 2 : N +reset_pin : K2 : input : 3.3-V LVTTL : : 2 : N +seven_seg_pin[9] : K3 : output : 3.3-V LVTTL : : 2 : N +seven_seg_pin[2] : K4 : output : 3.3-V LVTTL : : 2 : N +d_hsync_state[0] : K5 : output : 3.3-V LVTTL : : 2 : N +d_hsync_state[4] : K6 : output : 3.3-V LVTTL : : 2 : N +d_vsync_state[5] : K7 : output : 3.3-V LVTTL : : 2 : N +d_hsync_counter[2] : K8 : output : 3.3-V LVTTL : : 2 : N +d_line_counter[4] : K9 : output : 3.3-V LVTTL : : 2 : N +GND : K10 : gnd : : : : +VCCINT : K11 : power : : 1.5V : : +GND : K12 : gnd : : : : +VCCINT : K13 : power : : 1.5V : : +GND : K14 : gnd : : : : +VCCINT : K15 : power : : 1.5V : : +GND : K16 : gnd : : : : +VCCINT : K17 : power : : 1.5V : : +GND : K18 : gnd : : : : +GND* : K19 : : : : 5 : +GND* : K20 : : : : 5 : +GND* : K21 : : : : 5 : +GND* : K22 : : : : 5 : +GND* : K23 : : : : 5 : +GND* : K24 : : : : 5 : +d_set_vsync_counter : K25 : output : 3.3-V LVTTL : : 5 : N +GND* : K26 : : : : 5 : +VCCIO2 : L1 : power : : 3.3V : 2 : +d_hsync_counter[1] : L2 : output : 3.3-V LVTTL : : 2 : N +d_hsync_counter[5] : L3 : output : 3.3-V LVTTL : : 2 : N +d_column_counter[2] : L4 : output : 3.3-V LVTTL : : 2 : N +d_hsync_counter[3] : L5 : output : 3.3-V LVTTL : : 2 : N +d_column_counter[0] : L6 : output : 3.3-V LVTTL : : 2 : N +d_column_counter[1] : L7 : output : 3.3-V LVTTL : : 2 : N +GND : L8 : gnd : : : : +VCCIO2 : L9 : power : : 3.3V : 2 : +VCCINT : L10 : power : : 1.5V : : +GND : L11 : gnd : : : : +VCCINT : L12 : power : : 1.5V : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.5V : : +GND : L15 : gnd : : : : +VCCINT : L16 : power : : 1.5V : : +GND : L17 : gnd : : : : +VCCIO5 : L18 : power : : 3.3V : 5 : +GND : L19 : gnd : : : : +GND* : L20 : : : : 5 : +GND* : L21 : : : : 5 : +GND* : L22 : : : : 5 : +GND* : L23 : : : : 5 : +GND* : L24 : : : : 5 : +GND* : L25 : : : : 5 : +VCCIO5 : L26 : power : : 3.3V : 5 : +GND+ : M1 : : : : 2 : +VCCG_PLL1 : M2 : power : : 1.5V : : +VCCA_PLL1 : M3 : power : : 1.5V : : +seven_seg_pin[10] : M4 : output : 3.3-V LVTTL : : 2 : N +GND* : M5 : : : : 2 : +d_h_enable : M6 : output : 3.3-V LVTTL : : 2 : N +seven_seg_pin[11] : M7 : output : 3.3-V LVTTL : : 2 : N +GND* : M8 : : : : 2 : +seven_seg_pin[1] : M9 : output : 3.3-V LVTTL : : 2 : N +GND : M10 : gnd : : : : +VCCINT : M11 : power : : 1.5V : : +GND : M12 : gnd : : : : +VCCINT : M13 : power : : 1.5V : : +GND : M14 : gnd : : : : +VCCINT : M15 : power : : 1.5V : : +GND : M16 : gnd : : : : +VCCINT : M17 : power : : 1.5V : : +GND* : M18 : : : : 5 : +GND* : M19 : : : : 5 : +GND* : M20 : : : : 5 : +GND* : M21 : : : : 5 : +GND* : M22 : : : : 5 : +GND* : M23 : : : : 5 : +GND+ : M24 : : : : 5 : +GND+ : M25 : : : : 5 : +GND+ : M26 : : : : 5 : +GND : N1 : gnd : : : : +GND+ : N2 : : : : 2 : +GND+ : N3 : : : : 2 : +GNDG_PLL1 : N4 : gnd : : : : +GNDA_PLL1 : N5 : gnd : : : : +GND* : N6 : : : : 2 : +GND* : N7 : : : : 2 : +d_state_clk : N8 : output : 3.3-V LVTTL : : 2 : N +GND : N9 : gnd : : : : +VCCINT : N10 : power : : 1.5V : : +GND : N11 : gnd : : : : +VCCINT : N12 : power : : 1.5V : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.5V : : +GND : N15 : gnd : : : : +VCCINT : N16 : power : : 1.5V : : +GND : N17 : gnd : : : : +GND : N18 : gnd : : : : +GND* : N19 : : : : 6 : +GND* : N20 : : : : 5 : +GND* : N21 : : : : 5 : +GNDG_PLL4 : N22 : gnd : : : : +GNDA_PLL4 : N23 : gnd : : : : +VCCG_PLL4 : N24 : power : : 1.5V : : +VCCA_PLL4 : N25 : power : : 1.5V : : +GND : N26 : gnd : : : : +GND : P1 : gnd : : : : +GNDG_PLL2 : P2 : gnd : : : : +GNDA_PLL2 : P3 : gnd : : : : +VCCG_PLL2 : P4 : power : : 1.5V : : +VCCA_PLL2 : P5 : power : : 1.5V : : +GND* : P6 : : : : 1 : +GND* : P7 : : : : 1 : +GND* : P8 : : : : 2 : +GND : P9 : gnd : : : : +GND : P10 : gnd : : : : +VCCINT : P11 : power : : 1.5V : : +GND : P12 : gnd : : : : +VCCINT : P13 : power : : 1.5V : : +GND : P14 : gnd : : : : +VCCINT : P15 : power : : 1.5V : : +GND : P16 : gnd : : : : +VCCINT : P17 : power : : 1.5V : : +GND : P18 : gnd : : : : +GND* : P19 : : : : 6 : +GND* : P20 : : : : 6 : +GND* : P21 : : : : 6 : +VCCA_PLL3 : P22 : power : : 1.5V : : +VCCG_PLL3 : P23 : power : : 1.5V : : +GND+ : P24 : : : : 6 : +GND+ : P25 : : : : 6 : +GND : P26 : gnd : : : : +GND+ : R1 : : : : 1 : +GND+ : R2 : : : : 1 : +clk_pin : R3 : input : 3.3-V LVTTL : : 1 : N +GND* : R4 : : : : 1 : +GND* : R5 : : : : 1 : +GND* : R6 : : : : 1 : +GND* : R7 : : : : 1 : +GND* : R8 : : : : 1 : +GND* : R9 : : : : 1 : +VCCINT : R10 : power : : 1.5V : : +GND : R11 : gnd : : : : +VCCINT : R12 : power : : 1.5V : : +GND : R13 : gnd : : : : +VCCINT : R14 : power : : 1.5V : : +GND : R15 : gnd : : : : +VCCINT : R16 : power : : 1.5V : : +GND : R17 : gnd : : : : +GND : R18 : gnd : : : : +GND* : R19 : : : : 6 : +GND* : R20 : : : : 6 : +GND* : R21 : : : : 6 : +GND* : R22 : : : : 6 : +GND* : R23 : : : : 6 : +GNDA_PLL3 : R24 : gnd : : : : +GNDG_PLL3 : R25 : gnd : : : : +GND+ : R26 : : : : 6 : +VCCIO1 : T1 : power : : 3.3V : 1 : +GND* : T2 : : : : 1 : +GND* : T3 : : : : 1 : +GND* : T4 : : : : 1 : +GND* : T5 : : : : 1 : +GND* : T6 : : : : 1 : +GND* : T7 : : : : 1 : +GND : T8 : gnd : : : : +VCCIO1 : T9 : power : : 3.3V : 1 : +GND : T10 : gnd : : : : +VCCINT : T11 : power : : 1.5V : : +GND : T12 : gnd : : : : +VCCINT : T13 : power : : 1.5V : : +GND : T14 : gnd : : : : +VCCINT : T15 : power : : 1.5V : : +GND : T16 : gnd : : : : +VCCINT : T17 : power : : 1.5V : : +VCCIO6 : T18 : power : : 3.3V : 6 : +GND* : T19 : : : : 6 : +GND* : T20 : : : : 6 : +GND* : T21 : : : : 6 : +GND* : T22 : : : : 6 : +GND* : T23 : : : : 6 : +GND* : T24 : : : : 6 : +GND* : T25 : : : : 6 : +VCCIO6 : T26 : power : : 3.3V : 6 : +GND* : U1 : : : : 1 : +GND* : U2 : : : : 1 : +GND* : U3 : : : : 1 : +GND* : U4 : : : : 1 : +GND* : U5 : : : : 1 : +GND* : U6 : : : : 1 : +GND* : U7 : : : : 1 : +GND* : U8 : : : : 1 : +GND* : U9 : : : : 1 : +VCCINT : U10 : power : : 1.5V : : +GND : U11 : gnd : : : : +VCCINT : U12 : power : : 1.5V : : +GND : U13 : gnd : : : : +VCCINT : U14 : power : : 1.5V : : +GND : U15 : gnd : : : : +VCCINT : U16 : power : : 1.5V : : +GND : U17 : gnd : : : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +GND* : U21 : : : : 6 : +GND* : U22 : : : : 6 : +GND* : U23 : : : : 6 : +GND* : U24 : : : : 6 : +GND* : U25 : : : : 6 : +GND* : U26 : : : : 6 : +GND* : V1 : : : : 1 : +GND* : V2 : : : : 1 : +GND* : V3 : : : : 1 : +GND* : V4 : : : : 1 : +GND* : V5 : : : : 1 : +GND* : V6 : : : : 1 : +GND : V7 : gnd : : : : +GND* : V8 : : : : 1 : +GND : V9 : gnd : : : : +GND : V10 : gnd : : : : +VCCIO8 : V11 : power : : 3.3V : 8 : +VCCIO8 : V12 : power : : 3.3V : 8 : +GND : V13 : gnd : : : : +GND : V14 : gnd : : : : +VCCIO7 : V15 : power : : 3.3V : 7 : +VCCIO7 : V16 : power : : 3.3V : 7 : +GND : V17 : gnd : : : : +GND : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND : V20 : gnd : : : : +GND* : V21 : : : : 6 : +GND* : V22 : : : : 6 : +GND* : V23 : : : : 6 : +GND* : V24 : : : : 6 : +GND* : V25 : : : : 6 : +GND* : V26 : : : : 6 : +GND* : W1 : : : : 1 : +GND* : W2 : : : : 1 : +GND* : W3 : : : : 1 : +GND* : W4 : : : : 1 : +GND* : W5 : : : : 1 : +GND* : W6 : : : : 1 : +GND* : W7 : : : : 1 : +GND* : W8 : : : : 1 : +GND* : W9 : : : : 8 : +d_g : W10 : output : 3.3-V LVTTL : : 8 : N +GND : W11 : gnd : : : : +PLL_ENA : W12 : : : : 8 : +MSEL2 : W13 : : : : 8 : +nCEO : W14 : : : : 7 : +GND* : W15 : : : : 7 : +PORSEL : W16 : : : : 7 : +GND* : W17 : : : : 7 : +GND* : W18 : : : : 7 : +GND* : W19 : : : : 6 : +GND* : W20 : : : : 6 : +GND* : W21 : : : : 6 : +GND* : W22 : : : : 6 : +GND* : W23 : : : : 6 : +GND* : W24 : : : : 6 : +GND* : W25 : : : : 6 : +GND* : W26 : : : : 6 : +GND* : Y1 : : : : 1 : +GND* : Y2 : : : : 1 : +GND* : Y3 : : : : 1 : +GND* : Y4 : : : : 1 : +GND* : Y5 : : : : 1 : +GND* : Y6 : : : : 1 : +GND : Y7 : gnd : : : : +GND* : Y8 : : : : 8 : +GND* : Y9 : : : : 8 : +g2_pin : Y10 : output : 3.3-V LVTTL : : 8 : N +d_column_counter[4] : Y11 : output : 3.3-V LVTTL : : 8 : N +MSEL0 : Y12 : : : : 8 : +MSEL1 : Y13 : : : : 8 : +nCE : Y14 : : : : 7 : +VCCSEL : Y15 : : : : 7 : +GND* : Y16 : : : : 7 : +GND* : Y17 : : : : 7 : +GND* : Y18 : : : : 7 : +GND* : Y19 : : : : 7 : +GND* : Y20 : : : : 7 : +GND : Y21 : gnd : : : : +GND* : Y22 : : : : 6 : +GND* : Y23 : : : : 6 : +GND* : Y24 : : : : 6 : +GND* : Y25 : : : : 6 : +GND* : Y26 : : : : 6 : diff --git a/bsp3/Designflow/ppr/sim/vga.pof b/bsp3/Designflow/ppr/sim/vga.pof new file mode 100644 index 0000000000000000000000000000000000000000..bcc8195780e206c933b9e349c5ff1e11106fee7b GIT binary patch literal 1048717 zcmeFa4PaAMnm2w^BXnm_l8}~yrES_2ssohL0!2%ko8FeFg%&Kz?o>;mGIa+$3ilY6Tvo)nUM&&P9~^E+S9bDr~2Q(eh0jE=bye=mpcRrfV)ZN6_?){Qr2)ok7T zovjUb-+kxStXuEgy6vvb_hc=dzaYzg-(8y;vkD3qW-VBlzi?6h!UYSKX5DgAR^@%0 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zG~MIgK4htns^81f`G+@ugJ$HLv3`}Vf_?KL(YQr#gD(Xes>3*pec9nDyPzSRzxgX- zC9@$(&LLx;aP=5p_7x>@GpR4br~hv7OGCw!eAI<*Wd6VZ!~grA{_LM${o8MK|1rcr z>^@TUZ@T}O{`e0M(m1QqM*W935P==2W4a(zJ2`CWf{#ZquD(BlaWIqU z2@5Sdu1Q0)gE*j>RNtam&vM*avv(A%OTQ|cz5RP)sTDa;u*FG=FZae(xK&=8&}88Bz3ZVMgRANZs6sfuQVR$a{jOXfR%s!)$Jc&f5AYX$~S-f$AbzZ%Q2mw z@PW@){FmR27?R@zP-dJCv9~%TQsrhtRhs?pf6)B|5pH?jhAOf2$tL!zeyA}d7~h|K lH_HJLv{|RUNtH*EtNq04bT9jq^rNoVmNk<<+56?y{|`&Z*rxyh literal 0 HcmV?d00001 diff --git a/bsp3/Designflow/ppr/sim/vga.tan.rpt b/bsp3/Designflow/ppr/sim/vga.tan.rpt new file mode 100644 index 0000000..766881b --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.tan.rpt @@ -0,0 +1,659 @@ +Classic Timing Analyzer report for vga +Thu Oct 29 17:00:52 2009 +Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Parallel Compilation + 6. Clock Setup: 'clk_pin' + 7. tsu + 8. tco + 9. tpd + 10. th + 11. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++------------------------------+-------+---------------+----------------------------------+--------------------------------------------+------------------------------------------+------------+----------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++------------------------------+-------+---------------+----------------------------------+--------------------------------------------+------------------------------------------+------------+----------+--------------+ +; Worst-case tsu ; N/A ; None ; 6.710 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_3 ; -- ; clk_pin ; 0 ; +; Worst-case tco ; N/A ; None ; 10.979 ns ; dly_counter[0] ; seven_seg_pin[1] ; clk_pin ; -- ; 0 ; +; Worst-case tpd ; N/A ; None ; 13.335 ns ; reset_pin ; seven_seg_pin[1] ; -- ; -- ; 0 ; +; Worst-case th ; N/A ; None ; -3.134 ns ; reset_pin ; vga_driver:vga_driver_unit|h_sync ; -- ; clk_pin ; 0 ; +; Clock Setup: 'clk_pin' ; N/A ; None ; 191.53 MHz ( period = 5.221 ns ) ; vga_driver:vga_driver_unit|vsync_counter_4 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; ++------------------------------+-------+---------------+----------------------------------+--------------------------------------------+------------------------------------------+------------+----------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Device Name ; EP1S25F672C6 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; Off ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; clk_pin ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'clk_pin' ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; N/A ; 191.53 MHz ( period = 5.221 ns ) ; vga_driver:vga_driver_unit|vsync_counter_4 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 5.035 ns ; +; N/A ; 196.04 MHz ( period = 5.101 ns ) ; vga_driver:vga_driver_unit|vsync_counter_4 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.915 ns ; +; N/A ; 197.63 MHz ( period = 5.060 ns ) ; vga_driver:vga_driver_unit|vsync_counter_6 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.874 ns ; +; N/A ; 199.88 MHz ( period = 5.003 ns ) ; vga_driver:vga_driver_unit|vsync_counter_4 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.817 ns ; +; N/A ; 199.88 MHz ( period = 5.003 ns ) ; vga_driver:vga_driver_unit|vsync_counter_4 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.817 ns ; +; N/A ; 199.88 MHz ( period = 5.003 ns ) ; vga_driver:vga_driver_unit|vsync_counter_4 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.817 ns ; +; N/A ; 201.21 MHz ( period = 4.970 ns ) ; vga_driver:vga_driver_unit|vsync_counter_7 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.784 ns ; +; N/A ; 202.43 MHz ( period = 4.940 ns ) ; vga_driver:vga_driver_unit|vsync_counter_6 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.754 ns ; +; N/A ; 206.19 MHz ( period = 4.850 ns ) ; vga_driver:vga_driver_unit|vsync_counter_7 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.664 ns ; +; N/A ; 206.53 MHz ( period = 4.842 ns ) ; vga_driver:vga_driver_unit|vsync_counter_6 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.656 ns ; +; N/A ; 206.53 MHz ( period = 4.842 ns ) ; vga_driver:vga_driver_unit|vsync_counter_6 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.656 ns ; +; N/A ; 206.53 MHz ( period = 4.842 ns ) ; vga_driver:vga_driver_unit|vsync_counter_6 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.656 ns ; +; N/A ; 208.20 MHz ( period = 4.803 ns ) ; vga_driver:vga_driver_unit|vsync_counter_8 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.617 ns ; +; N/A ; 210.44 MHz ( period = 4.752 ns ) ; vga_driver:vga_driver_unit|vsync_counter_7 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.566 ns ; +; N/A ; 210.44 MHz ( period = 4.752 ns ) ; vga_driver:vga_driver_unit|vsync_counter_7 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.566 ns ; +; N/A ; 210.44 MHz ( period = 4.752 ns ) ; vga_driver:vga_driver_unit|vsync_counter_7 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.566 ns ; +; N/A ; 212.09 MHz ( period = 4.715 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.529 ns ; +; N/A ; 213.13 MHz ( period = 4.692 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.506 ns ; +; N/A ; 213.54 MHz ( period = 4.683 ns ) ; vga_driver:vga_driver_unit|vsync_counter_8 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.497 ns ; +; N/A ; 214.09 MHz ( period = 4.671 ns ) ; vga_driver:vga_driver_unit|vsync_counter_2 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.485 ns ; +; N/A ; 217.20 MHz ( period = 4.604 ns ) ; vga_driver:vga_driver_unit|vsync_counter_3 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.418 ns ; +; N/A ; 217.58 MHz ( period = 4.596 ns ) ; vga_driver:vga_driver_unit|vsync_counter_5 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.410 ns ; +; N/A ; 218.10 MHz ( period = 4.585 ns ) ; vga_driver:vga_driver_unit|vsync_counter_8 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.399 ns ; +; N/A ; 218.10 MHz ( period = 4.585 ns ) ; vga_driver:vga_driver_unit|vsync_counter_8 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.399 ns ; +; N/A ; 218.10 MHz ( period = 4.585 ns ) ; vga_driver:vga_driver_unit|vsync_counter_8 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.399 ns ; +; N/A ; 219.39 MHz ( period = 4.558 ns ) ; vga_driver:vga_driver_unit|vsync_counter_0 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.372 ns ; +; N/A ; 219.73 MHz ( period = 4.551 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.365 ns ; +; N/A ; 219.73 MHz ( period = 4.551 ns ) ; vga_driver:vga_driver_unit|vsync_counter_2 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.365 ns ; +; N/A ; 220.07 MHz ( period = 4.544 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.358 ns ; +; N/A ; 220.07 MHz ( period = 4.544 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.358 ns ; +; N/A ; 220.07 MHz ( period = 4.544 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.358 ns ; +; N/A ; 220.07 MHz ( period = 4.544 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.358 ns ; +; N/A ; 220.07 MHz ( period = 4.544 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.358 ns ; +; N/A ; 220.12 MHz ( period = 4.543 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.357 ns ; +; N/A ; 221.19 MHz ( period = 4.521 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.335 ns ; +; N/A ; 221.19 MHz ( period = 4.521 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.335 ns ; +; N/A ; 221.19 MHz ( period = 4.521 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.335 ns ; +; N/A ; 221.19 MHz ( period = 4.521 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.335 ns ; +; N/A ; 221.19 MHz ( period = 4.521 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.335 ns ; +; N/A ; 223.02 MHz ( period = 4.484 ns ) ; vga_driver:vga_driver_unit|vsync_counter_3 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.298 ns ; +; N/A ; 223.41 MHz ( period = 4.476 ns ) ; vga_driver:vga_driver_unit|vsync_counter_5 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.290 ns ; +; N/A ; 223.81 MHz ( period = 4.468 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.282 ns ; +; N/A ; 224.52 MHz ( period = 4.454 ns ) ; vga_driver:vga_driver_unit|hsync_counter_3 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.268 ns ; +; N/A ; 224.57 MHz ( period = 4.453 ns ) ; vga_driver:vga_driver_unit|vsync_counter_2 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.267 ns ; +; N/A ; 224.57 MHz ( period = 4.453 ns ) ; vga_driver:vga_driver_unit|vsync_counter_2 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.267 ns ; +; N/A ; 224.57 MHz ( period = 4.453 ns ) ; vga_driver:vga_driver_unit|vsync_counter_2 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.267 ns ; +; N/A ; 225.33 MHz ( period = 4.438 ns ) ; vga_driver:vga_driver_unit|vsync_counter_0 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.252 ns ; +; N/A ; 225.43 MHz ( period = 4.436 ns ) ; vga_driver:vga_driver_unit|vsync_counter_1 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.250 ns ; +; N/A ; 227.38 MHz ( period = 4.398 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.212 ns ; +; N/A ; 227.43 MHz ( period = 4.397 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.211 ns ; +; N/A ; 227.53 MHz ( period = 4.395 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.209 ns ; +; N/A ; 227.58 MHz ( period = 4.394 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.208 ns ; +; N/A ; 227.63 MHz ( period = 4.393 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.207 ns ; +; N/A ; 227.74 MHz ( period = 4.391 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.205 ns ; +; N/A ; 227.89 MHz ( period = 4.388 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.202 ns ; +; N/A ; 228.00 MHz ( period = 4.386 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.200 ns ; +; N/A ; 228.00 MHz ( period = 4.386 ns ) ; vga_driver:vga_driver_unit|vsync_counter_3 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.200 ns ; +; N/A ; 228.00 MHz ( period = 4.386 ns ) ; vga_driver:vga_driver_unit|vsync_counter_3 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.200 ns ; +; N/A ; 228.00 MHz ( period = 4.386 ns ) ; vga_driver:vga_driver_unit|vsync_counter_3 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.200 ns ; +; N/A ; 228.05 MHz ( period = 4.385 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.199 ns ; +; N/A ; 228.15 MHz ( period = 4.383 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.197 ns ; +; N/A ; 228.31 MHz ( period = 4.380 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.194 ns ; +; N/A ; 228.31 MHz ( period = 4.380 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.194 ns ; +; N/A ; 228.31 MHz ( period = 4.380 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.194 ns ; +; N/A ; 228.31 MHz ( period = 4.380 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.194 ns ; +; N/A ; 228.31 MHz ( period = 4.380 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.194 ns ; +; N/A ; 228.31 MHz ( period = 4.380 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.194 ns ; +; N/A ; 228.41 MHz ( period = 4.378 ns ) ; vga_driver:vga_driver_unit|vsync_counter_5 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.192 ns ; +; N/A ; 228.41 MHz ( period = 4.378 ns ) ; vga_driver:vga_driver_unit|vsync_counter_5 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.192 ns ; +; N/A ; 228.41 MHz ( period = 4.378 ns ) ; vga_driver:vga_driver_unit|vsync_counter_5 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.192 ns ; +; N/A ; 228.73 MHz ( period = 4.372 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.186 ns ; +; N/A ; 228.73 MHz ( period = 4.372 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.186 ns ; +; N/A ; 228.73 MHz ( period = 4.372 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.186 ns ; +; N/A ; 228.73 MHz ( period = 4.372 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.186 ns ; +; N/A ; 228.73 MHz ( period = 4.372 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.186 ns ; +; N/A ; 229.67 MHz ( period = 4.354 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.193 ns ; +; N/A ; 230.41 MHz ( period = 4.340 ns ) ; vga_driver:vga_driver_unit|vsync_counter_0 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.154 ns ; +; N/A ; 230.41 MHz ( period = 4.340 ns ) ; vga_driver:vga_driver_unit|vsync_counter_0 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.154 ns ; +; N/A ; 230.41 MHz ( period = 4.340 ns ) ; vga_driver:vga_driver_unit|vsync_counter_0 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.154 ns ; +; N/A ; 230.47 MHz ( period = 4.339 ns ) ; vga_driver:vga_driver_unit|vsync_counter_9 ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.153 ns ; +; N/A ; 231.21 MHz ( period = 4.325 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.139 ns ; +; N/A ; 231.37 MHz ( period = 4.322 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.136 ns ; +; N/A ; 231.70 MHz ( period = 4.316 ns ) ; vga_driver:vga_driver_unit|vsync_counter_1 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.130 ns ; +; N/A ; 232.72 MHz ( period = 4.297 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.111 ns ; +; N/A ; 232.72 MHz ( period = 4.297 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.111 ns ; +; N/A ; 232.72 MHz ( period = 4.297 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.111 ns ; +; N/A ; 232.72 MHz ( period = 4.297 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.111 ns ; +; N/A ; 232.72 MHz ( period = 4.297 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.111 ns ; +; N/A ; 233.48 MHz ( period = 4.283 ns ) ; vga_driver:vga_driver_unit|hsync_counter_3 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.097 ns ; +; N/A ; 233.48 MHz ( period = 4.283 ns ) ; vga_driver:vga_driver_unit|hsync_counter_3 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.097 ns ; +; N/A ; 233.48 MHz ( period = 4.283 ns ) ; vga_driver:vga_driver_unit|hsync_counter_3 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.097 ns ; +; N/A ; 233.48 MHz ( period = 4.283 ns ) ; vga_driver:vga_driver_unit|hsync_counter_3 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.097 ns ; +; N/A ; 233.48 MHz ( period = 4.283 ns ) ; vga_driver:vga_driver_unit|hsync_counter_3 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.097 ns ; +; N/A ; 235.35 MHz ( period = 4.249 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.088 ns ; +; N/A ; 237.02 MHz ( period = 4.219 ns ) ; vga_driver:vga_driver_unit|vsync_counter_9 ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.033 ns ; +; N/A ; 237.08 MHz ( period = 4.218 ns ) ; vga_driver:vga_driver_unit|vsync_counter_1 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.032 ns ; +; N/A ; 237.08 MHz ( period = 4.218 ns ) ; vga_driver:vga_driver_unit|vsync_counter_1 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.032 ns ; +; N/A ; 237.08 MHz ( period = 4.218 ns ) ; vga_driver:vga_driver_unit|vsync_counter_1 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.032 ns ; +; N/A ; 237.25 MHz ( period = 4.215 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.029 ns ; +; N/A ; 237.25 MHz ( period = 4.215 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.029 ns ; +; N/A ; 237.25 MHz ( period = 4.215 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.029 ns ; +; N/A ; 237.25 MHz ( period = 4.215 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.029 ns ; +; N/A ; 237.25 MHz ( period = 4.215 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.029 ns ; +; N/A ; 239.06 MHz ( period = 4.183 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.022 ns ; +; N/A ; 239.06 MHz ( period = 4.183 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.022 ns ; +; N/A ; 239.06 MHz ( period = 4.183 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.022 ns ; +; N/A ; 239.06 MHz ( period = 4.183 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.022 ns ; +; N/A ; 239.06 MHz ( period = 4.183 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.022 ns ; +; N/A ; 240.73 MHz ( period = 4.154 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 3.968 ns ; +; N/A ; 240.73 MHz ( period = 4.154 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 3.968 ns ; +; N/A ; 240.73 MHz ( period = 4.154 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 3.968 ns ; +; N/A ; 240.73 MHz ( period = 4.154 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 3.968 ns ; +; N/A ; 240.73 MHz ( period = 4.154 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 3.968 ns ; +; N/A ; 240.91 MHz ( period = 4.151 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 3.965 ns ; +; N/A ; 240.91 MHz ( period = 4.151 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 3.965 ns ; +; N/A ; 240.91 MHz ( period = 4.151 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 3.965 ns ; +; N/A ; 240.91 MHz ( period = 4.151 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 3.965 ns ; +; N/A ; 240.91 MHz ( period = 4.151 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 3.965 ns ; +; N/A ; 242.66 MHz ( period = 4.121 ns ) ; vga_driver:vga_driver_unit|vsync_counter_9 ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 3.935 ns ; +; N/A ; 242.66 MHz ( period = 4.121 ns ) ; vga_driver:vga_driver_unit|vsync_counter_9 ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 3.935 ns ; +; N/A ; 242.66 MHz ( period = 4.121 ns ) ; vga_driver:vga_driver_unit|vsync_counter_9 ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 3.935 ns ; +; N/A ; 245.22 MHz ( period = 4.078 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 3.917 ns ; +; N/A ; 245.22 MHz ( period = 4.078 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 3.917 ns ; +; N/A ; 245.22 MHz ( period = 4.078 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 3.917 ns ; +; N/A ; 245.22 MHz ( period = 4.078 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 3.917 ns ; +; N/A ; 245.22 MHz ( period = 4.078 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 3.917 ns ; +; N/A ; 245.88 MHz ( period = 4.067 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|h_enable_sig ; clk_pin ; clk_pin ; None ; None ; 3.917 ns ; +; N/A ; 245.88 MHz ( period = 4.067 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 3.881 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 247.59 MHz ( period = 4.039 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 3.878 ns ; +; N/A ; 251.83 MHz ( period = 3.971 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|line_counter_sig_5 ; clk_pin ; clk_pin ; None ; None ; 3.760 ns ; +; N/A ; 252.40 MHz ( period = 3.962 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|h_enable_sig ; clk_pin ; clk_pin ; None ; None ; 3.812 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.19 MHz ( period = 3.934 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 3.773 ns ; +; N/A ; 254.97 MHz ( period = 3.922 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ; clk_pin ; None ; None ; 3.747 ns ; +; N/A ; 255.95 MHz ( period = 3.907 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ; clk_pin ; None ; None ; 3.732 ns ; +; N/A ; 255.95 MHz ( period = 3.907 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ; clk_pin ; None ; None ; 3.732 ns ; +; N/A ; 255.95 MHz ( period = 3.907 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ; clk_pin ; None ; None ; 3.732 ns ; +; N/A ; 255.95 MHz ( period = 3.907 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ; clk_pin ; None ; None ; 3.732 ns ; +; N/A ; 256.67 MHz ( period = 3.896 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 3.710 ns ; +; N/A ; 256.67 MHz ( period = 3.896 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 3.710 ns ; +; N/A ; 256.67 MHz ( period = 3.896 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 3.710 ns ; +; N/A ; 256.67 MHz ( period = 3.896 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 3.710 ns ; +; N/A ; 256.67 MHz ( period = 3.896 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 3.710 ns ; +; N/A ; 257.53 MHz ( period = 3.883 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ; clk_pin ; None ; None ; 3.697 ns ; +; N/A ; 257.53 MHz ( period = 3.883 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ; clk_pin ; None ; None ; 3.697 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.67 MHz ( period = 3.881 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 3.695 ns ; +; N/A ; 257.93 MHz ( period = 3.877 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ; clk_pin ; None ; None ; 3.702 ns ; +; N/A ; 257.93 MHz ( period = 3.877 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ; clk_pin ; None ; None ; 3.702 ns ; +; N/A ; 257.93 MHz ( period = 3.877 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ; clk_pin ; None ; None ; 3.702 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 259.40 MHz ( period = 3.855 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 3.669 ns ; +; N/A ; 260.28 MHz ( period = 3.842 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|vsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 3.631 ns ; +; N/A ; 260.28 MHz ( period = 3.842 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|vsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 3.631 ns ; +; N/A ; 260.28 MHz ( period = 3.842 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|vsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 3.631 ns ; +; N/A ; 260.28 MHz ( period = 3.842 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|vsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 3.631 ns ; +; N/A ; 260.28 MHz ( period = 3.842 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|vsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 3.631 ns ; +; N/A ; 260.62 MHz ( period = 3.837 ns ) ; vga_driver:vga_driver_unit|vsync_counter_4 ; vga_driver:vga_driver_unit|vsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 3.687 ns ; +; N/A ; 260.76 MHz ( period = 3.835 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|vsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 3.649 ns ; +; N/A ; 260.76 MHz ( period = 3.835 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|vsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 3.649 ns ; +; N/A ; 260.76 MHz ( period = 3.835 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|vsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 3.649 ns ; +; N/A ; 260.76 MHz ( period = 3.835 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|vsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 3.649 ns ; +; N/A ; 260.76 MHz ( period = 3.835 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|vsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 3.649 ns ; +; N/A ; 260.76 MHz ( period = 3.835 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|vsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 3.649 ns ; +; N/A ; 260.76 MHz ( period = 3.835 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|vsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 3.649 ns ; +; N/A ; 260.76 MHz ( period = 3.835 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|vsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 3.649 ns ; +; N/A ; 260.76 MHz ( period = 3.835 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|vsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 3.649 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; tsu ; ++-------+--------------+------------+-----------+-------------------------------------------------+----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-------+--------------+------------+-----------+-------------------------------------------------+----------+ +; N/A ; None ; 6.710 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; +; N/A ; None ; 6.539 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; +; N/A ; None ; 6.539 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; +; N/A ; None ; 6.539 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; +; N/A ; None ; 6.539 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; +; N/A ; None ; 6.539 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; +; N/A ; None ; 6.423 ns ; reset_pin ; vga_driver:vga_driver_unit|h_enable_sig ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; +; N/A ; None ; 6.395 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_0 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_1 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_2 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_3 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_4 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_5 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_6 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_7 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_8 ; clk_pin ; +; N/A ; None ; 6.191 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_9 ; clk_pin ; +; N/A ; None ; 6.146 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; +; N/A ; None ; 6.026 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; +; N/A ; None ; 5.928 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; +; N/A ; None ; 5.928 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; +; N/A ; None ; 5.928 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; +; N/A ; None ; 5.869 ns ; reset_pin ; vga_driver:vga_driver_unit|v_enable_sig ; clk_pin ; +; N/A ; None ; 5.795 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_6 ; clk_pin ; +; N/A ; None ; 5.555 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ; +; N/A ; None ; 5.540 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ; +; N/A ; None ; 5.540 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ; +; N/A ; None ; 5.540 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ; +; N/A ; None ; 5.540 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ; +; N/A ; None ; 5.510 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ; +; N/A ; None ; 5.510 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ; +; N/A ; None ; 5.510 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ; +; N/A ; None ; 5.495 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_1 ; clk_pin ; +; N/A ; None ; 5.356 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ; +; N/A ; None ; 5.045 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_1 ; clk_pin ; +; N/A ; None ; 5.045 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_2 ; clk_pin ; +; N/A ; None ; 5.045 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_3 ; clk_pin ; +; N/A ; None ; 5.045 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_4 ; clk_pin ; +; N/A ; None ; 5.045 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_7 ; clk_pin ; +; N/A ; None ; 5.038 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_0 ; clk_pin ; +; N/A ; None ; 5.038 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_6 ; clk_pin ; +; N/A ; None ; 5.038 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_8 ; clk_pin ; +; N/A ; None ; 5.009 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_8 ; clk_pin ; +; N/A ; None ; 4.641 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_5 ; clk_pin ; +; N/A ; None ; 3.474 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_6 ; clk_pin ; +; N/A ; None ; 3.469 ns ; reset_pin ; vga_driver:vga_driver_unit|v_sync ; clk_pin ; +; N/A ; None ; 3.465 ns ; reset_pin ; dly_counter[0] ; clk_pin ; +; N/A ; None ; 3.465 ns ; reset_pin ; dly_counter[1] ; clk_pin ; +; N/A ; None ; 3.244 ns ; reset_pin ; vga_driver:vga_driver_unit|h_sync ; clk_pin ; ++-------+--------------+------------+-----------+-------------------------------------------------+----------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; tco ; ++-------+--------------+------------+-------------------------------------------------+----------------------+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++-------+--------------+------------+-------------------------------------------------+----------------------+------------+ +; N/A ; None ; 10.979 ns ; dly_counter[0] ; seven_seg_pin[1] ; clk_pin ; +; N/A ; None ; 10.874 ns ; dly_counter[1] ; seven_seg_pin[1] ; clk_pin ; +; N/A ; None ; 10.512 ns ; dly_counter[0] ; seven_seg_pin[10] ; clk_pin ; +; N/A ; None ; 10.500 ns ; dly_counter[0] ; seven_seg_pin[11] ; clk_pin ; +; N/A ; None ; 10.407 ns ; dly_counter[1] ; seven_seg_pin[10] ; clk_pin ; +; N/A ; None ; 10.395 ns ; dly_counter[1] ; seven_seg_pin[11] ; clk_pin ; +; N/A ; None ; 10.367 ns ; dly_counter[0] ; seven_seg_pin[9] ; clk_pin ; +; N/A ; None ; 10.367 ns ; dly_counter[0] ; seven_seg_pin[2] ; clk_pin ; +; N/A ; None ; 10.262 ns ; dly_counter[1] ; seven_seg_pin[9] ; clk_pin ; +; N/A ; None ; 10.262 ns ; dly_counter[1] ; seven_seg_pin[2] ; clk_pin ; +; N/A ; None ; 10.189 ns ; vga_control:vga_control_unit|r ; r2_pin ; clk_pin ; +; N/A ; None ; 10.189 ns ; vga_control:vga_control_unit|r ; r1_pin ; clk_pin ; +; N/A ; None ; 10.189 ns ; vga_control:vga_control_unit|r ; r0_pin ; clk_pin ; +; N/A ; None ; 10.157 ns ; vga_control:vga_control_unit|r ; d_r ; clk_pin ; +; N/A ; None ; 10.096 ns ; vga_driver:vga_driver_unit|vsync_state_6 ; d_set_vsync_counter ; clk_pin ; +; N/A ; None ; 9.924 ns ; dly_counter[0] ; seven_seg_pin[12] ; clk_pin ; +; N/A ; None ; 9.924 ns ; dly_counter[0] ; seven_seg_pin[8] ; clk_pin ; +; N/A ; None ; 9.924 ns ; dly_counter[0] ; seven_seg_pin[7] ; clk_pin ; +; N/A ; None ; 9.819 ns ; dly_counter[1] ; seven_seg_pin[12] ; clk_pin ; +; N/A ; None ; 9.819 ns ; dly_counter[1] ; seven_seg_pin[8] ; clk_pin ; +; N/A ; None ; 9.819 ns ; dly_counter[1] ; seven_seg_pin[7] ; clk_pin ; +; N/A ; None ; 9.806 ns ; vga_driver:vga_driver_unit|vsync_state_0 ; d_set_vsync_counter ; clk_pin ; +; N/A ; None ; 9.798 ns ; vga_driver:vga_driver_unit|vsync_state_3 ; d_vsync_state[3] ; clk_pin ; +; N/A ; None ; 9.346 ns ; vga_driver:vga_driver_unit|hsync_state_1 ; d_hsync_state[1] ; clk_pin ; +; N/A ; None ; 9.346 ns ; vga_driver:vga_driver_unit|hsync_state_1 ; d_set_column_counter ; clk_pin ; +; N/A ; None ; 9.305 ns ; vga_driver:vga_driver_unit|hsync_state_6 ; d_hsync_state[6] ; clk_pin ; +; N/A ; None ; 9.275 ns ; vga_driver:vga_driver_unit|vsync_state_0 ; d_vsync_state[0] ; clk_pin ; +; N/A ; None ; 9.161 ns ; vga_driver:vga_driver_unit|hsync_state_0 ; d_set_hsync_counter ; clk_pin ; +; N/A ; None ; 9.123 ns ; vga_driver:vga_driver_unit|h_sync ; d_hsync ; clk_pin ; +; N/A ; None ; 9.123 ns ; vga_driver:vga_driver_unit|h_sync ; hsync_pin ; clk_pin ; +; N/A ; None ; 9.002 ns ; vga_driver:vga_driver_unit|column_counter_sig_5 ; d_column_counter[5] ; clk_pin ; +; N/A ; None ; 8.969 ns ; vga_driver:vga_driver_unit|column_counter_sig_7 ; d_column_counter[7] ; clk_pin ; +; N/A ; None ; 8.889 ns ; vga_driver:vga_driver_unit|column_counter_sig_9 ; d_column_counter[9] ; clk_pin ; +; N/A ; None ; 8.858 ns ; vga_control:vga_control_unit|g ; d_g ; clk_pin ; +; N/A ; None ; 8.858 ns ; vga_control:vga_control_unit|g ; g2_pin ; clk_pin ; +; N/A ; None ; 8.858 ns ; vga_control:vga_control_unit|g ; g1_pin ; clk_pin ; +; N/A ; None ; 8.858 ns ; vga_control:vga_control_unit|g ; g0_pin ; clk_pin ; +; N/A ; None ; 8.735 ns ; vga_control:vga_control_unit|b ; d_b ; clk_pin ; +; N/A ; None ; 8.735 ns ; vga_control:vga_control_unit|b ; b1_pin ; clk_pin ; +; N/A ; None ; 8.735 ns ; vga_control:vga_control_unit|b ; b0_pin ; clk_pin ; +; N/A ; None ; 8.601 ns ; vga_driver:vga_driver_unit|v_enable_sig ; d_v_enable ; clk_pin ; +; N/A ; None ; 8.569 ns ; vga_driver:vga_driver_unit|vsync_counter_8 ; d_vsync_counter[8] ; clk_pin ; +; N/A ; None ; 8.565 ns ; vga_driver:vga_driver_unit|vsync_counter_7 ; d_vsync_counter[7] ; clk_pin ; +; N/A ; None ; 8.562 ns ; vga_driver:vga_driver_unit|vsync_counter_9 ; d_vsync_counter[9] ; clk_pin ; +; N/A ; None ; 8.468 ns ; vga_driver:vga_driver_unit|v_sync ; d_vsync ; clk_pin ; +; N/A ; None ; 8.468 ns ; vga_driver:vga_driver_unit|v_sync ; vsync_pin ; clk_pin ; +; N/A ; None ; 8.431 ns ; vga_driver:vga_driver_unit|vsync_state_1 ; d_vsync_state[1] ; clk_pin ; +; N/A ; None ; 8.431 ns ; vga_driver:vga_driver_unit|vsync_state_1 ; d_set_line_counter ; clk_pin ; +; N/A ; None ; 8.361 ns ; vga_driver:vga_driver_unit|hsync_state_5 ; d_hsync_state[5] ; clk_pin ; +; N/A ; None ; 8.344 ns ; vga_driver:vga_driver_unit|vsync_state_5 ; d_vsync_state[5] ; clk_pin ; +; N/A ; None ; 8.342 ns ; vga_driver:vga_driver_unit|vsync_counter_2 ; d_vsync_counter[2] ; clk_pin ; +; N/A ; None ; 8.340 ns ; vga_driver:vga_driver_unit|vsync_counter_4 ; d_vsync_counter[4] ; clk_pin ; +; N/A ; None ; 8.340 ns ; vga_driver:vga_driver_unit|line_counter_sig_2 ; d_line_counter[2] ; clk_pin ; +; N/A ; None ; 8.317 ns ; vga_driver:vga_driver_unit|vsync_counter_3 ; d_vsync_counter[3] ; clk_pin ; +; N/A ; None ; 8.317 ns ; vga_driver:vga_driver_unit|vsync_counter_1 ; d_vsync_counter[1] ; clk_pin ; +; N/A ; None ; 8.285 ns ; vga_driver:vga_driver_unit|column_counter_sig_4 ; d_column_counter[4] ; clk_pin ; +; N/A ; None ; 8.275 ns ; vga_driver:vga_driver_unit|vsync_state_2 ; d_vsync_state[2] ; clk_pin ; +; N/A ; None ; 8.273 ns ; vga_driver:vga_driver_unit|vsync_counter_0 ; d_vsync_counter[0] ; clk_pin ; +; N/A ; None ; 8.271 ns ; vga_driver:vga_driver_unit|line_counter_sig_7 ; d_line_counter[7] ; clk_pin ; +; N/A ; None ; 8.270 ns ; vga_driver:vga_driver_unit|vsync_state_4 ; d_vsync_state[4] ; clk_pin ; +; N/A ; None ; 8.253 ns ; vga_driver:vga_driver_unit|h_enable_sig ; d_h_enable ; clk_pin ; +; N/A ; None ; 8.247 ns ; vga_driver:vga_driver_unit|line_counter_sig_8 ; d_line_counter[8] ; clk_pin ; +; N/A ; None ; 8.238 ns ; vga_driver:vga_driver_unit|hsync_state_4 ; d_hsync_state[4] ; clk_pin ; +; N/A ; None ; 8.236 ns ; vga_driver:vga_driver_unit|hsync_counter_9 ; d_hsync_counter[9] ; clk_pin ; +; N/A ; None ; 8.225 ns ; vga_driver:vga_driver_unit|column_counter_sig_2 ; d_column_counter[2] ; clk_pin ; +; N/A ; None ; 8.209 ns ; vga_driver:vga_driver_unit|hsync_state_6 ; d_set_hsync_counter ; clk_pin ; +; N/A ; None ; 8.209 ns ; vga_driver:vga_driver_unit|hsync_counter_4 ; d_hsync_counter[4] ; clk_pin ; +; N/A ; None ; 8.190 ns ; vga_driver:vga_driver_unit|hsync_state_0 ; d_hsync_state[0] ; clk_pin ; +; N/A ; None ; 8.114 ns ; vga_driver:vga_driver_unit|column_counter_sig_3 ; d_column_counter[3] ; clk_pin ; +; N/A ; None ; 8.092 ns ; vga_driver:vga_driver_unit|hsync_state_3 ; d_hsync_state[3] ; clk_pin ; +; N/A ; None ; 8.085 ns ; vga_driver:vga_driver_unit|hsync_counter_0 ; d_hsync_counter[0] ; clk_pin ; +; N/A ; None ; 8.084 ns ; vga_driver:vga_driver_unit|hsync_state_2 ; d_hsync_state[2] ; clk_pin ; +; N/A ; None ; 8.083 ns ; vga_driver:vga_driver_unit|vsync_counter_6 ; d_vsync_counter[6] ; clk_pin ; +; N/A ; None ; 8.074 ns ; vga_driver:vga_driver_unit|column_counter_sig_0 ; d_column_counter[0] ; clk_pin ; +; N/A ; None ; 8.067 ns ; vga_driver:vga_driver_unit|hsync_counter_8 ; d_hsync_counter[8] ; clk_pin ; +; N/A ; None ; 8.063 ns ; vga_driver:vga_driver_unit|hsync_counter_7 ; d_hsync_counter[7] ; clk_pin ; +; N/A ; None ; 8.024 ns ; vga_driver:vga_driver_unit|hsync_counter_6 ; d_hsync_counter[6] ; clk_pin ; +; N/A ; None ; 8.020 ns ; vga_driver:vga_driver_unit|hsync_counter_2 ; d_hsync_counter[2] ; clk_pin ; +; N/A ; None ; 8.019 ns ; vga_driver:vga_driver_unit|vsync_state_6 ; d_vsync_state[6] ; clk_pin ; +; N/A ; None ; 8.013 ns ; vga_driver:vga_driver_unit|hsync_counter_3 ; d_hsync_counter[3] ; clk_pin ; +; N/A ; None ; 8.011 ns ; vga_driver:vga_driver_unit|line_counter_sig_3 ; d_line_counter[3] ; clk_pin ; +; N/A ; None ; 8.010 ns ; vga_driver:vga_driver_unit|line_counter_sig_5 ; d_line_counter[5] ; clk_pin ; +; N/A ; None ; 8.003 ns ; vga_driver:vga_driver_unit|hsync_counter_5 ; d_hsync_counter[5] ; clk_pin ; +; N/A ; None ; 8.001 ns ; vga_driver:vga_driver_unit|line_counter_sig_6 ; d_line_counter[6] ; clk_pin ; +; N/A ; None ; 7.991 ns ; vga_driver:vga_driver_unit|line_counter_sig_0 ; d_line_counter[0] ; clk_pin ; +; N/A ; None ; 7.965 ns ; vga_driver:vga_driver_unit|hsync_counter_1 ; d_hsync_counter[1] ; clk_pin ; +; N/A ; None ; 7.891 ns ; vga_driver:vga_driver_unit|column_counter_sig_8 ; d_column_counter[8] ; clk_pin ; +; N/A ; None ; 7.833 ns ; vga_driver:vga_driver_unit|vsync_counter_5 ; d_vsync_counter[5] ; clk_pin ; +; N/A ; None ; 7.803 ns ; vga_driver:vga_driver_unit|column_counter_sig_1 ; d_column_counter[1] ; clk_pin ; +; N/A ; None ; 7.795 ns ; vga_driver:vga_driver_unit|column_counter_sig_6 ; d_column_counter[6] ; clk_pin ; +; N/A ; None ; 7.754 ns ; vga_driver:vga_driver_unit|line_counter_sig_4 ; d_line_counter[4] ; clk_pin ; +; N/A ; None ; 7.735 ns ; vga_driver:vga_driver_unit|line_counter_sig_1 ; d_line_counter[1] ; clk_pin ; ++-------+--------------+------------+-------------------------------------------------+----------------------+------------+ + + ++-----------------------------------------------------------------------------+ +; tpd ; ++-------+-------------------+-----------------+-----------+-------------------+ +; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; ++-------+-------------------+-----------------+-----------+-------------------+ +; N/A ; None ; 13.335 ns ; reset_pin ; seven_seg_pin[1] ; +; N/A ; None ; 12.868 ns ; reset_pin ; seven_seg_pin[10] ; +; N/A ; None ; 12.856 ns ; reset_pin ; seven_seg_pin[11] ; +; N/A ; None ; 12.723 ns ; reset_pin ; seven_seg_pin[9] ; +; N/A ; None ; 12.723 ns ; reset_pin ; seven_seg_pin[2] ; +; N/A ; None ; 12.280 ns ; reset_pin ; seven_seg_pin[12] ; +; N/A ; None ; 12.280 ns ; reset_pin ; seven_seg_pin[8] ; +; N/A ; None ; 12.280 ns ; reset_pin ; seven_seg_pin[7] ; +; N/A ; None ; 5.951 ns ; clk_pin ; d_state_clk ; ++-------+-------------------+-----------------+-----------+-------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; th ; ++---------------+-------------+-----------+-----------+-------------------------------------------------+----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++---------------+-------------+-----------+-----------+-------------------------------------------------+----------+ +; N/A ; None ; -3.134 ns ; reset_pin ; vga_driver:vga_driver_unit|h_sync ; clk_pin ; +; N/A ; None ; -3.355 ns ; reset_pin ; dly_counter[0] ; clk_pin ; +; N/A ; None ; -3.355 ns ; reset_pin ; dly_counter[1] ; clk_pin ; +; N/A ; None ; -3.359 ns ; reset_pin ; vga_driver:vga_driver_unit|v_sync ; clk_pin ; +; N/A ; None ; -3.364 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_6 ; clk_pin ; +; N/A ; None ; -4.063 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_9 ; clk_pin ; +; N/A ; None ; -4.065 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_4 ; clk_pin ; +; N/A ; None ; -4.065 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_7 ; clk_pin ; +; N/A ; None ; -4.065 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_8 ; clk_pin ; +; N/A ; None ; -4.066 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_3 ; clk_pin ; +; N/A ; None ; -4.066 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_5 ; clk_pin ; +; N/A ; None ; -4.066 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_6 ; clk_pin ; +; N/A ; None ; -4.067 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_2 ; clk_pin ; +; N/A ; None ; -4.068 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_0 ; clk_pin ; +; N/A ; None ; -4.068 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_1 ; clk_pin ; +; N/A ; None ; -4.378 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ; +; N/A ; None ; -4.531 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_5 ; clk_pin ; +; N/A ; None ; -4.775 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ; +; N/A ; None ; -4.899 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_8 ; clk_pin ; +; N/A ; None ; -4.928 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_0 ; clk_pin ; +; N/A ; None ; -4.928 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_6 ; clk_pin ; +; N/A ; None ; -4.928 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_8 ; clk_pin ; +; N/A ; None ; -4.935 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_1 ; clk_pin ; +; N/A ; None ; -4.935 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_2 ; clk_pin ; +; N/A ; None ; -4.935 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_3 ; clk_pin ; +; N/A ; None ; -4.935 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_4 ; clk_pin ; +; N/A ; None ; -4.935 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_7 ; clk_pin ; +; N/A ; None ; -4.977 ns ; reset_pin ; vga_driver:vga_driver_unit|v_enable_sig ; clk_pin ; +; N/A ; None ; -5.009 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; +; N/A ; None ; -5.012 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; +; N/A ; None ; -5.014 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; +; N/A ; None ; -5.017 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; +; N/A ; None ; -5.020 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; +; N/A ; None ; -5.022 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; +; N/A ; None ; -5.023 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; +; N/A ; None ; -5.024 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; +; N/A ; None ; -5.026 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; +; N/A ; None ; -5.027 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; +; N/A ; None ; -5.043 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ; +; N/A ; None ; -5.043 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ; +; N/A ; None ; -5.043 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ; +; N/A ; None ; -5.246 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ; +; N/A ; None ; -5.385 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_1 ; clk_pin ; +; N/A ; None ; -5.400 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ; +; N/A ; None ; -5.400 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ; +; N/A ; None ; -5.400 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ; +; N/A ; None ; -5.430 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ; +; N/A ; None ; -5.430 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ; +; N/A ; None ; -5.430 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ; +; N/A ; None ; -5.430 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ; +; N/A ; None ; -5.445 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ; +; N/A ; None ; -5.651 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; +; N/A ; None ; -5.651 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; +; N/A ; None ; -5.651 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; +; N/A ; None ; -5.651 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; +; N/A ; None ; -5.651 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; +; N/A ; None ; -5.671 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; +; N/A ; None ; -5.681 ns ; reset_pin ; vga_driver:vga_driver_unit|h_enable_sig ; clk_pin ; +; N/A ; None ; -5.685 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_6 ; clk_pin ; ++---------------+-------------+-----------+-----------+-------------------------------------------------+----------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.0 Build 132 02/25/2009 SJ Full Version + Info: Processing started: Thu Oct 29 17:00:51 2009 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Warning: Found pins functioning as undefined clocks and/or memory enables + Info: Assuming node "clk_pin" is an undefined clock +Info: Clock "clk_pin" has Internal fmax of 191.53 MHz between source register "vga_driver:vga_driver_unit|vsync_counter_4" and destination register "vga_driver:vga_driver_unit|vsync_state_3" (period= 5.221 ns) + Info: + Longest register to register delay is 5.035 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X37_Y35_N4; Fanout = 6; REG Node = 'vga_driver:vga_driver_unit|vsync_counter_4' + Info: 2: + IC(1.033 ns) + CELL(0.459 ns) = 1.492 ns; Loc. = LC_X38_Y35_N7; Fanout = 3; COMB Node = 'vga_driver:vga_driver_unit|un12_vsync_counter_7' + Info: 3: + IC(0.854 ns) + CELL(0.087 ns) = 2.433 ns; Loc. = LC_X36_Y35_N1; Fanout = 4; COMB Node = 'vga_driver:vga_driver_unit|un14_vsync_counter_8' + Info: 4: + IC(0.565 ns) + CELL(0.087 ns) = 3.085 ns; Loc. = LC_X35_Y35_N6; Fanout = 1; COMB Node = 'vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3' + Info: 5: + IC(0.564 ns) + CELL(0.087 ns) = 3.736 ns; Loc. = LC_X36_Y35_N7; Fanout = 5; COMB Node = 'vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa' + Info: 6: + IC(0.573 ns) + CELL(0.726 ns) = 5.035 ns; Loc. = LC_X35_Y35_N6; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|vsync_state_3' + Info: Total cell delay = 1.446 ns ( 28.72 % ) + Info: Total interconnect delay = 3.589 ns ( 71.28 % ) + Info: - Smallest clock skew is 0.000 ns + Info: + Shortest clock path from clock "clk_pin" to destination register is 3.191 ns + Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin' + Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X35_Y35_N6; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|vsync_state_3' + Info: Total cell delay = 1.428 ns ( 44.75 % ) + Info: Total interconnect delay = 1.763 ns ( 55.25 % ) + Info: - Longest clock path from clock "clk_pin" to source register is 3.191 ns + Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin' + Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X37_Y35_N4; Fanout = 6; REG Node = 'vga_driver:vga_driver_unit|vsync_counter_4' + Info: Total cell delay = 1.428 ns ( 44.75 % ) + Info: Total interconnect delay = 1.763 ns ( 55.25 % ) + Info: + Micro clock to output delay of source is 0.176 ns + Info: + Micro setup delay of destination is 0.010 ns +Info: tsu for register "vga_driver:vga_driver_unit|hsync_state_3" (data pin = "reset_pin", clock pin = "clk_pin") is 6.710 ns + Info: + Longest pin to register delay is 9.916 ns + Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K2; Fanout = 10; PIN Node = 'reset_pin' + Info: 2: + IC(4.777 ns) + CELL(0.459 ns) = 6.531 ns; Loc. = LC_X35_Y35_N2; Fanout = 32; COMB Node = 'vga_driver:vga_driver_unit|un6_dly_counter_0_x' + Info: 3: + IC(1.669 ns) + CELL(0.459 ns) = 8.659 ns; Loc. = LC_X29_Y33_N4; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0' + Info: 4: + IC(0.531 ns) + CELL(0.726 ns) = 9.916 ns; Loc. = LC_X28_Y33_N3; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|hsync_state_3' + Info: Total cell delay = 2.939 ns ( 29.64 % ) + Info: Total interconnect delay = 6.977 ns ( 70.36 % ) + Info: + Micro setup delay of destination is 0.010 ns + Info: - Shortest clock path from clock "clk_pin" to destination register is 3.216 ns + Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin' + Info: 2: + IC(1.788 ns) + CELL(0.560 ns) = 3.216 ns; Loc. = LC_X28_Y33_N3; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|hsync_state_3' + Info: Total cell delay = 1.428 ns ( 44.40 % ) + Info: Total interconnect delay = 1.788 ns ( 55.60 % ) +Info: tco from clock "clk_pin" to destination pin "seven_seg_pin[1]" through register "dly_counter[0]" is 10.979 ns + Info: + Longest clock path from clock "clk_pin" to source register is 3.191 ns + Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin' + Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X35_Y35_N5; Fanout = 10; REG Node = 'dly_counter[0]' + Info: Total cell delay = 1.428 ns ( 44.75 % ) + Info: Total interconnect delay = 1.763 ns ( 55.25 % ) + Info: + Micro clock to output delay of source is 0.176 ns + Info: + Longest register to pin delay is 7.612 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y35_N5; Fanout = 10; REG Node = 'dly_counter[0]' + Info: 2: + IC(0.476 ns) + CELL(0.332 ns) = 0.808 ns; Loc. = LC_X35_Y35_N2; Fanout = 32; COMB Node = 'vga_driver:vga_driver_unit|un6_dly_counter_0_x' + Info: 3: + IC(4.309 ns) + CELL(2.495 ns) = 7.612 ns; Loc. = PIN_M9; Fanout = 0; PIN Node = 'seven_seg_pin[1]' + Info: Total cell delay = 2.827 ns ( 37.14 % ) + Info: Total interconnect delay = 4.785 ns ( 62.86 % ) +Info: Longest tpd from source pin "reset_pin" to destination pin "seven_seg_pin[1]" is 13.335 ns + Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K2; Fanout = 10; PIN Node = 'reset_pin' + Info: 2: + IC(4.777 ns) + CELL(0.459 ns) = 6.531 ns; Loc. = LC_X35_Y35_N2; Fanout = 32; COMB Node = 'vga_driver:vga_driver_unit|un6_dly_counter_0_x' + Info: 3: + IC(4.309 ns) + CELL(2.495 ns) = 13.335 ns; Loc. = PIN_M9; Fanout = 0; PIN Node = 'seven_seg_pin[1]' + Info: Total cell delay = 4.249 ns ( 31.86 % ) + Info: Total interconnect delay = 9.086 ns ( 68.14 % ) +Info: th for register "vga_driver:vga_driver_unit|h_sync" (data pin = "reset_pin", clock pin = "clk_pin") is -3.134 ns + Info: + Longest clock path from clock "clk_pin" to destination register is 3.191 ns + Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin' + Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X34_Y35_N2; Fanout = 3; REG Node = 'vga_driver:vga_driver_unit|h_sync' + Info: Total cell delay = 1.428 ns ( 44.75 % ) + Info: Total interconnect delay = 1.763 ns ( 55.25 % ) + Info: + Micro hold delay of destination is 0.100 ns + Info: - Shortest pin to register delay is 6.425 ns + Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K2; Fanout = 10; PIN Node = 'reset_pin' + Info: 2: + IC(4.641 ns) + CELL(0.489 ns) = 6.425 ns; Loc. = LC_X34_Y35_N2; Fanout = 3; REG Node = 'vga_driver:vga_driver_unit|h_sync' + Info: Total cell delay = 1.784 ns ( 27.77 % ) + Info: Total interconnect delay = 4.641 ns ( 72.23 % ) +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 140 megabytes + Info: Processing ended: Thu Oct 29 17:00:52 2009 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/bsp3/Designflow/ppr/sim/vga.tan.summary b/bsp3/Designflow/ppr/sim/vga.tan.summary new file mode 100644 index 0000000..bef5743 --- /dev/null +++ b/bsp3/Designflow/ppr/sim/vga.tan.summary @@ -0,0 +1,66 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : N/A +Required Time : None +Actual Time : 6.710 ns +From : reset_pin +To : vga_driver:vga_driver_unit|hsync_state_3 +From Clock : -- +To Clock : clk_pin +Failed Paths : 0 + +Type : Worst-case tco +Slack : N/A +Required Time : None +Actual Time : 10.979 ns +From : dly_counter[0] +To : seven_seg_pin[1] +From Clock : clk_pin +To Clock : -- +Failed Paths : 0 + +Type : Worst-case tpd +Slack : N/A +Required Time : None +Actual Time : 13.335 ns +From : reset_pin +To : seven_seg_pin[1] +From Clock : -- +To Clock : -- +Failed Paths : 0 + +Type : Worst-case th +Slack : N/A +Required Time : None +Actual Time : -3.134 ns +From : reset_pin +To : vga_driver:vga_driver_unit|h_sync +From Clock : -- +To Clock : clk_pin +Failed Paths : 0 + +Type : Clock Setup: 'clk_pin' +Slack : N/A +Required Time : None +Actual Time : 191.53 MHz ( period = 5.221 ns ) +From : vga_driver:vga_driver_unit|vsync_counter_4 +To : vga_driver:vga_driver_unit|vsync_state_3 +From Clock : clk_pin +To Clock : clk_pin +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 0 + +-------------------------------------------------------------------------------------- + diff --git a/bsp3/Designflow/sim/beh/modelsim.ini b/bsp3/Designflow/sim/beh/modelsim.ini new file mode 100644 index 0000000..0a48df5 --- /dev/null +++ b/bsp3/Designflow/sim/beh/modelsim.ini @@ -0,0 +1,1305 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0-in compiler on the VHDL source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverageSub = 0 + +; Automatically exclude VHDL case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn off detection of FSMs having single bit current state variable. +; FsmSingle = 0 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/report/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect ; +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal +; to or greater than 1M are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Run the 0-in compiler on the Verilog source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a Verilog condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + + +; Turn on code coverage in VLOG `celldefine modules and modules included +; using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 1 to 4, with the following +; meanings (the default is 3): +; 1 -- Turn off all optimizations that affect coverage reports. +; 2 -- Allow optimizations that allow large performance improvements +; by invoking sequential processes only when the data changes. +; This may make major reductions in coverage counts. +; 3 -- In addition, allow optimizations that may change expressions or +; remove some statements. Allow constant propagation. Allow VHDL +; subprogram inlining and VHDL FF recognition. +; 4 -- In addition, allow optimizations that may remove major regions of +; code by changing assignments to built-ins or removing unused +; signals. Change Verilog gates to continuous assignments. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "merge_instances" option for +; the Covergroup Type. This is a compile time option which forces +; "merge_instances" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupMergeInstancesDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiOvm mtiUPF + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn off detection of FSMs having single bit current state variable. +; FsmSingle = 0 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SVFileExtensions = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2001 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "package_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a vopt condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; vopt automatic SDF +; If automatic design optimization is on, enables automatic compilation +; of SDF files. +; Default is on, uncomment to turn off. +; VoptAutoSDFCompile = 0 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Stop the simulator after a VHDL/Verilog immediate assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; VHDL assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %i - Instance pathname with process +; %O - Process name +; %K - Kind of object path is to return: Instance, Signal, Process or Unknown +; %P - Instance or Region path without leaf process +; %F - File +; %L - Line number of assertion or, if assertion is in a subprogram, line +; from which the call is made +; %% - Print '%' character +; If specific format for assertion level is defined, use its format. +; If specific format is not defined for assertion level: +; - and if failure occurs during elaboration, use MessageFormatBreakLine; +; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion +; level), use MessageFormatBreak; +; - otherwise, use MessageFormat. +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops do to a breakpoint or fatal error. +; Example w/function name: # Break in Process ctr at counter.vhd line 44 +; Example wo/function name: # Break at counter.vhd line 44 +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable System Verilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be indexed during +; simulation. If set to 0, the WLF file will not be indexed. +; The default is 1, indexed the WLF file. +; WLFIndex = 0 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 256M per open WLF file. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: these ini variables can be overriden by the vsim command +; line switch "-onfinish ". +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result at the end of simulation before shutdown. +; If this is enabled, the simstats result will be printed out before shutdown. +; The default is off. +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA concurrent assertion pass enable. +; For SVA, Default is on when the assertion has a pass action block, or +; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active. +; For PSL, Default is on only when vsim switch "-assertdebug" is used +; and the vopt "+acc=a" flag is active. +; AssertionPassEnable = 0 + +; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on. +; AssertionFailEnable = 0 + +; Set PSL/SVA concurrent assertion pass limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionPassLimit = 1 + +; Set PSL/SVA concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionFailLimit = 1 + +; Turn on/off PSL concurrent assertion pass log. Default is off. +; The flag does not affect SVA +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that +; are included for toggle coverage. This leads to a longer simulation time with bigger +; arrays covered with toggle coverage. Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable is 1 +; SVCovergroup63Compatibility = 1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0in runtime tool. +; Default value set to "". +; ZeroInOptions = "" + +; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog). +; Sv_Seed = 0 + +; Maximum size of dynamic arrays that are resized during randomize(). +; The default is 1000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 1000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; The default is 0 (no error). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures (SystemVerilog). +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; When SolveFailDebug is enabled, this value specifies the algorithm used to +; discover conflicts between constraints for randomize() failures. +; The default is "many". +; +; Valid schemes are: +; "many" = best for determining conflicts due to many related constraints +; "few" = best for determining conflicts due to few related constraints +; +; SolveFailDebugScheme = many + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum number of constraint subsets that will be tested for +; conflicts. +; The default is 0 (no limit). +; SolveFailDebugLimit = 0 + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum size of constraint subsets that will be tested for +; conflicts. +; The default value is 0 (no limit). +; SolveFailDebugMaxSet = 0 + +; Maximum size of the solution graph that may be generated during randomize(). +; This value can be used to force randomize() to abort if the memory +; requirements of the constraint scenario exceeds the specified limit. This +; value is specified in 1000s of nodes. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Maximum number of evaluations that may be performed on the solution graph +; generated during randomize(). This value can be used to force randomize() to +; abort if the complexity of the constraint scenario (in time) exceeds the +; specified limit. This value is specified in 10000s of evaluations. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of +; the constraint solver for others. +; The default value is "" (no options). +; +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints +; n = disable bit interleaving for all constraints +; r = reverse bit interleaving +; +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; Note: To achieve the same random sequences, solver optimizations and/or +; bug fixes introduced since the specified release may be disabled - +; yielding the performance / behavior of the prior release. +; Default value set to "" (random compatibility not required). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +; MvcHome = $MODEL_TECH/... + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; suppress = 3009,CNNODP,3043,TFMPC +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear in the transcript and recorded in the wlf +; file (messages that are recorded in the wlf file can be viewed +; in the MsgViewer). The other settings are to send messages +; only to the transcript or only to the wlf file. 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