From 1d3e86fec5ba52f04aefbb676c4d03446264c2c8 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Wed, 21 Oct 2009 18:01:48 +0200 Subject: [PATCH] bsp2 fail :( --- bsp2/Designflow/sim/beh/modelsim.ini | 1305 +++ bsp2/Designflow/sim/beh/vsim.wlf | Bin 0 -> 65536 bytes bsp2/Designflow/sim/beh/work/@_opt/_deps | Bin 0 -> 6080 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt0bs2x8 | Bin 0 -> 1580 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt0cjzjx | Bin 0 -> 384 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt0yenjz | Bin 0 -> 840 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt1957w4 | Bin 0 -> 773 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt1iz797 | Bin 0 -> 1180 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt2z1zfr | 78 + bsp2/Designflow/sim/beh/work/@_opt/vopt3m54vn | Bin 0 -> 1277 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt3tamac | Bin 0 -> 224 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt5mkn60 | Bin 0 -> 15586 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt6ys38z | Bin 0 -> 8815 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt7d04k7 | Bin 0 -> 3258 bytes bsp2/Designflow/sim/beh/work/@_opt/vopt7ict39 | Bin 0 -> 1838 bytes bsp2/Designflow/sim/beh/work/@_opt/voptac7ek2 | Bin 0 -> 4545 bytes bsp2/Designflow/sim/beh/work/@_opt/voptaktcq1 | Bin 0 -> 352 bytes bsp2/Designflow/sim/beh/work/@_opt/voptbsw4zv | Bin 0 -> 7704 bytes bsp2/Designflow/sim/beh/work/@_opt/voptch0esh | Bin 0 -> 11433 bytes bsp2/Designflow/sim/beh/work/@_opt/voptebbdqt | Bin 0 -> 1340 bytes bsp2/Designflow/sim/beh/work/@_opt/voptejdczt | Bin 0 -> 4987 bytes bsp2/Designflow/sim/beh/work/@_opt/voptfbaa2n | Bin 0 -> 596 bytes bsp2/Designflow/sim/beh/work/@_opt/voptfk8v07 | Bin 0 -> 3529 bytes bsp2/Designflow/sim/beh/work/@_opt/voptfwi5me | Bin 0 -> 4824 bytes bsp2/Designflow/sim/beh/work/@_opt/voptg1qkds | Bin 0 -> 6440 bytes bsp2/Designflow/sim/beh/work/@_opt/voptghbm62 | 417 + bsp2/Designflow/sim/beh/work/@_opt/voptgt6ndk | Bin 0 -> 5559 bytes bsp2/Designflow/sim/beh/work/@_opt/voptgw99md | Bin 0 -> 572 bytes bsp2/Designflow/sim/beh/work/@_opt/voptgxqqnc | 238 + bsp2/Designflow/sim/beh/work/@_opt/vopti55zgy | Bin 0 -> 248 bytes bsp2/Designflow/sim/beh/work/@_opt/voptikcy5f | Bin 0 -> 171 bytes bsp2/Designflow/sim/beh/work/@_opt/voptinez7z | Bin 0 -> 2525 bytes bsp2/Designflow/sim/beh/work/@_opt/voptjxs6b5 | Bin 0 -> 2661 bytes bsp2/Designflow/sim/beh/work/@_opt/voptkiwmfh | Bin 0 -> 21168 bytes bsp2/Designflow/sim/beh/work/@_opt/voptkzqyc7 | Bin 0 -> 572 bytes bsp2/Designflow/sim/beh/work/@_opt/voptmbg596 | Bin 0 -> 572 bytes bsp2/Designflow/sim/beh/work/@_opt/voptnfby50 | Bin 0 -> 1547 bytes bsp2/Designflow/sim/beh/work/@_opt/voptqhiwfn | Bin 0 -> 8860 bytes bsp2/Designflow/sim/beh/work/@_opt/voptqrfa3s | Bin 0 -> 458 bytes bsp2/Designflow/sim/beh/work/@_opt/vopts422ii | Bin 0 -> 2315 bytes bsp2/Designflow/sim/beh/work/@_opt/voptszb1wz | Bin 0 -> 4144 bytes bsp2/Designflow/sim/beh/work/@_opt/voptvshyjf | Bin 0 -> 45512 bytes bsp2/Designflow/sim/beh/work/@_opt/voptvsmqcj | Bin 0 -> 37208 bytes bsp2/Designflow/sim/beh/work/@_opt/voptxabtjv | Bin 0 -> 875 bytes bsp2/Designflow/sim/beh/work/@_opt/voptz36f0c | Bin 0 -> 571 bytes bsp2/Designflow/sim/beh/work/_info | 234 + bsp2/Designflow/sim/beh/work/_vmake | 3 + .../sim/beh/work/board_driver/_primary.dat | Bin 0 -> 352 bytes .../sim/beh/work/board_driver/_primary.dbs | Bin 0 -> 773 bytes .../sim/beh/work/board_driver/behav.dat | Bin 0 -> 1547 bytes .../sim/beh/work/board_driver/behav.dbs | Bin 0 -> 4824 bytes bsp2/Designflow/sim/beh/work/vga/_primary.dat | Bin 0 -> 1277 bytes bsp2/Designflow/sim/beh/work/vga/_primary.dbs | Bin 0 -> 2661 bytes bsp2/Designflow/sim/beh/work/vga/behav.dat | Bin 0 -> 3258 bytes bsp2/Designflow/sim/beh/work/vga/behav.dbs | Bin 0 -> 8815 bytes .../sim/beh/work/vga_conf_beh/_primary.dat | Bin 0 -> 171 bytes .../sim/beh/work/vga_conf_beh/_primary.dbs | Bin 0 -> 458 bytes .../sim/beh/work/vga_control/_primary.dat | Bin 0 -> 596 bytes .../sim/beh/work/vga_control/_primary.dbs | Bin 0 -> 1340 bytes .../sim/beh/work/vga_control/behav.dat | Bin 0 -> 1580 bytes .../sim/beh/work/vga_control/behav.dbs | Bin 0 -> 4987 bytes .../sim/beh/work/vga_driver/_primary.dat | Bin 0 -> 875 bytes .../sim/beh/work/vga_driver/_primary.dbs | Bin 0 -> 1838 bytes .../sim/beh/work/vga_driver/behav.dat | Bin 0 -> 5559 bytes .../sim/beh/work/vga_driver/behav.dbs | Bin 0 -> 15586 bytes .../sim/beh/work/vga_pak/_primary.dat | Bin 0 -> 2315 bytes .../sim/beh/work/vga_pak/_primary.dbs | Bin 0 -> 3529 bytes .../sim/beh/work/vga_tb/_primary.dat | Bin 0 -> 224 bytes .../sim/beh/work/vga_tb/_primary.dbs | Bin 0 -> 571 bytes .../sim/beh/work/vga_tb/behaviour.dat | Bin 0 -> 2525 bytes .../sim/beh/work/vga_tb/behaviour.dbs | Bin 0 -> 6440 bytes bsp2/Designflow/src/board_driver_arc.vhd | 102 + bsp2/Designflow/src/board_driver_ent.vhd | 42 + bsp2/Designflow/src/modelsim.ini | 1305 +++ bsp2/Designflow/src/vga.hex | 4097 ++++++++ bsp2/Designflow/src/vga_arc.vhd | 223 + bsp2/Designflow/src/vga_beh_tb.vhd | 194 + bsp2/Designflow/src/vga_control_arc.vhd | 129 + bsp2/Designflow/src/vga_control_arc.vhd~ | 129 + bsp2/Designflow/src/vga_control_ent.vhd | 53 + bsp2/Designflow/src/vga_driver_arc.vhd | 402 + bsp2/Designflow/src/vga_driver_ent.vhd | 60 + bsp2/Designflow/src/vga_ent.vhd | 73 + bsp2/Designflow/src/vga_pak.vhd | 85 + bsp2/Designflow/src/vga_pll.bdf | 847 ++ bsp2/Designflow/src/vga_pll.tcl | 184 + bsp2/Designflow/src/vga_pos_tb.vhd | 198 + bsp2/Designflow/src/vga_pre_tb.vhd | 197 + bsp2/Designflow/src/vpll.bsf | 49 + bsp2/Designflow/src/vpll.vhd | 274 + bsp2/Designflow/syn/rev_1/.recordref | 0 bsp2/Designflow/syn/rev_1/backup/vga.srr | 33 + bsp2/Designflow/syn/rev_1/rpt_vga.areasrr | 174 + bsp2/Designflow/syn/rev_1/rpt_vga_areasrr.htm | 193 + bsp2/Designflow/syn/rev_1/run_options.txt | 71 + bsp2/Designflow/syn/rev_1/scratchproject.prs | 71 + bsp2/Designflow/syn/rev_1/syntmp/sap.log | 13 + .../syn/rev_1/syntmp/sap_log_flink.htm | 8 + .../syn/rev_1/syntmp/sap_log_srr.htm | 0 bsp2/Designflow/syn/rev_1/syntmp/vga.msg | 22 + bsp2/Designflow/syn/rev_1/syntmp/vga.plg | 13 + .../syn/rev_1/syntmp/vga_cons_ui.tcl | 5 + .../syn/rev_1/syntmp/vga_driver_arc_flink.htm | 7 + .../Designflow/syn/rev_1/syntmp/vga_flink.htm | 8 + bsp2/Designflow/syn/rev_1/syntmp/vga_srr.htm | 315 + bsp2/Designflow/syn/rev_1/syntmp/vga_toc.htm | 17 + bsp2/Designflow/syn/rev_1/verif/vga.vif | 141 + bsp2/Designflow/syn/rev_1/vga.fse | 0 bsp2/Designflow/syn/rev_1/vga.htm | 12 + bsp2/Designflow/syn/rev_1/vga.map | 1 + bsp2/Designflow/syn/rev_1/vga.sap | 153 + bsp2/Designflow/syn/rev_1/vga.srd | Bin 0 -> 27844 bytes bsp2/Designflow/syn/rev_1/vga.srm | 8984 +++++++++++++++++ bsp2/Designflow/syn/rev_1/vga.srr | 312 + bsp2/Designflow/syn/rev_1/vga.srs | 685 ++ bsp2/Designflow/syn/rev_1/vga.sxr | 377 + bsp2/Designflow/syn/rev_1/vga.szr | Bin 0 -> 14253 bytes bsp2/Designflow/syn/rev_1/vga.tcl | 41 + bsp2/Designflow/syn/rev_1/vga.tlg | 12 + bsp2/Designflow/syn/rev_1/vga.vhm | 6862 +++++++++++++ bsp2/Designflow/syn/rev_1/vga.vqm | 6206 ++++++++++++ bsp2/Designflow/syn/rev_1/vga.xrf | 343 + bsp2/Designflow/syn/rev_1/vga_cons.tcl | 6 + bsp2/Designflow/syn/rev_1/vga_rm.tcl | 12 + bsp2/Designflow/syn/vga.prd | 13 + bsp2/Designflow/syn/vga.prj | 71 + bsp2/transcript | 13 + 127 files changed, 36112 insertions(+) create mode 100644 bsp2/Designflow/sim/beh/modelsim.ini create mode 100644 bsp2/Designflow/sim/beh/vsim.wlf create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/_deps create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt0bs2x8 create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt0cjzjx create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt0yenjz create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt1957w4 create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt1iz797 create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt2z1zfr create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt3m54vn create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt3tamac create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt5mkn60 create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt6ys38z create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt7d04k7 create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/vopt7ict39 create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptac7ek2 create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptaktcq1 create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptbsw4zv create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptch0esh create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptebbdqt create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptejdczt create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptfbaa2n create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptfk8v07 create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptfwi5me create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptg1qkds create mode 100644 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bsp2/Designflow/sim/beh/work/@_opt/voptszb1wz create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptvshyjf create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptvsmqcj create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptxabtjv create mode 100644 bsp2/Designflow/sim/beh/work/@_opt/voptz36f0c create mode 100644 bsp2/Designflow/sim/beh/work/_info create mode 100644 bsp2/Designflow/sim/beh/work/_vmake create mode 100644 bsp2/Designflow/sim/beh/work/board_driver/_primary.dat create mode 100644 bsp2/Designflow/sim/beh/work/board_driver/_primary.dbs create mode 100644 bsp2/Designflow/sim/beh/work/board_driver/behav.dat create mode 100644 bsp2/Designflow/sim/beh/work/board_driver/behav.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga/_primary.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga/_primary.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga/behav.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga/behav.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga_conf_beh/_primary.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga_conf_beh/_primary.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga_control/_primary.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga_control/_primary.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga_control/behav.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga_control/behav.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga_driver/_primary.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga_driver/_primary.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga_driver/behav.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga_driver/behav.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga_pak/_primary.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga_pak/_primary.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga_tb/_primary.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga_tb/_primary.dbs create mode 100644 bsp2/Designflow/sim/beh/work/vga_tb/behaviour.dat create mode 100644 bsp2/Designflow/sim/beh/work/vga_tb/behaviour.dbs create mode 100644 bsp2/Designflow/src/board_driver_arc.vhd create mode 100644 bsp2/Designflow/src/board_driver_ent.vhd create mode 100644 bsp2/Designflow/src/modelsim.ini create mode 100644 bsp2/Designflow/src/vga.hex create mode 100644 bsp2/Designflow/src/vga_arc.vhd create mode 100644 bsp2/Designflow/src/vga_beh_tb.vhd create mode 100644 bsp2/Designflow/src/vga_control_arc.vhd create mode 100644 bsp2/Designflow/src/vga_control_arc.vhd~ create mode 100644 bsp2/Designflow/src/vga_control_ent.vhd create mode 100644 bsp2/Designflow/src/vga_driver_arc.vhd create mode 100644 bsp2/Designflow/src/vga_driver_ent.vhd create mode 100644 bsp2/Designflow/src/vga_ent.vhd create mode 100644 bsp2/Designflow/src/vga_pak.vhd create mode 100755 bsp2/Designflow/src/vga_pll.bdf create mode 100755 bsp2/Designflow/src/vga_pll.tcl create mode 100644 bsp2/Designflow/src/vga_pos_tb.vhd create mode 100644 bsp2/Designflow/src/vga_pre_tb.vhd create mode 100644 bsp2/Designflow/src/vpll.bsf create mode 100644 bsp2/Designflow/src/vpll.vhd create mode 100644 bsp2/Designflow/syn/rev_1/.recordref create mode 100644 bsp2/Designflow/syn/rev_1/backup/vga.srr create mode 100644 bsp2/Designflow/syn/rev_1/rpt_vga.areasrr create mode 100644 bsp2/Designflow/syn/rev_1/rpt_vga_areasrr.htm create mode 100644 bsp2/Designflow/syn/rev_1/run_options.txt create mode 100644 bsp2/Designflow/syn/rev_1/scratchproject.prs create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/sap.log create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/sap_log_flink.htm create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/sap_log_srr.htm create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/vga.msg create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/vga.plg create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/vga_cons_ui.tcl create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/vga_driver_arc_flink.htm create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/vga_flink.htm create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/vga_srr.htm create mode 100644 bsp2/Designflow/syn/rev_1/syntmp/vga_toc.htm create mode 100644 bsp2/Designflow/syn/rev_1/verif/vga.vif create mode 100644 bsp2/Designflow/syn/rev_1/vga.fse create mode 100644 bsp2/Designflow/syn/rev_1/vga.htm create mode 100644 bsp2/Designflow/syn/rev_1/vga.map create mode 100644 bsp2/Designflow/syn/rev_1/vga.sap create mode 100644 bsp2/Designflow/syn/rev_1/vga.srd create mode 100644 bsp2/Designflow/syn/rev_1/vga.srm create mode 100644 bsp2/Designflow/syn/rev_1/vga.srr create mode 100644 bsp2/Designflow/syn/rev_1/vga.srs create mode 100644 bsp2/Designflow/syn/rev_1/vga.sxr create mode 100644 bsp2/Designflow/syn/rev_1/vga.szr create mode 100644 bsp2/Designflow/syn/rev_1/vga.tcl create mode 100644 bsp2/Designflow/syn/rev_1/vga.tlg create mode 100644 bsp2/Designflow/syn/rev_1/vga.vhm create mode 100644 bsp2/Designflow/syn/rev_1/vga.vqm create mode 100644 bsp2/Designflow/syn/rev_1/vga.xrf create mode 100644 bsp2/Designflow/syn/rev_1/vga_cons.tcl create mode 100644 bsp2/Designflow/syn/rev_1/vga_rm.tcl create mode 100644 bsp2/Designflow/syn/vga.prd create mode 100644 bsp2/Designflow/syn/vga.prj create mode 100644 bsp2/transcript diff --git a/bsp2/Designflow/sim/beh/modelsim.ini b/bsp2/Designflow/sim/beh/modelsim.ini new file mode 100644 index 0000000..0a48df5 --- /dev/null +++ b/bsp2/Designflow/sim/beh/modelsim.ini @@ -0,0 +1,1305 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0-in compiler on the VHDL source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverageSub = 0 + +; Automatically exclude VHDL case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn off detection of FSMs having single bit current state variable. +; FsmSingle = 0 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/report/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect ; +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal +; to or greater than 1M are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Run the 0-in compiler on the Verilog source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a Verilog condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + + +; Turn on code coverage in VLOG `celldefine modules and modules included +; using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 1 to 4, with the following +; meanings (the default is 3): +; 1 -- Turn off all optimizations that affect coverage reports. +; 2 -- Allow optimizations that allow large performance improvements +; by invoking sequential processes only when the data changes. +; This may make major reductions in coverage counts. +; 3 -- In addition, allow optimizations that may change expressions or +; remove some statements. Allow constant propagation. Allow VHDL +; subprogram inlining and VHDL FF recognition. +; 4 -- In addition, allow optimizations that may remove major regions of +; code by changing assignments to built-ins or removing unused +; signals. Change Verilog gates to continuous assignments. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "merge_instances" option for +; the Covergroup Type. This is a compile time option which forces +; "merge_instances" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupMergeInstancesDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiOvm mtiUPF + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn off detection of FSMs having single bit current state variable. +; FsmSingle = 0 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SVFileExtensions = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2001 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "package_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a vopt condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; vopt automatic SDF +; If automatic design optimization is on, enables automatic compilation +; of SDF files. +; Default is on, uncomment to turn off. +; VoptAutoSDFCompile = 0 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Stop the simulator after a VHDL/Verilog immediate assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; VHDL assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %i - Instance pathname with process +; %O - Process name +; %K - Kind of object path is to return: Instance, Signal, Process or Unknown +; %P - Instance or Region path without leaf process +; %F - File +; %L - Line number of assertion or, if assertion is in a subprogram, line +; from which the call is made +; %% - Print '%' character +; If specific format for assertion level is defined, use its format. +; If specific format is not defined for assertion level: +; - and if failure occurs during elaboration, use MessageFormatBreakLine; +; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion +; level), use MessageFormatBreak; +; - otherwise, use MessageFormat. +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops do to a breakpoint or fatal error. +; Example w/function name: # Break in Process ctr at counter.vhd line 44 +; Example wo/function name: # Break at counter.vhd line 44 +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable System Verilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be indexed during +; simulation. If set to 0, the WLF file will not be indexed. +; The default is 1, indexed the WLF file. +; WLFIndex = 0 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 256M per open WLF file. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: these ini variables can be overriden by the vsim command +; line switch "-onfinish ". +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result at the end of simulation before shutdown. +; If this is enabled, the simstats result will be printed out before shutdown. +; The default is off. +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA concurrent assertion pass enable. +; For SVA, Default is on when the assertion has a pass action block, or +; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active. +; For PSL, Default is on only when vsim switch "-assertdebug" is used +; and the vopt "+acc=a" flag is active. +; AssertionPassEnable = 0 + +; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on. +; AssertionFailEnable = 0 + +; Set PSL/SVA concurrent assertion pass limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionPassLimit = 1 + +; Set PSL/SVA concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionFailLimit = 1 + +; Turn on/off PSL concurrent assertion pass log. Default is off. +; The flag does not affect SVA +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that +; are included for toggle coverage. This leads to a longer simulation time with bigger +; arrays covered with toggle coverage. Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable is 1 +; SVCovergroup63Compatibility = 1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0in runtime tool. +; Default value set to "". +; ZeroInOptions = "" + +; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog). +; Sv_Seed = 0 + +; Maximum size of dynamic arrays that are resized during randomize(). +; The default is 1000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 1000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; The default is 0 (no error). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures (SystemVerilog). +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; When SolveFailDebug is enabled, this value specifies the algorithm used to +; discover conflicts between constraints for randomize() failures. +; The default is "many". +; +; Valid schemes are: +; "many" = best for determining conflicts due to many related constraints +; "few" = best for determining conflicts due to few related constraints +; +; SolveFailDebugScheme = many + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum number of constraint subsets that will be tested for +; conflicts. +; The default is 0 (no limit). +; SolveFailDebugLimit = 0 + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum size of constraint subsets that will be tested for +; conflicts. +; The default value is 0 (no limit). +; SolveFailDebugMaxSet = 0 + +; Maximum size of the solution graph that may be generated during randomize(). +; This value can be used to force randomize() to abort if the memory +; requirements of the constraint scenario exceeds the specified limit. This +; value is specified in 1000s of nodes. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Maximum number of evaluations that may be performed on the solution graph +; generated during randomize(). This value can be used to force randomize() to +; abort if the complexity of the constraint scenario (in time) exceeds the +; specified limit. This value is specified in 10000s of evaluations. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of +; the constraint solver for others. +; The default value is "" (no options). +; +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints +; n = disable bit interleaving for all constraints +; r = reverse bit interleaving +; +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; Note: To achieve the same random sequences, solver optimizations and/or +; bug fixes introduced since the specified release may be disabled - +; yielding the performance / behavior of the prior release. +; Default value set to "" (random compatibility not required). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +; MvcHome = $MODEL_TECH/... + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; suppress = 3009,CNNODP,3043,TFMPC +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear in the transcript and recorded in the wlf +; file (messages that are recorded in the wlf file can be viewed +; in the MsgViewer). The other settings are to send messages +; only to the transcript or only to the wlf file. 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z(&@wIffmn>lU#O_zzKOgJbab4BH zjTbscmENy#ygcr_^Nx_o6H`Ka{>RxR?orvq+|roiyMpH5{;XZy?UBu8d-C#g{yyP= zL&)PPVNy5l?OJcU(2>+sX zi-rl*J>rj_jMI*|39T` digit_right <= DIGIT_ZERO; -- ...to translation table + when "0001" => digit_right <= DIGIT_ONE; + when "0010" => digit_right <= DIGIT_TWO; + when "0011" => digit_right <= DIGIT_THREE; + when "0100" => digit_right <= DIGIT_FOUR; + when "0101" => digit_right <= DIGIT_FIVE; + when "0110" => digit_right <= DIGIT_SIX; + when "0111" => digit_right <= DIGIT_SEVEN; + when "1000" => digit_right <= DIGIT_EIGHT; + when "1001" => digit_right <= DIGIT_NINE; + when others => digit_right <= DIGIT_F; -- use "F" as overflow + end case; + + case ten_value is -- same for "ten" position + when "0000" => digit_left <= DIGIT_ZERO; + when "0001" => digit_left <= DIGIT_ONE; + when "0010" => digit_left <= DIGIT_TWO; + when "0011" => digit_left <= DIGIT_THREE; + when "0100" => digit_left <= DIGIT_FOUR; + when "0101" => digit_left <= DIGIT_FIVE; + when "0110" => digit_left <= DIGIT_SIX; + when "0111" => digit_left <= DIGIT_SEVEN; + when "1000" => digit_left <= DIGIT_EIGHT; + when "1001" => digit_left <= DIGIT_NINE; + when others => digit_left <= DIGIT_F; + end case; + end if; + end process; + + +-- combine the two digits to one bus + seven_seg(SEG_WIDTH-1 downto 0) <= digit_right; + seven_seg(2*SEG_WIDTH-1 downto SEG_WIDTH) <= digit_left; + +end behav; diff --git a/bsp2/Designflow/src/board_driver_ent.vhd b/bsp2/Designflow/src/board_driver_ent.vhd new file mode 100644 index 0000000..17e5cf7 --- /dev/null +++ b/bsp2/Designflow/src/board_driver_ent.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- Title : board_driver entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : board_driver_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: display number on 7-segment display +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + +entity board_driver is + + port ( + reset : in std_logic; + seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0) + ); +end board_driver; diff --git a/bsp2/Designflow/src/modelsim.ini b/bsp2/Designflow/src/modelsim.ini new file mode 100644 index 0000000..0a48df5 --- /dev/null +++ b/bsp2/Designflow/src/modelsim.ini @@ -0,0 +1,1305 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0-in compiler on the VHDL source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverageSub = 0 + +; Automatically exclude VHDL case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn off detection of FSMs having single bit current state variable. +; FsmSingle = 0 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/report/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect ; +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal +; to or greater than 1M are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Run the 0-in compiler on the Verilog source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a Verilog condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + + +; Turn on code coverage in VLOG `celldefine modules and modules included +; using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 1 to 4, with the following +; meanings (the default is 3): +; 1 -- Turn off all optimizations that affect coverage reports. +; 2 -- Allow optimizations that allow large performance improvements +; by invoking sequential processes only when the data changes. +; This may make major reductions in coverage counts. +; 3 -- In addition, allow optimizations that may change expressions or +; remove some statements. Allow constant propagation. Allow VHDL +; subprogram inlining and VHDL FF recognition. +; 4 -- In addition, allow optimizations that may remove major regions of +; code by changing assignments to built-ins or removing unused +; signals. Change Verilog gates to continuous assignments. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "merge_instances" option for +; the Covergroup Type. This is a compile time option which forces +; "merge_instances" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupMergeInstancesDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiOvm mtiUPF + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn off detection of FSMs having single bit current state variable. +; FsmSingle = 0 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SVFileExtensions = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2001 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "package_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a vopt condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; vopt automatic SDF +; If automatic design optimization is on, enables automatic compilation +; of SDF files. +; Default is on, uncomment to turn off. +; VoptAutoSDFCompile = 0 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Stop the simulator after a VHDL/Verilog immediate assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; VHDL assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %i - Instance pathname with process +; %O - Process name +; %K - Kind of object path is to return: Instance, Signal, Process or Unknown +; %P - Instance or Region path without leaf process +; %F - File +; %L - Line number of assertion or, if assertion is in a subprogram, line +; from which the call is made +; %% - Print '%' character +; If specific format for assertion level is defined, use its format. +; If specific format is not defined for assertion level: +; - and if failure occurs during elaboration, use MessageFormatBreakLine; +; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion +; level), use MessageFormatBreak; +; - otherwise, use MessageFormat. +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops do to a breakpoint or fatal error. +; Example w/function name: # Break in Process ctr at counter.vhd line 44 +; Example wo/function name: # Break at counter.vhd line 44 +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable System Verilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be indexed during +; simulation. If set to 0, the WLF file will not be indexed. +; The default is 1, indexed the WLF file. +; WLFIndex = 0 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 256M per open WLF file. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: these ini variables can be overriden by the vsim command +; line switch "-onfinish ". +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result at the end of simulation before shutdown. +; If this is enabled, the simstats result will be printed out before shutdown. +; The default is off. +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA concurrent assertion pass enable. +; For SVA, Default is on when the assertion has a pass action block, or +; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active. +; For PSL, Default is on only when vsim switch "-assertdebug" is used +; and the vopt "+acc=a" flag is active. +; AssertionPassEnable = 0 + +; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on. +; AssertionFailEnable = 0 + +; Set PSL/SVA concurrent assertion pass limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionPassLimit = 1 + +; Set PSL/SVA concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionFailLimit = 1 + +; Turn on/off PSL concurrent assertion pass log. Default is off. +; The flag does not affect SVA +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that +; are included for toggle coverage. This leads to a longer simulation time with bigger +; arrays covered with toggle coverage. Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable is 1 +; SVCovergroup63Compatibility = 1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0in runtime tool. +; Default value set to "". +; ZeroInOptions = "" + +; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog). +; Sv_Seed = 0 + +; Maximum size of dynamic arrays that are resized during randomize(). +; The default is 1000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 1000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; The default is 0 (no error). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures (SystemVerilog). +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; When SolveFailDebug is enabled, this value specifies the algorithm used to +; discover conflicts between constraints for randomize() failures. +; The default is "many". +; +; Valid schemes are: +; "many" = best for determining conflicts due to many related constraints +; "few" = best for determining conflicts due to few related constraints +; +; SolveFailDebugScheme = many + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum number of constraint subsets that will be tested for +; conflicts. +; The default is 0 (no limit). +; SolveFailDebugLimit = 0 + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum size of constraint subsets that will be tested for +; conflicts. +; The default value is 0 (no limit). +; SolveFailDebugMaxSet = 0 + +; Maximum size of the solution graph that may be generated during randomize(). +; This value can be used to force randomize() to abort if the memory +; requirements of the constraint scenario exceeds the specified limit. This +; value is specified in 1000s of nodes. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Maximum number of evaluations that may be performed on the solution graph +; generated during randomize(). This value can be used to force randomize() to +; abort if the complexity of the constraint scenario (in time) exceeds the +; specified limit. This value is specified in 10000s of evaluations. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of +; the constraint solver for others. +; The default value is "" (no options). +; +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints +; n = disable bit interleaving for all constraints +; r = reverse bit interleaving +; +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; Note: To achieve the same random sequences, solver optimizations and/or +; bug fixes introduced since the specified release may be disabled - +; yielding the performance / behavior of the prior release. +; Default value set to "" (random compatibility not required). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +; MvcHome = $MODEL_TECH/... + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; suppress = 3009,CNNODP,3043,TFMPC +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear in the transcript and recorded in the wlf +; file (messages that are recorded in the wlf file can be viewed +; in the MsgViewer). The other settings are to send messages +; only to the transcript or only to the wlf file. The valid +; values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/bsp2/Designflow/src/vga.hex b/bsp2/Designflow/src/vga.hex new file mode 100644 index 0000000..b3c05bd --- /dev/null +++ b/bsp2/Designflow/src/vga.hex @@ -0,0 +1,4097 @@ +:010000001ce3 +:010001001ce2 +:010002001ce1 +:010003001ce0 +:010004001cdf +:010005001cde +:010006001cdd +:010007001cdc +:010008001cdb +:010009001cda +:01000a001cd9 +:01000b001cd8 +:01000c001cd7 +:01000d001cd6 +:01000e001cd5 +:01000f001cd4 +:010010001cd3 +:010011001cd2 +:010012001cd1 +:010013001cd0 +:010014001ccf +:010015001cce +:010016001ccd +:010017001ccc +:010018001ccb +:010019001cca +:01001a001cc9 +:01001b001cc8 +:01001c001cc7 +:01001d001cc6 +:01001e001cc5 +:01001f001cc4 +:010020001cc3 +:010021001cc2 +:010022001cc1 +:010023001cc0 +:010024001cbf +:010025001cbe +:010026001cbd +:010027001cbc +:010028001cbb +:010029001cba +:01002a001cb9 +:01002b001cb8 +:01002c001cb7 +:01002d001cb6 +:01002e001cb5 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+:010fe900e027 +:010fea00e026 +:010feb00e025 +:010fec00e024 +:010fed00e023 +:010fee00e022 +:010fef00e021 +:010ff000e020 +:010ff100e01f +:010ff200e01e +:010ff300e01d +:010ff400e01c +:010ff500e01b +:010ff600e01a +:010ff700e019 +:010ff800e018 +:010ff900e017 +:010ffa00e016 +:010ffb00e015 +:010ffc00e014 +:010ffd00e013 +:010ffe00e012 +:010fff00e011 +:00000001ff diff --git a/bsp2/Designflow/src/vga_arc.vhd b/bsp2/Designflow/src/vga_arc.vhd new file mode 100644 index 0000000..3d2d158 --- /dev/null +++ b/bsp2/Designflow/src/vga_arc.vhd @@ -0,0 +1,223 @@ + ------------------------------------------------------------------------------- +-- Title : vga architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: arch of top level module, the sub-modules are connected here +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; -- include package + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + +------------------------------------------------------------------------------- +-- component declarations for the modules +------------------------------------------------------------------------------- + + component vga_driver + port ( + clk : in std_logic; + reset : in std_logic; + column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : out std_logic; + v_enable : out std_logic; + hsync : out std_logic; + vsync : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter : out std_logic; + d_set_vsync_counter : out std_logic; + d_set_column_counter : out std_logic; + d_set_line_counter : out std_logic); + end component; + + + component vga_control + port ( + clk : in std_logic; + reset : in std_logic; + column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : in std_logic; + v_enable : in std_logic; + toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + toggle : out std_logic; + r, g, b : out std_logic + ); + end component; + + + component board_driver + port ( + reset : in std_logic; + seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0)); + end component; + + +-- declare signals needed for internal wiring of these components later + signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal h_enable_sig : std_logic; + signal v_enable_sig : std_logic; + signal r_sig, g_sig, b_sig : std_logic; + signal hsync_sig, vsync_sig : std_logic; + +-- declare signals needed for prolongation of reset + signal dly_counter : std_logic_vector(1 downto 0); + signal dly_counter_next : std_logic_vector(1 downto 0); + constant MAX_DLY : std_logic_vector(1 downto 0) := "11"; + signal reset_dly : std_logic; -- + signal safe_reset : std_logic; + + +------------------------------------------------------------------------------- +-- prolong duration of reset to prevent glitches at power-up +------------------------------------------------------------------------------- + +begin + + DELAY_RESET_syn : process(clk_pin) -- synchronous capture + begin + if clk_pin'event and clk_pin = '1' then -- upon rising clock + dly_counter <= dly_counter_next; -- ... capture new counter value + end if; + end process; + + DELAY_RESET_next : process(dly_counter, reset_pin) -- next state logic + begin + if reset_pin = RES_ACT then -- upon reset + dly_counter_next <= (others => '0'); -- ...clear dly counter + elsif dly_counter < MAX_DLY then -- if no oflo + dly_counter_next <= dly_counter + '1'; -- ...increment dly counter + else + dly_counter_next <= dly_counter; -- freeze dly counter when oflo + end if; + end process; + + DELAY_RESET_out: process(dly_counter) + begin + if dly_counter < MAX_DLY then -- until dly counter reaches maximum + reset_dly <= RES_ACT; -- ...activate delayed reset signal + else -- upon counter oflo + reset_dly <= not(RES_ACT); -- ...finally deactivate delayed reset + end if; + end process; + + + + COMBINE_RESET: process(reset_pin, reset_dly) -- generate "safe" reset signal + begin + if reset_pin = RES_ACT or reset_dly = RES_ACT then -- ...by combining delayed reset with non-delayed reset input + safe_reset <= RES_ACT; + else + safe_reset <= not(RES_ACT); + end if; + end process; + + +------------------------------------------------------------------------------- +-- instantiate the components and connect to internal and external signals +------------------------------------------------------------------------------- + + +board_driver_unit : board_driver + port map ( + reset => safe_reset, + seven_seg => seven_seg_pin); + + +vga_driver_unit : vga_driver + port map ( + clk => clk_pin, + reset => safe_reset, + column_counter => column_counter_sig, + line_counter => line_counter_sig, + h_enable => h_enable_sig, + v_enable => v_enable_sig, + hsync => hsync_sig, + vsync => vsync_sig, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter); + +-- make the wiring for hsync and vsync pins +-- (pin is output only => internal _sig version required to allow readback of signal) + vsync_pin <= vsync_sig; + hsync_pin <= hsync_sig; + + + vga_control_unit : vga_control + port map ( + clk => clk_pin, + reset => safe_reset, + column_counter => column_counter_sig, + line_counter => line_counter_sig, + h_enable => h_enable_sig, + v_enable => v_enable_sig, + toggle_counter => d_toggle_counter, + toggle => d_toggle, + r => r_sig, + g => g_sig, + b => b_sig); + +-- make the wiring for RGB pins: drive all pins for same color from one source ("8 color mode") + r0_pin <= r_sig; r1_pin <= r_sig; r2_pin <= r_sig; + g0_pin <= g_sig; g1_pin <= g_sig; g2_pin <= g_sig; + b0_pin <= b_sig; b1_pin <= b_sig; + + +-- make extra pin connections for debug signals + d_hsync <= hsync_sig; -- make duplicate of signal for debug connector + d_vsync <= vsync_sig; -- make duplicate of signal for debug connector + d_column_counter <= column_counter_sig; + d_line_counter <= line_counter_sig; + d_h_enable <= h_enable_sig; + d_v_enable <= v_enable_sig; + d_r <= r_sig; + d_g <= g_sig; + d_b <= b_sig; + d_state_clk <= clk_pin; -- make duplicate of signal for debug connector + + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp2/Designflow/src/vga_beh_tb.vhd b/bsp2/Designflow/src/vga_beh_tb.vhd new file mode 100644 index 0000000..9530bed --- /dev/null +++ b/bsp2/Designflow/src/vga_beh_tb.vhd @@ -0,0 +1,194 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_tb is + +end vga_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture behaviour of vga_tb is + + constant cc : time := 39.7 ns; -- test clock period + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : hsync_state_type; + signal d_vsync_state : vsync_state_type; + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk_pin <= '1'; + wait for cc/2; + clk_pin <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk_pin = '1' and clk_pin'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + +end behaviour; + + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_beh of vga_tb is + for behaviour + for vga_unit : vga use entity work.vga(behav); + end for; + end for; +end vga_conf_beh; + + diff --git a/bsp2/Designflow/src/vga_control_arc.vhd b/bsp2/Designflow/src/vga_control_arc.vhd new file mode 100644 index 0000000..6329c7e --- /dev/null +++ b/bsp2/Designflow/src/vga_control_arc.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------- +-- Title : vga_control architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga_control is + + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + + -- signal and constant declarations + signal r_next, g_next, b_next : std_logic; -- auxiliary signals for next state logic + signal toggle_sig : std_logic; -- auxiliary signal to allow read back of toggle + signal toggle_counter_sig : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal to allow read back of blinker + signal toggle_next : std_logic; -- auxiliary signal for next state logic + signal toggle_counter_next : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal for next state logic +-- constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "1100000000010001111011000"; + constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "0000101101110001101100000"; + -- define half period of toggle frequency in clock ticks + +begin + ----------------------------------------------------------------------------- + -- draw rectangle on screen + ----------------------------------------------------------------------------- + + DRAW_SQUARE_syn: process(clk, reset) + begin + if (reset = RES_ACT) then -- draw black screen upon reset + r <= COLR_OFF; + g <= COLR_OFF; + b <= COLR_OFF; + elsif (clk'event and clk = '1') then -- synchronous capture + r <= r_next; + g <= g_next; + b <= b_next; + end if; + end process; + + + DRAW_SQUARE_next: process (column_counter, line_counter, v_enable, h_enable, toggle_sig) + begin + if v_enable = ENABLE and h_enable = ENABLE then + if (column_counter >= X_MIN and column_counter <= X_MAX and -- if pixel within the rectangle borders + line_counter >= Y_MIN and line_counter <= Y_MAX) then + r_next <= toggle_sig; -- ...red + g_next <= COLR_OFF; -- ...green + b_next <= not toggle_sig; -- ...blue + else -- if somewhere else on screen... + r_next <= COLR_OFF; + g_next <= COLR_OFF; -- ... draw background color + b_next <= COLR_OFF; + end if; + else -- if out of screen... + r_next <= COLR_OFF; + g_next <= COLR_OFF; -- ... do not activate any color + b_next <= COLR_OFF; -- (black screen) + end if; + end process; + + + ----------------------------------------------------------------------------- + -- control blinking of rectangle + ----------------------------------------------------------------------------- + + BLINKER_syn: process(clk, reset) + begin + if (reset = RES_ACT) then -- asyn reset + toggle_counter_sig <= (others => '0'); + toggle_sig <= COLR_OFF; + elsif(clk'event and clk = '1') then -- synchronous capture + toggle_counter_sig <= toggle_counter_next; + toggle_sig <= toggle_next; + end if; + end process; + + + BLINKER_next : process(toggle_counter_sig, toggle_sig) + begin + if toggle_counter_sig >= HALFPERIOD then -- after half period ... + toggle_counter_next <= (others => '0'); -- ... clear counter + toggle_next <= not(toggle_sig); -- ... and toggle colour. + else -- before half period ... + toggle_counter_next <= toggle_counter_sig + '1'; -- ... increment counter + toggle_next <= toggle_sig; -- ... and hold colour + end if; + end process; + + +-- assign auxiliary signals to module outputs +toggle <= toggle_sig; +toggle_counter <= toggle_counter_sig; + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp2/Designflow/src/vga_control_arc.vhd~ b/bsp2/Designflow/src/vga_control_arc.vhd~ new file mode 100644 index 0000000..69a192e --- /dev/null +++ b/bsp2/Designflow/src/vga_control_arc.vhd~ @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------- +-- Title : vga_control architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga_control is + + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + + -- signal and constant declarations + signal r_next, g_next, b_next : std_logic; -- auxiliary signals for next state logic + signal toggle_sig : std_logic; -- auxiliary signal to allow read back of toggle + signal toggle_counter_sig : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal to allow read back of blinker + signal toggle_next : std_logic; -- auxiliary signal for next state logic + signal toggle_counter_next : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal for next state logic +-- constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "1100000000010001111011000"; + constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "101101110001101100000"; + -- define half period of toggle frequency in clock ticks + +begin + ----------------------------------------------------------------------------- + -- draw rectangle on screen + ----------------------------------------------------------------------------- + + DRAW_SQUARE_syn: process(clk, reset) + begin + if (reset = RES_ACT) then -- draw black screen upon reset + r <= COLR_OFF; + g <= COLR_OFF; + b <= COLR_OFF; + elsif (clk'event and clk = '1') then -- synchronous capture + r <= r_next; + g <= g_next; + b <= b_next; + end if; + end process; + + + DRAW_SQUARE_next: process (column_counter, line_counter, v_enable, h_enable, toggle_sig) + begin + if v_enable = ENABLE and h_enable = ENABLE then + if (column_counter >= X_MIN and column_counter <= X_MAX and -- if pixel within the rectangle borders + line_counter >= Y_MIN and line_counter <= Y_MAX) then + r_next <= toggle_sig; -- ...red + g_next <= COLR_OFF; -- ...green + b_next <= not toggle_sig; -- ...blue + else -- if somewhere else on screen... + r_next <= COLR_OFF; + g_next <= COLR_OFF; -- ... draw background color + b_next <= COLR_OFF; + end if; + else -- if out of screen... + r_next <= COLR_OFF; + g_next <= COLR_OFF; -- ... do not activate any color + b_next <= COLR_OFF; -- (black screen) + end if; + end process; + + + ----------------------------------------------------------------------------- + -- control blinking of rectangle + ----------------------------------------------------------------------------- + + BLINKER_syn: process(clk, reset) + begin + if (reset = RES_ACT) then -- asyn reset + toggle_counter_sig <= (others => '0'); + toggle_sig <= COLR_OFF; + elsif(clk'event and clk = '1') then -- synchronous capture + toggle_counter_sig <= toggle_counter_next; + toggle_sig <= toggle_next; + end if; + end process; + + + BLINKER_next : process(toggle_counter_sig, toggle_sig) + begin + if toggle_counter_sig >= HALFPERIOD then -- after half period ... + toggle_counter_next <= (others => '0'); -- ... clear counter + toggle_next <= not(toggle_sig); -- ... and toggle colour. + else -- before half period ... + toggle_counter_next <= toggle_counter_sig + '1'; -- ... increment counter + toggle_next <= toggle_sig; -- ... and hold colour + end if; + end process; + + +-- assign auxiliary signals to module outputs +toggle <= toggle_sig; +toggle_counter <= toggle_counter_sig; + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp2/Designflow/src/vga_control_ent.vhd b/bsp2/Designflow/src/vga_control_ent.vhd new file mode 100644 index 0000000..2ff5a0a --- /dev/null +++ b/bsp2/Designflow/src/vga_control_ent.vhd @@ -0,0 +1,53 @@ +------------------------------------------------------------------------------- +-- Title : vga_control entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + + +entity vga_control is + port(clk : in std_logic; + reset : in std_logic; + column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); + toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + toggle : out std_logic; + line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + v_enable : in std_logic; + h_enable : in std_logic; + r, g, b : out std_logic + ); + +end vga_control; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp2/Designflow/src/vga_driver_arc.vhd b/bsp2/Designflow/src/vga_driver_arc.vhd new file mode 100644 index 0000000..1b89ac1 --- /dev/null +++ b/bsp2/Designflow/src/vga_driver_arc.vhd @@ -0,0 +1,402 @@ +------------------------------------------------------------------------------- +-- Title : vga_driver architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_driver.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-01-24 +------------------------------------------------------------------------------- +-- Description: generate hsync and vsync +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-01-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga_driver is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + constant TIME_A : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100011111"; + constant TIME_B : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0001011010"; + constant TIME_BC : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0010000111"; + constant TIME_BCD : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100000111"; + + constant TIME_O : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000001000"; + constant TIME_P : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000000001"; + constant TIME_PQ : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000100001"; + constant TIME_PQR : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000000001"; + + signal h_sync : std_logic; + signal h_sync_next : std_logic; + + signal hsync_state : hsync_state_type; + signal hsync_state_next : hsync_state_type; + + signal h_enable_sig : std_logic; + signal h_enable_next : std_logic; + + signal set_hsync_counter : std_logic; + signal hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal hsync_counter_next : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + constant HSYN_CNT_MAX : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1111111111"; + + signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal column_counter_next : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal set_column_counter : std_logic; + + signal v_sync : std_logic; + signal v_sync_next : std_logic; + + signal vsync_state : vsync_state_type; + signal vsync_state_next : vsync_state_type; + + signal v_enable_sig : std_logic; + signal v_enable_next : std_logic; + + signal set_vsync_counter : std_logic; + signal vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal vsync_counter_next : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + constant VSYN_CNT_MAX : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1111111111"; + + signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal line_counter_next : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal set_line_counter : std_logic; + + + +begin + +---------------------------------------------------------------------------- +-- Column_Counter [0..639]: calculates column number for next pixel to be displayed +---------------------------------------------------------------------------- + + COLUMN_COUNT_syn: process(clk, reset, column_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + column_counter_sig <= (others => '0'); + else + column_counter_sig <= column_counter_next; -- synchronous capture + end if; + end if; + end process; + + COLUMN_COUNT_next: process(set_column_counter, column_counter_sig) + begin + if set_column_counter = ENABLE then -- reset counter + column_counter_next <= (others => '0'); + else + if column_counter_sig < RIGHT_BORDER then + column_counter_next <= column_counter_sig + '1'; -- increment column + else + column_counter_next <= RIGHT_BORDER; -- ... but do not count beyond right border + end if; + end if; + end process; + +---------------------------------------------------------------------------- +-- Line_counter [0..479]: calculates line number for next pixel to be displayed +---------------------------------------------------------------------------- + + LINE_COUNT_syn: process(clk, reset, line_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + line_counter_sig <= (others => '0'); + else + line_counter_sig <= line_counter_next; -- synchronous capture + end if; + end if; + end process; + + LINE_COUNT_next: process(set_line_counter, line_counter_sig, set_hsync_counter) + begin + if set_line_counter = ENABLE then -- reset counter + line_counter_next <= (others => '0'); + else + if line_counter_sig < BOTTOM_BORDER then + if set_hsync_counter = '1' then -- when enabled + line_counter_next <= line_counter_sig + '1'; -- ... increment line + else + line_counter_next <= line_counter_sig; + end if; + else + line_counter_next <= BOTTOM_BORDER; -- ... but do not count below bottom + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- Hsync_Counter: generates time base for HSYNC State Machine +---------------------------------------------------------------------------- + + HSYNC_COUNT_syn: process(clk, reset, hsync_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + hsync_counter <= (others => '0'); + else + hsync_counter <= hsync_counter_next; -- synchronous capture + end if; + end if; + end process; + + HSYNC_COUNT_next: process(set_hsync_counter, hsync_counter) + begin + if set_hsync_counter = ENABLE then -- reset counter + hsync_counter_next <= (others => '0'); + else + if hsync_counter < HSYN_CNT_MAX then + hsync_counter_next <= hsync_counter + '1'; -- increment time + else + hsync_counter_next <= HSYN_CNT_MAX; -- ... but do not count beyond max period + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- HSYNC STATE MACHINE: generates hsync signal and controls hsync counter & column counter +---------------------------------------------------------------------------- + + HSYNC_FSM_syn: process (clk, reset) -- synchronous capture + begin + if clk'event and clk = '1' then + if reset = RES_ACT then + hsync_state <= RESET_STATE; + h_sync <= '1'; + v_enable_sig <= not(ENABLE); + else + hsync_state <= hsync_state_next; + h_sync <= h_sync_next; + v_enable_sig <= v_enable_next; + end if; + end if; + end process; + + HSYNC_FSM_next : process(hsync_state, hsync_counter, h_sync, v_enable_sig) -- next-state logic + begin -- default assignments + hsync_state_next <= hsync_state; -- ... hold current state + h_sync_next <= h_sync; -- ... and values + v_enable_next <= v_enable_sig; + + case hsync_state is + when RESET_STATE => + h_sync_next <= '0'; -- next signal values are defined here + v_enable_next <= not(ENABLE); + hsync_state_next <= B_STATE; -- ... as well as state transitions + when B_STATE => + h_sync_next <= '0'; + if hsync_counter = TIME_B then + hsync_state_next <= C_STATE; + end if; + when C_STATE => + h_sync_next <= '1'; + if hsync_counter = TIME_BC then + hsync_state_next <= pre_D_STATE; + end if; + when pre_D_STATE => + v_enable_next <= ENABLE; + hsync_state_next <= D_STATE; + when D_STATE => + v_enable_next <= ENABLE; + if hsync_counter = TIME_BCD then + hsync_state_next <= E_STATE; + end if; + when E_STATE => + v_enable_next <= not(ENABLE); + if hsync_counter = TIME_A then + hsync_state_next <= pre_B_STATE; + end if; + when pre_B_STATE => + h_sync_next <= '0'; + v_enable_next <= not(ENABLE); + hsync_state_next <= B_STATE; + when others => + null; + end case; + end process; + + HSYNC_FSM_out : process(hsync_state) -- output logic + begin + set_hsync_counter <= not(ENABLE); -- default assignments + set_column_counter <= not(ENABLE); + + case hsync_state is + when RESET_STATE => -- outputs for each state are defined here + set_hsync_counter <= ENABLE; + when pre_D_STATE => + set_column_counter <= ENABLE; + when pre_B_STATE => + set_hsync_counter <= ENABLE; + when others => + null; + end case; + end process; + + +---------------------------------------------------------------------------- +-- Vsync_Counter: generates time base for VSYNC State Machine +---------------------------------------------------------------------------- + + VSYNC_COUNT_syn: process(clk, reset, vsync_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + vsync_counter <= (others => '0'); + else + vsync_counter <= vsync_counter_next; -- synchronous capture + end if; + end if; + end process; + + VSYNC_COUNT_next: process(set_vsync_counter, vsync_counter, set_hsync_counter) + begin + if set_vsync_counter = ENABLE then -- reset counter + vsync_counter_next <= (others => '0'); + else + if vsync_counter < VSYN_CNT_MAX then + if set_hsync_counter = '1' then -- if enabled + vsync_counter_next <= vsync_counter + '1'; -- ... increment time + else + vsync_counter_next <= vsync_counter; + end if; + else + vsync_counter_next <= VSYN_CNT_MAX; -- ... but do not count beyond max period + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- VSYNC STATE MACHINE: generates vsync signal and controls vsync counter & line counter +---------------------------------------------------------------------------- + + VSYNC_FSM_syn : process (clk, reset) -- synchronous capture + begin + if clk'event and clk = '1' then + if reset = RES_ACT then + vsync_state <= RESET_STATE; + v_sync <= '1'; + h_enable_sig <= not(ENABLE); + else + vsync_state <= vsync_state_next; + v_sync <= v_sync_next; + h_enable_sig <= h_enable_next; + end if; + end if; + end process; + + VSYNC_FSM_next : process(vsync_state, vsync_counter, v_sync, h_enable_sig) + begin -- next state logic + vsync_state_next <= vsync_state; -- default assignments + v_sync_next <= v_sync; + h_enable_next <= h_enable_sig; + + case vsync_state is -- state transitions and next signals are defined here + when RESET_STATE => + v_sync_next <= '0'; + h_enable_next <= not(ENABLE); + vsync_state_next <= P_STATE; + when P_STATE => + v_sync_next <= '0'; + if vsync_counter = time_p then + vsync_state_next <= Q_STATE; + end if; + when Q_STATE => + v_sync_next <= '1'; + if vsync_counter = time_pq then + vsync_state_next <= pre_R_STATE; + end if; + when pre_R_STATE => + h_enable_next <= ENABLE; + vsync_state_next <= R_STATE; + when R_STATE => + h_enable_next <= ENABLE; + if vsync_counter = time_pqr then + vsync_state_next <= S_STATE; + end if; + when S_STATE => + h_enable_next <= not(ENABLE); + if vsync_counter = time_o then + vsync_state_next <= pre_P_STATE; + end if; + when pre_P_STATE => + v_sync_next <= '0'; + h_enable_next <= not(ENABLE); + vsync_state_next <= P_STATE; + when others => + null; + end case; + end process; + + VSYNC_FSM_out : process(vsync_state) + begin -- output logic + set_vsync_counter <= not(ENABLE); -- output values for each state defined here + set_line_counter <= not(ENABLE); + + case vsync_state is + when RESET_STATE => + set_vsync_counter <= ENABLE; + when pre_R_STATE => + set_line_counter <= ENABLE; + when pre_P_STATE => + set_vsync_counter <= ENABLE; + when others => + null; + end case; + end process; + + + +-- signal wiring for entity (introduced _sig to allow readback of output signals) + + column_counter <= column_counter_sig; + v_enable <= v_enable_sig; + line_counter <= line_counter_sig; + h_enable <= h_enable_sig; + + + hsync <= h_sync; + vsync <= v_sync; + + ----------------------------------------------------------------------------- + -- debug signals + ----------------------------------------------------------------------------- + d_hsync_state <= hsync_state; + d_vsync_state <= vsync_state; + d_hsync_counter <= hsync_counter; + d_vsync_counter <= vsync_counter; + d_set_hsync_counter <= set_hsync_counter; + d_set_vsync_counter <= set_vsync_counter; + d_set_column_counter <= set_column_counter; + d_set_line_counter <= set_line_counter; + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp2/Designflow/src/vga_driver_ent.vhd b/bsp2/Designflow/src/vga_driver_ent.vhd new file mode 100644 index 0000000..f4c00be --- /dev/null +++ b/bsp2/Designflow/src/vga_driver_ent.vhd @@ -0,0 +1,60 @@ +------------------------------------------------------------------------------- +-- Title : vga_driver entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_driver_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generate vsync and hsync +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + + +entity vga_driver is + port(clk : in std_logic; + reset : in std_logic; + column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : out std_logic; + v_enable : out std_logic; + hsync, vsync : out std_logic; + + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter : out std_logic; + d_set_vsync_counter : out std_logic; + d_set_column_counter : out std_logic; + d_set_line_counter : out std_logic + ); + +end vga_driver; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp2/Designflow/src/vga_ent.vhd b/bsp2/Designflow/src/vga_ent.vhd new file mode 100644 index 0000000..a32ebc0 --- /dev/null +++ b/bsp2/Designflow/src/vga_ent.vhd @@ -0,0 +1,73 @@ +------------------------------------------------------------------------------- +-- Title : vga entitiy +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: entity of top level module, external pins defined here +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + +entity vga is + port( +-- input pins from PCB board + clk_pin : in std_logic; -- clock pin + reset_pin : in std_logic; -- reset pins (from switch) +-- output pins to RGB connector / VGA screen + r0_pin, r1_pin, r2_pin : out std_logic; -- to RGB connector "red" + g0_pin, g1_pin, g2_pin : out std_logic; -- to RGB connector "green" + b0_pin, b1_pin : out std_logic; -- to RGB connector "blue" + hsync_pin : out std_logic; -- to RGB connector "Hsync" + vsync_pin : out std_logic; -- to RGB connector "Vsync" +-- output pins to 7-segment display + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); +-- output pins provided for debugging only / logic analyzer + d_hsync, d_vsync : out std_logic; -- copy of hsync_pin, vsync_pin + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0) + ); + +end vga; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp2/Designflow/src/vga_pak.vhd b/bsp2/Designflow/src/vga_pak.vhd new file mode 100644 index 0000000..61c8adf --- /dev/null +++ b/bsp2/Designflow/src/vga_pak.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------- +-- Title : vga package +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_pak.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-08-19 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: definitions of global constants and enumerated types +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-08-19 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + + +------------------------------------------------------------------------------- +-- PACKAGE +------------------------------------------------------------------------------- + +package vga_pak is + + constant RES_ACT : std_logic := '0'; -- define reset active LO + constant ENABLE : std_logic := '1'; -- define diverse enable HI + constant COLR_ON : std_logic := '1'; -- define VGA color on as HI + constant COLR_OFF : std_logic := '0'; -- define VGA color off as LO + constant SEG_WIDTH : integer := 7; -- display has 7 segments + constant BCD_WIDTH : integer := 4; -- BCD number has 4 bit + constant TOG_CNT_WIDTH : integer := 25; -- bitwidth of counter that controls blinking + + constant COL_CNT_WIDTH : integer := 10; -- width of the column counter + constant LINE_CNT_WIDTH : integer := 9; -- width of the line counter + constant HSYN_CNT_WIDTH : integer := 10; -- width of the h-sync counter + constant VSYN_CNT_WIDTH : integer := 10; -- width of the v-sync counter + + constant RIGHT_BORDER: std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "1001111111"; -- 640 columns (0...639) + constant BOTTOM_BORDER: std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "111011111"; -- 480 lines (0...479) + + -- define coordinates of rectangle + constant X_MIN : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0001100100"; -- 100 + constant X_MAX : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0011001000"; -- 200 + constant Y_MIN : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "001100100"; + constant Y_MAX : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "011001000"; + + -- define emumerated types for state machines + type hsync_state_type is (RESET_STATE, B_STATE, C_STATE, D_STATE, E_STATE, + pre_D_STATE, pre_B_STATE); + type vsync_state_type is (RESET_STATE, P_STATE, Q_STATE, R_STATE, S_STATE, + pre_R_STATE, pre_P_STATE); + + -- Definitions for 7-segment display gfedcba + constant DIGIT_ZERO : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000000"; + constant DIGIT_ONE : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111001"; + constant DIGIT_TWO : std_logic_vector(SEG_WIDTH-1 downto 0) := "0100100"; + constant DIGIT_THREE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110000"; + constant DIGIT_FOUR : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011001"; + constant DIGIT_FIVE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0010010"; + constant DIGIT_SIX : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000010"; + constant DIGIT_SEVEN : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111000"; + constant DIGIT_EIGHT : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000000"; + constant DIGIT_NINE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011000"; + constant DIGIT_MINUS : std_logic_vector(SEG_WIDTH-1 downto 0) := "0111111"; + constant DIGIT_A : std_logic_vector(SEG_WIDTH-1 downto 0) := "0001000"; + constant DIGIT_B : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000011"; + constant DIGIT_C : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110001"; + constant DIGIT_D : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000010"; + constant DIGIT_E : std_logic_vector(SEG_WIDTH-1 downto 0) := "1001111"; + constant DIGIT_F : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000111"; + constant DIGIT_OFF : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111111"; + +end package; diff --git a/bsp2/Designflow/src/vga_pll.bdf b/bsp2/Designflow/src/vga_pll.bdf new file mode 100755 index 0000000..906c435 --- /dev/null +++ b/bsp2/Designflow/src/vga_pll.bdf @@ -0,0 +1,847 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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) + (port + (pt 216 368) + (output) + (text "d_h_enable" (rect 0 0 55 12)(font "Arial" )) + (text "d_h_enable" (rect 140 363 195 375)(font "Arial" )) + (line (pt 216 368)(pt 200 368)(line_width 1)) + ) + (port + (pt 216 384) + (output) + (text "d_v_enable" (rect 0 0 56 12)(font "Arial" )) + (text "d_v_enable" (rect 139 379 195 391)(font "Arial" )) + (line (pt 216 384)(pt 200 384)(line_width 1)) + ) + (port + (pt 216 400) + (output) + (text "d_r" (rect 0 0 15 12)(font "Arial" )) + (text "d_r" (rect 180 395 195 407)(font "Arial" )) + (line (pt 216 400)(pt 200 400)(line_width 1)) + ) + (port + (pt 216 416) + (output) + (text "d_g" (rect 0 0 17 12)(font "Arial" )) + (text "d_g" (rect 178 411 195 423)(font "Arial" )) + (line (pt 216 416)(pt 200 416)(line_width 1)) + ) + (port + (pt 216 432) + (output) + (text "d_b" (rect 0 0 17 12)(font "Arial" )) + (text "d_b" (rect 178 427 195 439)(font "Arial" )) + (line (pt 216 432)(pt 200 432)(line_width 1)) + ) + (port + (pt 216 448) + (output) + (text "d_hsync_state[0..6]" (rect 0 0 99 12)(font "Arial" )) + (text "d_hsync_state[0..6]" (rect 96 443 195 455)(font "Arial" )) + (line (pt 216 448)(pt 200 448)(line_width 3)) + ) + (port + (pt 216 464) + (output) + (text "d_vsync_state[0..6]" (rect 0 0 100 12)(font "Arial" )) + (text "d_vsync_state[0..6]" (rect 95 459 195 471)(font "Arial" )) + (line (pt 216 464)(pt 200 464)(line_width 3)) + ) + (port + (pt 216 480) + (output) + (text "d_state_clk" (rect 0 0 56 12)(font "Arial" )) + (text "d_state_clk" (rect 139 475 195 487)(font "Arial" )) + (line (pt 216 480)(pt 200 480)(line_width 1)) + ) + (port + (pt 216 496) + (output) + (text "d_toggle" (rect 0 0 41 12)(font "Arial" )) + (text "d_toggle" (rect 154 491 195 503)(font "Arial" )) + (line (pt 216 496)(pt 200 496)(line_width 1)) + ) + (port + (pt 216 512) + (output) + (text "d_toggle_counter[24..0]" (rect 0 0 115 12)(font "Arial" )) + (text "d_toggle_counter[24..0]" (rect 80 507 195 519)(font "Arial" )) + (line (pt 216 512)(pt 200 512)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 200 528)(line_width 1)) + ) +) +(symbol + (rect 416 56 512 152) + (text "vpll" (rect 5 0 22 12)(font "Arial" )) + (text "inst1" (rect 8 80 31 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inclk0" (rect 0 0 28 12)(font "Arial" )) + (text "inclk0" (rect 21 27 49 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 96 32) + (output) + (text "c0" (rect 0 0 11 12)(font "Arial" )) + (text "c0" (rect 64 27 75 39)(font "Arial" )) + (line (pt 96 32)(pt 80 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 80 80)(line_width 1)) + ) +) +(connector + (pt 512 88) + (pt 712 88) +) diff --git a/bsp2/Designflow/src/vga_pll.tcl b/bsp2/Designflow/src/vga_pll.tcl new file mode 100755 index 0000000..c260434 --- /dev/null +++ b/bsp2/Designflow/src/vga_pll.tcl @@ -0,0 +1,184 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: vga_pll.tcl +# Generated on: Fri Sep 29 09:31:24 2006 + +# Load Quartus II Tcl Project package +package require ::quartus::project +package require ::quartus::flow + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "vga_pll"]} { + puts "Project vga_pll is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists vga_pll]} { + project_open -cmp vga_pll vga_pll + } else { + project_new -cmp vga_pll vga_pll + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + catch { set_global_assignment -name FAMILY Stratix } result + catch { set_global_assignment -name DEVICE EP1S25F672C6 } result + catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result + catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result + catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result + catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result + catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result + catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result + catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result + catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result + catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result + catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result + catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result + catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result + + set_location_assignment PIN_E24 -to b0_pin + set_location_assignment PIN_T6 -to b1_pin + set_location_assignment PIN_N3 -to board_clk + set_location_assignment PIN_E23 -to g0_pin + set_location_assignment PIN_T5 -to g1_pin + set_location_assignment PIN_T24 -to g2_pin + set_location_assignment PIN_F1 -to hsync_pin + set_location_assignment PIN_E22 -to r0_pin + set_location_assignment PIN_T4 -to r1_pin + set_location_assignment PIN_T7 -to r2_pin + set_location_assignment PIN_A5 -to reset + set_location_assignment PIN_F2 -to vsync_pin + set_location_assignment PIN_Y5 -to d_hsync_state[0] + set_location_assignment PIN_F19 -to d_hsync_state[1] + set_location_assignment PIN_F17 -to d_hsync_state[2] + set_location_assignment PIN_Y2 -to d_hsync_state[3] + set_location_assignment PIN_F10 -to d_hsync_state[4] + set_location_assignment PIN_F9 -to d_hsync_state[5] + set_location_assignment PIN_F6 -to d_hsync_state[6] + set_location_assignment PIN_H4 -to d_hsync_counter[0] + set_location_assignment PIN_G25 -to d_hsync_counter[7] + set_location_assignment PIN_G22 -to d_hsync_counter[8] + set_location_assignment PIN_G18 -to d_hsync_counter[9] + set_location_assignment PIN_F5 -to d_vsync_state[0] + set_location_assignment PIN_F4 -to d_vsync_state[1] + set_location_assignment PIN_F3 -to d_vsync_state[2] + set_location_assignment PIN_M19 -to d_vsync_state[3] + set_location_assignment PIN_M18 -to d_vsync_state[4] + set_location_assignment PIN_M7 -to d_vsync_state[5] + set_location_assignment PIN_M4 -to d_vsync_state[6] + set_location_assignment PIN_G9 -to d_vsync_counter[0] + set_location_assignment PIN_G6 -to d_vsync_counter[7] + set_location_assignment PIN_G4 -to d_vsync_counter[8] + set_location_assignment PIN_G2 -to d_vsync_counter[9] + set_location_assignment PIN_K6 -to d_line_counter[0] + set_location_assignment PIN_K4 -to d_line_counter[1] + set_location_assignment PIN_J22 -to d_line_counter[2] + set_location_assignment PIN_M9 -to d_line_counter[3] + set_location_assignment PIN_M8 -to d_line_counter[4] + set_location_assignment PIN_M6 -to d_line_counter[5] + set_location_assignment PIN_M5 -to d_line_counter[6] + set_location_assignment PIN_L24 -to d_line_counter[7] + set_location_assignment PIN_L25 -to d_line_counter[8] + set_location_assignment PIN_L23 -to d_column_counter[0] + set_location_assignment PIN_L22 -to d_column_counter[1] + set_location_assignment PIN_L21 -to d_column_counter[2] + set_location_assignment PIN_L20 -to d_column_counter[3] + set_location_assignment PIN_L6 -to d_column_counter[4] + set_location_assignment PIN_L4 -to d_column_counter[5] + set_location_assignment PIN_L2 -to d_column_counter[6] + set_location_assignment PIN_K23 -to d_column_counter[7] + set_location_assignment PIN_K19 -to d_column_counter[8] + set_location_assignment PIN_K5 -to d_column_counter[9] + set_location_assignment PIN_L7 -to d_hsync + set_location_assignment PIN_L5 -to d_vsync + set_location_assignment PIN_F26 -to d_set_hsync_counter + set_location_assignment PIN_F24 -to d_set_vsync_counter + set_location_assignment PIN_F21 -to d_set_line_counter + set_location_assignment PIN_Y23 -to d_set_column_counter + set_location_assignment PIN_L3 -to d_r + set_location_assignment PIN_K24 -to d_g + set_location_assignment PIN_K20 -to d_b + set_location_assignment PIN_H18 -to d_v_enable + set_location_assignment PIN_J21 -to d_h_enable + set_location_assignment PIN_R8 -to seven_seg_pin[0] + set_location_assignment PIN_R9 -to seven_seg_pin[1] + set_location_assignment PIN_R19 -to seven_seg_pin[2] + set_location_assignment PIN_R20 -to seven_seg_pin[3] + set_location_assignment PIN_R21 -to seven_seg_pin[4] + set_location_assignment PIN_R22 -to seven_seg_pin[5] + set_location_assignment PIN_R23 -to seven_seg_pin[6] + set_location_assignment PIN_Y11 -to seven_seg_pin[7] + set_location_assignment PIN_N7 -to seven_seg_pin[8] + set_location_assignment PIN_N8 -to seven_seg_pin[9] + set_location_assignment PIN_R4 -to seven_seg_pin[10] + set_location_assignment PIN_R6 -to seven_seg_pin[11] + set_location_assignment PIN_AA11 -to seven_seg_pin[12] + set_location_assignment PIN_T2 -to seven_seg_pin[13] + set_location_assignment PIN_K3 -to d_state_clk + set_location_assignment PIN_H3 -to d_toggle + set_location_assignment PIN_H26 -to d_toggle_counter[0] + set_location_assignment PIN_G24 -to d_toggle_counter[15] + set_location_assignment PIN_G23 -to d_toggle_counter[16] + set_location_assignment PIN_G21 -to d_toggle_counter[17] + set_location_assignment PIN_G20 -to d_toggle_counter[18] + set_location_assignment PIN_G5 -to d_toggle_counter[19] + set_location_assignment PIN_G3 -to d_toggle_counter[20] + set_location_assignment PIN_G1 -to d_toggle_counter[21] + set_location_assignment PIN_F25 -to d_toggle_counter[22] + set_location_assignment PIN_F23 -to d_toggle_counter[23] + set_location_assignment PIN_T19 -to d_toggle_counter[24] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin + + + # Commit assignments + export_assignments + +execute_flow -compile + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/bsp2/Designflow/src/vga_pos_tb.vhd b/bsp2/Designflow/src/vga_pos_tb.vhd new file mode 100644 index 0000000..ebcff70 --- /dev/null +++ b/bsp2/Designflow/src/vga_pos_tb.vhd @@ -0,0 +1,198 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pos_tb is + +end vga_pos_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pos_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(1000000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pos of vga_pos_tb is + for structure + for vga_unit : vga use entity work.vga(structure); + end for; + end for; +end vga_conf_pos; + + + diff --git a/bsp2/Designflow/src/vga_pre_tb.vhd b/bsp2/Designflow/src/vga_pre_tb.vhd new file mode 100644 index 0000000..dc010f7 --- /dev/null +++ b/bsp2/Designflow/src/vga_pre_tb.vhd @@ -0,0 +1,197 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pre_tb is + +end vga_pre_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pre_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pre of vga_pre_tb is + for structure + for vga_unit : vga use entity work.vga(beh); + end for; + end for; +end vga_conf_pre; + + + diff --git a/bsp2/Designflow/src/vpll.bsf b/bsp2/Designflow/src/vpll.bsf new file mode 100644 index 0000000..63c3118 --- /dev/null +++ b/bsp2/Designflow/src/vpll.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2004 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 112 112) + (text "vpll" (rect 5 0 22 12)(font "Arial" )) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inclk0" (rect 0 0 28 12)(font "Arial" )) + (text "inclk0" (rect 21 27 49 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 96 32) + (output) + (text "c0" (rect 0 0 11 12)(font "Arial" )) + (text "c0" (rect 64 27 75 39)(font "Arial" )) + (line (pt 96 32)(pt 80 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 80 80)(line_width 1)) + ) +) diff --git a/bsp2/Designflow/src/vpll.vhd b/bsp2/Designflow/src/vpll.vhd new file mode 100644 index 0000000..dbb347f --- /dev/null +++ b/bsp2/Designflow/src/vpll.vhd @@ -0,0 +1,274 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: vpll.vhd +-- Megafunction Name(s): +-- altpll +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 4.1 Build 181 06/29/2004 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2004 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY vpll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; +-- pllena : IN STD_LOGIC := '1'; +-- areset : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC +-- locked : OUT STD_LOGIC + ); +END vpll; + + +ARCHITECTURE SYN OF vpll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (3 DOWNTO 0); + +signal pllena_int : std_logic; +signal areset_int : std_logic; +signal locked : std_logic; + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_duty_cycle : NATURAL; + lpm_type : STRING; + clk0_multiply_by : NATURAL; + invalid_lock_multiplier : NATURAL; + inclk0_input_frequency : NATURAL; + gate_lock_signal : STRING; + clk0_divide_by : NATURAL; + pll_type : STRING; + valid_lock_multiplier : NATURAL; + clk0_time_delay : STRING; + spread_frequency : NATURAL; + intended_device_family : STRING; + operation_mode : STRING; + compensate_clock : STRING; + clk0_phase_shift : STRING + ); + PORT ( + clkena : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + pllena : IN STD_LOGIC ; + extclkena : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + locked : OUT STD_LOGIC ; + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire3_bv(0 DOWNTO 0) <= "0"; + sub_wire3 <= To_stdlogicvector(sub_wire3_bv); + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= NOT(To_stdlogicvector(sub_wire5_bv)); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + locked <= sub_wire2; + sub_wire4 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire5(0 DOWNTO 0); + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire3(0 DOWNTO 0) & sub_wire6; + sub_wire8 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0); + +areset_int <= '0'; +pllena_int <= '1'; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_duty_cycle => 50, + lpm_type => "altpll", + clk0_multiply_by => 5435, + invalid_lock_multiplier => 5, + inclk0_input_frequency => 30003, + gate_lock_signal => "NO", + clk0_divide_by => 6666, + pll_type => "AUTO", + valid_lock_multiplier => 1, + clk0_time_delay => "0", + spread_frequency => 0, + intended_device_family => "Stratix", + operation_mode => "NORMAL", + compensate_clock => "CLK0", + clk0_phase_shift => "0" + ) + PORT MAP ( + clkena => sub_wire4, + inclk => sub_wire7, + pllena => pllena_int, + extclkena => sub_wire8, + areset => areset_int, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.175" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix" +-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5435" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6666" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" +-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE FALSE diff --git a/bsp2/Designflow/syn/rev_1/.recordref b/bsp2/Designflow/syn/rev_1/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/bsp2/Designflow/syn/rev_1/backup/vga.srr b/bsp2/Designflow/syn/rev_1/backup/vga.srr new file mode 100644 index 0000000..2a81acf --- /dev/null +++ b/bsp2/Designflow/syn/rev_1/backup/vga.srr @@ -0,0 +1,33 @@ +#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009 +#install: /opt/synplify/fpga_c200906 +#OS: Linux +#Hostname: ti12 + +#Implementation: rev_1 + +#Wed Oct 21 17:21:16 2009 + +$ Start of Compile +#Wed Oct 21 17:21:16 2009 + +Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009 +Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved + +@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns +@N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga. +VHDL syntax check successful! +@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav +@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000") +@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000") +@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav +@E: CD395 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd":50:73:50:95|Constant width 21 does not match context width 25 +@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav +@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000") +@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000") +@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav +1 errors during synthesis +@END +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Wed Oct 21 17:21:16 2009 + +###########################################################] diff --git a/bsp2/Designflow/syn/rev_1/rpt_vga.areasrr b/bsp2/Designflow/syn/rev_1/rpt_vga.areasrr new file mode 100644 index 0000000..63ef2cf --- /dev/null +++ b/bsp2/Designflow/syn/rev_1/rpt_vga.areasrr @@ -0,0 +1,174 @@ +#### START OF AREA REPORT #####[ + +Part: EP1S25FC672-6 (Altera) + +------------------------------------------------------------------- +######## Utilization report for Top level view: vga ######## +=================================================================== + +SEQUENTIAL ATOMS +**************** + +Name Total elements Utilization Notes +------------------------------------------------------ +REGISTERS 88 100 % +====================================================== +Total SEQUENTIAL ATOMS in the block vga: 88 (29.43 % Utilization) + + +COMBINATIONAL ATOMS +******************* + +Name Total elements Utilization Notes +------------------------------------------------------------ +ATOMS 72 100 % +ARITHMETIC MODE 53 100 % +============================================================ +Total COMBINATIONAL ATOMS in the block vga: 125 (41.81 % Utilization) + + +RAMS +**** + +Name Total elements Number of bits Utilization Notes +------------------------------------------------------------------------- +SYNC RAMS 0 0 0 % +LPMs 0 0 0 % +========================================================================= +Total RAMS in the block vga: 0 (0.00 % Utilization) + + +DSPs +**** + +Name Total elements Utilization Notes +------------------------------------------------- +MACs 0 0 % +================================================= +Total DSPs in the block vga: 0 (0.00 % Utilization) + + +Black Boxes +*********** + +Name Total elements Utilization Notes +-------------------------------------------------------- +BLACK BOXES 0 0 % +======================================================== +Total Black Boxes in the block vga: 0 (0.00 % Utilization) + +----------------------------------------------------------------- +######## Utilization report for cell: vga_control ######## +Instance path: vga.vga_control +================================================================= + +SEQUENTIAL ATOMS +**************** + +Name Total elements Utilization Notes +------------------------------------------------------ +REGISTERS 29 33 % +====================================================== +Total SEQUENTIAL ATOMS in the block vga.vga_control: 29 (9.70 % Utilization) + + +COMBINATIONAL ATOMS +******************* + +Name Total elements Utilization Notes +------------------------------------------------------------ +ATOMS 19 26.4 % +ARITHMETIC MODE 19 35.8 % +============================================================ +Total COMBINATIONAL ATOMS in the block vga.vga_control: 38 (12.71 % Utilization) + + +RAMS +**** + +Name Total elements Number of bits Utilization Notes +------------------------------------------------------------------------- +SYNC RAMS 0 0 0 % +LPMs 0 0 0 % +========================================================================= +Total RAMS in the block vga.vga_control: 0 (0.00 % Utilization) + + +DSPs +**** + +Name Total elements Utilization Notes +------------------------------------------------- +MACs 0 0 % +================================================= +Total DSPs in the block vga.vga_control: 0 (0.00 % Utilization) + + +Black Boxes +*********** + +Name Total elements Utilization Notes +-------------------------------------------------------- +BLACK BOXES 0 0 % +======================================================== +Total Black Boxes in the block vga.vga_control: 0 (0.00 % Utilization) + +---------------------------------------------------------------- +######## Utilization report for cell: vga_driver ######## +Instance path: vga.vga_driver +================================================================ + +SEQUENTIAL ATOMS +**************** + +Name Total elements Utilization Notes +------------------------------------------------------ +REGISTERS 57 64.8 % +====================================================== +Total SEQUENTIAL ATOMS in the block vga.vga_driver: 57 (19.06 % Utilization) + + +COMBINATIONAL ATOMS +******************* + +Name Total elements Utilization Notes +------------------------------------------------------------ +ATOMS 53 73.6 % +ARITHMETIC MODE 34 64.2 % +============================================================ +Total COMBINATIONAL ATOMS in the block vga.vga_driver: 87 (29.10 % Utilization) + + +RAMS +**** + +Name Total elements Number of bits Utilization Notes +------------------------------------------------------------------------- +SYNC RAMS 0 0 0 % +LPMs 0 0 0 % +========================================================================= +Total RAMS in the block vga.vga_driver: 0 (0.00 % Utilization) + + +DSPs +**** + +Name Total elements Utilization Notes +------------------------------------------------- +MACs 0 0 % +================================================= +Total DSPs in the block vga.vga_driver: 0 (0.00 % Utilization) + + +Black Boxes +*********** + +Name Total elements Utilization Notes +-------------------------------------------------------- +BLACK BOXES 0 0 % +======================================================== +Total Black Boxes in the block vga.vga_driver: 0 (0.00 % Utilization) + + +##### END OF AREA REPORT #####] + diff --git a/bsp2/Designflow/syn/rev_1/rpt_vga_areasrr.htm b/bsp2/Designflow/syn/rev_1/rpt_vga_areasrr.htm new file mode 100644 index 0000000..ab047d4 --- /dev/null +++ b/bsp2/Designflow/syn/rev_1/rpt_vga_areasrr.htm @@ -0,0 +1,193 @@ + +#### START OF AREA REPORT #####[
+Part:			EP1S25FC672-6 (Altera)
+
+Click here to go to specific block report:
+
vga

vga_driver

vga_control


+-------------------------------------------------------------------
+########   Utilization report for  Top level view:   vga   ########
+===================================================================
+
+SEQUENTIAL ATOMS
+****************
+
+Name          Total elements     Utilization     Notes
+------------------------------------------------------
+REGISTERS     88                 100 %                
+======================================================
+Total SEQUENTIAL ATOMS in the block vga:	88 (29.43 % Utilization)
+
+
Top

+
+COMBINATIONAL ATOMS
+*******************
+
+Name                Total elements     Utilization     Notes
+------------------------------------------------------------
+ATOMS               72                 100 %                
+ARITHMETIC MODE     53                 100 %                
+============================================================
+Total COMBINATIONAL ATOMS in the block vga:	125 (41.81 % Utilization)
+
+
Top

+
+RAMS
+****
+
+Name          Total elements     Number of bits     Utilization     Notes
+-------------------------------------------------------------------------
+SYNC RAMS     0                  0                  0 %                  
+LPMs          0                  0                  0 %                  
+=========================================================================
+Total RAMS in the block vga:	0 (0.00 % Utilization)
+
+
Top

+
+DSPs
+****
+
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+MACs     0                  0 %                  
+=================================================
+Total DSPs in the block vga:	0 (0.00 % Utilization)
+
+
Top

+
+Black Boxes
+***********
+
+Name            Total elements     Utilization     Notes
+--------------------------------------------------------
+BLACK BOXES     0                  0 %                  
+========================================================
+Total Black Boxes in the block vga:	0 (0.00 % Utilization)
+
+
Top

+
+-----------------------------------------------------------------
+########   Utilization report for  cell:   vga_control   ########
+Instance path:   vga.vga_control                                 
+=================================================================
+
+SEQUENTIAL ATOMS
+****************
+
+Name          Total elements     Utilization     Notes
+------------------------------------------------------
+REGISTERS     29                 33 %                 
+======================================================
+Total SEQUENTIAL ATOMS in the block vga.vga_control:	29 (9.70 % Utilization)
+
+
Top

+
+COMBINATIONAL ATOMS
+*******************
+
+Name                Total elements     Utilization     Notes
+------------------------------------------------------------
+ATOMS               19                 26.4 %               
+ARITHMETIC MODE     19                 35.8 %               
+============================================================
+Total COMBINATIONAL ATOMS in the block vga.vga_control:	38 (12.71 % Utilization)
+
+
Top

+
+RAMS
+****
+
+Name          Total elements     Number of bits     Utilization     Notes
+-------------------------------------------------------------------------
+SYNC RAMS     0                  0                  0 %                  
+LPMs          0                  0                  0 %                  
+=========================================================================
+Total RAMS in the block vga.vga_control:	0 (0.00 % Utilization)
+
+
Top

+
+DSPs
+****
+
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+MACs     0                  0 %                  
+=================================================
+Total DSPs in the block vga.vga_control:	0 (0.00 % Utilization)
+
+
Top

+
+Black Boxes
+***********
+
+Name            Total elements     Utilization     Notes
+--------------------------------------------------------
+BLACK BOXES     0                  0 %                  
+========================================================
+Total Black Boxes in the block vga.vga_control:	0 (0.00 % Utilization)
+
+
Top

+
+----------------------------------------------------------------
+########   Utilization report for  cell:   vga_driver   ########
+Instance path:   vga.vga_driver                                 
+================================================================
+
+SEQUENTIAL ATOMS
+****************
+
+Name          Total elements     Utilization     Notes
+------------------------------------------------------
+REGISTERS     57                 64.8 %               
+======================================================
+Total SEQUENTIAL ATOMS in the block vga.vga_driver:	57 (19.06 % Utilization)
+
+
Top

+
+COMBINATIONAL ATOMS
+*******************
+
+Name                Total elements     Utilization     Notes
+------------------------------------------------------------
+ATOMS               53                 73.6 %               
+ARITHMETIC MODE     34                 64.2 %               
+============================================================
+Total COMBINATIONAL ATOMS in the block vga.vga_driver:	87 (29.10 % Utilization)
+
+
Top

+
+RAMS
+****
+
+Name          Total elements     Number of bits     Utilization     Notes
+-------------------------------------------------------------------------
+SYNC RAMS     0                  0                  0 %                  
+LPMs          0                  0                  0 %                  
+=========================================================================
+Total RAMS in the block vga.vga_driver:	0 (0.00 % Utilization)
+
+
Top

+
+DSPs
+****
+
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+MACs     0                  0 %                  
+=================================================
+Total DSPs in the block vga.vga_driver:	0 (0.00 % Utilization)
+
+
Top

+
+Black Boxes
+***********
+
+Name            Total elements     Utilization     Notes
+--------------------------------------------------------
+BLACK BOXES     0                  0 %                  
+========================================================
+Total Black Boxes in the block vga.vga_driver:	0 (0.00 % Utilization)
+
+
Top

+
+##### END OF AREA REPORT #####]
+
diff --git a/bsp2/Designflow/syn/rev_1/run_options.txt b/bsp2/Designflow/syn/rev_1/run_options.txt
new file mode 100644
index 0000000..e582c9d
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/run_options.txt
@@ -0,0 +1,71 @@
+#-- Synplicity, Inc.
+#-- Version C-2009.06
+#-- Project file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/run_options.txt
+#-- Written on Wed Oct 21 17:26:30 2009
+
+
+#project files
+add_file -vhdl -lib work "../src/vga_pak.vhd"
+add_file -vhdl -lib work "../src/vga_ent.vhd"
+add_file -vhdl -lib work "../src/vga_arc.vhd"
+add_file -vhdl -lib work "../src/board_driver_ent.vhd"
+add_file -vhdl -lib work "../src/board_driver_arc.vhd"
+add_file -vhdl -lib work "../src/vga_control_ent.vhd"
+add_file -vhdl -lib work "../src/vga_control_arc.vhd"
+add_file -vhdl -lib work "../src/vga_driver_ent.vhd"
+add_file -vhdl -lib work "../src/vga_driver_arc.vhd"
+
+
+#implementation: "rev_1"
+impl -add rev_1 -type fpga
+
+#device options
+set_option -technology STRATIX
+set_option -part EP1S25
+set_option -package FC672
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "vga"
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# mapper_options
+set_option -frequency 25.175
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# Altera STRATIX
+set_option -run_prop_extract 1
+set_option -maxfan 500
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -quartus_version 9.0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./rev_1/vga.vqm"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "rev_1"
diff --git a/bsp2/Designflow/syn/rev_1/scratchproject.prs b/bsp2/Designflow/syn/rev_1/scratchproject.prs
new file mode 100644
index 0000000..09934b5
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/scratchproject.prs
@@ -0,0 +1,71 @@
+#-- Synplicity, Inc.
+#-- Version C-2009.06
+#-- Project file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/scratchproject.prs
+#-- Written on Wed Oct 21 17:26:30 2009
+
+
+#project files
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd"
+
+
+#implementation: "rev_1"
+impl -add /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1 -type fpga
+
+#device options
+set_option -technology STRATIX
+set_option -part EP1S25
+set_option -package FC672
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "vga"
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# mapper_options
+set_option -frequency 25.175
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# Altera STRATIX
+set_option -run_prop_extract 1
+set_option -maxfan 500
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -quartus_version 9.0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "rev_1"
diff --git a/bsp2/Designflow/syn/rev_1/syntmp/sap.log b/bsp2/Designflow/syn/rev_1/syntmp/sap.log
new file mode 100644
index 0000000..4b5d11a
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/sap.log
@@ -0,0 +1,13 @@
+Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
+Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
+Product Version C-2009.06
+@N: MF249 |Running in 32-bit mode.
+@N: MF257 |Gated clock conversion enabled 
+@N|Running in logic synthesis mode without enhanced optimization
+@W|Ignoring synthesis effort setting for the design. This is not supported by the current technology.
+
+@N: BN225 |Writing default property annotation file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.sap.
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Oct 21 17:26:30 2009
+
+###########################################################]
diff --git a/bsp2/Designflow/syn/rev_1/syntmp/sap_log_flink.htm b/bsp2/Designflow/syn/rev_1/syntmp/sap_log_flink.htm
new file mode 100644
index 0000000..94ee5b3
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/sap_log_flink.htm
@@ -0,0 +1,8 @@
+
+
+

+
+Log File Links:

+
rev_1

+
Hierarchical Area Report (/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/rpt_vga) (17:24 21-Oct)


+

Session Log

diff --git a/bsp2/Designflow/syn/rev_1/syntmp/sap_log_srr.htm b/bsp2/Designflow/syn/rev_1/syntmp/sap_log_srr.htm
new file mode 100644
index 0000000..e69de29
diff --git a/bsp2/Designflow/syn/rev_1/syntmp/vga.msg b/bsp2/Designflow/syn/rev_1/syntmp/vga.msg
new file mode 100644
index 0000000..a701b62
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/vga.msg
@@ -0,0 +1,22 @@
+@TM:1256138598
+@N:  :"":0:0:0:-1|Running in logic synthesis mode without enhanced optimization
+@N: FA174 :"":0:0:0:-1|The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
+@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
+@N: MF257 :"":0:0:0:-1|Gated clock conversion enabled 
+@N: MF276 :"":0:0:0:-1|Gated clock conversion enabled, but no gated clocks found in design 
+@N: MF333 :"":0:0:0:-1|Generated clock conversion enabled, but no generated clocks found in design 
+@N: MT320 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
+@N: MT322 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
+@TM:1256138589
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|M
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|M
+@TM:1256138598
+@N:  :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":158:4:158:5|M
+@N:  :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":267:4:267:5|M
+@TM:1256138589
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|M
+@N:  :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|M
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|M
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|M
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|M
+@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|M
diff --git a/bsp2/Designflow/syn/rev_1/syntmp/vga.plg b/bsp2/Designflow/syn/rev_1/syntmp/vga.plg
new file mode 100644
index 0000000..9be8937
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/vga.plg
@@ -0,0 +1,13 @@
+@P:  Part : EP1S25FC672-6
+@P:  Worst Slack : 34.458
+@P:  vga|clk_pin - Estimated Frequency : 190.0 MHz
+@P:  vga|clk_pin - Requested Frequency : 25.2 MHz
+@P:  vga|clk_pin - Estimated Period : 5.264
+@P:  vga|clk_pin - Requested Period : 39.722
+@P:  vga|clk_pin - Slack : 34.458
+@P: vga Part : ep1s25fc672-6
+@P: vga I/O ATOMs : 117
+@P: vga Total LUTs: : 179 of 25660 ( 0%)
+@P: vga Logic resources : 181 ATOMs of 25660 ( 0%)
+@P: vga DSP Blocks : 0 (0 nine-bit DSP elements)
+@P:  CPU Time : 0h:00m:04s
diff --git a/bsp2/Designflow/syn/rev_1/syntmp/vga_cons_ui.tcl b/bsp2/Designflow/syn/rev_1/syntmp/vga_cons_ui.tcl
new file mode 100644
index 0000000..c791b24
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/vga_cons_ui.tcl
@@ -0,0 +1,5 @@
+source "/opt/synplify/fpga_c200906/lib/altera/quartus_cons.tcl"
+syn_create_and_open_prj vga
+source $::quartus(binpath)/prj_asd_import.tcl
+syn_create_and_open_csf vga
+syn_handle_cons vga
diff --git a/bsp2/Designflow/syn/rev_1/syntmp/vga_driver_arc_flink.htm b/bsp2/Designflow/syn/rev_1/syntmp/vga_driver_arc_flink.htm
new file mode 100644
index 0000000..8a1f00c
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/vga_driver_arc_flink.htm
@@ -0,0 +1,7 @@
+
+
+

+
+Log File Links:

+
rev_1

+

Session Log

diff --git a/bsp2/Designflow/syn/rev_1/syntmp/vga_flink.htm b/bsp2/Designflow/syn/rev_1/syntmp/vga_flink.htm
new file mode 100644
index 0000000..c09947c
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/vga_flink.htm
@@ -0,0 +1,8 @@
+
+
+

+
+Log File Links:

+
rev_1

+
Hierarchical Area Report (/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/rpt_vga) (17:26 21-Oct)


+

Session Log

diff --git a/bsp2/Designflow/syn/rev_1/syntmp/vga_srr.htm b/bsp2/Designflow/syn/rev_1/syntmp/vga_srr.htm
new file mode 100644
index 0000000..c565093
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/vga_srr.htm
@@ -0,0 +1,315 @@
+
+
+#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
+#install: /opt/synplify/fpga_c200906
+#OS: Linux 
+#Hostname: ti12
+
+#Implementation: rev_1
+
+#Wed Oct 21 17:26:30 2009
+
+$ Start of Compile
+#Wed Oct 21 17:26:30 2009
+
+Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
+Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
+
+@N:CD720 : std.vhd(123) | Setting time resolution to ns
+@N: : vga_ent.vhd(38) | Top entity is set to vga.
+VHDL syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+@N:CD630 : vga_ent.vhd(38) | Synthesizing work.vga.behav 
+@N:CD231 : vga_pak.vhd(60) | Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N:CD231 : vga_pak.vhd(62) | Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N:CD630 : vga_control_ent.vhd(37) | Synthesizing work.vga_control.behav 
+Post processing for work.vga_control.behav
+@N:CD630 : vga_driver_ent.vhd(37) | Synthesizing work.vga_driver.behav 
+@N:CD231 : vga_pak.vhd(60) | Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N:CD231 : vga_pak.vhd(62) | Using onehot encoding for type vsync_state_type (reset_state="1000000")
+Post processing for work.vga_driver.behav
+@N:CD630 : board_driver_ent.vhd(36) | Synthesizing work.board_driver.behav 
+Post processing for work.board_driver.behav
+Post processing for work.vga.behav
+@END
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Oct 21 17:26:30 2009
+
+###########################################################]
+Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
+Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
+Product Version C-2009.06
+@N:MF249 :  | Running in 32-bit mode. 
+@N:MF257 :  | Gated clock conversion enabled  
+@N: :  | Running in logic synthesis mode without enhanced optimization 
+
+Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
+Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+@N: : vga_driver_arc.vhd(267) | Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
+@N: : vga_driver_arc.vhd(158) | Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
+
+
+
+#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
+
+======================================================================================
+                                Instance:Pin        Generated Clock Optimization Status
+======================================================================================
+
+
+##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
+
+Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
+
+Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
+
+Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 68MB)
+
+
+Writing Analyst data base /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.srm
+Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Writing Verilog Netlist and constraint files
+Writing .vqm output for Quartus
+Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.xrf
+Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Writing VHDL Simulation files
+Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+@N:MF276 :  | Gated clock conversion enabled, but no gated clocks found in design  
+Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+@N:MF333 :  | Generated clock conversion enabled, but no generated clocks found in design  
+Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Found clock vga|clk_pin with period 39.72ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Wed Oct 21 17:26:36 2009
+#
+
+
+Top view:               vga
+Requested Frequency:    25.2 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    
+@N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 
+
+@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 34.458
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock              
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
+----------------------------------------------------------------------------------------------------------------------
+vga|clk_pin        25.2 MHz      190.0 MHz     39.722        5.264         34.458     inferred     Inferred_clkgroup_0
+======================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-----------------------------------------------------------------------------------------------------------------
+Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-----------------------------------------------------------------------------------------------------------------
+vga|clk_pin  vga|clk_pin  |  39.722      34.458  |  No paths    -      |  No paths    -      |  No paths    -    
+=================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+		No IO constraint found 
+
+
+
+====================================
+Detailed Report for Clock: vga|clk_pin
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                           Starting                                                                 Arrival           
+Instance                                   Reference       Type                 Pin        Net                      Time        Slack 
+                                           Clock                                                                                      
+--------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[6]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_6     0.176       34.458
+dly_counter[0]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[0]           0.176       34.465
+dly_counter[1]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[1]           0.176       34.584
+vga_control_unit.toggle_counter_sig[5]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_5     0.176       34.585
+vga_driver_unit.vsync_counter[6]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_6          0.176       34.836
+vga_driver_unit.vsync_counter[7]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_7          0.176       34.865
+vga_control_unit.toggle_counter_sig[8]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_8     0.176       34.921
+vga_driver_unit.vsync_counter[3]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_3          0.176       34.992
+vga_driver_unit.vsync_counter[8]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_8          0.176       34.992
+vga_control_unit.toggle_counter_sig[9]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_9     0.176       35.048
+======================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                           Starting                                                              Required           
+Instance                                   Reference       Type                 Pin      Net                     Time         Slack 
+                                           Clock                                                                                    
+------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[0]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[1]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[2]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[3]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[4]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[5]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[6]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[7]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[8]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[9]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+====================================================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+    Requested Period:                        39.722
+    - Setup time:                            0.792
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         38.930
+
+    - Propagation time:                      4.472
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     34.458
+
+    Number of logic level(s):                6
+    Starting point:                          vga_control_unit.toggle_counter_sig[6] / regout
+    Ending point:                            vga_control_unit.toggle_counter_sig[0] / sclr
+    The start point is clocked by            vga|clk_pin [rising] on pin clk
+    The end   point is clocked by            vga|clk_pin [rising] on pin clk
+
+Instance / Net                                                                     Pin         Pin               Arrival     No. of    
+Name                                                          Type                 Name        Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[6]                        stratix_lcell_ff     regout      Out     0.176     0.176       -         
+toggle_counter_sig_6                                          Net                  -           -       1.000     -           4         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6      stratix_lcell        dataa       In      -         1.176       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6      stratix_lcell        combout     Out     0.459     1.635       -         
+un1_toggle_counter_siglt6                                     Net                  -           -       0.376     -           1         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9     stratix_lcell        datad       In      -         2.011       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9     stratix_lcell        combout     Out     0.087     2.098       -         
+un1_toggle_counter_siglto9                                    Net                  -           -       0.376     -           1         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12    stratix_lcell        datad       In      -         2.474       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12    stratix_lcell        combout     Out     0.087     2.561       -         
+un1_toggle_counter_siglto12                                   Net                  -           -       0.376     -           1         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15    stratix_lcell        datad       In      -         2.938       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15    stratix_lcell        combout     Out     0.087     3.025       -         
+un1_toggle_counter_siglto15                                   Net                  -           -       0.376     -           1         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18    stratix_lcell        datad       In      -         3.401       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18    stratix_lcell        combout     Out     0.087     3.488       -         
+un1_toggle_counter_siglto18                                   Net                  -           -       0.376     -           1         
+vga_control_unit.toggle_sig_0_0_0_g1                          stratix_lcell        datad       In      -         3.864       -         
+vga_control_unit.toggle_sig_0_0_0_g1                          stratix_lcell        combout     Out     0.087     3.951       -         
+toggle_sig_0_0_0_g1                                           Net                  -           -       0.521     -           22(6)     
+vga_control_unit.toggle_counter_sig[0]                        stratix_lcell_ff     sclr        In      -         4.472       -         
+=======================================================================================================================================
+Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.264 is 1.862(35.4%) logic and 3.402(64.6%) route.
+Fanout format: logic fanout (physical fanout)
+Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
+*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
+
+
+
+##### END OF TIMING REPORT #####]
+
+##### START OF AREA REPORT #####[
+Design view:work.vga(behav)
+Selecting part EP1S25F672C6
+@N:FA174 :  | The following device usage report estimates place and route data. Please look at the place and route report for final resource usage.. 
+
+I/O ATOMs:       117
+
+Total LUTs:  179 of 25660 ( 0%)
+Logic resources:  181 ATOMs of 25660 ( 0%)
+
+Number of I/O registers
+			Output DDRs   :0
+
+ATOM count by mode:
+  normal:       128
+  arithmetic:   53
+
+DSP Blocks:     0  (0 nine-bit DSP elements).
+DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
+ShiftTap:       0  (0 registers)
+MRAM:           0  (0% of 2)
+M4Ks:           0  (0% of 138)
+M512s:          0  (0% of 224)
+Total ESB:      0 bits 
+
+ATOMs using regout pin: 88
+  also using enable pin: 12
+  also using combout pin: 1
+ATOMs using combout pin: 91
+Number of Inputs on ATOMs: 760
+Number of Nets:   54954
+
+##### END OF AREA REPORT #####]
+
+Mapper successful!
+Process took 0h:00m:05s realtime, 0h:00m:04s cputime
+# Wed Oct 21 17:26:36 2009
+
+###########################################################]
diff --git a/bsp2/Designflow/syn/rev_1/syntmp/vga_toc.htm b/bsp2/Designflow/syn/rev_1/syntmp/vga_toc.htm
new file mode 100644
index 0000000..26d593f
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/vga_toc.htm
@@ -0,0 +1,17 @@
+
+
+

+
+

+rev_1 (vga)

+Compiler Report

+Mapper Report

+Timing Report

+Performance Summary

+Clock Relationships

+Interface Information

+Detailed Report for Clock: vga|clk_pin

+   Starting Points with Worst Slack

+   Ending Points with Worst Slack

+   Worst Path Information

+Resource Utilization

diff --git a/bsp2/Designflow/syn/rev_1/verif/vga.vif b/bsp2/Designflow/syn/rev_1/verif/vga.vif
new file mode 100644
index 0000000..0705776
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/verif/vga.vif
@@ -0,0 +1,141 @@
+#
+# Synplicity Verification Interface File
+# Generated using Synplify-pro
+#
+# Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
+
+# All rights reserved
+#
+
+# Set logfile options
+vif_set_result_file  vga.vlf
+
+# Set technology for TCL script
+vif_set_technology -architecture FPGA -vendor Altera
+
+# RTL and technology files
+vif_add_file -original -vhdl -lib work ../../src/vga_pak.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_ent.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_arc.vhd
+vif_add_file -original -vhdl -lib work ../../src/board_driver_ent.vhd
+vif_add_file -original -vhdl -lib work ../../src/board_driver_arc.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_control_ent.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_control_arc.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_driver_ent.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_driver_arc.vhd
+vif_set_top_module -original -top vga
+ 
+vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
+vif_add_file -translated -verilog vga.vqm
+vif_set_top_module -translated -top vga 
+# Read FSM encoding
+
+# Memory map points
+
+# SRL map points
+
+# Compiler constant registers
+
+# Compiler constant latches
+
+# Compiler RTL sequential redundancies
+
+# RTL sequential redundancies
+
+# Technology sequential redundancies
+
+# Inversion map points
+
+# Port mappping and directions
+
+# Black box mapping
+
+
+# Other sequential cells, including multidimensional arrays
+vif_set_map_point -register -original vga_driver_unit/hsync_state[0] -translated vga_driver_unit/hsync_state_0_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[1] -translated vga_driver_unit/hsync_state_1_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[2] -translated vga_driver_unit/hsync_state_2_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[3] -translated vga_driver_unit/hsync_state_3_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[4] -translated vga_driver_unit/hsync_state_4_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[5] -translated vga_driver_unit/hsync_state_5_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[2] -translated vga_driver_unit/vsync_state_2_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[3] -translated vga_driver_unit/vsync_state_3_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[4] -translated vga_driver_unit/vsync_state_4_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[5] -translated vga_driver_unit/vsync_state_5_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[0] -translated vga_driver_unit/line_counter_sig_0_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[1] -translated vga_driver_unit/line_counter_sig_1_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[2] -translated vga_driver_unit/line_counter_sig_2_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[3] -translated vga_driver_unit/line_counter_sig_3_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[4] -translated vga_driver_unit/line_counter_sig_4_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[5] -translated vga_driver_unit/line_counter_sig_5_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[6] -translated vga_driver_unit/line_counter_sig_6_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[7] -translated vga_driver_unit/line_counter_sig_7_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[8] -translated vga_driver_unit/line_counter_sig_8_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[6] -translated vga_driver_unit/vsync_state_6_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[1] -translated vga_driver_unit/vsync_state_1_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[0] -translated vga_driver_unit/vsync_state_0_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[6] -translated vga_driver_unit/hsync_state_6_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[0] -translated vga_driver_unit/column_counter_sig_0_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[1] -translated vga_driver_unit/column_counter_sig_1_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[2] -translated vga_driver_unit/column_counter_sig_2_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[3] -translated vga_driver_unit/column_counter_sig_3_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[4] -translated vga_driver_unit/column_counter_sig_4_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[5] -translated vga_driver_unit/column_counter_sig_5_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[6] -translated vga_driver_unit/column_counter_sig_6_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[7] -translated vga_driver_unit/column_counter_sig_7_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[8] -translated vga_driver_unit/column_counter_sig_8_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[9] -translated vga_driver_unit/column_counter_sig_9_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[9] -translated vga_driver_unit/vsync_counter_9_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[8] -translated vga_driver_unit/vsync_counter_8_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[7] -translated vga_driver_unit/vsync_counter_7_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[6] -translated vga_driver_unit/vsync_counter_6_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[5] -translated vga_driver_unit/vsync_counter_5_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[4] -translated vga_driver_unit/vsync_counter_4_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[3] -translated vga_driver_unit/vsync_counter_3_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[2] -translated vga_driver_unit/vsync_counter_2_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[1] -translated vga_driver_unit/vsync_counter_1_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[0] -translated vga_driver_unit/vsync_counter_0_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[9] -translated vga_driver_unit/hsync_counter_9_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[8] -translated vga_driver_unit/hsync_counter_8_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[7] -translated vga_driver_unit/hsync_counter_7_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[6] -translated vga_driver_unit/hsync_counter_6_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[5] -translated vga_driver_unit/hsync_counter_5_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[4] -translated vga_driver_unit/hsync_counter_4_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[3] -translated vga_driver_unit/hsync_counter_3_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[2] -translated vga_driver_unit/hsync_counter_2_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[1] -translated vga_driver_unit/hsync_counter_1_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[0] -translated vga_driver_unit/hsync_counter_0_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[0] -translated vga_control_unit/toggle_counter_sig_0_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[1] -translated vga_control_unit/toggle_counter_sig_1_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[2] -translated vga_control_unit/toggle_counter_sig_2_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[3] -translated vga_control_unit/toggle_counter_sig_3_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[4] -translated vga_control_unit/toggle_counter_sig_4_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[5] -translated vga_control_unit/toggle_counter_sig_5_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[6] -translated vga_control_unit/toggle_counter_sig_6_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[7] -translated vga_control_unit/toggle_counter_sig_7_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[8] -translated vga_control_unit/toggle_counter_sig_8_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[9] -translated vga_control_unit/toggle_counter_sig_9_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[10] -translated vga_control_unit/toggle_counter_sig_10_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[11] -translated vga_control_unit/toggle_counter_sig_11_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[12] -translated vga_control_unit/toggle_counter_sig_12_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[13] -translated vga_control_unit/toggle_counter_sig_13_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[14] -translated vga_control_unit/toggle_counter_sig_14_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[15] -translated vga_control_unit/toggle_counter_sig_15_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[16] -translated vga_control_unit/toggle_counter_sig_16_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[17] -translated vga_control_unit/toggle_counter_sig_17_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[18] -translated vga_control_unit/toggle_counter_sig_18_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[19] -translated vga_control_unit/toggle_counter_sig_19_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[20] -translated vga_control_unit/toggle_counter_sig_20_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[21] -translated vga_control_unit/toggle_counter_sig_21_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[22] -translated vga_control_unit/toggle_counter_sig_22_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[23] -translated vga_control_unit/toggle_counter_sig_23_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[24] -translated vga_control_unit/toggle_counter_sig_24_
+vif_set_map_point -register -original dly_counter[0] -translated dly_counter_0_
+vif_set_map_point -register -original dly_counter[1] -translated dly_counter_1_
+
+# Constant Registers
+
+# Retimed Registers
+
+# Altera MAC annotations
+
diff --git a/bsp2/Designflow/syn/rev_1/vga.fse b/bsp2/Designflow/syn/rev_1/vga.fse
new file mode 100644
index 0000000..e69de29
diff --git a/bsp2/Designflow/syn/rev_1/vga.htm b/bsp2/Designflow/syn/rev_1/vga.htm
new file mode 100644
index 0000000..2e5be3d
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.htm
@@ -0,0 +1,12 @@
+
+
+syntmp/vga_srr.htm log file
+
+
+	
+		
+		
+	
+	
+
+
diff --git a/bsp2/Designflow/syn/rev_1/vga.map b/bsp2/Designflow/syn/rev_1/vga.map
new file mode 100644
index 0000000..2b02f94
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.map
@@ -0,0 +1 @@
+%%% protect protected_file
diff --git a/bsp2/Designflow/syn/rev_1/vga.sap b/bsp2/Designflow/syn/rev_1/vga.sap
new file mode 100644
index 0000000..feb1d5f
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.sap
@@ -0,0 +1,153 @@
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diff --git a/bsp2/Designflow/syn/rev_1/vga.srd b/bsp2/Designflow/syn/rev_1/vga.srd
new file mode 100644
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diff --git a/bsp2/Designflow/syn/rev_1/vga.srm b/bsp2/Designflow/syn/rev_1/vga.srm
new file mode 100644
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+bHRsCC#0N;
+H$R#M#_N$EMOR
+4;HMRCNH;
+R
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+RMRq pa)qq_uR XN(4jdB_nnbBRs;Hl
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+R08NN
+L;HNR80;NO
+OHRD
+	;N#HR$HM_#FODO4	R;R
+FOLFlFRk0on4U;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jHRMP8NN0LR_H8NN0L__H4NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jHRMP8NN0OR_H8NN0O__H4NR80;NO
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_RUo4nDRO	hRt7hRt7BReBb;
+R:fjjsRFRUo4n4RoU8nRNN0N_4H_,08NNHL__84,NO0N_4H_;
+
+
+
+RMRq pa)qq_uR XVgVcUj_jUbjRs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R08NN
+L;HNR80;NO
+8HRN80N;R
+HO;D	
+RNH#_$MHD#OFRO	4F;
+RosCFRk0h;_4
+RoMh;_4
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RPHMR08NNH8_R08NNH8__84RN80N;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
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+B;bjRf:NjRMo8R4Rg4o44gR08NN8N,NL0N,08NN8O,N80N_4H_;
+
+
+
+RMRq pa)qq_uR XVgVcUB_jqb Rs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
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+H8NN0NH;
+R08NN
+L;HNR80;NO
+8HRN80N;R
+HO;D	
+RNH#_$MHD#OFRO	4F;
+RosCFRk0h;_4
+RoMh;_4
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:j8sVV#wCRw_Rh44RogO6RDt	Rht7Rhe7RB
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+
+
+
+RMRq pa)qq_uR XVUVdnw_wjbjRs;Hl
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+H8NN08H;
+R	OD;H
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+4;FCRso0FkR4h_;M
+oR4h_;M
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+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_84RN80NR	ODR7thR7thRBeB;
+
+
+
+RMRq pa)qq_uR XVcVUg(U_(R((blsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
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+OHRD
+	;N#HR$HM_#FODO4	R;R
+H#sOD;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMh;_.
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RPHMR08NNHL_R08NNHL__84RNL0N;R
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+fbRjR:j0CskRBeBRBeB;R
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+.;
+RMRq pa)qq_uR XO.M06Ugd_66qqsRbH
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+OHRH
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+OHRD
+	;N#HR$HM_#FODO4	R;R
+H#sOD;R
+H#NDF8F;
+RosCFRk0h;_4
+8HRNO0N;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.no;
+M_Rh.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_
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+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
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+.;
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+NR#3H_RVV4N;
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+HO;HM
+8HRNN0N;R
+HO;D	
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+RF#DN
+8;FCRso0FkR4h_;R
+FO0FkRjo.(H;
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+RoMh;_.
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+oRdh_;M
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+#HRO;Ds
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+8HRNO0N;M
+oR4h_;M
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+R:fjjsR0keCRBeBRB
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+
+
+
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+s;HDR#F;N8
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+NR#3HblsHR
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+
+
+
+RMRq pa)qq_uR XN_cg4444RHbslN;
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+;
+
+RMRq pa)qq_uR XNd44_ww  sRbH
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+
+
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+
+
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+.;
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+
+
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+
+
+
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+
+
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+
+
+
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+";N3PRHs#bH4lR;P
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+oR4h_;M
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+R:fjjMRHPNR80_NNHNR80_NNHR_48NN0Nb;
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+";N3PRHs#bH4lR;P
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+bfjj:RV8VsR#CwhwR_o4R.RU4ORD	NsODR7thRBeB;
+
+
+
+RMRq pa)qq_uR XV.V46_n.6666RHbslN;
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+	;N#HR$HM_#FODO4	R;R
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+R:fjjFRGs.RoUocR.RUc8NN0NN,80;NL
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+OFRFRk0og.U;M
+oR4h_;M
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+;
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+RMRq pa)qq_uR XVdV4n_..nBBn_UUjjsRbH
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+RosCFRk0h;_4
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+oR4h_;M
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+
+
+
+RMRq pa)qq_uR XVdV4n_4UnBBnRHbslN;
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+
+
+
+RMRq pa)qq_uR XVdV46_Un6qq6RHbslN;
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+RNP3M8FCl#sR
+4;HHROMH;
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+NHRO;Ds
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+n;ohMR_
+.;N3MR#CNP_0MC_NVDoR#4.;6n
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+;
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+B;b@R@nc:c:c(:c.:4:_sjbRHMfjj:RH0sR4Q_3H0sR8bNH8FRNH0NMBReB
+;
+
+RMRvB )z_)YpRQA#N0s0_HGHmF_uRajblsH;P
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+
+
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+RNO30CGCNsMD8_CHMV_NRlC"s#0NG0H_CDOD;D"
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+FO0Fk;H
+NRH3#lV8CN0kDRz'hp;p'
+OFRNF#Ok
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+RNH3lPJ8NCVkRD0'7th'H;
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+N;N3HR#8HlCkVND'0Re'BB;H
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+';N3HRP8JlCkVND'0Re'BB;R
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+RNH3lPJ8NCVkRD0'BeB'H;
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+RNH3lPJ8NCVkRD0'7th'N;
+H$R#M#_N$EMOR
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+';HDR#F;N8
+RNH3l#H8NCVkRD0'7th'N;
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+CHRM
+N;N3HR#8HlCkVND'0Re'BB;H
+NRJ3PlV8CN0kDRB'eB
+';HHROMN;
+H#R3HCl8VDNk0tR'h;7'
+HHRMsPC0
+N;N3HR#8HlCkVND'0Rt'h7;H
+NRJ3PlV8CN0kDRh't7
+';HDRNF;N8
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+RNH#_$MNM#$O4ER;R
+HsOCoNH#OMN;
+H#R3HCl8VDNk0hR'z'pp;H
+NRJ3PlV8CN0kDRh't7
+';
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+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_	bN38PE"y;RVCHDRN.
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+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOLsFN8s_8HsPC_0CM38PE"y;RVCHDRN(
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+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8R";yDVHC4R4
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+NRHR3#E_P84DR;R
+MRaqp _)qqXu Rs#0NG0H_CDODVD_V)RuQ
+v;N3ORCCG0sDMN_HC8VN_Ml"CR#N0s0_HGDDOCD
+";N3OR#b	H_8PED#_kC;R4
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP30CGCNsMDC_PsFHDoN_Ml"CR#N0s0_HGDDOCD
+";N3PRCCG0sDMN_8PEDN_Ml"CR#N0s0_HGDDOCD
+";N3PR#8HlCkVND'0R8bCPF8s,CDPOs;M'
+RNP3$bE_0#HCwR"w
+";N3PRPDE8_H#	b;R4
+OFRFFlLk
+0;N3HR#8HlCkVND'0Rhpzp'F;
+RosCF;k0
+RNH3l#H8NCVkRD0'phzp
+';N3HRHN#DM#8_CCJkMN0HDH_bM;R4
+OFRF;k0
+RNH3l#H8NCVkRD0'phzp
+';FNRO#kOF0H;
+R	OD;H
+NRH3#lV8CN0kDRh't7
+';N3HRP8JlCkVND'0Rt'h7;H
+NRM#$_OH#D	FOR
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+RNH3l#H8NCVkRD0'BeB'N;
+HPR3JCl8VDNk0eR'B;B'
+8HRNL0N;H
+NRH3#lV8CN0kDRB'eB
+';N3HRP8JlCkVND'0Re'BB;R
+H8NN0ON;
+H#R3HCl8VDNk0eR'B;B'
+RNH3lPJ8NCVkRD0'BeB'H;
+R08NN
+8;N3HR#8HlCkVND'0Re'BB;H
+NRJ3PlV8CN0kDRB'eB
+';HORND
+s;N3HR#8HlCkVND'0Rt'h7;H
+NRJ3PlV8CN0kDRh't7
+';N3HRl	Ns_$N#MsO_C0#CR
+4;N#HR$NM_#O$ME;R4
+#HRO;Ds
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+#HRD8FN;H
+NRH3#lV8CN0kDRh't7
+';N3HRP8JlCkVND'0Rt'h7;H
+NRN3ls#	_$_MOsCC#0;R4
+CHRM
+N;N3HR#8HlCkVND'0Re'BB;H
+NRJ3PlV8CN0kDRB'eB
+';N3HRl	Ns_FODOC	_MDNLC;R4
+OHRH
+M;N3HR#8HlCkVND'0Rt'h7;R
+HHCMPs;0N
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+NHRD8FN;H
+NRH3#lV8CN0kDRh't7
+';N3HRP8JlCkVND'0Rt'h7;H
+NRM#$_$N#MROE4H;
+RosCOON#H
+M;N3HR#8HlCkVND'0Rhpzp'N;
+HPR3JCl8VDNk0tR'h;7'
+"VRMNFMl;C"RHyVDjCR
+"VR/0Fb/M#$bVDH$b/VoON_.gjjjDn/HPL/E#8/0P83E;8"RHyVD4CR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_	bN38PE"y;RVCHDRN.
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/8#04c4n38PE"y;RVCHDRNd
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/#kMHCoM8E3P8R";yDVHC
+RcNRVR3_H#PDE8R
+4;V/R"F/b0#b$MD$HV/oVbN._OjjjgnH/DLE/P8s/NH30EP"E8;VRyHRDC6V
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8R";yDVHC
+RnNRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOLsFN8s_8HsPC_0CM38PE"y;RVCHDRN(
+V3RRHP#_ER8D4V;
+RE"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/oON_FsM0FCD_MP03E;8"RHyVDUCR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsC3M0P"E8;VRyHRDCgV
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNs_NOE3P8R";yDVHCjR4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8R";yDVHC4R4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_MOF0DsF_ONs38PE"y;RVCHDR
+4.NRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCNs_sPO3E;8"RHyVD4CRdV
+NRHR3#E_P84DR;R
+MRaqp _)qqXu Rs#0NG0H_RHFuv)Q;O
+NRG3C0MCsNCD_8_HVMCNlR0"#sHN0GF_H"N;
+PDR3ClV_NFOsMCNlRm"Q"N;
+PHR3#Hbsl;R4
+RNP3bH#N48R;P
+NRH3#lV8CN0kDRC'8PsbF,P8COMDs,P8CF;C'
+RNP3$bE_0#HCQR"mwAz"N;
+PHR3FH_PC4IR;P
+NRE3P8#D_	RHb4N;
+PCR3Gs0CM_NDPHCsD_FoMCNlR0"#sHN0GF_H"N;
+PCR3Gs0CM_NDPDE8_lMNC#R"00sNHHG_F
+";LNRb8;HF
+RNH3bH#N48R;H
+NRM#$_H0s#00NC;R4
+sFRCkoF0N;
+H#R3HCl8VDNk0hR'z'pp;R
+FOLFlF;k0
+RNH3l#H8NCVkRD0'phzp
+';F8R8HCFso0Fk;H
+NRH3#lV8CN0kDRz'hp;p'
+8HRNH0NMN;
+H#R3HCl8VDNk0hR'z'pp;H
+NRJ3PlV8CN0kDRh't7
+';H8R8HNF80MNH;H
+NRH3#lV8CN0kDRz'hp;p'
+FHRCN;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'BeB'H;
+R0FkO;D	
+RNH3l#H8NCVkRD0'phzp
+';N3HRP8JlCkVND'0Rt'h7;R
+HFOk0DM	CNN;
+H#R3HCl8VDNk0eR'B;B'
+RNH3lPJ8NCVkRD0'BeB'H;
+ROFCDM	CNH;
+ROHMD
+	;N3HR#8HlCkVND'0Rhpzp'N;
+HPR3JCl8VDNk0tR'h;7'
+HHRM	ODC;MN
+RNH3l#H8NCVkRD0'BeB'N;
+HPR3JCl8VDNk0eR'B;B'
+NHRsCC#0N;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'7th'N;
+HlR3N_s	NM#$OC_s#RC04H;
+RC#s#;C0
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+RNH3slN	$_#MsO_C0#CR
+4;FVR8VN_80FN_k
+0;
+"VRMNFMl;C"RHyVDjCR
+"VR/0Fb/M#$bVDH$b/VoON_.gjjjDn/HPL/E#8/0P83E;8"RHyVD4CR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_	bN38PE"y;RVCHDRN.
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/8#04c4n38PE"y;RVCHDRNd
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/#kMHCoM8E3P8R";yDVHC
+RcNRVR3_H#PDE8R
+4;V/R"F/b0#b$MD$HV/oVbN._OjjjgnH/DLE/P8s/NH30EP"E8;VRyHRDC6V
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8R";yDVHC
+RnNRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOLsFN8s_8HsPC_0CM38PE"y;RVCHDRN(
+V3RRHP#_ER8D4V;
+RE"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/oON_FsM0FCD_MP03E;8"RHyVDUCR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsC3M0P"E8;VRyHRDCgV
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNs_NOE3P8R";yDVHCjR4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8R";yDVHC4R4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_MOF0DsF_ONs38PE"y;RVCHDR
+4.NRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCNs_sPO3E;8"RHyVD4CRdV
+NRHR3#E_P84DR;R
+MRaqp _)qqXu Rs#0NG0H__HFVuVR);Qv
+RNO30CGCNsMD8_CHMV_NRlC"s#0NG0H_"HF;O
+NR	3#HPb_E_8DkR#C4N;
+PHR3#Hbsl;R4
+RNP3bH#N48R;P
+NRE3b$H_#0"CRQzmAw
+";N3PRCCG0sDMN_sPCHoDF_lMNC#R"00sNHHG_F
+";N3PRCCG0sDMN_8PEDN_Ml"CR#N0s0_HGH;F"
+RNP3l#H8NCVkRD0'P8Cb,Fs8OCPD,sM8FCPC
+';N3PRHPF_HRCI4N;
+PPR3E_8D#b	HR
+4;LNRb8;HF
+RNH3bH#N48R;H
+NRM#$_H0s#00NC;R4
+sFRCkoF0N;
+H#R3HCl8VDNk0hR'z'pp;R
+FOLFlF;k0
+RNH3l#H8NCVkRD0'phzp
+';F8R8HCFso0Fk;H
+NRH3#lV8CN0kDRz'hp;p'
+8HRNH0NMN;
+H#R3HCl8VDNk0hR'z'pp;H
+NRJ3PlV8CN0kDRh't7
+';H8R8HNF80MNH;H
+NRH3#lV8CN0kDRz'hp;p'
+FHRCN;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'BeB'H;
+R0FkO;D	
+RNH3l#H8NCVkRD0'phzp
+';N3HRP8JlCkVND'0Rt'h7;H
+NRM#$_OH#D	FOR
+4;HkRF0	ODC;MN
+RNH3l#H8NCVkRD0'BeB'N;
+HPR3JCl8VDNk0eR'B;B'
+FHRC	ODC;MN
+HHRM	OD;H
+NRH3#lV8CN0kDRz'hp;p'
+RNH3lPJ8NCVkRD0'7th'N;
+H$R#M#_HOODF	;R4
+HHRM	ODC;MN
+RNH3l#H8NCVkRD0'BeB'N;
+HPR3JCl8VDNk0eR'B;B'
+NHRsCC#0N;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'7th'N;
+HlR3N_s	NM#$OC_s#RC04H;
+RC#s#;C0
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+RNH3slN	$_#MsO_C0#CR
+4;FVR8VN_80FN_k
+0;
+"VRMNFMl;C"RHyVDjCR
+"VR/0Fb/M#$bVDH$b/VoON_.gjjjDn/HPL/E#8/0P83E;8"RHyVD4CR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_	bN38PE"y;RVCHDRN.
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/8#04c4n38PE"y;RVCHDRNd
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/#kMHCoM8E3P8R";yDVHC
+RcNRVR3_H#PDE8R
+4;V/R"F/b0#b$MD$HV/oVbN._OjjjgnH/DLE/P8s/NH30EP"E8;VRyHRDC6V
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8R";yDVHC
+RnNRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOLsFN8s_8HsPC_0CM38PE"y;RVCHDRN(
+V3RRHP#_ER8D4V;
+RE"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/oON_FsM0FCD_MP03E;8"RHyVDUCR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsC3M0P"E8;VRyHRDCgV
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNs_NOE3P8R";yDVHCjR4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8R";yDVHC4R4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_MOF0DsF_ONs38PE"y;RVCHDR
+4.NRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCNs_sPO3E;8"RHyVD4CRdV
+NRHR3#E_P84DR;h
+eqRv 'sIF	o3PNs_8HsPC3ELCN;P'RPyRHRCIHj8R
+qehv' RI	Fs3NPo_H8sP3CsMDC0H'#0;RRyPIHCRRH84h
+eqRv 'sIF	o3PNC3LE'NP;RRyPIHCRRH8.h
+eqRv 'sIF	o3PNF_OMF0sDC3M0#DH0R';yHRPCHIR8
+Rdevhq IR'F3s	P_oNO0FMs3FDLNCEPR';yHRPCHIR8
+Rc@
+ 
+
+ftell;
+@ERMRI	FsRNPo_H8sPRCsMDC0H;#0
+RNP3_H##sFkO4CR;P
+NRH3DMFCMR;n(
+RNP3PH#ER8D4N;
+PHR3#E_P84DR;P
+NRs3FHNohl"CRP_oN8PsHC;s"
+RNP#_$Mb#sCCCsPR
+4;N3PRNNDlON_b0OE_F0kMR
+4;N3PRFosHPIHCMCNlRC'LE'NP;P
+NRN3E#l0HHRMo4N;
+PkR3HD_M_N#DOd	Rc6cn4F;
+RMDHCF_OkCM0sH_#o;_j
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FDCHM_kOFMs0C_o#H_
+4;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+DFRH_MCOMFk0_Cs#_Ho.N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FHRDMOC_F0kMC#s_Hdo_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+RMDHCF_OkCM0sH_#o;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FDCHM_kOFMs0C_o#H_
+6;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+DFRH_MCOMFk0_Cs#_HonN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FHRDMOC_F0kMC#s_H(o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+RMDHCF_OkCM0sH_#o;_U
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+H8_D$OMFk0_Cs4N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRM"H"H;
+R$8D_kOFMs0C_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";F#RP$_MO#00NC;_.
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$O0_#N_0C6N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RP$_MO#00NC;_d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$O0_#N_0CnN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RP$_MO#00NC;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$O0_#N_0C4N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RP$_MO#00NC;_j
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$O0_#N_0C.N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RE$_MO#00NC;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$O0_#N_0CjN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RE$_MO#00NC;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$O0_#N_0C4N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RE$_MO#00NC;_d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$O0_#N_0CnN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFRODMkl_kOFMs0C_o#H_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+OFRFlDkMF_OkCM0sH_#o;_4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FOkFDlOM_F0kMC#s_H.o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+RDOFk_lMOMFk0_Cs#_HodN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFRODMkl_kOFMs0C_o#H_
+c;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+OFRFlDkMF_OkCM0sH_#o;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FOkFDlOM_F0kMC#s_Hno_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+RDOFk_lMOMFk0_Cs#_Ho(N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFRODMkl_kOFMs0C_o#H_
+U;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+OFRFlDkMF_OkCM0sH_#o;_g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_U
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_(
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_n
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_.
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_j
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_U
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_(
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_n
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_.
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_j
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F8C_#0#_P$_MOOMFk0;Cs
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FP$_#M
+O;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+EFR_M#$ON;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F_RECLMND#C_H
+o;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+PFR_NCML_DC#;Ho
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+HsCC#0H_bM;_O
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRH;M"
+kFRM8n_DO$_F0kMCjs__
+G;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+8FR_0#C_$E#MOO_F0kMC
+s;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+OHRDb	_HOM_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;M
+oRgkM_$E#MOO_F0kMC0sDgN;
+MsR30MD_CM0_NRlC"NPo_H8sP_Csk0MH3gkM_$E#MOO_F0kMC0sDg
+";oOMRDb	_HOM_;M
+NRD3OFRO	"NPo|	OD_MbH"N;
+MOR3D	FO_oC8CsR"H"#C;M
+NR#3H_FODO4	R;M
+oRgkM_$P#MOO_F0kMC0sDgN;
+MsR30MD_CM0_NRlC"NPo_H8sP_Csk0MH3gkM_$P#MOO_F0kMC0sDg
+";okMRM8n_DO$_F0kMCjs__
+G;N3MRs_0DM_C0MCNlR "7p_qY)  1aC_MG30\k_Mn8_D$OMFk0_Csj"_G;M
+oR$P#M#O_0CN0_GMC0__.#kJlG
+N;N3MRs_0DM_C0MCNlRo"PNs_8HsPC_HkM0#3P$_MO#00NCC_MG.0__l#Jk"GN;M
+oRCP_MDNLCH_#o__4j__jjj_o_FH_cN;
+MsR30MD_CM0_NRlC"NPo_H8sP_Csk0MH3CP_MDNLCH_#o__4j__jjj_o_FH_c
+";oEMR_NCML_DC#_Ho4__jj__joHj__;Fc
+RNM3Ds0_0MC_lMNCPR"o8N_sCHPsM_kHE03_NCML_DC#_Ho4__jj__joHj__"Fc;M
+oR$E#M#O_0CN0_jd__jj__j_o_
+j;N3MRs_0DM_C0MCNlRo"PNs_8HsPC_HkM0#3E$_MO#00NC__dj__jjo__j"_j;R
+s@d@4:U46:4c:66U::$E#MOO_F0kMCgsr:Rj9fcc4Ud(:Ugg.UpRqaq )_ quXMRO0g.c66j_6_66qqqqRHbsl#RE$_MOOMFk0rCsjS9
+sFCokE0=#O$M_kOFMs0C_fjRmn4(j6:d6j(dRO
+SF=k0EM#$OF_OkCM0sF_Okj0r9mRf4jU.jg:djU.dRO
+SDO	=Db	_HOM_
+NS80=NNEM#$OF_OkCM0sR_jf4Q4(:njd(Udg
+URS08NNEO=#O$M_kOFMs0C_GMC0__4#kJlGfNRQj.g6dj:g4(4USR
+#sOD!_=t.R_Hf4Qcc:U(d.Ugg
+URSF#DN=8!k_MgEM#$OF_OkCM0sgD0R.fQnndc:UdUjR(U;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;4
+ARj4,y?5jV2:0RA;
+.,R4j5y!j:?V0;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MRgN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"6"NN;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$E#MOO_F0kMC4sr9s
+SCkoF0#=E$_MOOMFk0_Cs4mRf4j(n:gd66R6(
+FSOkE0=#O$M_kOFMs0C_kOF09r4R4fmUjc(:jdg6RjU
+DSO	D=O	H_bM
+_OS08NNEN=#O$M_kOFMs0C_f4RQ(44ndj:UncjUSR
+8NN0O#=E$_MOOMFk0_CsM0CG_#4_JGlkNQRf.6gjjg:d(U44R#
+SO!Ds=.t__fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MEg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$E#MOO_F0kMCOs_Frk0jf9RQ.4Ujdj:gdj.U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;6U
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgEM#$OF_OkCM0sgD0"s;
+R4@@d6:4U::c4:6U6#:E$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHElR#O$M_kOFMs0Cr
+.9SosCF=k0EM#$OF_OkCM0sR_.f(m4ndj:6d6U(SR
+O0Fk=$E#MOO_F0kMCOs_Frk0.f9Rm(4Ucdj:g(j(USR
+O=D	O_D	b_HMO8
+SNN0N=$E#MOO_F0kMC.s_R4fQ4j(n:cdUdRdU
+NS80=NOEM#$OF_OkCM0sC_MG40__l#JkRGNfgQ.j:6jd4g(4
+URSD#Ost!=_H._RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$E#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHEM=#O$M_kOFMs0C_kOF09r4R4fQUjc(:jdg6RjU;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MR(N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$E#MOO_F0kMCdsr9s
+SCkoF0#=E$_MOOMFk0_CsdmRf4j(n:(d64Rj(
+FSOkE0=#O$M_kOFMs0C_kOF09rdR4fmgjj4:4dgjRcU
+DSO	D=O	H_bM
+_OS08NNEN=#O$M_kOFMs0C_fdRQ(44ndj:UjcnUSR
+8NN0O#=E$_MOOMFk0_CsM0CG_#4_JGlkNQRf.6gjjg:d(U44R#
+SO!Ds=.t__fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MEg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$E#MOO_F0kMCOs_Frk0.f9RQ(4Ucdj:g(j(U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;6n
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgEM#$OF_OkCM0sgD0"s;
+R4@@d6:4U::c4:6U6#:E$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHElR#O$M_kOFMs0Cr
+c9SosCF=k0EM#$OF_OkCM0sR_cf(m4ndj:6j(.USR
+O0Fk=$E#MOO_F0kMCOs_Frk0cf9Rm.4gUdj:g44dUSR
+O=D	O_D	b_HMO8
+SNN0N=$E#MOO_F0kMCcs_R4fQ4j(n:cdUUR(U
+NS80=NOEM#$OF_OkCM0sC_MG40__l#JkRGNfgQ.j:6jd4g(4
+URSD#Ost!=_H._RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$E#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHEM=#O$M_kOFMs0C_kOF09rdR4fQgjj4:4dgjRcU;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MR6N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$E#MOO_F0kMC6sr9s
+SCkoF0#=E$_MOOMFk0_Cs6mRf4j(n:nd66R(U
+FSOkE0=#O$M_kOFMs0C_kOF09r6R4fmgj66:4dg6RUU
+DSO	D=O	H_bM
+_OS08NNEN=#O$M_kOFMs0C_f6RQ(44ndj:Uc64USR
+8NN0O#=E$_MOOMFk0_CsM0CG_#4_JGlkNQRf.6gjjg:d(U44R#
+SO!Ds=.t__fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MEg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$E#MOO_F0kMCOs_Frk0cf9RQ.4gUdj:g44dU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;6c
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgEM#$OF_OkCM0sgD0"s;
+R4@@d6:4U::c4:6U6#:E$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHElR#O$M_kOFMs0Cr
+n9SosCF=k0EM#$OF_OkCM0sR_nf(m4ndj:6n(.USR
+O0Fk=$E#MOO_F0kMCOs_Frk0nf9RmU4g.dj:g64UUSR
+O=D	O_D	b_HMO8
+SNN0N=$E#MOO_F0kMCns_R4fQ4j(n:6dUcR4U
+NS80=NOEM#$OF_OkCM0sC_MG40__l#JkRGNfgQ.j:6jd4g(4
+URSD#Ost!=_H._RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$E#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHEM=#O$M_kOFMs0C_kOF09r6R4fQgj66:4dg6RUU;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MRdN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$E#MOO_F0kMC(sr9s
+SCkoF0#=E$_MOOMFk0_Cs(mRf4j(n:(d6jRjj
+FSOkE0=#O$M_kOFMs0C_kOF09r(R.fmjjjg:.dg4R.U
+DSO	D=O	H_bM
+_OS08NNEN=#O$M_kOFMs0C_f(RQ(44ndj:UU6nUSR
+8NN0O#=E$_MOOMFk0_CsM0CG_#4_JGlkNQRf.6gjjg:d(U44R#
+SO!Ds=.t__fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MEg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$E#MOO_F0kMCOs_Frk0nf9RQU4g.dj:g64UU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;6.
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgEM#$OF_OkCM0sgD0"s;
+R4@@d6:4U::c4:6U6#:E$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHElR#O$M_kOFMs0Cr
+U9SosCF=k0EM#$OF_OkCM0sR_Uf(m4ndj:6cc(USR
+O0Fk=$E#MOO_F0kMCOs_Frk0Uf9Rmd.jndj:gg.dUSR
+O=D	O_D	b_HMO8
+SNN0N=$E#MOO_F0kMCUs_R4fQ4j(n:6dUgR6U
+NS80=NOEM#$OF_OkCM0sC_MG40__l#JkRGNfgQ.j:6jd4g(4
+URSD#Ost!=_H._RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$E#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHEM=#O$M_kOFMs0C_kOF09r(R.fQjjjg:.dg4R.U;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MR4N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.d6gUq_66bqRsRHlEM#$OF_OkCM0s9rg
+CSso0Fk=$E#MOO_F0kMCgs_R4fm(:njdj6n4
+URS	OD=	OD_MbH_SO
+8NN0N#=E$_MOOMFk0_CsgQRf4n4(jg:d(U44R8
+SNO0N=$E#MOO_F0kMCMs_C_G04J_#lNkGR.fQgjj6:(dg4R4U
+OS#D=s!t__.HQRfcU4c(U:dgU.gR#
+SD8FN!M=kg#_E$_MOOMFk0DCs0fgRQd.ncdn:U(UjUSR
+O=HMEM#$OF_OkCM0sF_OkU0r9QRf.njdjg:d.UdgRo;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MRjN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"6N;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d.:n(cn:.(::6PM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.6cgjn_nnUn_URUUblsHR$P#MOO_F0kMCjsr9s
+SCkoF0#=P$_MOOMFk0_CsjmRf4j(n:nd6jRjU
+FSOkP0=#O$M_kOFMs0C_kOF09rjR.fm(c6d:jdg.RdU
+DSO	D=O	H_bM
+_OS08NNPN=#O$M_kOFMs0C_fjRQ(44ndj:Ugd(USR
+8NN0L_=8#_C0EM#$OF_OkCM0sQRf.g4jcU:ddU(gR8
+SNO0N=$P#MOO_F0kMCMs_C_G04J_#lNkGR.fQUg.d:(dg4R4U
+OS#D=s!tn_4_fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MPg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(;UR
+RobsFCok
+0;oObRF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o#bRO;Ds
+Rob#NDF8A;
+4,R444y5?5j*j:?V0!2:fRj2;.
+ARj4,y4!5??5jV2:0:R02;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCPR"#O$M_kOFMs0C"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRN_MbOMFk0_CsV4VR;H
+NRD3N#O0_ERHMc
+g;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRnUnU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3M#$OC_s#RC0"PM:o8N_sCHPsM_kHk03MPg_#O$M_kOFMs0CD"0g;R
+s@d@4:(.n:.c:n6(::$P#MOO_F0kMCgsr:Rj9fcc4Ud(:Ugg.UpRqaq )_ quXMRO0g.6c6._q_6qqjjqRHbsl#RP$_MOOMFk0rCs4S9
+sFCokP0=#O$M_kOFMs0C_f4Rmn4(j6:dcc4cRO
+SF=k0PM#$OF_OkCM0sF_Ok40r9mRf.j(Ucg:djU6jRO
+SDO	=Db	_HOM_
+NS80=NNPM#$OF_OkCM0sR_4f4Q4(:njdjUcn
+URS08NNPO=#O$M_kOFMs0C_GMC0__4#kJlGfNRQ..Uddg:g4(4USR
+#sOD!_=t4Hn_RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$P#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHPM=#O$M_kOFMs0C_kOF09rjR.fQ(c6d:jdg.RdU;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OHcMRUN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_P$_MOOMFk0DCs0;g"
+@sR@:4d.:n(cn:.(::6PM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$P#MOO_F0kMC.sr9s
+SCkoF0#=P$_MOOMFk0_Cs.mRf4j(n:6d6cRjc
+FSOkP0=#O$M_kOFMs0C_kOF09r.R.fmUcj(:jdg(R(U
+DSO	D=O	H_bM
+_OS08NNPN=#O$M_kOFMs0C_f.RQ(44ndj:UdcdUSR
+8NN0O#=P$_MOOMFk0_CsM0CG_#4_JGlkNQRf.dU.gg:d(U44R#
+SO!Ds=4t_nR_Hf4Qcc:U(d.Ugg
+URSF#DN=8!k_MgPM#$OF_OkCM0sgD0R.fQnndc:UdUjR(U
+HSOM#=P$_MOOMFk0_CsO0FkrR49f(Q.U:jcd6gjj;UR
+RobsFCok
+0;oObRF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNO0N;b
+oRD#Oso;
+bDR#F;N8
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?j:?V002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#MOO_F0kMC;s"
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3NbF_OkCM0sV_VR
+4;N3HRN0D#_HOEM(Rc;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRN"6N;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+H#R3$_MOsCC#0MR":NPo_H8sP_Csk0MH3gkM_$P#MOO_F0kMC0sDg
+";s@R@4.d:nc(::(.n:P6:#O$M_kOFMs0Crjg:9cRf4(cU:gdU.RgUq pa)qq_uR XO.M06.gc_66qqj_qqbjRsRHlPM#$OF_OkCM0s9rd
+CSso0Fk=$P#MOO_F0kMCds_R4fm(:njdn64U
+cRSkOF0#=P$_MOOMFk0_CsO0FkrRd9fUm.d:ccdjg4c
+URS	OD=	OD_MbH_SO
+8NN0N#=P$_MOOMFk0_CsdQRf4n4(jU:dcUnjR8
+SNO0N=$P#MOO_F0kMCMs_C_G04J_#lNkGR.fQUg.d:(dg4R4U
+OS#D=s!tn_4_fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MPg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$P#MOO_F0kMCOs_Frk0.f9RQj.U(dc:g(j(U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$OF_OkCM0s
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;cn
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgPM#$OF_OkCM0sgD0"s;
+R4@@dn:.(::c.:n(6#:P$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHPlR#O$M_kOFMs0Cr
+c9SosCF=k0PM#$OF_OkCM0sR_cf(m4ndj:66.gcSR
+O0Fk=$P#MOO_F0kMCOs_Frk0cf9Rmn.U4dc:g44dUSR
+O=D	O_D	b_HMO8
+SNN0N=$P#MOO_F0kMCcs_R4fQ4j(n:cdUUR(U
+NS80=NOPM#$OF_OkCM0sC_MG40__l#JkRGNfUQ..:dgd4g(4
+URSD#Ost!=__4nHQRfcU4c(U:dgU.gR#
+SD8FN!M=kg#_P$_MOOMFk0DCs0fgRQd.ncdn:U(UjUSR
+O=HMPM#$OF_OkCM0sF_Okd0r9QRf.cUdcg:d4UjcRo;
+bCRso0Fk;b
+oRkOF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+O;o#bRO;Ds
+Rob#NDF8o;
+bHROMA;
+4,R44.y5?5j*j:?V0!2:fRj2;.
+ARj4,y.!5??5jV2:0:R02;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCPR"#O$M_kOFMs0C"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRN_MbOMFk0_CsV4VR;H
+NRD3N#O0_ERHMc
+6;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNN"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3M#$OC_s#RC0"PM:o8N_sCHPsM_kHk03MPg_#O$M_kOFMs0CD"0g;R
+s@d@4:(.n:.c:n6(::$P#MOO_F0kMCgsr:Rj9fcc4Ud(:Ugg.UpRqaq )_ quXMRO0g.6c6._q_6qqjjqRHbsl#RP$_MOOMFk0rCs6S9
+sFCokP0=#O$M_kOFMs0C_f6Rmn4(j6:d.cU(RO
+SF=k0PM#$OF_OkCM0sF_Ok60r9mRf.UUUcg:d4U6URO
+SDO	=Db	_HOM_
+NS80=NNPM#$OF_OkCM0sR_6f4Q4(:njd4U6c
+URS08NNPO=#O$M_kOFMs0C_GMC0__4#kJlGfNRQ..Uddg:g4(4USR
+#sOD!_=t4Hn_RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$P#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHPM=#O$M_kOFMs0C_kOF09rcR.fQUcn4:4dgdR4U;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OHcMRcN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_P$_MOOMFk0DCs0;g"
+@sR@:4d.:n(cn:.(::6PM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$P#MOO_F0kMCnsr9s
+SCkoF0#=P$_MOOMFk0_CsnmRf4j(n:jd64R4n
+FSOkP0=#O$M_kOFMs0C_kOF09rnR.fmgc46:4dgUR6U
+DSO	D=O	H_bM
+_OS08NNPN=#O$M_kOFMs0C_fnRQ(44ndj:U46cUSR
+8NN0O#=P$_MOOMFk0_CsM0CG_#4_JGlkNQRf.dU.gg:d(U44R#
+SO!Ds=4t_nR_Hf4Qcc:U(d.Ugg
+URSF#DN=8!k_MgPM#$OF_OkCM0sgD0R.fQnndc:UdUjR(U
+HSOM#=P$_MOOMFk0_CsO0FkrR69fUQ.U:Ucd6g4U;UR
+RobsFCok
+0;oObRF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNO0N;b
+oRD#Oso;
+bDR#F;N8
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?j:?V002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#MOO_F0kMC;s"
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3NbF_OkCM0sV_VR
+4;N3HRN0D#_HOEMdRc;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRN"6N;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+H#R3$_MOsCC#0MR":NPo_H8sP_Csk0MH3gkM_$P#MOO_F0kMC0sDg
+";s@R@4.d:nc(::(.n:P6:#O$M_kOFMs0Crjg:9cRf4(cU:gdU.RgUq pa)qq_uR XO.M06.gc_66qqj_qqbjRsRHlPM#$OF_OkCM0s9r(
+CSso0Fk=$P#MOO_F0kMC(s_R4fm(:njdc6j4
+cRSkOF0#=P$_MOOMFk0_CsO0FkrR(9fgm.c:.cd4g..
+URS	OD=	OD_MbH_SO
+8NN0N#=P$_MOOMFk0_Cs(QRf4n4(jU:d6UnUR8
+SNO0N=$P#MOO_F0kMCMs_C_G04J_#lNkGR.fQUg.d:(dg4R4U
+OS#D=s!tn_4_fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MPg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$P#MOO_F0kMCOs_Frk0nf9RQ4.g6dc:g64UU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$OF_OkCM0s
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;c.
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgPM#$OF_OkCM0sgD0"s;
+R4@@dn:.(::c.:n(6#:P$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHPlR#O$M_kOFMs0Cr
+U9SosCF=k0PM#$OF_OkCM0sR_Uf(m4ndj:6U4ncSR
+O0Fk=$P#MOO_F0kMCOs_Frk0Uf9Rmn.ggdc:gg.dUSR
+O=D	O_D	b_HMO8
+SNN0N=$P#MOO_F0kMCUs_R4fQ4j(n:6dUgR6U
+NS80=NOPM#$OF_OkCM0sC_MG40__l#JkRGNfUQ..:dgd4g(4
+URSD#Ost!=__4nHQRfcU4c(U:dgU.gR#
+SD8FN!M=kg#_P$_MOOMFk0DCs0fgRQd.ncdn:U(UjUSR
+O=HMPM#$OF_OkCM0sF_Ok(0r9QRf..gccg:d.U4.Ro;
+bCRso0Fk;b
+oRkOF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+O;o#bRO;Ds
+Rob#NDF8o;
+bHROMA;
+4,R44.y5?5j*j:?V0!2:fRj2;.
+ARj4,y.!5??5jV2:0:R02;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCPR"#O$M_kOFMs0C"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRN_MbOMFk0_CsV4VR;H
+NRD3N#O0_ERHMc
+4;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNN"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3M#$OC_s#RC0"PM:o8N_sCHPsM_kHk03MPg_#O$M_kOFMs0CD"0g;R
+s@d@4:(.n:.c:n6(::$P#MOO_F0kMCgsr:Rj9fcc4Ud(:Ugg.UpRqaq )_ quXMRO0g.6d6U_qR6qblsHR$P#MOO_F0kMCgsr9s
+SCkoF0#=P$_MOOMFk0_CsgmRf4j(n:dd6URdn
+DSO	D=O	H_bM
+_OS08NNPN=#O$M_kOFMs0C_fgRQ(44ndj:g4(4USR
+8NN0O#=P$_MOOMFk0_CsM0CG_#4_JGlkNQRf.dU.gg:d(U44R#
+SO!Ds=4t_nR_Hf4Qcc:U(d.Ugg
+URSF#DN=8!k_MgPM#$OF_OkCM0sgD0R.fQnndc:UdUjR(U
+HSOM#=P$_MOOMFk0_CsO0FkrRU9fgQ.n:gcddg.g;UR
+RobsFCok
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$OF_OkCM0s
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;cj
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"66NN
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgPM#$OF_OkCM0sgD0"s;
+R4@@d(:g:gc:(::6OkFDlOM_F0kMC#s_Hgor:Rj9f(d.jdj:g4(4UpRqaq )_ quXVRVUUcg_AAAAsRbHOlRFlDkMF_OkCM0sH_#o9rg
+CSso0Fk=DOFk_lMOMFk0_Cs#_HogmRf4j(n:jd(6Rd4
+DSO	D=O	H_bM
+_OS08NNkN=MO._FlDkMF_OkCM0sC_MGO0_FFlLkg0r9QRf.g(c.g:d(U44R8
+SNL0N=4kMjF_ODMkl_kOFMs0C_o#HDg0FRdfQ.j(j:(dg4R4U
+OS#D=s!OkFDlOM_F0kMCMs_C_G0jJ_#lNkG_44_R4fQg6d6:gdU.RgU;b
+oRosCF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R4j5y!4j?5?0V:22:VRN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CROkFDlOM_F0kMC#s_H;o"
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMCgGR;H
+NRO3#DVs_V;R4
+RNH3#ND0E_OHdMR(N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blLR"L"LL;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";s@R@4gd:(::cg6(::DOFk_lMOMFk0_Cs#rHog9:jR.fd(:jjd4g(4qURp)a qu_q VXRVjd(_UUjjsRbHOlRFlDkMF_OkCM0sH_#o9rU
+CSso0Fk=DOFk_lMOMFk0_Cs#_HoUmRf4j(n:UdnjR(4
+DSO	D=O	H_bM
+_OS08NNkN=MO._FlDkMF_OkCM0sC_MGO0_FFlLkU0r9QRf.g(c.g:d(U44R8
+SNL0N=4kMjF_ODMkl_kOFMs0C_o#HDg0FRdfQ.j(j:(dg4R4U
+NS80=NOOkFDlOM_F0kMCMs_C_G0jJ_#lNkG_44_R4fQg6d6:(dg4R4U;b
+oRosCF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;A44R,!jy55.?4j?5?0V:22:0:R02;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCOR"FlDkMF_OkCM0sH_#o
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;RU
+RNH3#ND0E_OHdMRnN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blUR"j"Uj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9Rdj.(jg:d(U44Raqp _)qqXu RdVV(Uj_jRUjblsHRDOFk_lMOMFk0_Cs#rHo(S9
+sFCokO0=FlDkMF_OkCM0sH_#oR_(f(m4ndj:(g.4nSR
+O=D	O_D	b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrR(9f(Q..:..d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+8NN0OF=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:g4(4U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;4
+ARj4,y.!5??545Vj?::02002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG(N;
+HNR3D_#0OMEHR;d6
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UUjj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";s@R@4gd:(::cg6(::DOFk_lMOMFk0_Cs#rHog9:jR.fd(:jjd4g(4qURp)a qu_q VXRVgUcUA_AAbARsRHlOkFDlOM_F0kMC#s_Hnor9s
+SCkoF0F=ODMkl_kOFMs0C_o#H_fnRmn4(j(:dj4njRO
+SDO	=Db	_HOM_
+NS80=NNk_M.OkFDlOM_F0kMCMs_C_G0OLFlFrk0nf9RQ..(.d.:g4(4USR
+8NN0LM=k4Oj_FlDkMF_OkCM0sH_#oFD0gQRfdj.(jg:d(U44R#
+SO!Ds=DOFk_lMOMFk0_CsM0CG_#j_JGlkN__44QRf46gd6U:dgU.gRo;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;A44R,!jy554?j:?V0V2:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGnN;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHMd
+c;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRLLLL"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+@sR@:4dgc(:::g(6F:ODMkl_kOFMs0C_o#Hrjg:9dRf.j(j:(dg4R4Uq pa)qq_uR XVcVUgAU_ARAAblsHRDOFk_lMOMFk0_Cs#rHo6S9
+sFCokO0=FlDkMF_OkCM0sH_#oR_6f(m4ndj:ndgd4SR
+O=D	O_D	b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrR69fnQ.g:6.d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?545Vj?::02V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+6;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;dd
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9R4j(n:cdn(Rjgq pa)qq_uR XVcVUgAU_ARAAblsHRDOFk_lMOMFk0_Cs#rHocS9
+sFCokO0=FlDkMF_OkCM0sH_#oR_cf(m4ndj:njc(gSR
+O=D	O_D	b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrRc9fnQ.g:6.d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?545Vj?::02V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+c;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;d.
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9R4j(n:ddncRdgq pa)qq_uR XVcVUgAU_ARAAblsHRDOFk_lMOMFk0_Cs#rHodS9
+sFCokO0=FlDkMF_OkCM0sH_#oR_df(m4ndj:nddcgSR
+O=D	O_D	b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrRd9fnQ.n:U.d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?545Vj?::02V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+d;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;d4
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9R4j(n:6dnURggq pa)qq_uR XVcVUgAU_ARAAblsHRDOFk_lMOMFk0_Cs#rHo.S9
+sFCokO0=FlDkMF_OkCM0sH_#oR_.f(m4ndj:ng6UgSR
+O=D	O_D	b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrR.9fnQ.n:U.d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?545Vj?::02V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+.;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;dj
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9Rdj.(jg:d(U44Raqp _)qqXu RUVVc_gUAAAARHbslFRODMkl_kOFMs0C_o#Hr
+49SosCF=k0OkFDlOM_F0kMC#s_H4o_R4fm(:njdjnU(
+4RS	OD=	OD_MbH_SO
+8NN0NM=k.F_ODMkl_kOFMs0C_GMC0F_OlkLF09r4R.fQj.44:(dg4R4U
+NS80=NLkjM4_DOFk_lMOMFk0_Cs#DHo0RFgf.Qd(:jjd4g(4
+URSD#OsO!=FlDkMF_OkCM0sC_MGj0__l#Jk_GN4R_4fgQ4d:66d.Ugg;UR
+RobsFCok
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;4
+ARj4,y4!5??5jV2:0:RV2;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCOR"FlDkMF_OkCM0sH_#o
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R4
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEMgR.;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRL"LL;L"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"s;
+R4@@d(:g:gc:(::6OkFDlOM_F0kMC#s_Hgor:Rj9f(d.jdj:g4(4UpRqaq )_ quXVRVUUcg_((((sRbHOlRFlDkMF_OkCM0sH_#o9rj
+CSso0Fk=DOFk_lMOMFk0_Cs#_HojmRf4j(n:UdnnRdU
+DSO	D=O	H_bM
+_OS08NNON=FlDkMF_OkCM0sH_#oR_jf4Q4(:njd4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j554?j:?V002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGjN;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM.
+U;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR(((("N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+@sR@:4d4:U(cU:4(::6EM#$O0_#Nr0Cj9:nR(f4ndj:n6.j.pRqaq )_ quXVRVd_UnwjwjRHbsl#RE$_MO#00NC9rn
+CSso0Fk=$E#M#O_0CN0_fnRmn4(jn:d..j6RO
+SDO	=Db	_HOM_
+NS80=N8k_Mn8_D$OMFk0_CsjR_GfnQdn:Ucd4g(4;UR
+RobsFCok
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN08A;
+4,R4j5y!d:?V0;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MO#00NC
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rj
+RNH3#ND0E_OH.MR(N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blVR"V"jj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4:jdj:dc:j6j::$P#M#O_0CN0rnj:9cRf6(.j:(dg4R4Uq pa)qq_uR XVgVcUB_jqb RsRHlPM#$O0_#Nr0CjS9
+sFCokP0=#O$M_N#00jC_R4fm(:njd((j(
+6RS	OD=	OD_MbH_SO
+8NN0N#=P$_MO#00NCR_jf4Q4(:njd4g(4
+URS08NNPL=#O$M_N#00dC___HPj__j__ojjd_N_fjRQjd.nd(:g4(4USR
+8NN0OM=knD_8$F_OkCM0s__jGQRfdUnncg:d(U44R8
+SN80N=$P#M#O_0CN0_GMC0__.#kJlGfNRQ.c6jd(:g4(4U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,54yd.?5?!V:5V4?:202:.!5?5j*j:?V052:4:?Vf2j22
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#M#O_0CN0"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+n;N3HRN0D#_HOEMnR.;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRO"jN;C"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+@sR@:4dd:jjcj:dj::6PM#$O0_#Nr0Cj9:nRnfdn:Ucd4g(4qURp)a qu_q VXRVUcg_UjjjsRbHPlR#O$M_N#004Cr9s
+SCkoF0#=P$_MO#00NCR_4f(m4ndj:(.cdcSR
+O=D	O_D	b_HMO8
+SNN0N=$P#M#O_0CN0_fcRQ(44ndj:g4(4USR
+8NN0LM=k4P._#O$M_kOFMs0C_f(RQc.j6dc:g4(4USR
+8NN0OM=k4Pd_#O$M_kOFMs0C_fcRQ4.n(d6:g4(4USR
+8NN08M=knD_8$F_OkCM0s__jGQRfdUnncg:d(U44Ro;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4jdy5?!V:55.?4j?5?0V:22:0:202RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$O0_#N"0C;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG6N;
+HNR3D_#0OMEHR;.6
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"Ujjj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";s@R@4dd:jcj::jdj:P6:#O$M_N#00jCr:Rn9fj46Udj:6dg(4pRqaq )_ quXVRVd_(4(ww(RHbsl#RP$_MO#00NC9rn
+FSOlkLF0M=knD_8$F_OkCM0s__jGmRf4U6jj6:dg4(dRs
+SCkoF0#=P$_MO#00NCR_nf(m4ndj:(djngSR
+O=D	O_D	b_HMO8
+SNN0N=#sCCb0_HOM_
+NS80=NL8_D$OMFk0_CsjQRf4n4(j6:dn4c4R8
+SNO0N=$8D_kOFMs0C_f4RQ(44ndj:6j(n4
+R;oObRFFlLk
+0;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNL0N;b
+oR08NN
+O;A44R,5jy.4?5??5jV2:0::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MO#00NC
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rj
+RNH3#ND0E_OH.MRcN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl(R"V"(V;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4:64.:4c:.66::MDHCF_OkCM0sH_#o:rUjf9Rd.nUng:d(U44Raqp _)qqXu RUVVc_gU7777RHbslHRDMOC_F0kMC#s_HUor9s
+SCkoF0H=DMOC_F0kMC#s_HUo_R4fm(:njd((4g
+4RS	OD=	OD_MbH_SO
+8NN0NM=k4Dj_H_MCOMFk0_Cs#DHo0RFUf.Qd.:d.d4g(4
+URS08NNkL=MD4_H_MCOMFk0_Cs#_HoOLFlFrk0gf9RQUdn.dn:g4(4USR
+#sOD!H=DMOC_F0kMCMs_C_G0jJ_#lNkG_44_R4fQgc4U:gdU.RgU;b
+oRosCF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R4j5y!4:?V!?5jV2:02
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0sH_#o
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;RU
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEMdR.;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboR8"88;8"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"s;
+R4@@d.:46::c4:.66H:DMOC_F0kMC#s_HUor:Rj9fUdn.dn:g4(4UpRqaq )_ quXVRVUUcg_7777sRbHDlRH_MCOMFk0_Cs#rHo(S9
+sFCokD0=H_MCOMFk0_Cs#_Ho(mRf4j(n:(d(4RUj
+DSO	D=O	H_bM
+_OS08NNkN=M_4jDCHM_kOFMs0C_o#HDU0FRdfQ...d:(dg4R4U
+NS80=NLk_M4DCHM_kOFMs0C_o#H_lOFL0FkrRU9fnQdU:.nd4g(4
+URSD#OsD!=H_MCOMFk0_CsM0CG_#j_JGlkN__44QRf4Ug4cU:dgU.gRo;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;A44R,!jy5V4?:j!5?0V:2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRH"DMOC_F0kMC#s_H;o"
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC(GR;H
+NRO3#DVs_V;R4
+RNH3#ND0E_OH.MR.N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl8R"8"88;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";s@R@44d:.c6::64.:D6:H_MCOMFk0_Cs#rHoU9:jRnfd6:6nd4g(4qURp)a qu_q VXRVgUcU7_77b7RsRHlDCHM_kOFMs0C_o#Hr
+n9SosCF=k0DCHM_kOFMs0C_o#H_fnRmn4(j(:d.n4gRO
+SDO	=Db	_HOM_
+NS80=NNkjM4_MDHCF_OkCM0sH_#oFD0UQRfdd...g:d(U44R8
+SNL0N=4kM_MDHCF_OkCM0sH_#oF_OlkLF09r(RdfQnn66:(dg4R4U
+OS#D=s!DCHM_kOFMs0C_GMC0__j#kJlG4N__f4RQ44gUdc:Ugg.U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?54V5:!j:?V0R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCDR"H_MCOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGnN;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM.
+4;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR8888"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+@sR@:4d4:.6c.:46::6DCHM_kOFMs0C_o#HrjU:9dRfnn66:(dg4R4Uq pa)qq_uR XV(Vdjj_UUbjRsRHlDCHM_kOFMs0C_o#Hr
+69SosCF=k0DCHM_kOFMs0C_o#H_f6Rmn4(j(:d.n4gRO
+SDO	=Db	_HOM_
+NS80=NNkjM4_MDHCF_OkCM0sH_#oFD0UQRfdd...g:d(U44R8
+SNL0N=4kM_MDHCF_OkCM0sH_#oF_OlkLF09rnRdfQnn66:(dg4R4U
+NS80=NODCHM_kOFMs0C_GMC0__j#kJlG4N__f4RQ44gUdc:g4(4U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;4
+ARj4,y.!5??545Vj?::02002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0sH_#o
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R6
+RNH3#ND0E_OH.MRjN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blUR"j"Uj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4:64.:4c:.66::MDHCF_OkCM0sH_#o:rUjf9RdUn.ng:d(U44Raqp _)qqXu RUVVc_gU7777RHbslHRDMOC_F0kMC#s_Hcor9s
+SCkoF0H=DMOC_F0kMC#s_Hco_R4fm(:njdgn(4
+nRS	OD=	OD_MbH_SO
+8NN0NM=k4Dj_H_MCOMFk0_Cs#DHo0RFUf.Qd.:d.d4g(4
+URS08NNkL=MD4_H_MCOMFk0_Cs#_HoOLFlFrk06f9RQ.dnUdn:g4(4USR
+#sOD!H=DMOC_F0kMCMs_C_G0jJ_#lNkG_44_R4fQgc4U:gdU.RgU;b
+oRosCF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R4j5y!4:?V!?5jV2:02
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0sH_#o
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rc
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEMgR4;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboR8"88;8"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"s;
+R4@@d.:46::c4:.66H:DMOC_F0kMC#s_HUor:Rj9f.dnUdn:g4(4UpRqaq )_ quXVRVUUcg_7777sRbHDlRH_MCOMFk0_Cs#rHodS9
+sFCokD0=H_MCOMFk0_Cs#_HodmRf4j(n:ndnnRcn
+DSO	D=O	H_bM
+_OS08NNkN=M_4jDCHM_kOFMs0C_o#HDU0FRdfQ...d:(dg4R4U
+NS80=NLk_M4DCHM_kOFMs0C_o#H_lOFL0FkrRc9fnQd.:Und4g(4
+URSD#OsD!=H_MCOMFk0_CsM0CG_#j_JGlkN__44QRf4Ug4cU:dgU.gRo;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;A44R,!jy5V4?:j!5?0V:2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRH"DMOC_F0kMC#s_H;o"
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMCdGR;H
+NRO3#DVs_V;R4
+RNH3#ND0E_OH4MRUN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl8R"8"88;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";s@R@44d:.c6::64.:D6:H_MCOMFk0_Cs#rHoU9:jRnfdj:4nd4g(4qURp)a qu_q VXRVgUcU7_77b7RsRHlDCHM_kOFMs0C_o#Hr
+.9SosCF=k0DCHM_kOFMs0C_o#H_f.Rmn4(jn:dg4dcRO
+SDO	=Db	_HOM_
+NS80=NNkjM4_MDHCF_OkCM0sH_#oFD0UQRfdd...g:d(U44R8
+SNL0N=4kM_MDHCF_OkCM0sH_#oF_OlkLF09rdRdfQnnj4:(dg4R4U
+OS#D=s!DCHM_kOFMs0C_GMC0__j#kJlG4N__f4RQ44gUdc:Ugg.U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?54V5:!j:?V0R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCDR"H_MCOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG.N;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM4
+(;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR8888"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+@sR@:4d4:.6c.:46::6DCHM_kOFMs0C_o#HrjU:9dRfnnj4:(dg4R4Uq pa)qq_uR XVcVUg7U_7R77blsHRMDHCF_OkCM0sH_#o9r4
+CSso0Fk=MDHCF_OkCM0sH_#oR_4f(m4ndj:ndgd4SR
+O=D	O_D	b_HMO8
+SNN0N=4kMjH_DMOC_F0kMC#s_H0oDFfURQ.d.dd.:g4(4USR
+8NN0LM=k4H_DMOC_F0kMC#s_HOo_FFlLk.0r9QRfd4njng:d(U44R#
+SO!Ds=MDHCF_OkCM0sC_MGj0__l#Jk_GN4R_4fgQ44:Ucd.Ugg;UR
+RobsFCok
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;4
+ARj4,y4!5?!V:5Vj?:202RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRDCHM_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+4;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;4n
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"8888
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4:64.:4c:.66::MDHCF_OkCM0sH_#o:rUjf9Rdd...g:d(U44Raqp _)qqXu RUVVc_gUAAAARHbslHRDMOC_F0kMC#s_Hjor9s
+SCkoF0H=DMOC_F0kMC#s_Hjo_R4fm(:njd4ngj
+nRS	OD=	OD_MbH_SO
+8NN0NM=k4H_DMOC_F0kMC#s_HOo_FFlLk40r9QRf.cgcng:d(U44R8
+SNL0N=4kMjH_DMOC_F0kMC#s_H0oDFfURQ.d.dd.:g4(4USR
+#sOD!H=DMOC_F0kMCMs_C_G0jJ_#lNkG_44_R4fQgc4U:gdU.RgU;b
+oRosCF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R4j5y!4j?5?0V:22:VRN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRDCHM_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+j;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;46
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4:(4U:4c:U6(::CP_MDNLCH_#ocRf.n6(:gdUUR6Uq pa)qq_uR XVjVg4 j_ R  blsHRCP_MDNLCH_#os
+SCkoF0_=PCLMND#C_HfoRmn4(jU:d(U44RO
+SDO	=Db	_HOM_
+NS80=NNEM#$O0_#N_0CdQRf4n4(jg:d(U44R8
+SNL0N=$E#M#O_0CN0_f4RQ(44ndj:g4(4USR
+#sOD=nkM_$8D_kOFMs0C_Gj_RdfQncnU:gdU.RgU
+MSCN_=PCLMND#C_H4o__jj__oj_j__HFfcRQ6c.(dn:U6gUU
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobC;MN
+RA44y,j!?54Vj:5?0V:2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR_"PCLMND#C_H;o"
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRO3#DVs_V;R4
+RNH3#ND0E_OH4MRcN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDC4N;
+HDR3ko0blCR"C"CC;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HROODF	M_CNCLDR:"MP_oN8PsHCks_M3H0PM_CNCLD_o#H_j4__jj___ojHc_F"s;
+R4@@dj:dj::cd:jj6_:ECLMND#C_HfoRc(.6nU:dgUU6Raqp _)qqXu RgVVj_4j    RHbsl_RECLMND#C_HSo
+sFCokE0=_NCML_DC#RHof(m4ndj:ncgd4SR
+O=D	O_D	b_HMO8
+SNN0N=$P#M#O_0CN0_fdRQ(44ndj:g4(4USR
+8NN0L#=P$_MO#00NCR_4f4Q4(:njd4g(4
+URSD#OsM=knD_8$F_OkCM0s__jGQRfdUnncU:dgU.gRC
+SMEN=_NCML_DC#_Ho4__jj__joHj__RFcf.Qc6:(ndUUg6;UR
+RobsFCok
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRNCM;4
+ARj4,y4!5?5V:j:?V0R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCER"_NCML_DC#"Ho;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM4
+d;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRCCCC"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3FODOC	_MDNLCMR":NPo_H8sP_Csk0MH3CE_MDNLCH_#o__4j__jjj_o_FH_c
+";s@R@44d:Uc(::(4U:E6:_M#$O.Rfcc(c:(dg4R4Uq pa)qq_uR XVgVcUw_w(bwRsRHlE$_#MSO
+sFCokE0=_M#$OmRf4j(n:jdUjRdn
+DSO	D=O	H_bM
+_OS08NNsN=C0#C_MbH_SO
+8NN0LD=8$F_OkCM0sR_jf4Q4(:njd4g(4
+URS08NN8O=DO$_F0kMC4s_R4fQ4j(n:(dg4R4U
+NS80=N8E$_#M4O__jj__oj_4QRf.cc(cg:d(U44Ro;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j!?5dV5:!.4?5??5jV2:0::020R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCER"_M#$O
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3#ND0E_OH4MR.N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blVR"V"(V;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;R
+s@d@4:jdj:dc:j6j::#P_$RMOf(.ccdc:g4(4UpRqaq )_ quXVRVc_gUwww(RHbsl_RP#O$M
+CSso0Fk=#P_$RMOf(m4ndj:UdjjnSR
+O=D	O_D	b_HMO8
+SNN0N=#sCCb0_HOM_
+NS80=NL8_D$OMFk0_CsjQRf4n4(jg:d(U44R8
+SNO0N=$8D_kOFMs0C_f4RQ(44ndj:g4(4USR
+8NN08_=P#O$M_j4__jj__Ro4fcQ.(:ccd4g(4;UR
+RobsFCok
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4j5y!d:?V!?5.554?j:?V002:22:02
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"#P_$"MO;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3D_#0OMEHR;44
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"(VVV
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";s@R@4dd:jcj::jdj:P6:#O$M_N#00jCr:Rn9f.c6jd(:U6gUUpRqaq )_ quXVRVgjj4_    sRbHPlR#O$M_N#006Cr9s
+SCkoF0#=P$_MO#00NCR_6f(m4ndj:n4n(dSR
+O=D	O_D	b_HMO8
+SNN0N=$P#M#O_0CN0_fnRQ(44ndj:g4(4USR
+8NN0L#=P$_MO#00NCR_jf4Q4(:njd4g(4
+URSD#OsM=knD_8$F_OkCM0s__jGQRfdUnncU:dgU.gRC
+SMPN=#O$M_N#00MC_C_G0.J_#lNkGRcfQ6(.j:gdUUR6U;b
+oRosCF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bMRCNA;
+4,R4j5y!4:?V5Vj?:202RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$O0_#N"0C;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG4N;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM4
+j;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRCCCC"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3FODOC	_MDNLCMR":NPo_H8sP_Csk0MH3$P#M#O_0CN0_GMC0__.#kJlG;N"
+@sR@:4dd:jjcj:dj::6PM#$O0_#Nr0Cj9:nR6fc.:j(dUUg6qURp)a qu_q VXRVjg..j_.jbjRsRHlPM#$O0_#Nr0CcS9
+sFCokP0=#O$M_N#00cC_R4fm(:njdjn.(
+4RS	OD=	OD_MbH_SO
+8NN0N#=P$_MOOMFk0_CsjQRf4n4(jg:d(U44R8
+SNL0N=$P#MOO_F0kMCgs_R4fQ4j(n:(dg4R4U
+NS80=NOPM#$O0_#N_0C6QRf4n4(jg:d(U44R8
+SN80N=4kMc#_P$_MOOMFk0_CsUQRf.4gdgg:d(U44R#
+SO=Dsk_Mn8_D$OMFk0_CsjR_GfnQdn:Ucd.Ugg
+URSNCM=$P#M#O_0CN0_GMC0__.#kJlGfNRQ.c6jd(:U6gUU
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;o#bRO;Ds
+RobC;MN
+RA44y,j55d?.4?5?!V:5Vj?:202::V2V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MO#00NC
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R.
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEM;Rg
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;R4
+RNH30DkbRol"j.jj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NRD3OF_O	CLMND"CRMo:PNs_8HsPC_HkM0#3P$_MO#00NCC_MG.0__l#Jk"GN;R
+s@d@4:jdj:dc:j6j::$P#M#O_0CN0rnj:9cRf6(.j:gdUUR6Uq pa)qq_uR XVgVU(qU_qRqqblsHR$P#M#O_0CN0r
+d9SosCF=k0PM#$O0_#N_0CdmRf4j(n:(dngRjd
+DSO	D=O	H_bM
+_OS08NNPN=#O$M_N#004C_R4fQ4j(n:(dg4R4U
+OS#Dks=M8n_DO$_F0kMCjs__fGRQndnUdc:Ugg.USR
+C=MNPM#$O0_#N_0CM0CG_#._JGlkNQRfcj6.(U:dgUU6Ro;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob#sOD;b
+oRNCM;4
+ARj4,yj!5?0V:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#M#O_0CN0"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+d;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR
+U;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRNNNN"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3FODOC	_MDNLCMR":NPo_H8sP_Csk0MH3$P#M#O_0CN0_GMC0__.#kJlG;N"
+@sR@:4dd:jjcj:dj::6PM#$O0_#Nr0Cj9:nR6fc.:j(dUUg6qURp)a qu_q VXRVjg..j_UjbjRsRHlPM#$O0_#Nr0C.S9
+sFCokP0=#O$M_N#00.C_R4fm(:njd(nnj
+dRS	OD=	OD_MbH_SO
+8NN0N#=P$_MOOMFk0_CsjQRf4n4(jg:d(U44R8
+SNL0N=$P#MOO_F0kMCgs_R4fQ4j(n:(dg4R4U
+NS80=NOPM#$O0_#N_0CdQRf4n4(jg:d(U44R8
+SN80N=4kMc#_P$_MOOMFk0_CsUQRf.4gdgg:d(U44R#
+SO=Dsk_Mn8_D$OMFk0_CsjR_GfnQdn:Ucd.Ugg
+URSNCM=$P#M#O_0CN0_GMC0__.#kJlGfNRQ.c6jd(:U6gUU
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;o#bRO;Ds
+RobC;MN
+RA44y,j!?5d55.?4j?5?0V:22:0::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MO#00NC
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rc
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEM;R(
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;R4
+RNH30DkbRol"jUjj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NRD3OF_O	CLMND"CRMo:PNs_8HsPC_HkM0#3P$_MO#00NCC_MG.0__l#Jk"GN;R
+s@d@4:(4U:4c:U6(::$E#M#O_0CN0rnj:9cRf.((c:gdUUR6Uq pa)qq_uR XVjVg4 j_ R  blsHR$E#M#O_0CN0r
+69SosCF=k0EM#$O0_#N_0C6mRf4j(n:.dngRUd
+DSO	D=O	H_bM
+_OS08NNEN=#O$M_N#00nC_R4fQ4j(n:(dg4R4U
+NS80=NLEM#$O0_#N_0CjQRf4n4(jg:d(U44R#
+SO=Dsk_Mn8_D$OMFk0_CsjR_GfnQdn:Ucd.Ugg
+URSNCM=$E#M#O_0CN0_jd__jj__j_o_fjRQ(c.cd(:U6gUU
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobC;MN
+RA44y,j!?54Vj:5?0V:2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MO#00NC
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R4
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEM;Rn
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;R4
+RNH30DkbRol"CCCC
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NRD3OF_O	CLMND"CRMo:PNs_8HsPC_HkM0#3E$_MO#00NC__dj__jjo__j"_j;R
+s@d@4:(4U:4c:U6(::$E#M#O_0CN0rnj:9cRf.((c:gdUUR6Uq pa)qq_uR XV.VgjU._jRjjblsHR$E#M#O_0CN0r
+c9SosCF=k0EM#$O0_#N_0CcmRf4j(n:cdn.R6d
+DSO	D=O	H_bM
+_OS08NNEN=#O$M_N#006C_R4fQ4j(n:(dg4R4U
+NS80=NLkjM4_$E#MOO_F0kMCds_R.fQjd.U:(dg4R4U
+NS80=NOkjM4_$E#MOO_F0kMC4s_R.fQj6n.:(dg4R4U
+NS80=N8kjM4_$E#MOO_F0kMCcs_R.fQjd.U:(dg4R4U
+OS#Dks=M8n_DO$_F0kMCjs__fGRQndnUdc:Ugg.USR
+C=MNEM#$O0_#N_0Cd__jj__j__ojjQRfcc.((U:dgUU6Ro;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08o;
+bOR#D
+s;oCbRM
+N;A44R,!jy55d?.4?5??5jV2:0::02002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$E#M#O_0CN0"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+.;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR
+6;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRUjjj"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3FODOC	_MDNLCMR":NPo_H8sP_Csk0MH3$E#M#O_0CN0_jd__jj__j_o_;j"
+@sR@:4d4:U(cU:4(::6EM#$O0_#Nr0Cj9:nR.fc(:c(dUUg6qURp)a qu_q VXRV(UgUq_qqbqRsRHlEM#$O0_#Nr0CdS9
+sFCokE0=#O$M_N#00dC_R4fm(:njdgn((
+dRS	OD=	OD_MbH_SO
+8NN0N#=E$_MO#00NCR_4f4Q4(:njd4g(4
+URSD#OsM=knD_8$F_OkCM0s__jGQRfdUnncU:dgU.gRC
+SMEN=#O$M_N#00dC__jj___j_ojj_RcfQ.((c:gdUUR6U;b
+oRosCF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o#bRO;Ds
+RobC;MN
+RA44y,j!?5jV2:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$O0_#N"0C;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGdN;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHMcN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDC4N;
+HDR3ko0blNR"N"NN;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HROODF	M_CNCLDR:"MP_oN8PsHCks_M3H0EM#$O0_#N_0Cd__jj__j__ojj
+";s@R@44d:Uc(::(4U:E6:#O$M_N#00jCr:Rn9f(c.cd(:U6gUUpRqaq )_ quXVRVgjj4_UUUUsRbHElR#O$M_N#00.Cr9s
+SCkoF0#=E$_MO#00NCR_.f(m4ndj:njn(dSR
+O=D	O_D	b_HMO8
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+8NN0LM=k4E._#O$M_kOFMs0CR.fQn64(:(dg4R4U
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+C=MNEM#$O0_#N_0Cd__jj__j__ojjQRfcc.((U:dgUU6Ro;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oCbRM
+N;A44R,!jy554?j:?V002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$E#M#O_0CN0"N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+c;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR
+d;N3HRN0D#_C0DM;R4
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+NRF3l84CR;H
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+4;N3HRDbk0o"lRUUUU"N;
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+RNH3l#k_0DkOM_HbRk04N;
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+';N3HROODF	PR"oON|Db	_H;M"
+RNH3FODOC	_MDNLCMR":NPo_H8sP_Csk0MH3$E#M#O_0CN0_jd__jj__j_o_;j"
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+dRS	OD=	OD_MbH_SO
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+oRosCF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;b
+oRD#Oso;
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+RNHP|oNO_D	bRHM{H
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+};}N;
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+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
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+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
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+O=HMk_M.OkFDlOM_F0kMCMs_C_G0O0FkrRj9fUQ4.:jjdUU(.;nR
+RobOLFlF;k0
+RobO0Fk;b
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+oRMOH;4
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+RA.4y,j!?5.554?j:?V002:22:0RN;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U6Nj
+";N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo's;
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+OLFlF=k0k_M.OkFDlOM_F0kMCMs_C_G0OLFlFrk04f9Rmd4n6dj:g6ddnSR
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+oRlOFL0Fk;b
+oRkOF0o;
+bNR80;NN
+Rob8NN0LA;
+4,R444y5?5j*j:?V0!2:fRj2;.
+ARj4,y4!5??5jV2:0:R02;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRnUnU"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:.44::d44:4.6jc+:.kM_DOFk_lMOMFk0_CsM0CGrjg:94RfUj.j:(dUUR.nq pa)qq_uR XN_6.6666_UUUUsRbHklRMO._FlDkMF_OkCM0sC_MGj0r9O
+SF=k0k_M.OkFDlOM_F0kMCMs_C_G0O0FkrRj9fUm4.:jjdUU(.
+nRS08NNON=FlDkMF_OkCM0sH_#oR_jf4Q4(:njddU4U
+nRS08NNOL=FlDkMF_OkCM0sH_#oR_4f4Q4(:njddU4U;nR
+RobO0Fk;b
+oR08NN
+N;o8bRNL0N;4
+ARj4,y?5jV2:0RA;
+.,R4j5y!4j?5?0V:22:0RN;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U66U
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'b;
+R4@@:44::.4:+0.:sRkCfjj:Rk0sCsR0keCRB
+B;NsHRCFoHMPR'o;N'
+fbRjR:jV#NDChRt7hRt7@;
+ 
+
+
+
+ftell;
+@ERMRI	FsRNPo_MOF0DsFR0MCD0H#;P
+NR#3H_k#FsROC4N;
+PDR3HMMCFgRdUN;
+PHR3#8PED;R4
+RNP3_H#PDE8R
+4;N3PRFosHhCNlRo"PNF_OMF0sD
+";N#PR$bM_sCC#sRPC4N;
+PNR3DOlN_0bNEF_OkRM04N;
+PFR3sPHoHMCINRlC'ELCN;P'
+RNP3#EN0HHlM4oR;P
+NRH3k__MD#ODN	cRdcn6(;R
+HDCHM_kOFMs0C_o#H_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HHRDMOC_F0kMC#s_H.o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;R
+HDCHM_kOFMs0C_o#H_
+4;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HHRDMOC_F0kMC#s_Hdo_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;R
+HDCHM_kOFMs0C_o#H_
+n;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HHRDMOC_F0kMC#s_H6o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;R
+HDCHM_kOFMs0C_o#H_
+c;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HHRDMOC_F0kMC#s_H(o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;R
+HDCHM_kOFMs0C_o#H_
+U;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+4;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+.;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+U;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+d;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+6;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+c;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+g;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+(;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+n;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";FFR0oCoD_kOFMs0C_o#H_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+0FRFDooCF_OkCM0sH_#o;_4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H.o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+Ro0Fo_DCOMFk0_Cs#_HodN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_
+c;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+0FRFDooCF_OkCM0sH_#o;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_Hno_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+Ro0Fo_DCOMFk0_Cs#_Ho(N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_
+U;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+0FRFDooCF_OkCM0sH_#o;_g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_jN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;44
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_.N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;4d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_cN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;46
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_nN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;4(
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_UN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;4g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H.o_jN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;.4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H.o_.N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;.d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H.o_cN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";H_RECLMND#C_H
+o;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";F;Ro
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FLN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";H_RPCLMND#C_H
+o;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";F;Rs
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoD#C_H
+o;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+kHRM8n_DO$_F0kMCjs__
+G;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HDRO	H_bM;_O
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRH;M"
+RoMO_D	b_HMON;
+MOR3D	FORo"PND|O	H_bM
+";N3MROODF	8_Co"CRsCH#"N;
+MHR3#D_OFRO	4s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jR(f4ndj:n(cUcpRqaq )_ quXVRVc.cU_jwwjsRbH0lRFDooCF_OkCM0sH_#ocr.9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R.cf(m4ndj:n(cUcSR
+O=D	O_D	b_HMO8
+SN80N=7th
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};A44R,!jy5Vd?:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GcR.;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jR(f4ndj:njdncpRqaq )_ quXVRVc.cU_jwwjsRbH0lRFDooCF_OkCM0sH_#odr.9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R.df(m4ndj:njdncSR
+O=D	O_D	b_HMO8
+SN80N=7th
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};A44R,!jy5Vd?:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GdR.;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jR(f4ndj:n.(dcpRqaq )_ quXVRVc.cU_jwwjsRbH0lRFDooCF_OkCM0sH_#o.r.9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R..f(m4ndj:n.(dcSR
+O=D	O_D	b_HMO8
+SN80N=7th
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};A44R,!jy5Vd?:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G.R.;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jR(f4ndj:nnnjcpRqaq )_ quXVRVc.cU_jwwjsRbH0lRFDooCF_OkCM0sH_#o4r.9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R.4f(m4ndj:nnnjcSR
+O=D	O_D	b_HMO8
+SN80N=7th
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};A44R,!jy5Vd?:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G4R.;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRV64dU6n_qR6qblsHRo0Fo_DCOMFk0_Cs#rHo.
+j9SosCF=k00oFoDOC_F0kMC#s_H.o_jmRf4j(n:jd((Rnn
+DSO	D=O	H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oj_.R4fQ4j(n:(dg4R4U
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Ok40rUf9RQn.jddj:gg.dU
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5?5j*j:?V0!2:fRj2;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GjR.;H
+NRO3#DVs_V;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"6N;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1)  Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_4UnBBnRHbslFR0oCoD_kOFMs0C_o#Hr94g
+CSso0Fk=o0Fo_DCOMFk0_Cs#_Ho4fgRmn4(jn:dgncgRO
+SDO	=Db	_HOM_
+NS80=NN0oFoDOC_F0kMC#s_H4o_UQRf4n4(jg:d(U44R8
+SNL0N=o0Fo_DCOMFk0_Cs#_Ho4fgRQ(44ndj:g4(4USR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=o0Fo_DCOMFk0_Cs#_HoO0Fkr94(R.fQjjdn:.dgdRgU;b
+oRosCF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5??54jj*5?0V:2f:!j!2:5V4?:202RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC4GRgN;
+H#R3O_DsV4VR;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRnOOn"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_kOFMs0C_o#Hr:.cjf9Rc.c(.U:dgU.gRaqp _)qqXu R4VVd.n._66qqj_UUbjRsRHl0oFoDOC_F0kMC#s_H4orUS9
+sFCok00=FDooCF_OkCM0sH_#oU_4R4fm(:njd4nnd
+cRSkOF0F=0oCoD_kOFMs0C_o#H_kOF0Ur49mRf.djnjg:d.UdgRO
+SDO	=Db	_HOM_
+NS80=NN0oFoDOC_F0kMC#s_H4o_UQRf4n4(jU:d6Ug6R8
+SNL0N=o0Fo_DCOMFk0_Cs#_Ho4fgRQ(44ndj:U66gUSR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=o0Fo_DCOMFk0_Cs#_HoO0Fkr94nR.fQjjdn:.dg4R.U;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR;4U
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRN"6U;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRVn4d.n._B_nBUjjURHbslFR0oCoD_kOFMs0C_o#Hr94(
+CSso0Fk=o0Fo_DCOMFk0_Cs#_Ho4f(Rmn4(jn:dccUnRO
+SF=k00oFoDOC_F0kMC#s_HOo_Frk04R(9fjm.d:njddg.g
+URS	OD=	OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_R4nf4Q4(:njdgU66
+URS08NN0L=FDooCF_OkCM0sH_#o(_4R4fQ4j(n:6dUgR6U
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Ok40r6f9RQj.jgdj:g..4U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.5j4?*?5jV2:0:j!f25:!4:?V0R22;.
+ARj4,y.!5??545Vj?::02002:2
+R;N3HRs_0DFosHMCNlRF"0oCoD_kOFMs0C_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG4
+(;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UnOj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4.dn.q_66Uq_jRUjblsHRo0Fo_DCOMFk0_Cs#rHo4
+n9SosCF=k00oFoDOC_F0kMC#s_H4o_nmRf4j(n:(dndR.c
+FSOk00=FDooCF_OkCM0sH_#oF_Ok40rnf9Rmd.jndj:g..4USR
+O=D	O_D	b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_Ho4fnRQ(44ndj:UU6nUSR
+8NN0LF=0oCoD_kOFMs0C_o#H_R4(f4Q4(:njdnU6U
+URSDNOsM=knD_8$F_OkCM0s__jG#
+SO!Ds=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:gdU.RgU
+HSOMF=0oCoD_kOFMs0C_o#H_kOF0cr49QRf.gjjjg:d4UU6Ro;
+bCRso0Fk;b
+oRkOF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GnR4;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1)  Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..nBBn_UUjjsRbH0lRFDooCF_OkCM0sH_#o6r49s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R46f(m4ndj:ng.n.SR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0Fkr946R.fmjjjg:.dg4R.U
+DSO	D=O	H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oc_4R4fQ4j(n:6dUnRUU
+NS80=NL0oFoDOC_F0kMC#s_H4o_6QRf4n4(jU:d6UnURN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk04Rd9fgQ4U:.jdUg46;UR
+RobsFCok
+0;oObRF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5??54jj*5?0V:2f:!j!2:5V4?:202RA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR;46
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRO"nU;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRVn4d.6._q_6qUjjURHbslFR0oCoD_kOFMs0C_o#Hr94c
+CSso0Fk=o0Fo_DCOMFk0_Cs#_Ho4fcRmn4(jn:d4.6jRO
+SF=k00oFoDOC_F0kMC#s_HOo_Frk04Rc9fjm.j:gjdUg46
+URS	OD=	OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_R4cf4Q4(:njdcU64
+URS08NN0L=FDooCF_OkCM0sH_#o6_4R4fQ4j(n:6dUcR4U
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Ok40r.f9RQU4g.dj:gU46U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC4GRcN;
+H#R3O_DsV4VR;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_kOFMs0C_o#Hr:.cjf9Rc.c(.U:dgU.gRaqp _)qqXu R4VVd.n._nnBBj_UUbjRsRHl0oFoDOC_F0kMC#s_H4ordS9
+sFCok00=FDooCF_OkCM0sH_#od_4R4fm(:njd.njd
+.RSkOF0F=0oCoD_kOFMs0C_o#H_kOF0dr49mRf4.gUjg:d4UU6RO
+SDO	=Db	_HOM_
+NS80=NN0oFoDOC_F0kMC#s_H4o_.QRf4n4(jU:d6Uc4R8
+SNL0N=o0Fo_DCOMFk0_Cs#_Ho4fdRQ(44ndj:U46cUSR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=o0Fo_DCOMFk0_Cs#_HoO0Fkr944R4fQgj66:4dg6RUU;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.4?5?5j*j:?V0!2:f:j2!?54V2:02
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GdR4;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0blnR"O"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1)  Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..6qq6_UUjjsRbH0lRFDooCF_OkCM0sH_#o.r49s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R4.f(m4ndj:6nUjjSR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0Fkr94.R4fmgjU.:4dg6RUU
+DSO	D=O	H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#o._4R4fQ4j(n:6dU4RcU
+NS80=NL0oFoDOC_F0kMC#s_H4o_dQRf4n4(jU:d6U4cRN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk04Rj9fgQ46:6jddg44;UR
+RobsFCok
+0;oObRF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5?5j*j:?V0!2:fRj2;.
+ARj4,y.!5??545Vj?::02002:2
+R;N3HRs_0DFosHMCNlRF"0oCoD_kOFMs0C_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG4
+.;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4.dn.B_nnUB_jRUjblsHRo0Fo_DCOMFk0_Cs#rHo4
+49SosCF=k00oFoDOC_F0kMC#s_H4o_4mRf4j(n:nd6UR(j
+FSOk00=FDooCF_OkCM0sH_#oF_Ok40r4f9Rm64g6dj:gU46USR
+O=D	O_D	b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_Ho4fjRQ(44ndj:Uc64USR
+8NN0LF=0oCoD_kOFMs0C_o#H_R44f4Q4(:njd4U6c
+URSDNOsM=knD_8$F_OkCM0s__jG#
+SO!Ds=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:gdU.RgU
+HSOMF=0oCoD_kOFMs0C_o#H_kOF09rgR4fQgj.U:4dgdR4U;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.4?5?5j*j:?V0!2:f:j2!?54V2:02
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G4R4;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0blnR"O"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1)  Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..6qq6_UUjjsRbH0lRFDooCF_OkCM0sH_#ojr49s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R4jf(m4ndj:6j6njSR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0Fkr94jR4fmgj66:4dgdR4U
+DSO	D=O	H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oj_4R4fQ4j(n:cdUUR(U
+NS80=NL0oFoDOC_F0kMC#s_H4o_4QRf4n4(jU:dcUU(RN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk0Uf9RQ.4gUdj:gc4jU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC4GRjN;
+H#R3O_DsV4VR;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_kOFMs0C_o#Hr:.cjf9Rc.c(.U:dgU.gRaqp _)qqXu R4VVd.n._nnBBj_UUbjRsRHl0oFoDOC_F0kMC#s_Hgor9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_fgRmn4(j6:d.U.dRO
+SF=k00oFoDOC_F0kMC#s_HOo_Frk0gf9Rm.4gUdj:g44dUSR
+O=D	O_D	b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_HoUQRf4n4(jU:dcUU(R8
+SNL0N=o0Fo_DCOMFk0_Cs#_HogQRf4n4(jU:dcUU(RN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk0(f9RQj4g4dj:gc4jU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.5j4?*?5jV2:0:j!f25:!4:?V0R22;.
+ARj4,y.!5??545Vj?::02002:2
+R;N3HRs_0DFosHMCNlRF"0oCoD_kOFMs0C_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGgN;
+H#R3O_DsV4VR;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRnjOU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_kOFMs0C_o#Hr:.cjf9Rc.c(.U:dgU.gRaqp _)qqXu R4VVd.n._66qqj_UUbjRsRHl0oFoDOC_F0kMC#s_HUor9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_fURmn4(j6:djUgnRO
+SF=k00oFoDOC_F0kMC#s_HOo_Frk0Uf9Rm.4gUdj:gc4jUSR
+O=D	O_D	b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_HoUQRf4n4(jU:dcUnjR8
+SNL0N=o0Fo_DCOMFk0_Cs#_HogQRf4n4(jU:dcUnjRN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk0nf9RQj4g4dj:g(j(U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMCUGR;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1)  Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..nBBn_UUjjsRbH0lRFDooCF_OkCM0sH_#o9r(
+CSso0Fk=o0Fo_DCOMFk0_Cs#_Ho(mRf4j(n:dd6cR.U
+FSOk00=FDooCF_OkCM0sH_#oF_Ok(0r9mRf44gjjg:d4UjcRO
+SDO	=Db	_HOM_
+NS80=NN0oFoDOC_F0kMC#s_Hno_R4fQ4j(n:cdUnRjU
+NS80=NL0oFoDOC_F0kMC#s_H(o_R4fQ4j(n:cdUnRjU
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Ok60r9QRf4cU(jg:djU((Ro;
+bCRso0Fk;b
+oRkOF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobO;HM
+RA44y,455.?4*?j5Vj?::02!2fj:4!5?0V:2;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC(GR;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0blnR"O"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1)  Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..6qq6_UUjjsRbH0lRFDooCF_OkCM0sH_#o9rn
+CSso0Fk=o0Fo_DCOMFk0_Cs#_HonmRf4j(n:ndcdRdn
+FSOk00=FDooCF_OkCM0sH_#oF_Okn0r9mRf44gjjg:djU((RO
+SDO	=Db	_HOM_
+NS80=NN0oFoDOC_F0kMC#s_Hno_R4fQ4j(n:cdUdRdU
+NS80=NL0oFoDOC_F0kMC#s_H(o_R4fQ4j(n:cdUdRdU
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Okc0r9QRf4cU(jg:djU6jRo;
+bCRso0Fk;b
+oRkOF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rn
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRN"6U;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRVn4d.n._B_nBUjjURHbslFR0oCoD_kOFMs0C_o#Hr
+69SosCF=k00oFoDOC_F0kMC#s_H6o_R4fm(:njdnc(j
+nRSkOF0F=0oCoD_kOFMs0C_o#H_kOF09r6R4fmUj(c:jdg(R(U
+DSO	D=O	H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oR_cf4Q4(:njddUcd
+URS08NN0L=FDooCF_OkCM0sH_#oR_6f4Q4(:njddUcd
+URSDNOsM=knD_8$F_OkCM0s__jG#
+SO!Ds=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:gdU.RgU
+HSOMF=0oCoD_kOFMs0C_o#H_kOF09rdR4fQUjc(:jdg6RjU;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.4?5?5j*j:?V0!2:f:j2!?54V2:02
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R6
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRO"nU;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRVn4d.6._q_6qUjjURHbslFR0oCoD_kOFMs0C_o#Hr
+c9SosCF=k00oFoDOC_F0kMC#s_Hco_R4fm(:njdj(cn
+URSkOF0F=0oCoD_kOFMs0C_o#H_kOF09rcR4fmUj(c:jdg6RjU
+DSO	D=O	H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oR_cf4Q4(:njdjUcn
+URS08NN0L=FDooCF_OkCM0sH_#oR_6f4Q4(:njdjUcn
+URSDNOsM=knD_8$F_OkCM0s__jG#
+SO!Ds=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:gdU.RgU
+HSOMF=0oCoD_kOFMs0C_o#H_kOF09r.R4fQUjc(:jdg.RdU;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+c;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4.dn.B_nnUB_jRUjblsHRo0Fo_DCOMFk0_Cs#rHodS9
+sFCok00=FDooCF_OkCM0sH_#oR_df(m4ndj:(gd(USR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0FkrRd9fUm4c:(jd6gjj
+URS	OD=	OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_f.RQ(44ndj:UncjUSR
+8NN0LF=0oCoD_kOFMs0C_o#H_fdRQ(44ndj:UncjUSR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=o0Fo_DCOMFk0_Cs#_HoO0FkrR49fUQ4.:jjd.gjd;UR
+RobsFCok
+0;oObRF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5??54jj*5?0V:2f:!j!2:5V4?:202RA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+d;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UnOj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4.dn.q_66Uq_jRUjblsHRo0Fo_DCOMFk0_Cs#rHo.S9
+sFCok00=FDooCF_OkCM0sH_#oR_.f(m4ndj:(gd(USR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0FkrR.9fUm4c:(jd.gjd
+URS	OD=	OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_f.RQ(44ndj:Ugd(USR
+8NN0LF=0oCoD_kOFMs0C_o#H_fdRQ(44ndj:Ugd(USR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=.kM_o0Fo_DCOMFk0_CsM0CG_kOF09rjR4fQUj.j:gdUgRnU;b
+oRosCF;k0
+RobO0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO	{H
+NRNPo|	OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+.;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO"	RP|oNO_D	b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4g.6Un_nnUn_URUUblsHRo0Fo_DCOMFk0_Cs#rHo4S9
+sFCok00=FDooCF_OkCM0sH_#oR_4f(m4ndj:(.d6USR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0FkrR49fUm4.:jjd.gjd
+URS	OD=	OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_fjRQ(44ndj:Ugd(USR
+8NN0LF=0oCoD_kOFMs0C_o#H_f4RQ(44ndj:Ugd(USR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg;UR
+RobsFCok
+0;oObRF;k0
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R444y5?5j*j:?V0!2:fRj2;.
+ARj4,y4!5??5jV2:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R4
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRn"nU;U"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRV64.n6._6R66blsHRo0Fo_DCOMFk0_Cs#rHojS9
+sFCok00=FDooCF_OkCM0sH_#oR_jf(m4ndj:(.d6USR
+O=D	O_D	b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_HojQRf4n4(jg:d(U44RN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.U
+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oRD#OsA;
+4,R4jjy5?0V:2
+R;N3HRs_0DFosHMCNlRF"0oCoD_kOFMs0C_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGjN;
+H#R3O_DsV4VR;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6666"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF	PR"oON|Db	_H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_o#HRcfc(:..d4g(4qURp)a qu_q VXRVjcc.g_ggbgRsRHl0oFoD#C_HSo
+sFCok00=FDooCH_#omRf4j(n:(dU4R4U
+DSO	D=O	H_bM
+_OS08NN0N=FDooCH_#oQRf4n4(jg:d(U44R8
+SNL0N=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:(dg4R4U
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;A44R,!4y5j4?*?5jV2:0:j!f2
+R;N3HRs_0DFosHMCNlRF"0oCoD_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"gggg
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1)  Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4n.:j::cn6j::fsRdd6cgg:d(U44Raqp _)qqXu RcVV6_gcUjjjRHbsl
+RsSosCF=k0sO
+SDO	=Db	_HOM_
+NS80=NN0oFoD#C_HfoRQ(44ndj:g4(4USR
+8NN0L_=PCLMND#C_HfoRQ(44ndj:g4(4USR
+8NN0O_=LM0CG_#j_JGlkN__(cQRfdjjU(g:d(U44R8
+SN80N=ML_C_G0jJ_#lNkG_6(_RdfQ6gcd:(dg4R4U
+OSNDks=M8n_DO$_F0kMCjs__
+G;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j!?5d55.?4j?5?0V:22:0::020;2R
+RNH3Ds0_HFsolMNCsR""N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{	R
+RNHP|oNO_D	bRHM{H
+NR#sHC;R4
+
+};}N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"jUjj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D	FORo"PND|O	H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1)  Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4n.:j::cn6j::fLRdd6cgg:d(U44Raqp _)qqXu RcVV6_gccjjjRHbsl
+RLSosCF=k0LO
+SDO	=Db	_HOM_
+NS80=NN0oFoD#C_HfoRQ(44ndj:g4(4USR
+8NN0L_=PCLMND#C_HfoRQ(44ndj:g4(4USR
+8NN0O_=LM0CG_#j_JGlkN__(cQRfdjjU(g:d(U44R8
+SN80N=ML_C_G0jJ_#lNkG_6(_RdfQ6gcd:(dg4R4U
+OSNDks=M8n_DO$_F0kMCjs__
+G;oObRD
+	;N3bR#_$MNOH_D	FORN{
+boRPND|O	H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j55d?.4?5??5jV2:0::V2VV2:2
+R;N3HRs_0DFosHMCNlR""L;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRcjjj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.j:n:nc:j::6ojRf:qjRp)a qu_q VXRVUcc.w_wjbjRsRHlos
+SCkoF0
+=oS	OD=	OD_MbH_SO
+8NN08h=t7N
+SO=Dsk_Mn8_D$OMFk0_Csj;_G
+RobO;D	
+RNb3M#$__NHOODF	
+R{NPbRoON|Db	_H{MR
+RNbsCH#R
+4;}};
+;4
+ARj4,yd!5?0V:2
+R;N3HRs_0DFosHMCNlR""o;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY)  1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+Rgfd6:4jdjUcUqnRp)a qu_q NXR._c4jd(jRHbslFR0oCoD_o#H_jj__oj_4O
+SFFlLk00=FDooCH_#o__jj__jof4Rm6dg4dj:UUcjnSR
+8NN0NF=0oCoD_kOFMs0C_o#H_R4gf4Q4(:njdc(gg
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+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5d5V.?:?545Vj?::020:225V.?:?54V2:02;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"("jd;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4.4:44(4:44U:d+Ac:piQh M)_C\G034kM_o0Fo_DCOMFk0_Cs#RHofUdc(dU:(6gccpRqaq )_ quX.RNc(4_wR((blsHRQAph)i _GMC0k\3M04_FDooCF_OkCM0sH_#oFD04SU
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+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R44dy5??5.j4*5??5jV2:0::020f2:j;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl(R"V"((;H
+NRk3#lk_D0HO_M0bkR
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+@sR@:4.(46:jn:(:+njc_:LM0CG_#j_JGlkNdRf4n6j:ddg4RU6q pa)qq_uR XN4.c_j(wjsRbHLlR_GMC0__j#kJlG(N__S6
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+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,5jyd.?5??545Vj?::02002:22:VRN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"j(Vj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
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+FSOlkLF0_=LM0CG_#j_JGlkN__(cmRf.(nUcg:dd64UR8
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+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
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+RA44y,4!?5d55.?4:?Vjj*5?0V:2V2:25:!.4?5?!V:f:j25V4?:2022
+R;N3HRlCF8R
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+RNH3l#k_0DkOM_HbRk04N;
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+';s@R@4(.:6j:4::(nncj+:ML_C_G0jJ_#lNkGRjf.g:U.d6UU6qdRp)a qu_q NXR._c4jww4RHbsl_RLM0CG_#j_JGlkN__(c
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+8NN0OH=DMOC_F0kMC#s_Hno_R4fQ4j(n:ndUcR.d
+NS80=N8k(M4_CP_MDNLCFD0dQRf.4j4.U:d(dnURo;
+bFROlkLF0o;
+bNR80;NN
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+Rob8NN08A;
+4,R4jdy5??5.V2:0:?5.5V4?:?5jV2:022:02
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"j4;V"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4(.:6j:4::(nncj+:ML_C_G0jJ_#lNkGRnf.U:(cd6UU6qdRp)a qu_q NXR._c4 jjwRHbsl_RLM0CG_#j_JGlkN__(dO
+SFFlLkL0=_GMC0__j#kJlG(N__fdRmU.n(dc:U6U6dSR
+8NN0NF=ODMkl_kOFMs0C_o#H_f(RQ(44ndj:UndgdSR
+8NN0LF=ODMkl_kOFMs0C_o#H_fgRQ(44ndj:Ud6.dSR
+8NN0O_=LM0CG_#j_JGlkN__(.QRf.4j4.U:dndc.R8
+SN80N=gkM_CP_MDNLCFD0nQRf.jnjcU:d(dnURo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
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+Rob8NN08A;
+4,R4j5y!d.?5??54Vj:5?0V:202:2.:5?0V:2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blCR"j"Vj;H
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+4;NsHRCFoHMPR'o;N'
+@sR@:4.4:44(4:44U:d+Ac:piQh M)_C\G034kM_o0Fo_DCOMFk0_Cs#RHof.djcdn:(.cU.pRqaq )_ quX.RNcw4_wR(wblsHRQAph)i _GMC0k\3M04_FDooCF_OkCM0sH_#oFD04S6
+OLFlF=k0k_M40oFoDOC_F0kMC#s_H0oDFR46fjmd.:cndU(c.
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+SNO0N=o0Fo_DCOMFk0_Cs#_Ho4f6RQ(44ndj:(g.n.SR
+8NN08M=k4F_0oCoD_kOFMs0C_o#HD40F.QRf.(gdn(:dd.g6Ro;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4j5y!d:?V!?5.554?j:?V002:22:02
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"V(;V"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4(.:6U:d::(6ncj+:q7)WT_1z q)_GMC0k\3MP6__NCMLRDCfg.jUd.:Ug(.dpRqaq )_ quX.RNcw4_ R  blsHRq7)WT_1z q)_GMC0k\3MP6__NCMLDDC0
+F6SlOFL0Fk=6kM_CP_MDNLCFD06mRf.Ujg.U:d(d.gR8
+SNN0N=DOFk_lMOMFk0_Cs#_HocQRf4n4(jU:d.d(jR8
+SNL0N=DOFk_lMOMFk0_Cs#_Ho6QRf4n4(jU:dddg(R8
+SNO0N=DOFk_lMOMFk0_Cs#_HodQRf4n4(jU:d6d4nR8
+SN80N=6kM_CP_MDNLC.D0R.fQj.44:ndUcR.d;b
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+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+AR44,yd!5??5.V*:j5V4?:?5jV2:02f2:j;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blVR"C"CC;H
+NRk3#lk_D0HO_M0bkR
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+@sR@:4.4:44(4:44U:d+Ac:piQh M)_C\G034kM_o0Fo_DCOMFk0_Cs#RHofn.64dc:(gj4jpRqaq )_ quX.RNcj4_4RjjblsHRQAph)i _GMC0k\3M04_FDooCF_OkCM0sH_#oFD04S.
+OLFlF=k0k_M40oFoDOC_F0kMC#s_H0oDFR4.f6m.n:4cd4(jg
+jRS08NN0N=FDooCF_OkCM0sH_#oj_4R4fQ4j(n:6dnnRjj
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+SNO0N=o0Fo_DCOMFk0_Cs#_Ho4f.RQ(44ndj:nnUjjSR
+8NN08M=k4F_0oCoD_kOFMs0C_o#HDg0FR.fQcc(c:gdndR.j;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5d5V.?:?54Vj:5?0V:2:22V;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"4"jj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4.(4n:jn:(:+d.c):7q1W_T)zq C_MG30\kdM4_CP_MDNLC.Rfj.gU:(dU.Rgdq pa)qq_uR XN4.c_((w(sRbH7lR)_qW1qTz)M _C\G034kMd__PCLMND0CDFSn
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+dRS08NNk8=M_4dPM_CNCLDDc0F_fjRQ4.j4d.:U.ncd
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,54yd.?5?5j*4j?5?0V:22:0::02fRj2;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR((V("N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
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+Rob8NN0No;
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+Rob8NN0OA;
+4,R4j5y!.:?V!?545Vj?::020R22;H
+NRF3l84CR;H
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+j;N3HRDbk0o"lRV((V"N;
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+8NN0OF=0oCoD_kOFMs0C_o#H_f(RQ(44ndj:n.dcUSR
+8NN08M=k4F_0oCoD_kOFMs0C_o#HDR0nfjQ.4:4.dnncU;UR
+RobOLFlF;k0
+Rob8NN0No;
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+RA44y,455d?.*?j554?j:?V002:22:0:2fjRN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"((V(
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
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+Rob8NN0No;
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+Rob8NN0Oo;
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+RA44y,j!?5d5V.?:?54Vj:5?0V:2:220;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
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+fsR46ndj(:dUc4gRaqp _)qqXu RcN.4w_wwb RsRHl0oFoD#C_Hjo__jj___o4.O
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+8NN0OF=0oCoD_kOFMs0C_o#H_R.4f4Q4(:njdj(nn
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+R;oObRFFlLk
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+B;@
+ 
+
+ftell;
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+NR83OLN_#P{CR
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+P$R#MC_sVCCsM_OCOODF	
+R{NPPRoON|Db	_H{MR
+RNP3M#$_VsCOODF	$_0bnCR;;
+}
+
+};}N;
+PMR3NNsC8FCOl4bR;P
+NRC38ObFl_HbslN#_sRCN4N;
+PNR3DOlN_0bNEF_OkRM04N;
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+j;N3PRk0H_HMlHoO_#NRDC4jjjjN;
+PER3NH#0loHMR
+4;N3PRkMH_DD_#NRO	d6cc(
+n;H@R@n4:c:c(:4d:4:	OD_MbHR	OD_MbH;H
+NR03sDs_FHNoMl"CRO_D	b"HM;H
+NR83OL
+R{N4HRjRjj{H
+NR[FLCRO0{H
+NR4jR;;
+}
+
+};}N;
+HOR38OL_b
+R{NjHRRd"6d_jn4_U(njcgjc_n6_4..c(dgg_6d_4n4..ncU_..4n_j(U._64.n4c_4ncc_((4c._ng"4.;;
+}
+RNH3#EN_NMLON	_040R;H
+NRF3bsD0N8RHs""HM;b
+oR	OD_MbH;b
+NR83OL
+R{N4bRjRjj{b
+NR[FLCRO0{b
+NR4jR;;
+}
+
+};}N;
+bHR3#N_o0_C8OODF	;R4
+RNb3_H#OODF	;R4
+RNb3FODO"	RP|oNO_D	b"HM;R
+H@:@nc(.:::c.4s6:C0#C_MbHR#sCCb0_H
+M;N3HRs_0DFosHMCNlRC"s#_C0b"HM;H
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+F@:@nc(c:::cc4s.:jH_bMjRs_MbH;H
+NR03sDs_FHNoMl"CRsbj_H;M"
+RNH3sbF08NDH"sRF"k0;R
+F@:@nc4c:6c:c::.jsb4_HsMR4H_bMN;
+HsR30FD_sMHoNRlC"_s4b"HM;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::cc.cd:cU:.:_s.bRHMsb._H
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+HbR3FNs0Ds8HRk"F0
+";F@R@n6:c:c(:6.:4:_ojbRHMobj_H
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+HbR3FNs0Ds8HRk"F0
+";F@R@n6:c::46c.6:j4:o_MbHR_o4b;HM
+RNH3Ds0_HFsolMNCoR"4H_bM
+";N3HRb0FsNHD8sFR"k;0"
+@FR@cn:6d:.::c6.oU:.H_bM.Ro_MbH;H
+NR03sDs_FHNoMl"CRob._H;M"
+RNH3sbF08NDH"sRF"k0;R
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+RNH3sbF08NDH"sRF"k0;R
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+Rn@@::c(((:c::46EM#$OH_bM#RE$_MOb;HM
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+HbR3FNs0Ds8HRk"F0
+";F@R@nU:c:c(:U6:4:$P#MbO_HPMR#O$M_MbH;H
+NR03sDs_FHNoMl"CRPM#$OH_bM
+";N3HRb0FsNHD8sFR"k;0"
+@FR@6n:j::(64j:gC:#P_CM#_CobrHM4jd:9CR#P_CM#_CobrHM4jd:9CR#P_CM#_CobrHM4jd:9N;
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+RNH3sbF08NDH"sRF"k0;R
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+O;N3HRs_0DFosHMCNlR_"8EM#$O
+";N3HRb0FsNHD8sFR"k;0"
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+";N3HRb0FsNHD8sFR"k;0"
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+Rn@@::6c(c:6::.j8H_DMOC_F0kMCUsr:Rj98H_DMOC_F0kMCUsr:Rj98H_DMOC_F0kMCUsr:;j9
+RNH3Ds0_HFsolMNC8R"_MDHCF_OkCM0s
+";N3HRb0FsNHD8sFR"k;0"
+@FR@6n:6::(6.6:n_:8#_C0OkFDlOM_F0kMC8sR_0#C_DOFk_lMOMFk0;Cs
+RNH3Ds0_HFsolMNC8R"_0#C_DOFk_lMOMFk0"Cs;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::66.6g:6n:c:#8_CD0_H_MCOMFk0RCs8C_#0H_DMOC_F0kMC
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+RNH3Ds0_HFsolMNC8R"_$E#MOO_F0kMC;s"
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+NR03sDs_FHNoMl"CR8C_#0#_P$_MOOMFk0"Cs;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::6g(g:6::4n8__ECLMND8CR_CE_MDNLCN;
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+Rn@@::n4(4:n:8g:_8sR_
+s;N3HRs_0DFosHMCNlR_"8s
+";N3HRb0FsNHD8sFR"k;0"
+@FR@nn:4.:4::n448c:_8oR_
+o;N3HRs_0DFosHMCNlR_"8o
+";N3HRb0FsNHD8sFR"k;0"
+@FR@nn:4(:4::n448g:_8LR_
+L;N3HRs_0DFosHMCNlR_"8L
+";N3HRb0FsNHD8sFR"k;0"
+@FR@nn:.::(n4.:g_:8EM#$O0_#Nr0Cj9:nRE8_#O$M_N#00jCr:Rn98#_E$_MO#00NC:rjn
+9;N3HRs_0DFosHMCNlR_"8EM#$O0_#N"0C;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::nd(d:n::4g8#_P$_MO#00NC:rjn89R_$P#M#O_0CN0rnj:9_R8PM#$O0_#Nr0Cj9:n;H
+NR03sDs_FHNoMl"CR8#_P$_MO#00NC
+";N3HRb0FsNHD8sFR"k;0"
+@FR@nn:c::(n4c:(_:8#00NCD_O	_R8#00NCD_O	N;
+HsR30FD_sMHoNRlC"#8_0CN0_	OD"N;
+HbR3FNs0Ds8HRk"F0
+";F@R@n6:n:n(:6c:4:08_FDooC_R80oFoD
+C;N3HRs_0DFosHMCNlR_"80oFoD;C"
+RNH3sbF08NDH"sRF"k0;R
+F@:@nn(n:::nn.8.:_o0Fo_DCOMFk0rCs.jc:9_R80oFoDOC_F0kMC.src9:jR08_FDooCF_OkCM0scr.:;j9
+RNH3Ds0_HFsolMNC8R"_o0Fo_DCOMFk0"Cs;H
+NRF3bsD0N8RHs"0Fk"o;
+LDRO	H_bMN;
+LOR38{LR
+RNL4jjjRN{
+LLRF[0CORN{
+LRRj4};
+;;
+}
+
+};N#LR$OM_D	FO_VHMCCss8;R4
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+NRD3OF_O	CC8oRH"s#;C"
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+NRosCHRFM'NPo'N;
+MHR3#D_OFRO	4N;
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+RoMO_D	b_HMON;
+MOR3D	FORo"PND|O	H_bM
+";N3MROODF	8_Co"CRsCH#"N;
+MHR3#D_OFRO	4N;
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+RoMO_D	b;HM
+RNM3_H#OODF	;R4
+RNM3_H#oCN08D_OFRO	4b;
+R4@@:44::.4:+0.:sRkCfjj:Rk0sCsR0keCRB
+B;NsHRCFoHMPR'o;N'
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+RNHsHCoF'MRP'oN;R
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+SCkoF0D=8$F_OkCM0s9r4R4fm(:njdnc(j
+4RS	OD=	OD_MbH_SO
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+URS08NN8O=DO$_F0kMC4sr9QRf4n4(jg:d(U44Ro;
+bCRso0Fk;b
+oR	OD;b
+NR$3#MH_N_FODO{	R
+RNbP|oNO_D	bRHM{b
+NR#sHC;R4
+
+};}N;
+bHR3#N_o0_C8OODF	;R4
+RNb3_H#OODF	;R4
+Rob8NN0Lo;
+bNR80;NO
+RA44y,4!?5.jj*5?0V:24:5?:fj0R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNC8R"DO$_F0kMC;s"
+RNH3M#$__NHOODF	
+R{NPHRoON|Db	_H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC4GR;H
+NRD3N#O0_ERHMd
+g;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRNUUN"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO	"NPo|	OD_MbH"s;
+R4@@j4:4d::c4:4d6D:8$F_OkCM0s:r4jf9R4j(n:ndccR44q pa)qq_uR XV(Vdj._qqb.RsRHl8_D$OMFk0rCsjS9
+sFCok80=DO$_F0kMCjsr9mRf4j(n:ndccR44
+DSO	D=O	H_bM
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+R;osbRCkoF0o;
+bDRO	N;
+b#R3$NM_HD_OFRO	{b
+NRNPo|	OD_MbHRN{
+bHRs#4CR;;
+}
+
+};N3bRHo#_N80C_FODO4	R;b
+NR#3H_FODO4	R;b
+oR08NN
+L;o8bRNO0N;4
+AR44,y.!5?5j*j:?V0!2:5V4?:j!f2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRD"8$F_OkCM0s
+";N3HR#_$MNOH_D	FORN{
+HoRPND|O	H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rj
+RNH3#ND0E_OHdMRUN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blNR"."N.;H
+NRk3#lk_D0HO_M0bkR
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diff --git a/bsp2/Designflow/syn/rev_1/vga.srr b/bsp2/Designflow/syn/rev_1/vga.srr
new file mode 100644
index 0000000..940092d
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.srr
@@ -0,0 +1,312 @@
+#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
+#install: /opt/synplify/fpga_c200906
+#OS: Linux 
+#Hostname: ti12
+
+#Implementation: rev_1
+
+#Wed Oct 21 17:26:30 2009
+
+$ Start of Compile
+#Wed Oct 21 17:26:30 2009
+
+Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
+Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
+
+@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
+VHDL syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav 
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav 
+Post processing for work.vga_control.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav 
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+Post processing for work.vga_driver.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav 
+Post processing for work.board_driver.behav
+Post processing for work.vga.behav
+@END
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Oct 21 17:26:30 2009
+
+###########################################################]
+Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
+Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
+Product Version C-2009.06
+@N: MF249 |Running in 32-bit mode.
+@N: MF257 |Gated clock conversion enabled 
+@N|Running in logic synthesis mode without enhanced optimization
+
+Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
+Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+@N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":267:4:267:5|Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
+@N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":158:4:158:5|Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
+
+
+
+#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
+
+======================================================================================
+                                Instance:Pin        Generated Clock Optimization Status
+======================================================================================
+
+
+##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
+
+Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
+
+Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
+
+Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 68MB)
+
+
+Writing Analyst data base /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.srm
+Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Writing Verilog Netlist and constraint files
+Writing .vqm output for Quartus
+Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.xrf
+Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Writing VHDL Simulation files
+Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design 
+Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design 
+Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Found clock vga|clk_pin with period 39.72ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Wed Oct 21 17:26:36 2009
+#
+
+
+Top view:               vga
+Requested Frequency:    25.2 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    
+@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 34.458
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock              
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
+----------------------------------------------------------------------------------------------------------------------
+vga|clk_pin        25.2 MHz      190.0 MHz     39.722        5.264         34.458     inferred     Inferred_clkgroup_0
+======================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-----------------------------------------------------------------------------------------------------------------
+Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-----------------------------------------------------------------------------------------------------------------
+vga|clk_pin  vga|clk_pin  |  39.722      34.458  |  No paths    -      |  No paths    -      |  No paths    -    
+=================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+		No IO constraint found 
+
+
+
+====================================
+Detailed Report for Clock: vga|clk_pin
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                           Starting                                                                 Arrival           
+Instance                                   Reference       Type                 Pin        Net                      Time        Slack 
+                                           Clock                                                                                      
+--------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[6]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_6     0.176       34.458
+dly_counter[0]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[0]           0.176       34.465
+dly_counter[1]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[1]           0.176       34.584
+vga_control_unit.toggle_counter_sig[5]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_5     0.176       34.585
+vga_driver_unit.vsync_counter[6]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_6          0.176       34.836
+vga_driver_unit.vsync_counter[7]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_7          0.176       34.865
+vga_control_unit.toggle_counter_sig[8]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_8     0.176       34.921
+vga_driver_unit.vsync_counter[3]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_3          0.176       34.992
+vga_driver_unit.vsync_counter[8]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_8          0.176       34.992
+vga_control_unit.toggle_counter_sig[9]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_9     0.176       35.048
+======================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                           Starting                                                              Required           
+Instance                                   Reference       Type                 Pin      Net                     Time         Slack 
+                                           Clock                                                                                    
+------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[0]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[1]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[2]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[3]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[4]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[5]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[6]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[7]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[8]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+vga_control_unit.toggle_counter_sig[9]     vga|clk_pin     stratix_lcell_ff     sclr     toggle_sig_0_0_0_g1     38.930       34.458
+====================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+    Requested Period:                        39.722
+    - Setup time:                            0.792
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         38.930
+
+    - Propagation time:                      4.472
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     34.458
+
+    Number of logic level(s):                6
+    Starting point:                          vga_control_unit.toggle_counter_sig[6] / regout
+    Ending point:                            vga_control_unit.toggle_counter_sig[0] / sclr
+    The start point is clocked by            vga|clk_pin [rising] on pin clk
+    The end   point is clocked by            vga|clk_pin [rising] on pin clk
+
+Instance / Net                                                                     Pin         Pin               Arrival     No. of    
+Name                                                          Type                 Name        Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[6]                        stratix_lcell_ff     regout      Out     0.176     0.176       -         
+toggle_counter_sig_6                                          Net                  -           -       1.000     -           4         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6      stratix_lcell        dataa       In      -         1.176       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6      stratix_lcell        combout     Out     0.459     1.635       -         
+un1_toggle_counter_siglt6                                     Net                  -           -       0.376     -           1         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9     stratix_lcell        datad       In      -         2.011       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9     stratix_lcell        combout     Out     0.087     2.098       -         
+un1_toggle_counter_siglto9                                    Net                  -           -       0.376     -           1         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12    stratix_lcell        datad       In      -         2.474       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12    stratix_lcell        combout     Out     0.087     2.561       -         
+un1_toggle_counter_siglto12                                   Net                  -           -       0.376     -           1         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15    stratix_lcell        datad       In      -         2.938       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15    stratix_lcell        combout     Out     0.087     3.025       -         
+un1_toggle_counter_siglto15                                   Net                  -           -       0.376     -           1         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18    stratix_lcell        datad       In      -         3.401       -         
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18    stratix_lcell        combout     Out     0.087     3.488       -         
+un1_toggle_counter_siglto18                                   Net                  -           -       0.376     -           1         
+vga_control_unit.toggle_sig_0_0_0_g1                          stratix_lcell        datad       In      -         3.864       -         
+vga_control_unit.toggle_sig_0_0_0_g1                          stratix_lcell        combout     Out     0.087     3.951       -         
+toggle_sig_0_0_0_g1                                           Net                  -           -       0.521     -           22(6)     
+vga_control_unit.toggle_counter_sig[0]                        stratix_lcell_ff     sclr        In      -         4.472       -         
+=======================================================================================================================================
+Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.264 is 1.862(35.4%) logic and 3.402(64.6%) route.
+Fanout format: logic fanout (physical fanout)
+Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
+*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
+
+
+
+##### END OF TIMING REPORT #####]
+
+##### START OF AREA REPORT #####[
+Design view:work.vga(behav)
+Selecting part EP1S25F672C6
+@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
+
+I/O ATOMs:       117
+
+Total LUTs:  179 of 25660 ( 0%)
+Logic resources:  181 ATOMs of 25660 ( 0%)
+
+Number of I/O registers
+			Output DDRs   :0
+
+ATOM count by mode:
+  normal:       128
+  arithmetic:   53
+
+DSP Blocks:     0  (0 nine-bit DSP elements).
+DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
+ShiftTap:       0  (0 registers)
+MRAM:           0  (0% of 2)
+M4Ks:           0  (0% of 138)
+M512s:          0  (0% of 224)
+Total ESB:      0 bits 
+
+ATOMs using regout pin: 88
+  also using enable pin: 12
+  also using combout pin: 1
+ATOMs using combout pin: 91
+Number of Inputs on ATOMs: 760
+Number of Nets:   54954
+
+##### END OF AREA REPORT #####]
+
+Mapper successful!
+Process took 0h:00m:05s realtime, 0h:00m:04s cputime
+# Wed Oct 21 17:26:36 2009
+
+###########################################################]
diff --git a/bsp2/Designflow/syn/rev_1/vga.srs b/bsp2/Designflow/syn/rev_1/vga.srs
new file mode 100644
index 0000000..f131007
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.srs
@@ -0,0 +1,685 @@
+%%% protect protected_file
+@E
+@ 
+#
+#
+#
+# Created by Synplify VHDL Compiler version comp400rc, Build 020R from Synplicity, Inc.
+# Copyright 1994-2009 Synopsys, Inc. , All rights reserved.
+# Synthesis Netlist written on Wed Oct 21 17:23:09 2009
+#
+#
+#OPTIONS:"|-top|vga|-infer_seqShift|-primux|-fixsmult|-dspmac|-nram|-divnmod|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|on|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplify/fpga_c200906/linux/c_vhdl":1242928055
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/location.map":1242864830
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":1242776237
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":1255952276
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd":1242776237
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd":1242776237
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/arith.vhd":1242776237
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":1256135047
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd":1256135072
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd":1256138582
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":1256135040
+f "/opt/synplify/fpga_c200906/lib/vhd/std.vhd"; # file 0
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd"; # file 1
+af .is_vhdl 1;
+f "/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd"; # file 2
+af .is_vhdl 1;
+f "/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd"; # file 3
+af .is_vhdl 1;
+f "/opt/synplify/fpga_c200906/lib/vhd/arith.vhd"; # file 4
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd"; # file 5
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd"; # file 6
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd"; # file 7
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd"; # file 8
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd"; # file 9
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd"; # file 10
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd"; # file 11
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd"; # file 12
+af .is_vhdl 1;
+@E
+@ 
+ftell;
+@E@MR@dn:n::(d4n:UFRIsL	RF8Ns_H8sPRCsLNCEPN;
+PHR3#8PED;R4
+RNP3_H#PDE8R
+4;N3PRFosHhCNlRF"LN_s88PsHC;s"
+RNP#_$Mb#sCCCsPR
+4;
+@HR@dn:g::Ud4g:.CRs#RC0sCC#0N;
+HsR30FD_sMHoNRlC"#sCC;0"
+@FR@cn:j::Uc4j:nCR#P_CM#rCo4jd:9sR0k8C,H0oH_VDC09rj,o8HHD0_CrV0j89,H0oH_VDC09rj,o8HHD0_CrV0j89,H0oH_VDC09rj,o8HHD0_CrV0j09,s,kC0Csk,k0sCs,0k8C,H0oH_VDC09rj,o8HHD0_CrV0j09,s;kC
+RNH3Ds0_HFsolMNC#R"CMPC_o#C"b;
+Rj@@:44::.4:Rk0sCsR0k0CRs;kC
+@bR@4j::44::V.RNCD#RDVN#VCRNCD#;R
+b@j@4::ndcd:n:l6Rk8GRH0oH_VDC09rjRo8HHD0_CrV0j09RsRkCV#NDCCRs#;C0
+-y---------------------------------
+
+@ 
+ftell;
+@E@MR@dU:(::(d4(:nFRIsP	Ro8N_sCHPsCRLE;NP
+RNP3PH#ER8D4N;
+PHR3#E_P84DR;P
+NRs3FHNohl"CRP_oN8PsHC;s"
+RNP#_$Mb#sCCCsPR
+4;
+@HR@dU:U::(dgU:R	ODR	OD;H
+NR03sDs_FHNoMl"CRO"D	;
+
+
+
+@HR@dU:g::(d4g:4CRs#RC0sCC#0N;
+HsR30FD_sMHoNRlC"#sCC;0"
+@FR@cU:j::(c.j:jFRODMkl_kOFMs0Crjg:9FRODMkl_kOFMs0C_o#Hrjg:9N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0"Cs;
+
+
+
+@FR@cU:4::(c44:UHRDMOC_F0kMCUsr:Rj9DCHM_kOFMs0C_o#HrjU:9N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0s
+";
+@FR@cU:.::(c4.:c_RECLMNDECR_NCML_DC#;Ho
+RNH3Ds0_HFsolMNCER"_NCML"DC;
+
+
+
+@FR@cU:d::(c4d:c_RPCLMNDPCR_NCML_DC#;Ho
+RNH3Ds0_HFsolMNCPR"_NCML"DC;
+
+
+
+@FR@cU:c::(c4c:4#RE$RMOE$_#M
+O;N3HRs_0DFosHMCNlR#"E$"MO;
+
+
+
+@FR@cU:cc:4::cc4PUR#O$MR#P_$;MO
+RNH3Ds0_HFsolMNCPR"#O$M"
+;
+
+@FR@cU:n::(c4n:g_R8EM#$O0_#Nr0Cj9:nR$E#M#O_0CN0rnj:9N;
+HsR30FD_sMHoNRlC"E8_#O$M_N#00;C"
+@FR@cU:(::(c4(:g_R8PM#$O0_#Nr0Cj9:nR$P#M#O_0CN0rnj:9N;
+HsR30FD_sMHoNRlC"P8_#O$M_N#00;C"
+@FR@cU:U::(c.U:4_R8EM#$OF_OkCM0s:rgjE9R#O$M_kOFMs0Crjg:9N;
+HsR30FD_sMHoNRlC"E8_#O$M_kOFMs0C"
+;
+
+@FR@cU:g::(c.g:4_R8PM#$OF_OkCM0s:rgjP9R#O$M_kOFMs0Crjg:9N;
+HsR30FD_sMHoNRlC"P8_#O$M_kOFMs0C"
+;
+
+@FR@6U:j::(6.j:6_R8#_C0EM#$OF_OkCM0s_R8#_C0EM#$OF_OkCM0sN;
+HsR30FD_sMHoNRlC"#8_CE0_#O$M_kOFMs0C"
+;
+
+@FR@6U:4::(6.4:6_R8#_C0PM#$OF_OkCM0s_R8#_C0PM#$OF_OkCM0sN;
+HsR30FD_sMHoNRlC"#8_CP0_#O$M_kOFMs0C"
+;
+
+@FR@6U:.::(6..:n_R8#_C0OkFDlOM_F0kMC8sR_0#C_DOFk_lMOMFk0;Cs
+RNH3Ds0_HFsolMNC8R"_0#C_DOFk_lMOMFk0"Cs;
+
+
+
+@FR@6U:d::(6.d:c_R8#_C0DCHM_kOFMs0CR#8_CD0_H_MCOMFk0;Cs
+RNH3Ds0_HFsolMNC8R"_0#C_MDHCF_OkCM0s
+";b@R@Ug:d:d(:g4:4RPHMR4kM_#sCCk0RMs4_C0#CR#sCC
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+@bR@:4..:jj4.g:j.j:6MRHPMRk4#_E$_MOOMFk0rCsg9:.R4kM_$E#MOO_F0kMCgsr:R.9EM#$OF_OkCM0s:rg.
+9;b@R@4..:c4d:Uc:.dc:.RPHMR4kM_$E#M#O_0CN0r6.:9MRk4#_E$_MO#00NC:r.6E9R#O$M_N#00.Cr:;69
+@bR@:4..:cUcc:.UR:(LRkV8C_#0F_ODMkl_kOFMs0CR#8_CO0_FlDkMF_OkCM0s#RE$_MO#00NC9r4;R
+b@.@4:U.c:.c:c(U:RPHMRDOFk_lMOMFk0_CsM0CG4OjRFlDkMF_OkCM0sC_MGj04R$E#M#O_0CN0r;49
+@bR@:4.d:4d4dg:4.d:6MRHPMRk4#_P$_MOOMFk0rCsg9:jR4kM_$P#MOO_F0kMCgsr:Rj9PM#$OF_OkCM0s:rgj
+9;b@R@4d.:64n:U6:dnc:.RPHMR4kM_$P#M#O_0CN0r6.:9MRk4#_P$_MO#00NC:r.6P9R#O$M_N#00.Cr:;69
+@bR@:4.d:n4cn:d4R:(LRkV8C_#0H_DMOC_F0kMC8sR_0#C_MDHCF_OkCM0s#RP$_MO#00NC9r4;R
+b@.@4:4dn:dc:n(4:RPHMRMDHCF_OkCM0sC_MGd04RMDHCF_OkCM0sC_MGd04R$P#M#O_0CN0r;49
+@bR@4j::44::0.RsRkC0CskRk0sCb;
+Rj@@:44::.4:RDVN#VCRNCD#RDVN#
+C;b@R@4g.:(::cg6(:R8NMP#RE$_MO#00NCC_MGc0__l#JkRGNEM#$O0_#N_0CM0CG_#c_JGlkNCRs#
+C0RRRREM#$O0_#Nr0C4
+9;b@R@4g.:(::cg6(:R8NMP#RP$_MO#00NCC_MGc0__l#JkRGNPM#$O0_#N_0CM0CG_#c_JGlkNCRs#
+C0RRRRPM#$O0_#Nr0C4
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+RsRRC0#CR$E#M#O_0CN0r;49
+@bR@:4.4:dn(d:4n4:dR8NMPHRDMOC_F0kMCMs_C_G0jJ_#lNkGRMDHCF_OkCM0sC_MGj0__l#Jk
+GNRRRRsCC#0#RP$_MO#00NC9r4;R
+b@.@4:n.j:.c:j(n:RPFsR4kM_$E#M#O_0CN0_k4RME4_#O$M_N#004C_R$E#M#O_0CN0rRn9EM#$O0_#Nr0Cj
+9;b@R@4..:jcn::n.j:F(RskPRME4_#O$M_N#00.C_R4kM_$E#M#O_0CN0_E.R#O$M_N#00dCr9#RE$_MO#00NC9r4;R
+b@.@4:n.j:.c:j(n:RPFsR4kM_$E#M#O_0CN0_kdRME4_#O$M_N#00dC_R$E#M#O_0CN0rR49EM#$O0_#Nr0CdR9
+RERR#O$M_N#00.Cr9b;
+R4@@.j:.n::c.:jn(sRFPMRk4#_E$_MO#00NCR_ck_M4EM#$O0_#N_0Cc#RE$_MO#00NC9r6R$E#M#O_0CN0r;c9
+@bR@:4.d:4gc4:dgR:(FRsPk_M4PM#$O0_#N_0C4MRk4#_P$_MO#00NCR_4PM#$O0_#Nr0CnP9R#O$M_N#00jCr9b;
+R4@@.4:dg::cd:4g(sRFPMRk4#_P$_MO#00NCR_.k_M4PM#$O0_#N_0C.#RP$_MO#00NC9r4R$P#M#O_0CN0r
+d9RRRRPM#$O0_#Nr0C.
+9;b@R@4d.:4cg::gd4:F(RskPRMP4_#O$M_N#00dC_R4kM_$P#M#O_0CN0_PdR#O$M_N#00dCr9#RP$_MO#00NC9r4;R
+b@.@4:gd4:dc:4(g:RPFsR4kM_$P#M#O_0CN0_kcRMP4_#O$M_N#00cC_R$P#M#O_0CN0rR69PM#$O0_#Nr0Cc
+9;b@R@44.:j(U::U4j:RddNPM8RDOFk_lMOMFk0_CsM0CG_#4_JGlkNFRODMkl_kOFMs0C_GMC0__4#kJlGRN
+RsRRC0#CRDOFk_lMOMFk0_CsM0CG4
+j;b@R@44.:d(n::n4d:Rd4NPM8RMDHCF_OkCM0sC_MG40__l#JkRGNDCHM_kOFMs0C_GMC0__4#kJlGRN
+RsRRC0#CRMDHCF_OkCM0sC_MGd04;R
+b@.@4:n.j:.c:j(n:RPHMR4kM_$E#M#O_0CN0_k6RME4_#O$M_N#006C_R4kM_$E#M#O_0CN0_
+c;b@R@4..:jcn::n.j:H(RMkPRME4_#O$M_N#00nC_R4kM_$E#M#O_0CN0_knRME4_#O$M_N#00dC_;R
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+R4@@.j:d4::nd:j4(MRHPMRk4C_s#_C0.MRk4C_s#_C0.MRk4C_s#_C04b;
+R4@@.(:g:gc:(R:68RVVOkFDlOM_F0kMC#s_Hgor:Rj9OkFDlOM_F0kMC#s_Hgor:Rj9BzmpvBh_mazh_M#$\F3ODMkl_kOFMs0C_o#H_gdr:
+j9RRRRO;D	
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"b;
+R4@@.U:4U::n4:UU(lRbkEGR#O$M_N#00dC_r6j:9#RE$_MO#00NCr_dj9:6R$E#M#O_0CN0r6j:9#,E$_MO#00NCC_MG.0__l#Jk
+GNRRRREM#$O0_#N_0CO0M#r6j:9M,k4#_E$_MO#00NCC_MG.0__l#Jk;GN
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+RR#RP$_MO#00NCM_O#.0r:,69k_M4PM#$O0_#N_0CM0CG_#._JGlkNb;
+R4@@.c:444:d:44c:R6.NR88k_M4DCHM_kOFMs0C_o#Hr4g:9MRk4H_DMOC_F0kMC#s_Hgor:R49DCHM_kOFMs0C_o#HrjU:9R
+RR_R8#_C0EM#$OF_OkCM0sb;
+R4@@.U:.d.:d:d.U:R6jNR88k_M4PM#$OF_OkCM0sr_444j:9MRk4#_P$_MOOMFk0_Cs4jr4:R49PM#$OF_OkCM0s:rgjR9
+R8RR_0#C_$E#MOO_F0kMC
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+j9RRRRV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#Ck_M4sCC#0R
+RRNRVD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDC#,E$_MOOMFk0_CsM0CG_#j_JGlkNR
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+@bR@:4.4:U(cU:4(R:68RVVEM#$O0_#Nr0Cj9:nR$E#M#O_0CN0rnj:9#RE$_MO#00NCr_dj9:6,4kM_#sCCR0
+RORRD
+	;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$E#M#O_0CN0"b;
+R4@@.6:4U::c4:6U6VR8V#RE$_MOOMFk0rCsg9:jR$E#MOO_F0kMCgsr:Rj9]h1YBm_Bz_ha#\$M3$E#MOO_F0kMCds_rjg:9R
+RRDRO	N;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";b@R@44.:Uc(::(4U:#6R8#VVC_RE#O$MR#E_$RMOEM#$O0_#Nr0CcO9RDk	RMs4_C0#CR4kM_$E#M#O_0CN0_
+n;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"#E_$"MO;R
+b@.@4:4dj:dn:j(4:RkblG#RP$_MO#00NCr_djP9R#O$M_N#00dC_rRj9V#NDCM,k4C_s#_C0.#RP$_MO#00NC9rj,$P#M#O_0CN0_GMC0__.#kJlGRN
+R0RRs,kCPM#$O0_#N_0CM0CG_#n_JGlkNb;
+R4@@..:4n::n4:.n(lRbkpGRQ_h Bhmza$_#MD\3H_MCOMFk0_Cs#_Hod:rUjp9RQ_h Bhmza$_#MD\3H_MCOMFk0_Cs#_Hod:rUjR9
+RVRRNCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,4kM_#sCCV0RNCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,MDHCF_OkCM0sC_MGj0__l#Jk
+GNRRRRk_M4DCHM_kOFMs0C_o#Hr4g:9H,DMOC_F0kMCMs_C_G0jJ_#lNkG_04Rs,kC0Csk,k0sCN,VD,#C0Csk,k0sCs,0k0C,s,kC0Csk,MDHCF_OkCM0sC_MG40__l#Jk_GN4b;
+R4@@.n:.U::n.:nU(lRbkeGR1BYh_zBmh#a_$3M\PM#$OF_OkCM0sr_dg9:jRYe1hBB_mazh_M#$\#3P$_MOOMFk0_Csd:rgjR9
+RVRRNCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#kC,Ms4_C0#C
+RRRRDVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,$P#MOO_F0kMCMs_C_G0jJ_#lNkG
+RRRR4kM_$P#MOO_F0kMC4s_r:4j4P9,#O$M_kOFMs0C_GMC0__j#kJlG4N_Rk0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0kPC,#O$M_kOFMs0C_GMC0__4#kJlG4N_;R
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+RORRD
+	;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#M#O_0CN0"b;
+R4@@..:46::c4:.66VR8VHRDMOC_F0kMC#s_HUor:Rj9DCHM_kOFMs0C_o#HrjU:9QRphB _mazh_M#$\H3DMOC_F0kMC#s_Hdo_rjU:9R
+RRDRO	N;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRDCHM_kOFMs0C_o#H"b;
+R4@@.n:.(::c.:n(6VR8V#RP$_MOOMFk0rCsg9:jR$P#MOO_F0kMCgsr:Rj9eh1YBm_Bz_ha#\$M3$P#MOO_F0kMCds_rjg:9R
+RRDRO	N;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$OF_OkCM0s
+";b@R@4d.:jcj::jdj:#6R8#VVC_RP#O$MR#P_$RMOPM#$O0_#Nr0CcO9RDk	RMs4_C0#CR4kM_$P#M#O_0CN0_
+n;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"#P_$"MO;-
+y--------------------------------- 
+@
+ftell;
+@E@MR@d(:(::(d4(:(FRIsP	RoON_FsM0FLDRCPEN;P
+NR#3HPDE8R
+4;N3PRHP#_ER8D4N;
+PFR3shHoNRlC"NPo_MOF0DsF"N;
+P$R#Ms_bCs#CP4CR;
+
+
+
+@HR@d(:U::(dgU:R	ODR	OD;H
+NR03sDs_FHNoMl"CRO"D	;
+
+
+
+@HR@d(:g::(d4g:4CRs#RC0sCC#0N;
+HsR30FD_sMHoNRlC"#sCC;0"
+@HR@c(:j::(c.j:jFRODMkl_kOFMs0Crjg:9FRODMkl_kOFMs0Crjg:9N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0"Cs;
+
+
+
+@FR@c(:4::(c.4:jFR0oCoD_kOFMs0Cr:.cj09RFDooCF_OkCM0sH_#ocr.:;j9
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0s
+";
+@FR@c(:.::(c4.:.FR0oCoDRo0Fo_DC#;Ho
+RNH3Ds0_HFsolMNC0R"FDooC
+";
+@HR@c(:d::(c4d:UHRDMOC_F0kMCUsr:Rj9DCHM_kOFMs0CrjU:9N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0s
+";
+@HR@c(:c::(c4c:c_RPCLMNDPCR_NCML;DC
+RNH3Ds0_HFsolMNCPR"_NCML"DC;
+
+
+
+@HR@c(:6::(c46:c_RECLMNDECR_NCML;DC
+RNH3Ds0_HFsolMNCER"_NCML"DC;
+
+
+
+@FR@c(:n::(c(n:RssR;H
+NR03sDs_FHNoMl"CRs
+";
+@FR@c(:nj:4::cn4ojRR
+o;N3HRs_0DFosHMCNlR""o;
+
+
+
+@FR@c(:nd:4::cn4LdRR
+L;N3HRs_0DFosHMCNlR""L;R
+b@:@(d(g:::dg4H4RMkPRMs4_C0#CR4kM_#sCCs0RC0#C;R
+b@4@4::ggcg:g:H6RMLPR_GMC0_RLM0CGRo0Fo_DC#;Ho
+@bR@4j::44::0.RsRkC0CskRk0sCb;
+Rj@@:44::.4:RDVN#VCRNCD#RDVN#
+C;b@R@4n4:j::cn6j:RV8VsRRooNRVDR#CORD	k_M4sCC#0N;
+HsR30FD_sMHoNRlC";o"
+RNH#_$Mb#sCCCsPR
+4;b@R@4(4:6U:d::(6nDjR0)R7q1W_T)zq C_MG30\k_M6PM_CNCLDRq7)WT_1z q)_GMC0k\3MP6__NCML
+DCRRRRV#NDCN,VD,#C0Csk,k0sCN,VD,#CV#NDCs,0kVC,NCD#,DVN#VC,NCD#RDOFk_lMOMFk0rCsg9:j;R
+b@4@4::(64(j:6.:dRRD07W)q_z1Tq_) M0CG\M3kg__PCLMND7CR)_qW1qTz)M _C\G03gkM_CP_MDNLCR
+RRFRODMkl_kOFMs0Crjg:9NRVD,#CV#NDCN,VD,#C0Csk,k0sCN,VD,#CV#NDCs,0kVC,NCD#,DVN#
+C;b@R@4(4:nj:4::(ndD.R0)R7q1W_T)zq C_MG30\kdM4_CP_MDNLC)R7q1W_T)zq C_MG30\kdM4_CP_MDNLCR
+RRHRDMOC_F0kMCUsr:Rj9V#NDCN,VD,#C0Csk,k0sCN,VD,#CV#NDCs,0kVC,NCD#,DVN#
+C;b@R@4(4:nU:d::(nnDjR0)R7q1W_T)zq C_MG30\k(M4_CP_MDNLC)R7q1W_T)zq C_MG30\k(M4_CP_MDNLCR
+RRNRVD,#C0Csk,k0sCN,VD,#CV#NDCs,0kVC,NCD#,DVN#VC,NCD#RMDHCF_OkCM0s:rUj
+9;b@R@4(4:6U:d::(6nHjRMkPRMPn__NCMLRDCk_MnPM_CNCLDRq7)WT_1z q)_GMC0k\3MP6__NCML;DC
+@bR@:44(46:j6:(:Rd.HRMPkjM4_CP_MDNLCMRk4Pj__NCMLRDC7W)q_z1Tq_) M0CG\M3kg__PCLMND
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+R4@@44:44::(4:44dHURMkPRM04_FDooCF_OkCM0sH_#oMRk4F_0oCoD_kOFMs0C_o#HRQAph)i _GMC0k\3M04_FDooCF_OkCM0sH_#ob;
+R4@@4g:g:gc:gR:68sVVCFR0oCoD_o#HRo0Fo_DC#RHoLC_MGO0RDk	RMs4_C0#CR4kM_o0Fo_DCOMFk0_Cs#;Ho
+RNH3Ds0_HFsolMNC0R"FDooCH_#o
+";N#HR$bM_sCC#sRPC4b;
+R4@@46:(::4j(nn:jMRN8LPR_GMC0__j#kJlGLNR_GMC0__j#kJlGPNR_NCMLRDCEM_CNCLDRnkM_CP_MDNLCR
+RRMRk4Pj__NCMLRDCkcM4_CP_MDNLCMRk4PU__NCML;DC
+@bR@:444:46.4g:466:.8RN8MRk.F_0oCoD_kOFMs0C_GMC0jr.:Rj9k_M.0oFoDOC_F0kMCMs_CrG0.jj:9R
+RRFR0oCoD_kOFMs0C_o#Hr:.jj09Rs;kC
+@bR@:44(cc:::(c6kRlG_RLM0CG_L4R_GMC0R_4V#NDC_RLM0CGRML_C_G0jJ_#lNkG;R
+b@4@4::(ccc:(:l6RksGR_GMC0_RsM0CGRDVN#0CRFDooCH_#o_RLM0CG_#j_JGlkNb;
+R4@@44:44::c4:446kRlGFR0oCoD_kOFMs0C_GMC0jr.:Rj90oFoDOC_F0kMCMs_CrG0.jj:9NRVD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD
+#CRRRRk_M.0oFoDOC_F0kMCMs_CrG0.jj:9pRAQ hi)C_MG30\k_M40oFoDOC_F0kMC#s_H
+o;b@R@4n4:j::cn6j:RV8VsRRLL_RLM0CG_O4RDk	RMs4_C0#C;H
+NR03sDs_FHNoMl"CRL
+";N#HR$bM_sCC#sRPC4b;
+R4@@4j:n:nc:jR:68sVVRssRRMs_CRG0ORD	k_M4sCC#0N;
+HsR30FD_sMHoNRlC";s"
+RNH#_$Mb#sCCCsPR
+4;b@R@4g4:g::cg6g:RV8VsFR0oCoD_kOFMs0C_o#Hr:.cj09RFDooCF_OkCM0sH_#ocr.:Rj9V#NDCN,VD,#CV#NDCN,VD,#C0oFoDOC_F0kMCMs_CrG0.jj:9R
+RRDRO	MRk4C_s#;C0
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4y;
+---------------------------------@-
+ 
+
+
+
+ftell;
+@E@MR@d6:U::(dgU:RsIF	oRPNCRLE;NP
+RNP3PH#ER8D4N;
+PHR3#E_P84DR;P
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+Is\	R"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8
+\"I	FsR/\"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oNN3sOP\E8"F
+Is\	R"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#OF/LN_s88PsHCCs_MP03E"8\
+sIF	"R\/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8
+\"I	FsR/\"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oNO0FMs_FDC3M0P\E8"F
+Is\	R"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNF_OMF0sDs_NOE3P8
+\"I	FsR/\"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCCs_MP03E"8\
+sIF	"R\/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsN3sOP\E8";
+"
+RNP#_$Mb#sCCCsPR
+4;
+@HR@c6:4::(c44:dDRO	H_bMDRO	H_bMN;
+HsR30FD_sMHoNRlC"	OD_MbH"
+;
+
+@HR@c6:.::(c4.:6CRs#_C0bRHMsCC#0H_bMN;
+HsR30FD_sMHoNRlC"#sCCb0_H;M"
+@FR@c6:c::(c4c:.jRs_MbHR_sjb;HM
+RNH3Ds0_HFsolMNCsR"jH_bM
+";
+@FR@c6:c6:4::cc.sjR4H_bM4Rs_MbH;H
+NR03sDs_FHNoMl"CRsb4_H;M"
+@FR@c6:cd:.::cc.sUR.H_bM.Rs_MbH;H
+NR03sDs_FHNoMl"CRsb._H;M"
+@FR@c6:6::(c46:.jRo_MbHR_ojb;HM
+RNH3Ds0_HFsolMNCoR"jH_bM
+";
+@FR@c6:66:4::c6.ojR4H_bM4Ro_MbH;H
+NR03sDs_FHNoMl"CRob4_H;M"
+@FR@c6:6d:.::c6.oUR.H_bM.Ro_MbH;H
+NR03sDs_FHNoMl"CRob._H;M"
+@FR@c6:n::(c4n:.jRL_MbHR_Ljb;HM
+RNH3Ds0_HFsolMNCLR"jH_bM
+";
+@FR@c6:n6:4::cn.LjR4H_bM4RL_MbH;H
+NR03sDs_FHNoMl"CRLb4_H;M"
+@FR@c6:(::(c4(:6#RE$_MObRHMEM#$OH_bMN;
+HsR30FD_sMHoNRlC"$E#MbO_H;M"
+@FR@c6:U::(c4U:6#RP$_MObRHMPM#$OH_bMN;
+HsR30FD_sMHoNRlC"$P#MbO_H;M"
+@FR@66:j::(64j:gCR#P_CM#_CobrHM4jd:9CR#P_CM#_CobrHM4jd:9N;
+HsR30FD_sMHoNRlC"P#CC#M_Cbo_H;M"
+@FR@66:.::(64.:d_R8EM#$O_R8EM#$ON;
+HsR30FD_sMHoNRlC"E8_#O$M"
+;
+
+@FR@66:.n:4::6..8.R_$P#M8OR_$P#M
+O;N3HRs_0DFosHMCNlR_"8PM#$O
+";
+@FR@66:d::(6.d:._R8OkFDlOM_F0kMCgsr:Rj98F_ODMkl_kOFMs0Crjg:9N;
+HsR30FD_sMHoNRlC"O8_FlDkMF_OkCM0s
+";
+@FR@66:c::(6.c:j_R8DCHM_kOFMs0CrjU:9_R8DCHM_kOFMs0CrjU:9N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;
+
+
+
+@FR@66:6::(6.6:n_R8#_C0OkFDlOM_F0kMC8sR_0#C_DOFk_lMOMFk0;Cs
+RNH3Ds0_HFsolMNC8R"_0#C_DOFk_lMOMFk0"Cs;
+
+
+
+@FR@66:6g:.::66c8nR_0#C_MDHCF_OkCM0s_R8#_C0DCHM_kOFMs0C;H
+NR03sDs_FHNoMl"CR8C_#0H_DMOC_F0kMC;s"
+@FR@66:n::(6.n:4_R8EM#$OF_OkCM0s:rgj89R_$E#MOO_F0kMCgsr:;j9
+RNH3Ds0_HFsolMNC8R"_$E#MOO_F0kMC;s"
+@FR@66:(::(6.(:4_R8PM#$OF_OkCM0s:rgj89R_$P#MOO_F0kMCgsr:;j9
+RNH3Ds0_HFsolMNC8R"_$P#MOO_F0kMC;s"
+@FR@66:U::(6.U:6_R8#_C0EM#$OF_OkCM0s_R8#_C0EM#$OF_OkCM0sN;
+HsR30FD_sMHoNRlC"#8_CE0_#O$M_kOFMs0C"
+;
+
+@FR@66:UU:.::6Uc8nR_0#C_$P#MOO_F0kMC8sR_0#C_$P#MOO_F0kMC
+s;N3HRs_0DFosHMCNlR_"8#_C0PM#$OF_OkCM0s
+";
+@FR@66:g::(64g:n_R8EM_CNCLDRE8__NCML;DC
+RNH3Ds0_HFsolMNC8R"_CE_MDNLC
+";
+@FR@n6:j::(n4j:n_R8PM_CNCLDRP8__NCML;DC
+RNH3Ds0_HFsolMNC8R"_CP_MDNLC
+";
+@FR@n6:4::(ng4:Rs8_Rs8_;H
+NR03sDs_FHNoMl"CR8"_s;
+
+
+
+@FR@n6:4.:4::n448cR_8oR_
+o;N3HRs_0DFosHMCNlR_"8o
+";
+@FR@n6:4(:4::n448gR_8LR_
+L;N3HRs_0DFosHMCNlR_"8L
+";
+@FR@n6:.::(n4.:g_R8EM#$O0_#Nr0Cj9:nRE8_#O$M_N#00jCr:;n9
+RNH3Ds0_HFsolMNC8R"_$E#M#O_0CN0"
+;
+
+@FR@n6:d::(n4d:g_R8PM#$O0_#Nr0Cj9:nRP8_#O$M_N#00jCr:;n9
+RNH3Ds0_HFsolMNC8R"_$P#M#O_0CN0"
+;
+
+@FR@n6:c::(n4c:(_R8#00NCD_O	_R8#00NCD_O	N;
+HsR30FD_sMHoNRlC"#8_0CN0_	OD"
+;
+
+@FR@n6:6::(n46:c_R80oFoD8CR_o0Fo;DC
+RNH3Ds0_HFsolMNC8R"_o0Fo"DC;
+
+
+
+@FR@n6:n::(n.n:._R80oFoDOC_F0kMC.src9:jR08_FDooCF_OkCM0scr.:;j9
+RNH3Ds0_HFsolMNC8R"_o0Fo_DCOMFk0"Cs;R
+s@:@g4:66j6:46n:4RsIF	FRLN_s88PsHCLsRCPENRNLFs88_sCHPsM_kHS0
+sCC#0N=#VsC_C0#C
+CS#P_CM#rCo4jd:9C=#P_CM#_CobrHM4jd:9s;
+Rg@@:44n:4j:n44:cFRIsP	Ro8N_sCHPsCRLERNPP_oN8PsHCks_M
+H0S	OD=	OD_MbH
+CSs#=C0#CNV_#sCCS0
+OkFDlOM_F0kMCgsr:=j98F_ODMkl_kOFMs0Crjg:9D
+SH_MCOMFk0rCsU9:j=D8_H_MCOMFk0rCsU9:j
+_SECLMND8C=_CE_MDNLCP
+S_NCML=DC8__PCLMNDSC
+EM#$O#=E$_MO#
+HoS$P#MPO=#O$M_o#H
+_S8EM#$O0_#Nr0Cj9:n=E8_#O$M_N#00jCr:
+n9SP8_#O$M_N#00jCr:=n98#_P$_MO#00NC:rjnS9
+8#_E$_MOOMFk0rCsg9:j=E8_#O$M_kOFMs0Crjg:98
+S_$P#MOO_F0kMCgsr:=j98#_P$_MOOMFk0rCsg9:j
+_S8#_C0EM#$OF_OkCM0s_=8#_C0EM#$OF_OkCM0s8
+S_0#C_$P#MOO_F0kMC8s=_0#C_$P#MOO_F0kMCSs
+8C_#0F_ODMkl_kOFMs0C=#8_CO0_FlDkMF_OkCM0s8
+S_0#C_MDHCF_OkCM0s_=8#_C0DCHM_kOFMs0C;R
+s@:@g4:Un.U:4n(:4RsIF	oRPNF_OMF0sDCRLERNPP_oNO0FMs_FDk0MH
+DSO	D=O	H_bMs
+SC0#C=V#NCC_s#
+C0SDOFk_lMOMFk0rCsg9:j=O8_FlDkMF_OkCM0s:rgjS9
+0oFoDOC_F0kMC.src9:j=08_FDooCF_OkCM0scr.:
+j9So0Fo=DC8F_0oCoD
+HSDMOC_F0kMCUsr:=j98H_DMOC_F0kMCUsr:
+j9SCP_MDNLC_=8PM_CNCLD
+_SECLMND8C=_CE_MDNLCs
+S=#s_HSo
+o_=o#
+HoSLL=_o#H;R
+b@:@6c(4:::c44LdRk8VR_N#00OC_D8	R_N#00OC_DO	RDb	_H
+M;b@R@6.:c:c(:.6:4RPHMR4kM_#sCCb0_HkMRMs4_C0#C_MbHR#sCCb0_H
+M;b@R@gn:4gU:.:g4n:RdnLRkV8#_E$RMO8#_E$RMOEM#$OH_#ob;
+Rg@@:g4n::.U4:ngdLnRkEVR#O$M_MbHR$E#MbO_HEMR#O$M_o#H;R
+b@:@g4:(j.4U:(dj:nkRLV_R8PM#$O_R8PM#$O#RP$_MO#;Ho
+@bR@4g:(.j:U(:4jn:dRVLkR$P#MbO_HPMR#O$M_MbHR$P#M#O_H
+o;b@R@gg:4nc:.:n4g:R.ULRkV8R_s8R_ssH_#ob;
+Rg@@:n4g::.c4:gn.LURksVRjH_bMjRs_MbHR#s_H
+o;b@R@gg:4nc:.:n4g:R.ULRkVsb4_HsMR4H_bM_Rs#;Ho
+@bR@4g:g.n:cg:4nU:.RVLkR_s.bRHMsb._HsMR_o#H;R
+b@:@g4:g(.4c:g.(:UkRLV_R8o_R8o_Ro#;Ho
+@bR@4g:g.(:cg:4(U:.RVLkR_ojbRHMobj_HoMR_o#H;R
+b@:@g4:g(.4c:g.(:UkRLV4Ro_MbHR_o4bRHMoH_#ob;
+Rg@@:(4g::.c4:g(.LURkoVR.H_bM.Ro_MbHR#o_H
+o;b@R@gg:4Uc:.:U4g:R.ULRkVLbj_HLMRjH_bM_RL#;Ho
+@bR@4g:g.U:cg:4UU:.RVLkR_L4bRHMLb4_HLMR_o#H;R
+b@:@g4:gU.4c:g.U:UkRLV_R8L_R8L_RL#;Ho
+@bR@4j::44::0.RsRkC0CskRk0sCb;
+Rj@@:44::.4:RDVN#VCRNCD#RDVN#
+C;b@R@g.:4.j:4:.4.:RdjD70R Ypq_1)  Ma_C\G036kM_$8D_kOFMs0CRp7 q)Y_ a1 _GMC0k\3M86_DO$_F0kMCRs
+R8RRDO$_F0kMC4sr:Rj90Csk,k0sCb;
+Rg@@:.4.::4j4:..dFjRs7PR Ypq_1)  Ma_C\G03nkM_$8D_kOFMs0CRp7 q)Y_ a1 _GMC0k\3M8n_DO$_F0kMCRs
+RkRRMs4_C0#C_MbHRp7 q)Y_ a1 _GMC0k\3M86_DO$_F0kMC
+s;b@R@g.:4dn:.:d4.:Rc.NR88k_M48_D$OMFk0rCs.9:4R4kM_$8D_kOFMs0Cr4.:9DR8$F_OkCM0s:r4jR9
+R7RR Ypq_1)  Ma_C\G036kM_$8D_kOFMs0C;R
+b@:@g4:c.cc:4.R:6lRkG#CNV_#sCC#0RN_VCsCC#0sR0kVCRNCD#Rp7 q)Y_ a1 _GMC0k\3M8n_DO$_F0kMC
+s;b@R@g.:4j::c4:.j6kRlGDR8$F_OkCM0sC_MG40r:Rj98_D$OMFk0_CsM0CGrj4:9NRVD,#CV#NDCR
+RRMRk4D_8$F_OkCM0s:r.4s9RC0#C_MbH;R
+b@:@g4:4dc4:4dR:68RVV8_D$OMFk0rCs49:jR$8D_kOFMs0Crj4:9DR8$F_OkCM0sC_MG40r:
+j9RRRRO_D	b;HM
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRD"8$F_OkCM0s
+";C
+;
+
diff --git a/bsp2/Designflow/syn/rev_1/vga.sxr b/bsp2/Designflow/syn/rev_1/vga.sxr
new file mode 100644
index 0000000..4f45bb4
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.sxr
@@ -0,0 +1,377 @@
+
+BeginView vga NoName
+Inst: dly_counter[1]   dly_counter_1_ stratix_lcell_ff 
+Inst: dly_counter[0]   dly_counter_0_ stratix_lcell_ff 
+Inst: d_toggle_counter_out[24]   d_toggle_counter_out_24_ stratix_io 
+Inst: d_toggle_counter_out[23]   d_toggle_counter_out_23_ stratix_io 
+Inst: d_toggle_counter_out[22]   d_toggle_counter_out_22_ stratix_io 
+Inst: d_toggle_counter_out[21]   d_toggle_counter_out_21_ stratix_io 
+Inst: d_toggle_counter_out[20]   d_toggle_counter_out_20_ stratix_io 
+Inst: d_toggle_counter_out[19]   d_toggle_counter_out_19_ stratix_io 
+Inst: d_toggle_counter_out[18]   d_toggle_counter_out_18_ stratix_io 
+Inst: d_toggle_counter_out[17]   d_toggle_counter_out_17_ stratix_io 
+Inst: d_toggle_counter_out[16]   d_toggle_counter_out_16_ stratix_io 
+Inst: d_toggle_counter_out[15]   d_toggle_counter_out_15_ stratix_io 
+Inst: d_toggle_counter_out[14]   d_toggle_counter_out_14_ stratix_io 
+Inst: d_toggle_counter_out[13]   d_toggle_counter_out_13_ stratix_io 
+Inst: d_toggle_counter_out[12]   d_toggle_counter_out_12_ stratix_io 
+Inst: d_toggle_counter_out[11]   d_toggle_counter_out_11_ stratix_io 
+Inst: d_toggle_counter_out[10]   d_toggle_counter_out_10_ stratix_io 
+Inst: d_toggle_counter_out[9]   d_toggle_counter_out_9_ stratix_io 
+Inst: d_toggle_counter_out[8]   d_toggle_counter_out_8_ stratix_io 
+Inst: d_toggle_counter_out[7]   d_toggle_counter_out_7_ stratix_io 
+Inst: d_toggle_counter_out[6]   d_toggle_counter_out_6_ stratix_io 
+Inst: d_toggle_counter_out[5]   d_toggle_counter_out_5_ stratix_io 
+Inst: d_toggle_counter_out[4]   d_toggle_counter_out_4_ stratix_io 
+Inst: d_toggle_counter_out[3]   d_toggle_counter_out_3_ stratix_io 
+Inst: d_toggle_counter_out[2]   d_toggle_counter_out_2_ stratix_io 
+Inst: d_toggle_counter_out[1]   d_toggle_counter_out_1_ stratix_io 
+Inst: d_toggle_counter_out[0]   d_toggle_counter_out_0_ stratix_io 
+Inst: d_vsync_state_out[0]   d_vsync_state_out_0_ stratix_io 
+Inst: d_vsync_state_out[1]   d_vsync_state_out_1_ stratix_io 
+Inst: d_vsync_state_out[2]   d_vsync_state_out_2_ stratix_io 
+Inst: d_vsync_state_out[3]   d_vsync_state_out_3_ stratix_io 
+Inst: d_vsync_state_out[4]   d_vsync_state_out_4_ stratix_io 
+Inst: d_vsync_state_out[5]   d_vsync_state_out_5_ stratix_io 
+Inst: d_vsync_state_out[6]   d_vsync_state_out_6_ stratix_io 
+Inst: d_hsync_state_out[0]   d_hsync_state_out_0_ stratix_io 
+Inst: d_hsync_state_out[1]   d_hsync_state_out_1_ stratix_io 
+Inst: d_hsync_state_out[2]   d_hsync_state_out_2_ stratix_io 
+Inst: d_hsync_state_out[3]   d_hsync_state_out_3_ stratix_io 
+Inst: d_hsync_state_out[4]   d_hsync_state_out_4_ stratix_io 
+Inst: d_hsync_state_out[5]   d_hsync_state_out_5_ stratix_io 
+Inst: d_hsync_state_out[6]   d_hsync_state_out_6_ stratix_io 
+Inst: d_vsync_counter_out[9]   d_vsync_counter_out_9_ stratix_io 
+Inst: d_vsync_counter_out[8]   d_vsync_counter_out_8_ stratix_io 
+Inst: d_vsync_counter_out[7]   d_vsync_counter_out_7_ stratix_io 
+Inst: d_vsync_counter_out[6]   d_vsync_counter_out_6_ stratix_io 
+Inst: d_vsync_counter_out[5]   d_vsync_counter_out_5_ stratix_io 
+Inst: d_vsync_counter_out[4]   d_vsync_counter_out_4_ stratix_io 
+Inst: d_vsync_counter_out[3]   d_vsync_counter_out_3_ stratix_io 
+Inst: d_vsync_counter_out[2]   d_vsync_counter_out_2_ stratix_io 
+Inst: d_vsync_counter_out[1]   d_vsync_counter_out_1_ stratix_io 
+Inst: d_vsync_counter_out[0]   d_vsync_counter_out_0_ stratix_io 
+Inst: d_hsync_counter_out[9]   d_hsync_counter_out_9_ stratix_io 
+Inst: d_hsync_counter_out[8]   d_hsync_counter_out_8_ stratix_io 
+Inst: d_hsync_counter_out[7]   d_hsync_counter_out_7_ stratix_io 
+Inst: d_hsync_counter_out[6]   d_hsync_counter_out_6_ stratix_io 
+Inst: d_hsync_counter_out[5]   d_hsync_counter_out_5_ stratix_io 
+Inst: d_hsync_counter_out[4]   d_hsync_counter_out_4_ stratix_io 
+Inst: d_hsync_counter_out[3]   d_hsync_counter_out_3_ stratix_io 
+Inst: d_hsync_counter_out[2]   d_hsync_counter_out_2_ stratix_io 
+Inst: d_hsync_counter_out[1]   d_hsync_counter_out_1_ stratix_io 
+Inst: d_hsync_counter_out[0]   d_hsync_counter_out_0_ stratix_io 
+Inst: d_line_counter_out[8]   d_line_counter_out_8_ stratix_io 
+Inst: d_line_counter_out[7]   d_line_counter_out_7_ stratix_io 
+Inst: d_line_counter_out[6]   d_line_counter_out_6_ stratix_io 
+Inst: d_line_counter_out[5]   d_line_counter_out_5_ stratix_io 
+Inst: d_line_counter_out[4]   d_line_counter_out_4_ stratix_io 
+Inst: d_line_counter_out[3]   d_line_counter_out_3_ stratix_io 
+Inst: d_line_counter_out[2]   d_line_counter_out_2_ stratix_io 
+Inst: d_line_counter_out[1]   d_line_counter_out_1_ stratix_io 
+Inst: d_line_counter_out[0]   d_line_counter_out_0_ stratix_io 
+Inst: d_column_counter_out[9]   d_column_counter_out_9_ stratix_io 
+Inst: d_column_counter_out[8]   d_column_counter_out_8_ stratix_io 
+Inst: d_column_counter_out[7]   d_column_counter_out_7_ stratix_io 
+Inst: d_column_counter_out[6]   d_column_counter_out_6_ stratix_io 
+Inst: d_column_counter_out[5]   d_column_counter_out_5_ stratix_io 
+Inst: d_column_counter_out[4]   d_column_counter_out_4_ stratix_io 
+Inst: d_column_counter_out[3]   d_column_counter_out_3_ stratix_io 
+Inst: d_column_counter_out[2]   d_column_counter_out_2_ stratix_io 
+Inst: d_column_counter_out[1]   d_column_counter_out_1_ stratix_io 
+Inst: d_column_counter_out[0]   d_column_counter_out_0_ stratix_io 
+Inst: seven_seg_pin_tri[13]   seven_seg_pin_tri_13_ stratix_io 
+Inst: seven_seg_pin_out[12]   seven_seg_pin_out_12_ stratix_io 
+Inst: seven_seg_pin_out[11]   seven_seg_pin_out_11_ stratix_io 
+Inst: seven_seg_pin_out[10]   seven_seg_pin_out_10_ stratix_io 
+Inst: seven_seg_pin_out[9]   seven_seg_pin_out_9_ stratix_io 
+Inst: seven_seg_pin_out[8]   seven_seg_pin_out_8_ stratix_io 
+Inst: seven_seg_pin_out[7]   seven_seg_pin_out_7_ stratix_io 
+Inst: seven_seg_pin_tri[6]   seven_seg_pin_tri_6_ stratix_io 
+Inst: seven_seg_pin_tri[5]   seven_seg_pin_tri_5_ stratix_io 
+Inst: seven_seg_pin_tri[4]   seven_seg_pin_tri_4_ stratix_io 
+Inst: seven_seg_pin_tri[3]   seven_seg_pin_tri_3_ stratix_io 
+Inst: seven_seg_pin_out[2]   seven_seg_pin_out_2_ stratix_io 
+Inst: seven_seg_pin_out[1]   seven_seg_pin_out_1_ stratix_io 
+Inst: seven_seg_pin_tri[0]   seven_seg_pin_tri_0_ stratix_io 
+Net:  DELAY_RESET_next\.un6_dly_counter_0_x   DELAY_RESET_next_un6_dly_counter_0_x 
+Net:  vga_driver_unit.h_sync   vga_driver_unit_h_sync 
+Net:  vga_driver_unit.v_sync   vga_driver_unit_v_sync 
+Net:  vga_driver_unit.column_counter_sig[0]   vga_driver_unit_column_counter_sig[0] 
+Net:  vga_driver_unit.column_counter_sig[1]   vga_driver_unit_column_counter_sig[1] 
+Net:  vga_driver_unit.column_counter_sig[2]   vga_driver_unit_column_counter_sig[2] 
+Net:  vga_driver_unit.column_counter_sig[3]   vga_driver_unit_column_counter_sig[3] 
+Net:  vga_driver_unit.column_counter_sig[4]   vga_driver_unit_column_counter_sig[4] 
+Net:  vga_driver_unit.column_counter_sig[5]   vga_driver_unit_column_counter_sig[5] 
+Net:  vga_driver_unit.column_counter_sig[6]   vga_driver_unit_column_counter_sig[6] 
+Net:  vga_driver_unit.column_counter_sig[7]   vga_driver_unit_column_counter_sig[7] 
+Net:  vga_driver_unit.column_counter_sig[8]   vga_driver_unit_column_counter_sig[8] 
+Net:  vga_driver_unit.column_counter_sig[9]   vga_driver_unit_column_counter_sig[9] 
+Net:  vga_driver_unit.line_counter_sig[0]   vga_driver_unit_line_counter_sig[0] 
+Net:  vga_driver_unit.line_counter_sig[1]   vga_driver_unit_line_counter_sig[1] 
+Net:  vga_driver_unit.line_counter_sig[2]   vga_driver_unit_line_counter_sig[2] 
+Net:  vga_driver_unit.line_counter_sig[3]   vga_driver_unit_line_counter_sig[3] 
+Net:  vga_driver_unit.line_counter_sig[4]   vga_driver_unit_line_counter_sig[4] 
+Net:  vga_driver_unit.line_counter_sig[5]   vga_driver_unit_line_counter_sig[5] 
+Net:  vga_driver_unit.line_counter_sig[6]   vga_driver_unit_line_counter_sig[6] 
+Net:  vga_driver_unit.line_counter_sig[7]   vga_driver_unit_line_counter_sig[7] 
+Net:  vga_driver_unit.line_counter_sig[8]   vga_driver_unit_line_counter_sig[8] 
+Net:  vga_driver_unit.hsync_counter[0]   vga_driver_unit_hsync_counter[0] 
+Net:  vga_driver_unit.hsync_counter[1]   vga_driver_unit_hsync_counter[1] 
+Net:  vga_driver_unit.hsync_counter[2]   vga_driver_unit_hsync_counter[2] 
+Net:  vga_driver_unit.hsync_counter[3]   vga_driver_unit_hsync_counter[3] 
+Net:  vga_driver_unit.hsync_counter[4]   vga_driver_unit_hsync_counter[4] 
+Net:  vga_driver_unit.hsync_counter[5]   vga_driver_unit_hsync_counter[5] 
+Net:  vga_driver_unit.hsync_counter[6]   vga_driver_unit_hsync_counter[6] 
+Net:  vga_driver_unit.hsync_counter[7]   vga_driver_unit_hsync_counter[7] 
+Net:  vga_driver_unit.hsync_counter[8]   vga_driver_unit_hsync_counter[8] 
+Net:  vga_driver_unit.hsync_counter[9]   vga_driver_unit_hsync_counter[9] 
+Net:  vga_driver_unit.vsync_counter[0]   vga_driver_unit_vsync_counter[0] 
+Net:  vga_driver_unit.vsync_counter[1]   vga_driver_unit_vsync_counter[1] 
+Net:  vga_driver_unit.vsync_counter[2]   vga_driver_unit_vsync_counter[2] 
+Net:  vga_driver_unit.vsync_counter[3]   vga_driver_unit_vsync_counter[3] 
+Net:  vga_driver_unit.vsync_counter[4]   vga_driver_unit_vsync_counter[4] 
+Net:  vga_driver_unit.vsync_counter[5]   vga_driver_unit_vsync_counter[5] 
+Net:  vga_driver_unit.vsync_counter[6]   vga_driver_unit_vsync_counter[6] 
+Net:  vga_driver_unit.vsync_counter[7]   vga_driver_unit_vsync_counter[7] 
+Net:  vga_driver_unit.vsync_counter[8]   vga_driver_unit_vsync_counter[8] 
+Net:  vga_driver_unit.vsync_counter[9]   vga_driver_unit_vsync_counter[9] 
+Net:  vga_driver_unit.d_set_hsync_counter   vga_driver_unit_d_set_hsync_counter 
+Net:  vga_driver_unit.d_set_vsync_counter   vga_driver_unit_d_set_vsync_counter 
+Net:  vga_driver_unit.h_enable_sig   vga_driver_unit_h_enable_sig 
+Net:  vga_driver_unit.v_enable_sig   vga_driver_unit_v_enable_sig 
+Net:  vga_control_unit.r   vga_control_unit_r 
+Net:  vga_control_unit.g   vga_control_unit_g 
+Net:  vga_control_unit.b   vga_control_unit_b 
+Net:  vga_driver_unit.hsync_state[6]   vga_driver_unit_hsync_state[6] 
+Net:  vga_driver_unit.hsync_state[5]   vga_driver_unit_hsync_state[5] 
+Net:  vga_driver_unit.hsync_state[4]   vga_driver_unit_hsync_state[4] 
+Net:  vga_driver_unit.hsync_state[3]   vga_driver_unit_hsync_state[3] 
+Net:  vga_driver_unit.hsync_state[2]   vga_driver_unit_hsync_state[2] 
+Net:  vga_driver_unit.hsync_state[1]   vga_driver_unit_hsync_state[1] 
+Net:  vga_driver_unit.hsync_state[0]   vga_driver_unit_hsync_state[0] 
+Net:  vga_driver_unit.vsync_state[6]   vga_driver_unit_vsync_state[6] 
+Net:  vga_driver_unit.vsync_state[5]   vga_driver_unit_vsync_state[5] 
+Net:  vga_driver_unit.vsync_state[4]   vga_driver_unit_vsync_state[4] 
+Net:  vga_driver_unit.vsync_state[3]   vga_driver_unit_vsync_state[3] 
+Net:  vga_driver_unit.vsync_state[2]   vga_driver_unit_vsync_state[2] 
+Net:  vga_driver_unit.vsync_state[1]   vga_driver_unit_vsync_state[1] 
+Net:  vga_driver_unit.vsync_state[0]   vga_driver_unit_vsync_state[0] 
+Net:  vga_control_unit.toggle_sig   vga_control_unit_toggle_sig 
+Net:  vga_control_unit.toggle_counter_sig[0]   vga_control_unit_toggle_counter_sig[0] 
+Net:  vga_control_unit.toggle_counter_sig[1]   vga_control_unit_toggle_counter_sig[1] 
+Net:  vga_control_unit.toggle_counter_sig[2]   vga_control_unit_toggle_counter_sig[2] 
+Net:  vga_control_unit.toggle_counter_sig[3]   vga_control_unit_toggle_counter_sig[3] 
+Net:  vga_control_unit.toggle_counter_sig[4]   vga_control_unit_toggle_counter_sig[4] 
+Net:  vga_control_unit.toggle_counter_sig[5]   vga_control_unit_toggle_counter_sig[5] 
+Net:  vga_control_unit.toggle_counter_sig[6]   vga_control_unit_toggle_counter_sig[6] 
+Net:  vga_control_unit.toggle_counter_sig[7]   vga_control_unit_toggle_counter_sig[7] 
+Net:  vga_control_unit.toggle_counter_sig[8]   vga_control_unit_toggle_counter_sig[8] 
+Net:  vga_control_unit.toggle_counter_sig[9]   vga_control_unit_toggle_counter_sig[9] 
+Net:  vga_control_unit.toggle_counter_sig[10]   vga_control_unit_toggle_counter_sig[10] 
+Net:  vga_control_unit.toggle_counter_sig[11]   vga_control_unit_toggle_counter_sig[11] 
+Net:  vga_control_unit.toggle_counter_sig[12]   vga_control_unit_toggle_counter_sig[12] 
+Net:  vga_control_unit.toggle_counter_sig[13]   vga_control_unit_toggle_counter_sig[13] 
+Net:  vga_control_unit.toggle_counter_sig[14]   vga_control_unit_toggle_counter_sig[14] 
+Net:  vga_control_unit.toggle_counter_sig[15]   vga_control_unit_toggle_counter_sig[15] 
+Net:  vga_control_unit.toggle_counter_sig[16]   vga_control_unit_toggle_counter_sig[16] 
+Net:  vga_control_unit.toggle_counter_sig[17]   vga_control_unit_toggle_counter_sig[17] 
+Net:  vga_control_unit.toggle_counter_sig[18]   vga_control_unit_toggle_counter_sig[18] 
+Net:  vga_control_unit.toggle_counter_sig[19]   vga_control_unit_toggle_counter_sig[19] 
+Net:  vga_control_unit.toggle_counter_sig[20]   vga_control_unit_toggle_counter_sig[20] 
+Net:  vga_control_unit.toggle_counter_sig[21]   vga_control_unit_toggle_counter_sig[21] 
+Net:  vga_control_unit.toggle_counter_sig[22]   vga_control_unit_toggle_counter_sig[22] 
+Net:  vga_control_unit.toggle_counter_sig[23]   vga_control_unit_toggle_counter_sig[23] 
+Net:  vga_control_unit.toggle_counter_sig[24]   vga_control_unit_toggle_counter_sig[24] 
+Net:  clk_pin_c   G_33 
+EndView vga NoName
+
+BeginView vga_driver NoName
+Inst: hsync_counter[0]   hsync_counter_0_ stratix_lcell_ff 
+Inst: hsync_counter[1]   hsync_counter_1_ stratix_lcell_ff 
+Inst: hsync_counter[2]   hsync_counter_2_ stratix_lcell_ff 
+Inst: hsync_counter[3]   hsync_counter_3_ stratix_lcell_ff 
+Inst: hsync_counter[4]   hsync_counter_4_ stratix_lcell_ff 
+Inst: hsync_counter[5]   hsync_counter_5_ stratix_lcell_ff 
+Inst: hsync_counter[6]   hsync_counter_6_ stratix_lcell_ff 
+Inst: hsync_counter[7]   hsync_counter_7_ stratix_lcell_ff 
+Inst: hsync_counter[8]   hsync_counter_8_ stratix_lcell_ff 
+Inst: hsync_counter[9]   hsync_counter_9_ stratix_lcell_ff 
+Inst: vsync_counter[0]   vsync_counter_0_ stratix_lcell_ff 
+Inst: vsync_counter[1]   vsync_counter_1_ stratix_lcell_ff 
+Inst: vsync_counter[2]   vsync_counter_2_ stratix_lcell_ff 
+Inst: vsync_counter[3]   vsync_counter_3_ stratix_lcell_ff 
+Inst: vsync_counter[4]   vsync_counter_4_ stratix_lcell_ff 
+Inst: vsync_counter[5]   vsync_counter_5_ stratix_lcell_ff 
+Inst: vsync_counter[6]   vsync_counter_6_ stratix_lcell_ff 
+Inst: vsync_counter[7]   vsync_counter_7_ stratix_lcell_ff 
+Inst: vsync_counter[8]   vsync_counter_8_ stratix_lcell_ff 
+Inst: vsync_counter[9]   vsync_counter_9_ stratix_lcell_ff 
+Inst: column_counter_sig[9]   column_counter_sig_9_ stratix_lcell_ff 
+Inst: column_counter_sig[8]   column_counter_sig_8_ stratix_lcell_ff 
+Inst: column_counter_sig[7]   column_counter_sig_7_ stratix_lcell_ff 
+Inst: column_counter_sig[6]   column_counter_sig_6_ stratix_lcell_ff 
+Inst: column_counter_sig[5]   column_counter_sig_5_ stratix_lcell_ff 
+Inst: column_counter_sig[4]   column_counter_sig_4_ stratix_lcell_ff 
+Inst: column_counter_sig[3]   column_counter_sig_3_ stratix_lcell_ff 
+Inst: column_counter_sig[2]   column_counter_sig_2_ stratix_lcell_ff 
+Inst: column_counter_sig[1]   column_counter_sig_1_ stratix_lcell_ff 
+Inst: column_counter_sig[0]   column_counter_sig_0_ stratix_lcell_ff 
+Inst: hsync_state[6]   hsync_state_6_ stratix_lcell_ff 
+Inst: vsync_state[0]   vsync_state_0_ stratix_lcell_ff 
+Inst: vsync_state[1]   vsync_state_1_ stratix_lcell_ff 
+Inst: vsync_state[6]   vsync_state_6_ stratix_lcell_ff 
+Inst: line_counter_sig[8]   line_counter_sig_8_ stratix_lcell_ff 
+Inst: line_counter_sig[7]   line_counter_sig_7_ stratix_lcell_ff 
+Inst: line_counter_sig[6]   line_counter_sig_6_ stratix_lcell_ff 
+Inst: line_counter_sig[5]   line_counter_sig_5_ stratix_lcell_ff 
+Inst: line_counter_sig[4]   line_counter_sig_4_ stratix_lcell_ff 
+Inst: line_counter_sig[3]   line_counter_sig_3_ stratix_lcell_ff 
+Inst: line_counter_sig[2]   line_counter_sig_2_ stratix_lcell_ff 
+Inst: line_counter_sig[1]   line_counter_sig_1_ stratix_lcell_ff 
+Inst: line_counter_sig[0]   line_counter_sig_0_ stratix_lcell_ff 
+Inst: v_enable_sig   v_enable_sig_Z stratix_lcell_ff 
+Inst: h_enable_sig   h_enable_sig_Z stratix_lcell_ff 
+Inst: h_sync   h_sync_Z stratix_lcell_ff 
+Inst: v_sync   v_sync_Z stratix_lcell_ff 
+Inst: vsync_state[5]   vsync_state_5_ stratix_lcell_ff 
+Inst: vsync_state[4]   vsync_state_4_ stratix_lcell_ff 
+Inst: vsync_state[3]   vsync_state_3_ stratix_lcell_ff 
+Inst: vsync_state[2]   vsync_state_2_ stratix_lcell_ff 
+Inst: hsync_state[5]   hsync_state_5_ stratix_lcell_ff 
+Inst: hsync_state[4]   hsync_state_4_ stratix_lcell_ff 
+Inst: hsync_state[3]   hsync_state_3_ stratix_lcell_ff 
+Inst: hsync_state[2]   hsync_state_2_ stratix_lcell_ff 
+Inst: hsync_state[1]   hsync_state_1_ stratix_lcell_ff 
+Inst: hsync_state[0]   hsync_state_0_ stratix_lcell_ff 
+Inst: vsync_state_next_2_sqmuxa   vsync_state_next_2_sqmuxa_cZ stratix_lcell 
+Inst: hsync_state_3_0_0_0__g0_0   hsync_state_3_0_0_0__g0_0_cZ stratix_lcell 
+Inst: un1_hsync_state_next_1_sqmuxa_0   un1_hsync_state_next_1_sqmuxa_0_cZ stratix_lcell 
+Inst: un1_vsync_state_next_1_sqmuxa_0   un1_vsync_state_next_1_sqmuxa_0_cZ stratix_lcell 
+Inst: vsync_state_3_iv_0_0__g0_0_a3_0   vsync_state_3_iv_0_0__g0_0_a3_0_cZ stratix_lcell 
+Inst: LINE_COUNT_next\.un10_line_counter_siglto8   LINE_COUNT_next_un10_line_counter_siglto8 stratix_lcell 
+Inst: vsync_state_next_1_sqmuxa_1   vsync_state_next_1_sqmuxa_1_cZ stratix_lcell 
+Inst: vsync_state_next_1_sqmuxa_2   vsync_state_next_1_sqmuxa_2_cZ stratix_lcell 
+Inst: vsync_state_next_1_sqmuxa_3   vsync_state_next_1_sqmuxa_3_cZ stratix_lcell 
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglto9   COLUMN_COUNT_next_un10_column_counter_siglto9 stratix_lcell 
+Inst: hsync_state_next_1_sqmuxa_2   hsync_state_next_1_sqmuxa_2_cZ stratix_lcell 
+Inst: hsync_state_next_1_sqmuxa_1   hsync_state_next_1_sqmuxa_1_cZ stratix_lcell 
+Inst: HSYNC_FSM_next\.un13_hsync_counter   HSYNC_FSM_next_un13_hsync_counter stratix_lcell 
+Inst: HSYNC_COUNT_next\.un9_hsync_counterlt9   HSYNC_COUNT_next_un9_hsync_counterlt9 stratix_lcell 
+Inst: VSYNC_COUNT_next\.un9_vsync_counterlt9   VSYNC_COUNT_next_un9_vsync_counterlt9 stratix_lcell 
+Inst: HSYNC_FSM_next\.un12_hsync_counter   HSYNC_FSM_next_un12_hsync_counter stratix_lcell 
+Inst: LINE_COUNT_next\.un10_line_counter_siglto5   LINE_COUNT_next_un10_line_counter_siglto5 stratix_lcell 
+Inst: VSYNC_FSM_next\.un15_vsync_counter_4   VSYNC_FSM_next_un15_vsync_counter_4 stratix_lcell 
+Inst: VSYNC_FSM_next\.un13_vsync_counter_4   VSYNC_FSM_next_un13_vsync_counter_4 stratix_lcell 
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglt6   COLUMN_COUNT_next_un10_column_counter_siglt6 stratix_lcell 
+Inst: hsync_counter_next_1_sqmuxa   hsync_counter_next_1_sqmuxa_cZ stratix_lcell 
+Inst: VSYNC_FSM_next\.un14_vsync_counter_8   VSYNC_FSM_next_un14_vsync_counter_8 stratix_lcell 
+Inst: line_counter_next_0_sqmuxa_1_1   line_counter_next_0_sqmuxa_1_1_cZ stratix_lcell 
+Inst: v_sync_1_0_0_0_g1   v_sync_1_0_0_0_g1_cZ stratix_lcell 
+Inst: h_enable_sig_1_0_0_0_g0_i_o4   h_enable_sig_1_0_0_0_g0_i_o4_cZ stratix_lcell 
+Inst: vsync_counter_next_1_sqmuxa   vsync_counter_next_1_sqmuxa_cZ stratix_lcell 
+Inst: v_enable_sig_1_0_0_0_g0_i_o4   v_enable_sig_1_0_0_0_g0_i_o4_cZ stratix_lcell 
+Inst: h_sync_1_0_0_0_g1   h_sync_1_0_0_0_g1_cZ stratix_lcell 
+Inst: column_counter_next_0_sqmuxa_1_1   column_counter_next_0_sqmuxa_1_1_cZ stratix_lcell 
+Inst: HSYNC_FSM_next\.un12_hsync_counter_4   HSYNC_FSM_next_un12_hsync_counter_4 stratix_lcell 
+Inst: HSYNC_FSM_next\.un12_hsync_counter_3   HSYNC_FSM_next_un12_hsync_counter_3 stratix_lcell 
+Inst: HSYNC_FSM_next\.un11_hsync_counter_3   HSYNC_FSM_next_un11_hsync_counter_3 stratix_lcell 
+Inst: HSYNC_FSM_next\.un11_hsync_counter_2   HSYNC_FSM_next_un11_hsync_counter_2 stratix_lcell 
+Inst: HSYNC_COUNT_next\.un9_hsync_counterlt9_3   HSYNC_COUNT_next_un9_hsync_counterlt9_3 stratix_lcell 
+Inst: HSYNC_FSM_next\.un13_hsync_counter_2   HSYNC_FSM_next_un13_hsync_counter_2 stratix_lcell 
+Inst: VSYNC_COUNT_next\.un9_vsync_counterlt9_6   VSYNC_COUNT_next_un9_vsync_counterlt9_6 stratix_lcell 
+Inst: VSYNC_COUNT_next\.un9_vsync_counterlt9_5   VSYNC_COUNT_next_un9_vsync_counterlt9_5 stratix_lcell 
+Inst: HSYNC_FSM_next\.un10_hsync_counter_4   HSYNC_FSM_next_un10_hsync_counter_4 stratix_lcell 
+Inst: HSYNC_FSM_next\.un10_hsync_counter_3   HSYNC_FSM_next_un10_hsync_counter_3 stratix_lcell 
+Inst: VSYNC_FSM_next\.un15_vsync_counter_3   VSYNC_FSM_next_un15_vsync_counter_3 stratix_lcell 
+Inst: VSYNC_FSM_next\.un13_vsync_counter_3   VSYNC_FSM_next_un13_vsync_counter_3 stratix_lcell 
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglt6_4   COLUMN_COUNT_next_un10_column_counter_siglt6_4 stratix_lcell 
+Inst: LINE_COUNT_next\.un10_line_counter_siglt4_2   LINE_COUNT_next_un10_line_counter_siglt4_2 stratix_lcell 
+Inst: HSYNC_FSM_next\.un10_hsync_counter_1   HSYNC_FSM_next_un10_hsync_counter_1 stratix_lcell 
+Inst: VSYNC_FSM_next\.un12_vsync_counter_6   VSYNC_FSM_next_un12_vsync_counter_6 stratix_lcell 
+Inst: VSYNC_FSM_next\.un12_vsync_counter_7   VSYNC_FSM_next_un12_vsync_counter_7 stratix_lcell 
+Inst: HSYNC_FSM_next\.un13_hsync_counter_7   HSYNC_FSM_next_un13_hsync_counter_7 stratix_lcell 
+Inst: un1_hsync_state_3_0   un1_hsync_state_3_0_cZ stratix_lcell 
+Inst: un1_vsync_state_2_0   un1_vsync_state_2_0_cZ stratix_lcell 
+Inst: d_set_hsync_counter   d_set_hsync_counter_cZ stratix_lcell 
+Inst: d_set_vsync_counter   d_set_vsync_counter_cZ stratix_lcell 
+Inst: un1_line_counter_sig[9]   un1_line_counter_sig_9_ stratix_lcell 
+Inst: un1_line_counter_sig[8]   un1_line_counter_sig_8_ stratix_lcell 
+Inst: un1_line_counter_sig[7]   un1_line_counter_sig_7_ stratix_lcell 
+Inst: un1_line_counter_sig[6]   un1_line_counter_sig_6_ stratix_lcell 
+Inst: un1_line_counter_sig[5]   un1_line_counter_sig_5_ stratix_lcell 
+Inst: un1_line_counter_sig[4]   un1_line_counter_sig_4_ stratix_lcell 
+Inst: un1_line_counter_sig[3]   un1_line_counter_sig_3_ stratix_lcell 
+Inst: un1_line_counter_sig[2]   un1_line_counter_sig_2_ stratix_lcell 
+Inst: un1_line_counter_sig_a[1]   un1_line_counter_sig_a_1_ stratix_lcell 
+Inst: un1_line_counter_sig[1]   un1_line_counter_sig_1_ stratix_lcell 
+Inst: un2_column_counter_next[9]   un2_column_counter_next_9_ stratix_lcell 
+Inst: un2_column_counter_next[8]   un2_column_counter_next_8_ stratix_lcell 
+Inst: un2_column_counter_next[7]   un2_column_counter_next_7_ stratix_lcell 
+Inst: un2_column_counter_next[6]   un2_column_counter_next_6_ stratix_lcell 
+Inst: un2_column_counter_next[5]   un2_column_counter_next_5_ stratix_lcell 
+Inst: un2_column_counter_next[4]   un2_column_counter_next_4_ stratix_lcell 
+Inst: un2_column_counter_next[3]   un2_column_counter_next_3_ stratix_lcell 
+Inst: un2_column_counter_next[2]   un2_column_counter_next_2_ stratix_lcell 
+Inst: un2_column_counter_next[1]   un2_column_counter_next_1_ stratix_lcell 
+Inst: un2_column_counter_next[0]   un2_column_counter_next_0_ stratix_lcell 
+Inst: line_counter_next_0_sqmuxa_1_1_i   line_counter_next_0_sqmuxa_1_1_i_cZ inv 
+Inst: column_counter_next_0_sqmuxa_1_1_i   column_counter_next_0_sqmuxa_1_1_i_cZ inv 
+Inst: un9_vsync_counterlt9_i   un9_vsync_counterlt9_i_cZ inv 
+Inst: G_16_i_i   G_16_i_i_cZ inv 
+Inst: un9_hsync_counterlt9_i   un9_hsync_counterlt9_i_cZ inv 
+Inst: G_2_i_i   G_2_i_i_cZ inv 
+EndView vga_driver NoName
+
+BeginView vga_control NoName
+Inst: toggle_counter_sig[24]   toggle_counter_sig_24_ stratix_lcell_ff 
+Inst: toggle_counter_sig[23]   toggle_counter_sig_23_ stratix_lcell_ff 
+Inst: toggle_counter_sig[22]   toggle_counter_sig_22_ stratix_lcell_ff 
+Inst: toggle_counter_sig[21]   toggle_counter_sig_21_ stratix_lcell_ff 
+Inst: toggle_counter_sig[20]   toggle_counter_sig_20_ stratix_lcell_ff 
+Inst: toggle_counter_sig[19]   toggle_counter_sig_19_ stratix_lcell_ff 
+Inst: toggle_counter_sig[18]   toggle_counter_sig_18_ stratix_lcell_ff 
+Inst: toggle_counter_sig[17]   toggle_counter_sig_17_ stratix_lcell_ff 
+Inst: toggle_counter_sig[16]   toggle_counter_sig_16_ stratix_lcell_ff 
+Inst: toggle_counter_sig[15]   toggle_counter_sig_15_ stratix_lcell_ff 
+Inst: toggle_counter_sig[14]   toggle_counter_sig_14_ stratix_lcell_ff 
+Inst: toggle_counter_sig[13]   toggle_counter_sig_13_ stratix_lcell_ff 
+Inst: toggle_counter_sig[12]   toggle_counter_sig_12_ stratix_lcell_ff 
+Inst: toggle_counter_sig[11]   toggle_counter_sig_11_ stratix_lcell_ff 
+Inst: toggle_counter_sig[10]   toggle_counter_sig_10_ stratix_lcell_ff 
+Inst: toggle_counter_sig[9]   toggle_counter_sig_9_ stratix_lcell_ff 
+Inst: toggle_counter_sig[8]   toggle_counter_sig_8_ stratix_lcell_ff 
+Inst: toggle_counter_sig[7]   toggle_counter_sig_7_ stratix_lcell_ff 
+Inst: toggle_counter_sig[6]   toggle_counter_sig_6_ stratix_lcell_ff 
+Inst: toggle_counter_sig[5]   toggle_counter_sig_5_ stratix_lcell_ff 
+Inst: toggle_counter_sig[4]   toggle_counter_sig_4_ stratix_lcell_ff 
+Inst: toggle_counter_sig[3]   toggle_counter_sig_3_ stratix_lcell_ff 
+Inst: toggle_counter_sig[2]   toggle_counter_sig_2_ stratix_lcell_ff 
+Inst: toggle_counter_sig[1]   toggle_counter_sig_1_ stratix_lcell_ff 
+Inst: toggle_counter_sig[0]   toggle_counter_sig_0_ stratix_lcell_ff 
+Inst: toggle_sig   toggle_sig_Z stratix_lcell_ff 
+Inst: r   r_Z stratix_lcell_ff 
+Inst: b   b_Z stratix_lcell_ff 
+Inst: g   g_Z stratix_lcell_ff 
+Inst: toggle_sig_0_0_0_g1   toggle_sig_0_0_0_g1_cZ stratix_lcell 
+Inst: BLINKER_next\.un1_toggle_counter_siglto18   BLINKER_next_un1_toggle_counter_siglto18 stratix_lcell 
+Inst: b_next_0_sqmuxa_7_5   b_next_0_sqmuxa_7_5_cZ stratix_lcell 
+Inst: b_next_0_sqmuxa_7_4   b_next_0_sqmuxa_7_4_cZ stratix_lcell 
+Inst: b_next_0_sqmuxa_7_4_a   b_next_0_sqmuxa_7_4_a_cZ stratix_lcell 
+Inst: b_next_0_sqmuxa_7_3   b_next_0_sqmuxa_7_3_cZ stratix_lcell 
+Inst: BLINKER_next\.un1_toggle_counter_siglto15   BLINKER_next_un1_toggle_counter_siglto15 stratix_lcell 
+Inst: DRAW_SQUARE_next\.un5_v_enablelto5   DRAW_SQUARE_next_un5_v_enablelto5 stratix_lcell 
+Inst: BLINKER_next\.un1_toggle_counter_siglto12   BLINKER_next_un1_toggle_counter_siglto12 stratix_lcell 
+Inst: DRAW_SQUARE_next\.un13_v_enablelto6   DRAW_SQUARE_next_un13_v_enablelto6 stratix_lcell 
+Inst: DRAW_SQUARE_next\.un9_v_enablelto6   DRAW_SQUARE_next_un9_v_enablelto6 stratix_lcell 
+Inst: BLINKER_next\.un1_toggle_counter_siglto9   BLINKER_next_un1_toggle_counter_siglto9 stratix_lcell 
+Inst: DRAW_SQUARE_next\.un17_v_enablelto3   DRAW_SQUARE_next_un17_v_enablelto3 stratix_lcell 
+Inst: toggle_sig_0_0_0_g1_2   toggle_sig_0_0_0_g1_2_cZ stratix_lcell 
+Inst: b_next_0_sqmuxa_7_2   b_next_0_sqmuxa_7_2_cZ stratix_lcell 
+Inst: DRAW_SQUARE_next\.un9_v_enablelto4   DRAW_SQUARE_next_un9_v_enablelto4 stratix_lcell 
+Inst: DRAW_SQUARE_next\.un5_v_enablelt2   DRAW_SQUARE_next_un5_v_enablelt2 stratix_lcell 
+Inst: DRAW_SQUARE_next\.un13_v_enablelto4_0   DRAW_SQUARE_next_un13_v_enablelto4_0 stratix_lcell 
+Inst: BLINKER_next\.un1_toggle_counter_siglt6   BLINKER_next_un1_toggle_counter_siglt6 stratix_lcell 
+Inst: un2_toggle_counter_next[0]   un2_toggle_counter_next_0_ stratix_lcell 
+Inst: toggle_sig_0_0_0_g1_i   toggle_sig_0_0_0_g1_i_cZ inv 
+EndView vga_control NoName
diff --git a/bsp2/Designflow/syn/rev_1/vga.szr b/bsp2/Designflow/syn/rev_1/vga.szr
new file mode 100644
index 0000000000000000000000000000000000000000..7d8551151ff61756337b1da4e5ff9a486146f5d5
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HcmV?d00001

diff --git a/bsp2/Designflow/syn/rev_1/vga.tcl b/bsp2/Designflow/syn/rev_1/vga.tcl
new file mode 100644
index 0000000..65e3b45
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.tcl
@@ -0,0 +1,41 @@
+# Run with quartus_sh -t 
+
+# Global assignments 
+set_global_assignment -name TOP_LEVEL_ENTITY "|vga"
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE NORMAL
+set_global_assignment -name FAMILY "STRATIX"
+set_global_assignment -name DEVICE "EP1S25F672C6"
+set_global_assignment -section_id vga -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "SYNPLIFY"
+set_global_assignment -section_id eda_design_synthesis -name EDA_USE_LMF synplcty.lmf
+set_global_assignment -name TAO_FILE "myresults.tao"
+set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000" 
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "OFF"
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF"
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF"
+# set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+#set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY"
+set_global_assignment -name ENABLE_CLOCK_LATENCY "ON"
+
+# Clock assignments 
+
+create_base_clock clk_pin_setting -fmax 25.175mhz -duty_cycle 50.00 -target clk_pin 
+
+
+# False path constraints 
+
+# Multicycle constraints 
+
+# Path delay constraints 
+if {[file exists ___quartus_options.tcl]} {
+	source ___quartus_options.tcl
+}
+
+
+# Incremental Compilation
+    # this will synchronize any existing partitions declared in Synpilfy
+    # with partitions existing in Quartus. If partitions exist,
+    # incremental compilation will be enabled
+    variable compile_point_list
+    set compile_point_list [list]
+    source "/opt/synplify/fpga_c200906/lib/altera/qic.tcl"
diff --git a/bsp2/Designflow/syn/rev_1/vga.tlg b/bsp2/Designflow/syn/rev_1/vga.tlg
new file mode 100644
index 0000000..4c6754f
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.tlg
@@ -0,0 +1,12 @@
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav 
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav 
+Post processing for work.vga_control.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav 
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+Post processing for work.vga_driver.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav 
+Post processing for work.board_driver.behav
+Post processing for work.vga.behav
diff --git a/bsp2/Designflow/syn/rev_1/vga.vhm b/bsp2/Designflow/syn/rev_1/vga.vhm
new file mode 100644
index 0000000..1a32a88
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.vhm
@@ -0,0 +1,6862 @@
+--
+-- Written by Synplicity
+-- Product Version "C-2009.06"
+-- Program "Synplify Pro", Mapper "map450rc, Build 029R"
+-- Wed Oct 21 17:26:36 2009
+--
+
+--
+-- Written by Synplify Pro version Build 029R
+-- Wed Oct 21 17:26:36 2009
+--
+
+--
+library ieee, stratix;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+use stratix.stratix_components.all;
+
+entity vga_control is
+port(
+  line_counter_sig_0 :  in std_logic;
+  line_counter_sig_2 :  in std_logic;
+  line_counter_sig_1 :  in std_logic;
+  line_counter_sig_3 :  in std_logic;
+  line_counter_sig_6 :  in std_logic;
+  line_counter_sig_5 :  in std_logic;
+  line_counter_sig_4 :  in std_logic;
+  line_counter_sig_7 :  in std_logic;
+  line_counter_sig_8 :  in std_logic;
+  column_counter_sig_0 :  in std_logic;
+  column_counter_sig_1 :  in std_logic;
+  column_counter_sig_2 :  in std_logic;
+  column_counter_sig_8 :  in std_logic;
+  column_counter_sig_3 :  in std_logic;
+  column_counter_sig_5 :  in std_logic;
+  column_counter_sig_4 :  in std_logic;
+  column_counter_sig_9 :  in std_logic;
+  column_counter_sig_7 :  in std_logic;
+  column_counter_sig_6 :  in std_logic;
+  toggle_counter_sig_0 :  out std_logic;
+  toggle_counter_sig_1 :  out std_logic;
+  toggle_counter_sig_2 :  out std_logic;
+  toggle_counter_sig_3 :  out std_logic;
+  toggle_counter_sig_4 :  out std_logic;
+  toggle_counter_sig_5 :  out std_logic;
+  toggle_counter_sig_6 :  out std_logic;
+  toggle_counter_sig_7 :  out std_logic;
+  toggle_counter_sig_8 :  out std_logic;
+  toggle_counter_sig_9 :  out std_logic;
+  toggle_counter_sig_10 :  out std_logic;
+  toggle_counter_sig_11 :  out std_logic;
+  toggle_counter_sig_12 :  out std_logic;
+  toggle_counter_sig_13 :  out std_logic;
+  toggle_counter_sig_14 :  out std_logic;
+  toggle_counter_sig_15 :  out std_logic;
+  toggle_counter_sig_16 :  out std_logic;
+  toggle_counter_sig_17 :  out std_logic;
+  toggle_counter_sig_18 :  out std_logic;
+  toggle_counter_sig_19 :  out std_logic;
+  toggle_counter_sig_20 :  out std_logic;
+  toggle_counter_sig_21 :  out std_logic;
+  toggle_counter_sig_22 :  out std_logic;
+  toggle_counter_sig_23 :  out std_logic;
+  toggle_counter_sig_24 :  out std_logic;
+  h_enable_sig :  in std_logic;
+  g :  out std_logic;
+  b :  out std_logic;
+  v_enable_sig :  in std_logic;
+  r :  out std_logic;
+  toggle_sig :  out std_logic;
+  un6_dly_counter_0_x :  in std_logic;
+  clk_pin_c :  in std_logic);
+end vga_control;
+
+architecture beh of vga_control is
+  signal devclrn : std_logic := '1';
+  signal devpor : std_logic := '1';
+  signal devoe : std_logic := '0';
+  signal TOGGLE_COUNTER_SIG_COUT : std_logic_vector(18 downto 1);
+  signal UN2_TOGGLE_COUNTER_NEXT_COUT : std_logic_vector(0 to 0);
+  signal GND : std_logic ;
+  signal TOGGLE_SIG_0_0_0_G1 : std_logic ;
+  signal TOGGLE_SIG_83 : std_logic ;
+  signal B_NEXT_0_SQMUXA_7_4 : std_logic ;
+  signal B_NEXT_0_SQMUXA_7_5 : std_logic ;
+  signal TOGGLE_SIG_0_0_0_G1_2 : std_logic ;
+  signal UN1_TOGGLE_COUNTER_SIGLTO18 : std_logic ;
+  signal UN1_TOGGLE_COUNTER_SIGLTO15 : std_logic ;
+  signal UN5_V_ENABLELTO5 : std_logic ;
+  signal B_NEXT_0_SQMUXA_7_3 : std_logic ;
+  signal UN13_V_ENABLELTO6 : std_logic ;
+  signal B_NEXT_0_SQMUXA_7_4_A : std_logic ;
+  signal UN17_V_ENABLELTO3 : std_logic ;
+  signal B_NEXT_0_SQMUXA_7_2 : std_logic ;
+  signal UN9_V_ENABLELTO6 : std_logic ;
+  signal UN1_TOGGLE_COUNTER_SIGLTO12 : std_logic ;
+  signal UN5_V_ENABLELT2 : std_logic ;
+  signal UN1_TOGGLE_COUNTER_SIGLTO9 : std_logic ;
+  signal UN13_V_ENABLELTO4_0 : std_logic ;
+  signal UN9_V_ENABLELTO4 : std_logic ;
+  signal UN1_TOGGLE_COUNTER_SIGLT6 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_58 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_59 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_60 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_61 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_62 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_63 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_64 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_65 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_66 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_67 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_68 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_69 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_70 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_71 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_72 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_73 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_74 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_75 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_76 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_77 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_78 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_79 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_80 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_81 : std_logic ;
+  signal TOGGLE_COUNTER_SIG_82 : std_logic ;
+  signal VCC : std_logic ;
+  signal TOGGLE_SIG_0_0_0_G1_I : std_logic ;
+begin
+\TOGGLE_COUNTER_SIG_24_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff00")
+port map (
+regout => TOGGLE_COUNTER_SIG_82,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+	devpor => devpor,
+	devclrn => devclrn,
+	dataa => VCC,
+	datab => VCC,
+	datac => VCC,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_23_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff00")
+port map (
+regout => TOGGLE_COUNTER_SIG_81,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+	devpor => devpor,
+	devclrn => devclrn,
+	dataa => VCC,
+	datab => VCC,
+	datac => VCC,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_22_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff00")
+port map (
+regout => TOGGLE_COUNTER_SIG_80,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+	devpor => devpor,
+	devclrn => devclrn,
+	dataa => VCC,
+	datab => VCC,
+	datac => VCC,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_21_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff00")
+port map (
+regout => TOGGLE_COUNTER_SIG_79,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+	devpor => devpor,
+	devclrn => devclrn,
+	dataa => VCC,
+	datab => VCC,
+	datac => VCC,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_20_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a5a")
+port map (
+regout => TOGGLE_COUNTER_SIG_78,
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_78,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(18),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_19_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c6c")
+port map (
+regout => TOGGLE_COUNTER_SIG_77,
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_76,
+datab => TOGGLE_COUNTER_SIG_77,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(17),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_18_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_76,
+cout => TOGGLE_COUNTER_SIG_COUT(18),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_76,
+datab => TOGGLE_COUNTER_SIG_77,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(16),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_17_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_75,
+cout => TOGGLE_COUNTER_SIG_COUT(17),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_74,
+datab => TOGGLE_COUNTER_SIG_75,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(15),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_16_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_74,
+cout => TOGGLE_COUNTER_SIG_COUT(16),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_74,
+datab => TOGGLE_COUNTER_SIG_75,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(14),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_15_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_73,
+cout => TOGGLE_COUNTER_SIG_COUT(15),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_72,
+datab => TOGGLE_COUNTER_SIG_73,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(13),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_14_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_72,
+cout => TOGGLE_COUNTER_SIG_COUT(14),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_72,
+datab => TOGGLE_COUNTER_SIG_73,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(12),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_13_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_71,
+cout => TOGGLE_COUNTER_SIG_COUT(13),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_70,
+datab => TOGGLE_COUNTER_SIG_71,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(11),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_12_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_70,
+cout => TOGGLE_COUNTER_SIG_COUT(12),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_70,
+datab => TOGGLE_COUNTER_SIG_71,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(10),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_11_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_69,
+cout => TOGGLE_COUNTER_SIG_COUT(11),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_68,
+datab => TOGGLE_COUNTER_SIG_69,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(9),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_10_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_68,
+cout => TOGGLE_COUNTER_SIG_COUT(10),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_68,
+datab => TOGGLE_COUNTER_SIG_69,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(8),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_9_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_67,
+cout => TOGGLE_COUNTER_SIG_COUT(9),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_66,
+datab => TOGGLE_COUNTER_SIG_67,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(7),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_8_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_66,
+cout => TOGGLE_COUNTER_SIG_COUT(8),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_66,
+datab => TOGGLE_COUNTER_SIG_67,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(6),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_7_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_65,
+cout => TOGGLE_COUNTER_SIG_COUT(7),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_64,
+datab => TOGGLE_COUNTER_SIG_65,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(5),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_6_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_64,
+cout => TOGGLE_COUNTER_SIG_COUT(6),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_64,
+datab => TOGGLE_COUNTER_SIG_65,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(4),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_5_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_63,
+cout => TOGGLE_COUNTER_SIG_COUT(5),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_62,
+datab => TOGGLE_COUNTER_SIG_63,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(3),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_4_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_62,
+cout => TOGGLE_COUNTER_SIG_COUT(4),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_62,
+datab => TOGGLE_COUNTER_SIG_63,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(2),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_3_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_61,
+cout => TOGGLE_COUNTER_SIG_COUT(3),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_60,
+datab => TOGGLE_COUNTER_SIG_61,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(1),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_2_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_60,
+cout => TOGGLE_COUNTER_SIG_COUT(2),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_60,
+datab => TOGGLE_COUNTER_SIG_61,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => UN2_TOGGLE_COUNTER_NEXT_COUT(0),
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_1_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "6688")
+port map (
+regout => TOGGLE_COUNTER_SIG_59,
+cout => TOGGLE_COUNTER_SIG_COUT(1),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_58,
+datab => TOGGLE_COUNTER_SIG_59,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\TOGGLE_COUNTER_SIG_0_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "5555")
+port map (
+regout => TOGGLE_COUNTER_SIG_58,
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_58,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datac => VCC,
+	datad => VCC,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+TOGGLE_SIG_Z146: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "9999")
+port map (
+regout => TOGGLE_SIG_83,
+clk => clk_pin_c,
+dataa => TOGGLE_SIG_83,
+datab => TOGGLE_SIG_0_0_0_G1,
+aclr => un6_dly_counter_0_x,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+R_Z147: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8000")
+port map (
+regout => r,
+clk => clk_pin_c,
+dataa => TOGGLE_SIG_83,
+datab => v_enable_sig,
+datac => B_NEXT_0_SQMUXA_7_4,
+datad => B_NEXT_0_SQMUXA_7_5,
+aclr => un6_dly_counter_0_x,
+	devpor => devpor,
+	devclrn => devclrn,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+B_Z148: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "4000")
+port map (
+regout => b,
+clk => clk_pin_c,
+dataa => TOGGLE_SIG_83,
+datab => v_enable_sig,
+datac => B_NEXT_0_SQMUXA_7_4,
+datad => B_NEXT_0_SQMUXA_7_5,
+aclr => un6_dly_counter_0_x,
+	devpor => devpor,
+	devclrn => devclrn,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+G_Z149: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff00")
+port map (
+regout => g,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+	devpor => devpor,
+	devclrn => devclrn,
+	dataa => VCC,
+	datab => VCC,
+	datac => VCC,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+TOGGLE_SIG_0_0_0_G1_Z150: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0703")
+port map (
+combout => TOGGLE_SIG_0_0_0_G1,
+dataa => TOGGLE_COUNTER_SIG_77,
+datab => TOGGLE_COUNTER_SIG_78,
+datac => TOGGLE_SIG_0_0_0_G1_2,
+datad => UN1_TOGGLE_COUNTER_SIGLTO18,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO18: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7f77")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLTO18,
+dataa => TOGGLE_COUNTER_SIG_75,
+datab => TOGGLE_COUNTER_SIG_76,
+datac => TOGGLE_COUNTER_SIG_74,
+datad => UN1_TOGGLE_COUNTER_SIGLTO15,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+B_NEXT_0_SQMUXA_7_5_Z152: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7f00")
+port map (
+combout => B_NEXT_0_SQMUXA_7_5,
+dataa => column_counter_sig_6,
+datab => column_counter_sig_7,
+datac => UN5_V_ENABLELTO5,
+datad => B_NEXT_0_SQMUXA_7_3,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+B_NEXT_0_SQMUXA_7_4_Z153: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ef23")
+port map (
+combout => B_NEXT_0_SQMUXA_7_4,
+dataa => line_counter_sig_8,
+datab => line_counter_sig_7,
+datac => UN13_V_ENABLELTO6,
+datad => B_NEXT_0_SQMUXA_7_4_A,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+B_NEXT_0_SQMUXA_7_4_A_Z154: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0f1f")
+port map (
+combout => B_NEXT_0_SQMUXA_7_4_A,
+dataa => line_counter_sig_4,
+datab => line_counter_sig_5,
+datac => line_counter_sig_6,
+datad => UN17_V_ENABLELTO3,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+B_NEXT_0_SQMUXA_7_3_Z155: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "e0f0")
+port map (
+combout => B_NEXT_0_SQMUXA_7_3,
+dataa => column_counter_sig_7,
+datab => column_counter_sig_9,
+datac => B_NEXT_0_SQMUXA_7_2,
+datad => UN9_V_ENABLELTO6,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO15: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff7f")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLTO15,
+dataa => TOGGLE_COUNTER_SIG_71,
+datab => TOGGLE_COUNTER_SIG_72,
+datac => TOGGLE_COUNTER_SIG_73,
+datad => UN1_TOGGLE_COUNTER_SIGLTO12,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+DRAW_SQUARE_NEXT_UN5_V_ENABLELTO5: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "feee")
+port map (
+combout => UN5_V_ENABLELTO5,
+dataa => column_counter_sig_4,
+datab => column_counter_sig_5,
+datac => column_counter_sig_3,
+datad => UN5_V_ENABLELT2,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO12: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0100")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLTO12,
+dataa => TOGGLE_COUNTER_SIG_68,
+datab => TOGGLE_COUNTER_SIG_69,
+datac => TOGGLE_COUNTER_SIG_70,
+datad => UN1_TOGGLE_COUNTER_SIGLTO9,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+DRAW_SQUARE_NEXT_UN13_V_ENABLELTO6: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7f77")
+port map (
+combout => UN13_V_ENABLELTO6,
+dataa => line_counter_sig_5,
+datab => line_counter_sig_6,
+datac => line_counter_sig_3,
+datad => UN13_V_ENABLELTO4_0,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+DRAW_SQUARE_NEXT_UN9_V_ENABLELTO6: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "f7f7")
+port map (
+combout => UN9_V_ENABLELTO6,
+dataa => column_counter_sig_5,
+datab => column_counter_sig_6,
+datac => UN9_V_ENABLELTO4,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO9: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7f77")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLTO9,
+dataa => TOGGLE_COUNTER_SIG_66,
+datab => TOGGLE_COUNTER_SIG_67,
+datac => TOGGLE_COUNTER_SIG_65,
+datad => UN1_TOGGLE_COUNTER_SIGLT6,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+DRAW_SQUARE_NEXT_UN17_V_ENABLELTO3: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "fe00")
+port map (
+combout => UN17_V_ENABLELTO3,
+dataa => line_counter_sig_1,
+datab => line_counter_sig_2,
+datac => line_counter_sig_0,
+datad => line_counter_sig_3,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+TOGGLE_SIG_0_0_0_G1_2_Z163: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "fffe")
+port map (
+combout => TOGGLE_SIG_0_0_0_G1_2,
+dataa => TOGGLE_COUNTER_SIG_81,
+datab => TOGGLE_COUNTER_SIG_82,
+datac => TOGGLE_COUNTER_SIG_79,
+datad => TOGGLE_COUNTER_SIG_80,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+B_NEXT_0_SQMUXA_7_2_Z164: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0004")
+port map (
+combout => B_NEXT_0_SQMUXA_7_2,
+dataa => column_counter_sig_8,
+datab => h_enable_sig,
+datac => column_counter_sig_9,
+datad => line_counter_sig_8,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+DRAW_SQUARE_NEXT_UN9_V_ENABLELTO4: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0101")
+port map (
+combout => UN9_V_ENABLELTO4,
+dataa => column_counter_sig_3,
+datab => column_counter_sig_4,
+datac => column_counter_sig_2,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+DRAW_SQUARE_NEXT_UN5_V_ENABLELT2: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "fefe")
+port map (
+combout => UN5_V_ENABLELT2,
+dataa => column_counter_sig_1,
+datab => column_counter_sig_2,
+datac => column_counter_sig_0,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+DRAW_SQUARE_NEXT_UN13_V_ENABLELTO4_0: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "1111")
+port map (
+combout => UN13_V_ENABLELTO4_0,
+dataa => line_counter_sig_4,
+datab => line_counter_sig_2,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLT6: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7777")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLT6,
+dataa => TOGGLE_COUNTER_SIG_64,
+datab => TOGGLE_COUNTER_SIG_63,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\UN2_TOGGLE_COUNTER_NEXT_0_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "5588")
+port map (
+cout => UN2_TOGGLE_COUNTER_NEXT_COUT(0),
+dataa => TOGGLE_COUNTER_SIG_58,
+datab => TOGGLE_COUNTER_SIG_59,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+GND <= '0';
+VCC <= '1';
+TOGGLE_SIG_0_0_0_G1_I <= not TOGGLE_SIG_0_0_0_G1;
+toggle_counter_sig_0 <= TOGGLE_COUNTER_SIG_58;
+toggle_counter_sig_1 <= TOGGLE_COUNTER_SIG_59;
+toggle_counter_sig_2 <= TOGGLE_COUNTER_SIG_60;
+toggle_counter_sig_3 <= TOGGLE_COUNTER_SIG_61;
+toggle_counter_sig_4 <= TOGGLE_COUNTER_SIG_62;
+toggle_counter_sig_5 <= TOGGLE_COUNTER_SIG_63;
+toggle_counter_sig_6 <= TOGGLE_COUNTER_SIG_64;
+toggle_counter_sig_7 <= TOGGLE_COUNTER_SIG_65;
+toggle_counter_sig_8 <= TOGGLE_COUNTER_SIG_66;
+toggle_counter_sig_9 <= TOGGLE_COUNTER_SIG_67;
+toggle_counter_sig_10 <= TOGGLE_COUNTER_SIG_68;
+toggle_counter_sig_11 <= TOGGLE_COUNTER_SIG_69;
+toggle_counter_sig_12 <= TOGGLE_COUNTER_SIG_70;
+toggle_counter_sig_13 <= TOGGLE_COUNTER_SIG_71;
+toggle_counter_sig_14 <= TOGGLE_COUNTER_SIG_72;
+toggle_counter_sig_15 <= TOGGLE_COUNTER_SIG_73;
+toggle_counter_sig_16 <= TOGGLE_COUNTER_SIG_74;
+toggle_counter_sig_17 <= TOGGLE_COUNTER_SIG_75;
+toggle_counter_sig_18 <= TOGGLE_COUNTER_SIG_76;
+toggle_counter_sig_19 <= TOGGLE_COUNTER_SIG_77;
+toggle_counter_sig_20 <= TOGGLE_COUNTER_SIG_78;
+toggle_counter_sig_21 <= TOGGLE_COUNTER_SIG_79;
+toggle_counter_sig_22 <= TOGGLE_COUNTER_SIG_80;
+toggle_counter_sig_23 <= TOGGLE_COUNTER_SIG_81;
+toggle_counter_sig_24 <= TOGGLE_COUNTER_SIG_82;
+toggle_sig <= TOGGLE_SIG_83;
+end beh;
+
+--
+library ieee, stratix;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+use stratix.stratix_components.all;
+
+entity vga_driver is
+port(
+line_counter_sig_0 :  out std_logic;
+line_counter_sig_1 :  out std_logic;
+line_counter_sig_2 :  out std_logic;
+line_counter_sig_3 :  out std_logic;
+line_counter_sig_4 :  out std_logic;
+line_counter_sig_5 :  out std_logic;
+line_counter_sig_6 :  out std_logic;
+line_counter_sig_7 :  out std_logic;
+line_counter_sig_8 :  out std_logic;
+dly_counter_1 :  in std_logic;
+dly_counter_0 :  in std_logic;
+vsync_state_2 :  out std_logic;
+vsync_state_5 :  out std_logic;
+vsync_state_3 :  out std_logic;
+vsync_state_6 :  out std_logic;
+vsync_state_4 :  out std_logic;
+vsync_state_1 :  out std_logic;
+vsync_state_0 :  out std_logic;
+hsync_state_2 :  out std_logic;
+hsync_state_4 :  out std_logic;
+hsync_state_0 :  out std_logic;
+hsync_state_5 :  out std_logic;
+hsync_state_1 :  out std_logic;
+hsync_state_3 :  out std_logic;
+hsync_state_6 :  out std_logic;
+column_counter_sig_0 :  out std_logic;
+column_counter_sig_1 :  out std_logic;
+column_counter_sig_2 :  out std_logic;
+column_counter_sig_3 :  out std_logic;
+column_counter_sig_4 :  out std_logic;
+column_counter_sig_5 :  out std_logic;
+column_counter_sig_6 :  out std_logic;
+column_counter_sig_7 :  out std_logic;
+column_counter_sig_8 :  out std_logic;
+column_counter_sig_9 :  out std_logic;
+vsync_counter_9 :  out std_logic;
+vsync_counter_8 :  out std_logic;
+vsync_counter_7 :  out std_logic;
+vsync_counter_6 :  out std_logic;
+vsync_counter_5 :  out std_logic;
+vsync_counter_4 :  out std_logic;
+vsync_counter_3 :  out std_logic;
+vsync_counter_2 :  out std_logic;
+vsync_counter_1 :  out std_logic;
+vsync_counter_0 :  out std_logic;
+hsync_counter_9 :  out std_logic;
+hsync_counter_8 :  out std_logic;
+hsync_counter_7 :  out std_logic;
+hsync_counter_6 :  out std_logic;
+hsync_counter_5 :  out std_logic;
+hsync_counter_4 :  out std_logic;
+hsync_counter_3 :  out std_logic;
+hsync_counter_2 :  out std_logic;
+hsync_counter_1 :  out std_logic;
+hsync_counter_0 :  out std_logic;
+d_set_vsync_counter :  out std_logic;
+v_sync :  out std_logic;
+h_sync :  out std_logic;
+h_enable_sig :  out std_logic;
+v_enable_sig :  out std_logic;
+reset_pin_c :  in std_logic;
+un6_dly_counter_0_x :  out std_logic;
+d_set_hsync_counter :  out std_logic;
+clk_pin_c :  in std_logic);
+end vga_driver;
+
+architecture beh of vga_driver is
+signal devclrn : std_logic := '1';
+signal devpor : std_logic := '1';
+signal devoe : std_logic := '0';
+signal HSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
+signal VSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
+signal UN2_COLUMN_COUNTER_NEXT_COMBOUT : std_logic_vector(9 downto 1);
+signal UN1_LINE_COUNTER_SIG_COMBOUT : std_logic_vector(9 downto 1);
+signal UN1_LINE_COUNTER_SIG_COUT : std_logic_vector(7 downto 1);
+signal UN1_LINE_COUNTER_SIG_A_COUT : std_logic_vector(1 to 1);
+signal UN2_COLUMN_COUNTER_NEXT_COUT : std_logic_vector(7 downto 0);
+signal HSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
+signal G_2_I : std_logic ;
+signal UN9_HSYNC_COUNTERLT9 : std_logic ;
+signal VSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
+signal G_16_I : std_logic ;
+signal UN9_VSYNC_COUNTERLT9 : std_logic ;
+signal UN10_COLUMN_COUNTER_SIGLTO9 : std_logic ;
+signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
+signal \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\ : std_logic ;
+signal UN6_DLY_COUNTER_0_X_56 : std_logic ;
+signal VSYNC_STATE_NEXT_2_SQMUXA : std_logic ;
+signal UN12_VSYNC_COUNTER_7 : std_logic ;
+signal UN13_VSYNC_COUNTER_4 : std_logic ;
+signal UN10_LINE_COUNTER_SIGLTO8 : std_logic ;
+signal LINE_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
+signal V_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
+signal H_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
+signal H_SYNC_1_0_0_0_G1 : std_logic ;
+signal V_SYNC_1_0_0_0_G1 : std_logic ;
+signal UN14_VSYNC_COUNTER_8 : std_logic ;
+signal \HSYNC_STATE_3_0_0_0__G0_0\ : std_logic ;
+signal UN10_HSYNC_COUNTER_3 : std_logic ;
+signal UN10_HSYNC_COUNTER_1 : std_logic ;
+signal UN10_HSYNC_COUNTER_4 : std_logic ;
+signal UN12_HSYNC_COUNTER : std_logic ;
+signal UN11_HSYNC_COUNTER_2 : std_logic ;
+signal UN11_HSYNC_COUNTER_3 : std_logic ;
+signal UN13_HSYNC_COUNTER : std_logic ;
+signal VSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
+signal VSYNC_STATE_NEXT_1_SQMUXA_3 : std_logic ;
+signal UN1_VSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
+signal HSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
+signal HSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
+signal UN1_HSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
+signal UN12_VSYNC_COUNTER_6 : std_logic ;
+signal UN15_VSYNC_COUNTER_4 : std_logic ;
+signal VSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
+signal UN10_LINE_COUNTER_SIGLTO5 : std_logic ;
+signal UN10_COLUMN_COUNTER_SIGLT6 : std_logic ;
+signal UN13_HSYNC_COUNTER_2 : std_logic ;
+signal UN13_HSYNC_COUNTER_7 : std_logic ;
+signal UN9_HSYNC_COUNTERLT9_3 : std_logic ;
+signal UN9_VSYNC_COUNTERLT9_5 : std_logic ;
+signal UN9_VSYNC_COUNTERLT9_6 : std_logic ;
+signal UN12_HSYNC_COUNTER_3 : std_logic ;
+signal UN12_HSYNC_COUNTER_4 : std_logic ;
+signal UN10_LINE_COUNTER_SIGLT4_2 : std_logic ;
+signal UN15_VSYNC_COUNTER_3 : std_logic ;
+signal UN13_VSYNC_COUNTER_3 : std_logic ;
+signal UN10_COLUMN_COUNTER_SIGLT6_4 : std_logic ;
+signal D_SET_HSYNC_COUNTER_57 : std_logic ;
+signal V_SYNC_54 : std_logic ;
+signal UN1_VSYNC_STATE_2_0 : std_logic ;
+signal H_SYNC_55 : std_logic ;
+signal UN1_HSYNC_STATE_3_0 : std_logic ;
+signal D_SET_VSYNC_COUNTER_53 : std_logic ;
+signal VCC : std_logic ;
+signal LINE_COUNTER_SIG_0_0 : std_logic ;
+signal LINE_COUNTER_SIG_1_0 : std_logic ;
+signal LINE_COUNTER_SIG_2_0 : std_logic ;
+signal LINE_COUNTER_SIG_3_0 : std_logic ;
+signal LINE_COUNTER_SIG_4_0 : std_logic ;
+signal LINE_COUNTER_SIG_5_0 : std_logic ;
+signal LINE_COUNTER_SIG_6_0 : std_logic ;
+signal LINE_COUNTER_SIG_7_0 : std_logic ;
+signal LINE_COUNTER_SIG_8_0 : std_logic ;
+signal VSYNC_STATE_9 : std_logic ;
+signal VSYNC_STATE_10 : std_logic ;
+signal VSYNC_STATE_11 : std_logic ;
+signal VSYNC_STATE_12 : std_logic ;
+signal VSYNC_STATE_13 : std_logic ;
+signal VSYNC_STATE_14 : std_logic ;
+signal VSYNC_STATE_15 : std_logic ;
+signal HSYNC_STATE_16 : std_logic ;
+signal HSYNC_STATE_17 : std_logic ;
+signal HSYNC_STATE_18 : std_logic ;
+signal HSYNC_STATE_19 : std_logic ;
+signal HSYNC_STATE_20 : std_logic ;
+signal HSYNC_STATE_21 : std_logic ;
+signal HSYNC_STATE_22 : std_logic ;
+signal COLUMN_COUNTER_SIG_23 : std_logic ;
+signal COLUMN_COUNTER_SIG_24 : std_logic ;
+signal COLUMN_COUNTER_SIG_25 : std_logic ;
+signal COLUMN_COUNTER_SIG_26 : std_logic ;
+signal COLUMN_COUNTER_SIG_27 : std_logic ;
+signal COLUMN_COUNTER_SIG_28 : std_logic ;
+signal COLUMN_COUNTER_SIG_29 : std_logic ;
+signal COLUMN_COUNTER_SIG_30 : std_logic ;
+signal COLUMN_COUNTER_SIG_31 : std_logic ;
+signal COLUMN_COUNTER_SIG_32 : std_logic ;
+signal VSYNC_COUNTER_33 : std_logic ;
+signal VSYNC_COUNTER_34 : std_logic ;
+signal VSYNC_COUNTER_35 : std_logic ;
+signal VSYNC_COUNTER_36 : std_logic ;
+signal VSYNC_COUNTER_37 : std_logic ;
+signal VSYNC_COUNTER_38 : std_logic ;
+signal VSYNC_COUNTER_39 : std_logic ;
+signal VSYNC_COUNTER_40 : std_logic ;
+signal VSYNC_COUNTER_41 : std_logic ;
+signal VSYNC_COUNTER_42 : std_logic ;
+signal HSYNC_COUNTER_43 : std_logic ;
+signal HSYNC_COUNTER_44 : std_logic ;
+signal HSYNC_COUNTER_45 : std_logic ;
+signal HSYNC_COUNTER_46 : std_logic ;
+signal HSYNC_COUNTER_47 : std_logic ;
+signal HSYNC_COUNTER_48 : std_logic ;
+signal HSYNC_COUNTER_49 : std_logic ;
+signal HSYNC_COUNTER_50 : std_logic ;
+signal HSYNC_COUNTER_51 : std_logic ;
+signal HSYNC_COUNTER_52 : std_logic ;
+signal GND : std_logic ;
+signal LINE_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
+signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
+signal G_16_I_I : std_logic ;
+signal UN9_VSYNC_COUNTERLT9_I : std_logic ;
+signal G_2_I_I : std_logic ;
+signal UN9_HSYNC_COUNTERLT9_I : std_logic ;
+begin
+\HSYNC_COUNTER_0_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "55aa")
+port map (
+regout => HSYNC_COUNTER_52,
+cout => HSYNC_COUNTER_COUT(0),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_52,
+datab => VCC,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\HSYNC_COUNTER_1_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_51,
+cout => HSYNC_COUNTER_COUT(1),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_51,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(0),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\HSYNC_COUNTER_2_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_50,
+cout => HSYNC_COUNTER_COUT(2),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_50,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(1),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\HSYNC_COUNTER_3_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_49,
+cout => HSYNC_COUNTER_COUT(3),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_49,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(2),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\HSYNC_COUNTER_4_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_48,
+cout => HSYNC_COUNTER_COUT(4),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_48,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(3),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\HSYNC_COUNTER_5_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_47,
+cout => HSYNC_COUNTER_COUT(5),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_47,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(4),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\HSYNC_COUNTER_6_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_46,
+cout => HSYNC_COUNTER_COUT(6),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_46,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(5),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\HSYNC_COUNTER_7_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_45,
+cout => HSYNC_COUNTER_COUT(7),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(6),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\HSYNC_COUNTER_8_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_44,
+cout => HSYNC_COUNTER_COUT(8),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_44,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(7),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\HSYNC_COUNTER_9_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a5a")
+port map (
+regout => HSYNC_COUNTER_43,
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_43,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(8),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_0_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "6688")
+port map (
+regout => VSYNC_COUNTER_42,
+cout => VSYNC_COUNTER_COUT(0),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_42,
+datab => D_SET_HSYNC_COUNTER_57,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_1_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_41,
+cout => VSYNC_COUNTER_COUT(1),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_41,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(0),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_2_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_40,
+cout => VSYNC_COUNTER_COUT(2),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_40,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(1),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_3_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_39,
+cout => VSYNC_COUNTER_COUT(3),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_39,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(2),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_4_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_38,
+cout => VSYNC_COUNTER_COUT(4),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_38,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(3),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_5_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_37,
+cout => VSYNC_COUNTER_COUT(5),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_37,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(4),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_6_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_36,
+cout => VSYNC_COUNTER_COUT(6),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_36,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(5),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_7_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_35,
+cout => VSYNC_COUNTER_COUT(7),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_35,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(6),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_8_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "reg_and_comb",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_34,
+cout => VSYNC_COUNTER_COUT(8),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_34,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(7),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\VSYNC_COUNTER_9_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a5a")
+port map (
+regout => VSYNC_COUNTER_33,
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_33,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(8),
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datad => VCC,
+	aclr => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_9_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_32,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_8_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8080")
+port map (
+regout => COLUMN_COUNTER_SIG_31,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
+	devpor => devpor,
+	devclrn => devclrn,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_7_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8080")
+port map (
+regout => COLUMN_COUNTER_SIG_30,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
+	devpor => devpor,
+	devclrn => devclrn,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_6_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_29,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_5_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_28,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_4_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_27,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_3_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_26,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_2_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_25,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_1_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_24,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\COLUMN_COUNTER_SIG_0_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "7777")
+port map (
+regout => COLUMN_COUNTER_SIG_23,
+clk => clk_pin_c,
+dataa => COLUMN_COUNTER_SIG_23,
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\HSYNC_STATE_6_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff00")
+port map (
+regout => HSYNC_STATE_22,
+clk => clk_pin_c,
+datad => UN6_DLY_COUNTER_0_X_56,
+	devpor => devpor,
+	devclrn => devclrn,
+	dataa => VCC,
+	datab => VCC,
+	datac => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\VSYNC_STATE_0_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0cae")
+port map (
+regout => VSYNC_STATE_15,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_15,
+datab => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
+datac => UN6_DLY_COUNTER_0_X_56,
+datad => VSYNC_STATE_NEXT_2_SQMUXA,
+	devpor => devpor,
+	devclrn => devclrn,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\VSYNC_STATE_1_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0080")
+port map (
+regout => VSYNC_STATE_14,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_13,
+datab => UN12_VSYNC_COUNTER_7,
+datac => UN13_VSYNC_COUNTER_4,
+datad => UN6_DLY_COUNTER_0_X_56,
+	devpor => devpor,
+	devclrn => devclrn,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\VSYNC_STATE_6_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_and_comb",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7f7f")
+port map (
+combout => UN6_DLY_COUNTER_0_X_56,
+regout => VSYNC_STATE_12,
+clk => clk_pin_c,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+	devpor => devpor,
+	devclrn => devclrn,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_8_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(9),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_7_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(8),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_6_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(7),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8080")
+port map (
+regout => LINE_COUNTER_SIG_5_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(6),
+datac => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
+	devpor => devpor,
+	devclrn => devclrn,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_4_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(5),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_3_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(4),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_2_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(3),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_1_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(2),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\LINE_COUNTER_SIG_0_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "bbbb")
+port map (
+regout => LINE_COUNTER_SIG_0_0,
+clk => clk_pin_c,
+dataa => UN1_LINE_COUNTER_SIG_COMBOUT(1),
+datab => UN10_LINE_COUNTER_SIGLTO8,
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+V_ENABLE_SIG_Z283: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "eeee")
+port map (
+regout => v_enable_sig,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_21,
+datab => HSYNC_STATE_20,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+H_ENABLE_SIG_Z284: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "eeee")
+port map (
+regout => h_enable_sig,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_11,
+datab => VSYNC_STATE_14,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+H_SYNC_Z285: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff7f")
+port map (
+regout => H_SYNC_55,
+clk => clk_pin_c,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => H_SYNC_1_0_0_0_G1,
+	devpor => devpor,
+	devclrn => devclrn,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+V_SYNC_Z286: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff7f")
+port map (
+regout => V_SYNC_54,
+clk => clk_pin_c,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => V_SYNC_1_0_0_0_G1,
+	devpor => devpor,
+	devclrn => devclrn,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\VSYNC_STATE_5_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "eeee")
+port map (
+regout => VSYNC_STATE_10,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_12,
+datab => VSYNC_STATE_15,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => VSYNC_STATE_NEXT_2_SQMUXA,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\VSYNC_STATE_4_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "2000")
+port map (
+regout => VSYNC_STATE_13,
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_STATE_10,
+datad => UN14_VSYNC_COUNTER_8,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => VSYNC_STATE_NEXT_2_SQMUXA,
+	devpor => devpor,
+	devclrn => devclrn,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\VSYNC_STATE_3_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "aaaa")
+port map (
+regout => VSYNC_STATE_11,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_14,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => VSYNC_STATE_NEXT_2_SQMUXA,
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\VSYNC_STATE_2_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "8000")
+port map (
+regout => VSYNC_STATE_9,
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_STATE_11,
+datad => UN14_VSYNC_COUNTER_8,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => VSYNC_STATE_NEXT_2_SQMUXA,
+	devpor => devpor,
+	devclrn => devclrn,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\HSYNC_STATE_5_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "eeee")
+port map (
+regout => HSYNC_STATE_19,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_22,
+datab => HSYNC_STATE_18,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\HSYNC_STATE_4_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "8000")
+port map (
+regout => HSYNC_STATE_17,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_19,
+datab => UN10_HSYNC_COUNTER_3,
+datac => UN10_HSYNC_COUNTER_1,
+datad => UN10_HSYNC_COUNTER_4,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+	devpor => devpor,
+	devclrn => devclrn,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\HSYNC_STATE_3_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "aaaa")
+port map (
+regout => HSYNC_STATE_21,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_20,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+	devpor => devpor,
+	devclrn => devclrn,
+	datab => VCC,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\HSYNC_STATE_2_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "8888")
+port map (
+regout => HSYNC_STATE_16,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_21,
+datab => UN12_HSYNC_COUNTER,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\HSYNC_STATE_1_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "8000")
+port map (
+regout => HSYNC_STATE_20,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_17,
+datab => UN11_HSYNC_COUNTER_2,
+datac => UN10_HSYNC_COUNTER_1,
+datad => UN11_HSYNC_COUNTER_3,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+	devpor => devpor,
+	devclrn => devclrn,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\HSYNC_STATE_0_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "on",
+     sum_lutc_input => "datac",
+    lut_mask => "8888")
+port map (
+regout => HSYNC_STATE_18,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_16,
+datab => UN13_HSYNC_COUNTER,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+	devpor => devpor,
+	devclrn => devclrn,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sload => GND,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_STATE_NEXT_2_SQMUXA_Z297: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "aaab")
+port map (
+combout => VSYNC_STATE_NEXT_2_SQMUXA,
+dataa => UN6_DLY_COUNTER_0_X_56,
+datab => VSYNC_STATE_NEXT_1_SQMUXA_1,
+datac => VSYNC_STATE_NEXT_1_SQMUXA_3,
+datad => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\HSYNC_STATE_3_0_0_0__G0_0_Z298\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "f0f1")
+port map (
+combout => \HSYNC_STATE_3_0_0_0__G0_0\,
+dataa => HSYNC_STATE_NEXT_1_SQMUXA_1,
+datab => HSYNC_STATE_NEXT_1_SQMUXA_2,
+datac => UN6_DLY_COUNTER_0_X_56,
+datad => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+UN1_HSYNC_STATE_NEXT_1_SQMUXA_0_Z299: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0ace")
+port map (
+combout => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
+dataa => HSYNC_STATE_16,
+datab => HSYNC_STATE_21,
+datac => UN13_HSYNC_COUNTER,
+datad => UN12_HSYNC_COUNTER,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+UN1_VSYNC_STATE_NEXT_1_SQMUXA_0_Z300: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff2a")
+port map (
+combout => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
+dataa => VSYNC_STATE_9,
+datab => UN12_VSYNC_COUNTER_6,
+datac => UN15_VSYNC_COUNTER_4,
+datad => VSYNC_STATE_NEXT_1_SQMUXA_2,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\VSYNC_STATE_3_IV_0_0__G0_0_A3_0_Z301\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8080")
+port map (
+combout => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
+dataa => VSYNC_STATE_9,
+datab => UN12_VSYNC_COUNTER_6,
+datac => UN15_VSYNC_COUNTER_4,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO8: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff7f")
+port map (
+combout => UN10_LINE_COUNTER_SIGLTO8,
+dataa => LINE_COUNTER_SIG_6_0,
+datab => LINE_COUNTER_SIG_7_0,
+datac => LINE_COUNTER_SIG_8_0,
+datad => UN10_LINE_COUNTER_SIGLTO5,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+G_2: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0f1f")
+port map (
+combout => G_2_I,
+dataa => HSYNC_STATE_18,
+datab => HSYNC_STATE_22,
+datac => UN9_HSYNC_COUNTERLT9,
+datad => UN6_DLY_COUNTER_0_X_56,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_STATE_NEXT_1_SQMUXA_1_Z304: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "d0f0")
+port map (
+combout => VSYNC_STATE_NEXT_1_SQMUXA_1,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_STATE_10,
+datad => UN14_VSYNC_COUNTER_8,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_STATE_NEXT_1_SQMUXA_2_Z305: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "2a2a")
+port map (
+combout => VSYNC_STATE_NEXT_1_SQMUXA_2,
+dataa => VSYNC_STATE_13,
+datab => UN12_VSYNC_COUNTER_7,
+datac => UN13_VSYNC_COUNTER_4,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_STATE_NEXT_1_SQMUXA_3_Z306: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "70f0")
+port map (
+combout => VSYNC_STATE_NEXT_1_SQMUXA_3,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_STATE_11,
+datad => UN14_VSYNC_COUNTER_8,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+G_16: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0f1f")
+port map (
+combout => G_16_I,
+dataa => VSYNC_STATE_15,
+datab => VSYNC_STATE_12,
+datac => UN9_VSYNC_COUNTERLT9,
+datad => UN6_DLY_COUNTER_0_X_56,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLTO9: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "1f0f")
+port map (
+combout => UN10_COLUMN_COUNTER_SIGLTO9,
+dataa => COLUMN_COUNTER_SIG_30,
+datab => COLUMN_COUNTER_SIG_31,
+datac => COLUMN_COUNTER_SIG_32,
+datad => UN10_COLUMN_COUNTER_SIGLT6,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_STATE_NEXT_1_SQMUXA_2_Z309: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "2aaa")
+port map (
+combout => HSYNC_STATE_NEXT_1_SQMUXA_2,
+dataa => HSYNC_STATE_17,
+datab => UN11_HSYNC_COUNTER_2,
+datac => UN10_HSYNC_COUNTER_1,
+datad => UN11_HSYNC_COUNTER_3,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_STATE_NEXT_1_SQMUXA_1_Z310: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "2aaa")
+port map (
+combout => HSYNC_STATE_NEXT_1_SQMUXA_1,
+dataa => HSYNC_STATE_19,
+datab => UN10_HSYNC_COUNTER_3,
+datac => UN10_HSYNC_COUNTER_1,
+datad => UN10_HSYNC_COUNTER_4,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "1000")
+port map (
+combout => UN13_HSYNC_COUNTER,
+dataa => HSYNC_COUNTER_46,
+datab => HSYNC_COUNTER_45,
+datac => UN13_HSYNC_COUNTER_2,
+datad => UN13_HSYNC_COUNTER_7,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "f7ff")
+port map (
+combout => UN9_HSYNC_COUNTERLT9,
+dataa => HSYNC_COUNTER_44,
+datab => HSYNC_COUNTER_43,
+datac => UN9_HSYNC_COUNTERLT9_3,
+datad => UN13_HSYNC_COUNTER_7,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "fff7")
+port map (
+combout => UN9_VSYNC_COUNTERLT9,
+dataa => VSYNC_COUNTER_38,
+datab => VSYNC_COUNTER_37,
+datac => UN9_VSYNC_COUNTERLT9_5,
+datad => UN9_VSYNC_COUNTERLT9_6,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8000")
+port map (
+combout => UN12_HSYNC_COUNTER,
+dataa => HSYNC_COUNTER_52,
+datab => HSYNC_COUNTER_51,
+datac => UN12_HSYNC_COUNTER_3,
+datad => UN12_HSYNC_COUNTER_4,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO5: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0f07")
+port map (
+combout => UN10_LINE_COUNTER_SIGLTO5,
+dataa => LINE_COUNTER_SIG_1_0,
+datab => LINE_COUNTER_SIG_2_0,
+datac => LINE_COUNTER_SIG_5_0,
+datad => UN10_LINE_COUNTER_SIGLT4_2,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_4: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "1010")
+port map (
+combout => UN15_VSYNC_COUNTER_4,
+dataa => VSYNC_COUNTER_41,
+datab => VSYNC_COUNTER_38,
+datac => UN15_VSYNC_COUNTER_3,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_4: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8080")
+port map (
+combout => UN13_VSYNC_COUNTER_4,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_37,
+datac => UN13_VSYNC_COUNTER_3,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ff7f")
+port map (
+combout => UN10_COLUMN_COUNTER_SIGLT6,
+dataa => COLUMN_COUNTER_SIG_27,
+datab => COLUMN_COUNTER_SIG_29,
+datac => COLUMN_COUNTER_SIG_28,
+datad => UN10_COLUMN_COUNTER_SIGLT6_4,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_COUNTER_NEXT_1_SQMUXA_Z319: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0080")
+port map (
+combout => HSYNC_COUNTER_NEXT_1_SQMUXA,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => D_SET_HSYNC_COUNTER_57,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_FSM_NEXT_UN14_VSYNC_COUNTER_8: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8888")
+port map (
+combout => UN14_VSYNC_COUNTER_8,
+dataa => UN12_VSYNC_COUNTER_6,
+datab => UN12_VSYNC_COUNTER_7,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+LINE_COUNTER_NEXT_0_SQMUXA_1_1_Z321: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0080")
+port map (
+combout => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => VSYNC_STATE_14,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+V_SYNC_1_0_0_0_G1_Z322: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ccd8")
+port map (
+combout => V_SYNC_1_0_0_0_G1,
+dataa => VSYNC_STATE_9,
+datab => V_SYNC_54,
+datac => VSYNC_STATE_13,
+datad => UN1_VSYNC_STATE_2_0,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+H_ENABLE_SIG_1_0_0_0_G0_I_O4_Z323: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "f1f1")
+port map (
+combout => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
+dataa => VSYNC_STATE_13,
+datab => VSYNC_STATE_10,
+datac => UN6_DLY_COUNTER_0_X_56,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_COUNTER_NEXT_1_SQMUXA_Z324: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0080")
+port map (
+combout => VSYNC_COUNTER_NEXT_1_SQMUXA,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => D_SET_VSYNC_COUNTER_53,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+V_ENABLE_SIG_1_0_0_0_G0_I_O4_Z325: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "f1f1")
+port map (
+combout => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
+dataa => HSYNC_STATE_17,
+datab => HSYNC_STATE_19,
+datac => UN6_DLY_COUNTER_0_X_56,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+H_SYNC_1_0_0_0_G1_Z326: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "ccd8")
+port map (
+combout => H_SYNC_1_0_0_0_G1,
+dataa => HSYNC_STATE_16,
+datab => H_SYNC_55,
+datac => HSYNC_STATE_17,
+datad => UN1_HSYNC_STATE_3_0,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_Z327: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0080")
+port map (
+combout => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => HSYNC_STATE_20,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_4: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0010")
+port map (
+combout => UN12_HSYNC_COUNTER_4,
+dataa => HSYNC_COUNTER_46,
+datab => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_43,
+datad => HSYNC_COUNTER_49,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_3: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0008")
+port map (
+combout => UN12_HSYNC_COUNTER_3,
+dataa => HSYNC_COUNTER_50,
+datab => HSYNC_COUNTER_44,
+datac => HSYNC_COUNTER_48,
+datad => HSYNC_COUNTER_47,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_3: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0008")
+port map (
+combout => UN11_HSYNC_COUNTER_3,
+dataa => HSYNC_COUNTER_52,
+datab => HSYNC_COUNTER_51,
+datac => HSYNC_COUNTER_49,
+datad => HSYNC_COUNTER_48,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_2: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0808")
+port map (
+combout => UN11_HSYNC_COUNTER_2,
+dataa => HSYNC_COUNTER_50,
+datab => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_46,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9_3: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7fff")
+port map (
+combout => UN9_HSYNC_COUNTERLT9_3,
+dataa => HSYNC_COUNTER_46,
+datab => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_48,
+datad => HSYNC_COUNTER_47,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_2: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0080")
+port map (
+combout => UN13_HSYNC_COUNTER_2,
+dataa => HSYNC_COUNTER_44,
+datab => HSYNC_COUNTER_43,
+datac => HSYNC_COUNTER_48,
+datad => HSYNC_COUNTER_47,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_6: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7fff")
+port map (
+combout => UN9_VSYNC_COUNTERLT9_6,
+dataa => VSYNC_COUNTER_40,
+datab => VSYNC_COUNTER_39,
+datac => VSYNC_COUNTER_42,
+datad => VSYNC_COUNTER_41,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_5: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7fff")
+port map (
+combout => UN9_VSYNC_COUNTERLT9_5,
+dataa => VSYNC_COUNTER_34,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_COUNTER_36,
+datad => VSYNC_COUNTER_35,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_4: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8000")
+port map (
+combout => UN10_HSYNC_COUNTER_4,
+dataa => HSYNC_COUNTER_48,
+datab => HSYNC_COUNTER_46,
+datac => HSYNC_COUNTER_51,
+datad => HSYNC_COUNTER_49,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_3: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0101")
+port map (
+combout => UN10_HSYNC_COUNTER_3,
+dataa => HSYNC_COUNTER_52,
+datab => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_50,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_3: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0020")
+port map (
+combout => UN15_VSYNC_COUNTER_3,
+dataa => VSYNC_COUNTER_33,
+datab => VSYNC_COUNTER_40,
+datac => VSYNC_COUNTER_39,
+datad => VSYNC_COUNTER_42,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_3: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0001")
+port map (
+combout => UN13_VSYNC_COUNTER_3,
+dataa => VSYNC_COUNTER_36,
+datab => VSYNC_COUNTER_35,
+datac => VSYNC_COUNTER_34,
+datad => VSYNC_COUNTER_33,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6_4: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7fff")
+port map (
+combout => UN10_COLUMN_COUNTER_SIGLT6_4,
+dataa => COLUMN_COUNTER_SIG_25,
+datab => COLUMN_COUNTER_SIG_26,
+datac => COLUMN_COUNTER_SIG_23,
+datad => COLUMN_COUNTER_SIG_24,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLT4_2: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "7f7f")
+port map (
+combout => UN10_LINE_COUNTER_SIGLT4_2,
+dataa => LINE_COUNTER_SIG_3_0,
+datab => LINE_COUNTER_SIG_4_0,
+datac => LINE_COUNTER_SIG_0_0,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_1: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0101")
+port map (
+combout => UN10_HSYNC_COUNTER_1,
+dataa => HSYNC_COUNTER_47,
+datab => HSYNC_COUNTER_44,
+datac => HSYNC_COUNTER_43,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_6: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0001")
+port map (
+combout => UN12_VSYNC_COUNTER_6,
+dataa => VSYNC_COUNTER_35,
+datab => VSYNC_COUNTER_34,
+datac => VSYNC_COUNTER_37,
+datad => VSYNC_COUNTER_36,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_7: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0001")
+port map (
+combout => UN12_VSYNC_COUNTER_7,
+dataa => VSYNC_COUNTER_39,
+datab => VSYNC_COUNTER_38,
+datac => VSYNC_COUNTER_41,
+datad => VSYNC_COUNTER_40,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_7: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "8000")
+port map (
+combout => UN13_HSYNC_COUNTER_7,
+dataa => HSYNC_COUNTER_50,
+datab => HSYNC_COUNTER_49,
+datac => HSYNC_COUNTER_52,
+datad => HSYNC_COUNTER_51,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+UN1_HSYNC_STATE_3_0_Z346: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "eeee")
+port map (
+combout => UN1_HSYNC_STATE_3_0,
+dataa => HSYNC_STATE_21,
+datab => HSYNC_STATE_20,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+UN1_VSYNC_STATE_2_0_Z347: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "eeee")
+port map (
+combout => UN1_VSYNC_STATE_2_0,
+dataa => VSYNC_STATE_11,
+datab => VSYNC_STATE_14,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+D_SET_HSYNC_COUNTER_Z348: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "eeee")
+port map (
+combout => D_SET_HSYNC_COUNTER_57,
+dataa => HSYNC_STATE_22,
+datab => HSYNC_STATE_18,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+D_SET_VSYNC_COUNTER_Z349: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "eeee")
+port map (
+combout => D_SET_VSYNC_COUNTER_53,
+dataa => VSYNC_STATE_12,
+datab => VSYNC_STATE_15,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_9_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c6c")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(9),
+dataa => LINE_COUNTER_SIG_7_0,
+datab => LINE_COUNTER_SIG_8_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(7),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a5a")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(8),
+dataa => LINE_COUNTER_SIG_7_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(6),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datab => VCC,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(7),
+cout => UN1_LINE_COUNTER_SIG_COUT(7),
+dataa => LINE_COUNTER_SIG_5_0,
+datab => LINE_COUNTER_SIG_6_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(5),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(6),
+cout => UN1_LINE_COUNTER_SIG_COUT(6),
+dataa => LINE_COUNTER_SIG_5_0,
+datab => LINE_COUNTER_SIG_6_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(4),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(5),
+cout => UN1_LINE_COUNTER_SIG_COUT(5),
+dataa => LINE_COUNTER_SIG_3_0,
+datab => LINE_COUNTER_SIG_4_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(3),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(4),
+cout => UN1_LINE_COUNTER_SIG_COUT(4),
+dataa => LINE_COUNTER_SIG_3_0,
+datab => LINE_COUNTER_SIG_4_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(2),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(3),
+cout => UN1_LINE_COUNTER_SIG_COUT(3),
+dataa => LINE_COUNTER_SIG_1_0,
+datab => LINE_COUNTER_SIG_2_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(1),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(2),
+cout => UN1_LINE_COUNTER_SIG_COUT(2),
+dataa => LINE_COUNTER_SIG_1_0,
+datab => LINE_COUNTER_SIG_2_0,
+cin => UN1_LINE_COUNTER_SIG_A_COUT(1),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_A_1_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "0088")
+port map (
+cout => UN1_LINE_COUNTER_SIG_A_COUT(1),
+dataa => D_SET_HSYNC_COUNTER_57,
+datab => LINE_COUNTER_SIG_0_0,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\UN1_LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "6688")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(1),
+cout => UN1_LINE_COUNTER_SIG_COUT(1),
+dataa => D_SET_HSYNC_COUNTER_57,
+datab => LINE_COUNTER_SIG_0_0,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_9_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c6c")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
+dataa => COLUMN_COUNTER_SIG_31,
+datab => COLUMN_COUNTER_SIG_32,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(7),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_8_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a5a")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
+dataa => COLUMN_COUNTER_SIG_31,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(6),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datab => VCC,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_7_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(7),
+dataa => COLUMN_COUNTER_SIG_29,
+datab => COLUMN_COUNTER_SIG_30,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(5),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_6_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(6),
+dataa => COLUMN_COUNTER_SIG_29,
+datab => COLUMN_COUNTER_SIG_30,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(4),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_5_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(5),
+dataa => COLUMN_COUNTER_SIG_27,
+datab => COLUMN_COUNTER_SIG_28,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(3),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_4_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(4),
+dataa => COLUMN_COUNTER_SIG_27,
+datab => COLUMN_COUNTER_SIG_28,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(2),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_3_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "6c80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(3),
+dataa => COLUMN_COUNTER_SIG_25,
+datab => COLUMN_COUNTER_SIG_26,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(1),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_2_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "cin",
+     cin_used => "true",
+    lut_mask => "5a80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(2),
+dataa => COLUMN_COUNTER_SIG_25,
+datab => COLUMN_COUNTER_SIG_26,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(0),
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_1_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "6688")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(1),
+dataa => COLUMN_COUNTER_SIG_23,
+datab => COLUMN_COUNTER_SIG_24,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_0_\: stratix_lcell generic map (
+    operation_mode => "arithmetic",
+    output_mode => "comb_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "5588")
+port map (
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(0),
+dataa => COLUMN_COUNTER_SIG_23,
+datab => COLUMN_COUNTER_SIG_24,
+	devpor => devpor,
+	devclrn => devclrn,
+	clk => GND,
+	datac => VCC,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+VCC <= '1';
+GND <= '0';
+LINE_COUNTER_NEXT_0_SQMUXA_1_1_I <= not LINE_COUNTER_NEXT_0_SQMUXA_1_1;
+COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I <= not COLUMN_COUNTER_NEXT_0_SQMUXA_1_1;
+G_16_I_I <= not G_16_I;
+UN9_VSYNC_COUNTERLT9_I <= not UN9_VSYNC_COUNTERLT9;
+G_2_I_I <= not G_2_I;
+UN9_HSYNC_COUNTERLT9_I <= not UN9_HSYNC_COUNTERLT9;
+line_counter_sig_0 <= LINE_COUNTER_SIG_0_0;
+line_counter_sig_1 <= LINE_COUNTER_SIG_1_0;
+line_counter_sig_2 <= LINE_COUNTER_SIG_2_0;
+line_counter_sig_3 <= LINE_COUNTER_SIG_3_0;
+line_counter_sig_4 <= LINE_COUNTER_SIG_4_0;
+line_counter_sig_5 <= LINE_COUNTER_SIG_5_0;
+line_counter_sig_6 <= LINE_COUNTER_SIG_6_0;
+line_counter_sig_7 <= LINE_COUNTER_SIG_7_0;
+line_counter_sig_8 <= LINE_COUNTER_SIG_8_0;
+vsync_state_2 <= VSYNC_STATE_9;
+vsync_state_5 <= VSYNC_STATE_10;
+vsync_state_3 <= VSYNC_STATE_11;
+vsync_state_6 <= VSYNC_STATE_12;
+vsync_state_4 <= VSYNC_STATE_13;
+vsync_state_1 <= VSYNC_STATE_14;
+vsync_state_0 <= VSYNC_STATE_15;
+hsync_state_2 <= HSYNC_STATE_16;
+hsync_state_4 <= HSYNC_STATE_17;
+hsync_state_0 <= HSYNC_STATE_18;
+hsync_state_5 <= HSYNC_STATE_19;
+hsync_state_1 <= HSYNC_STATE_20;
+hsync_state_3 <= HSYNC_STATE_21;
+hsync_state_6 <= HSYNC_STATE_22;
+column_counter_sig_0 <= COLUMN_COUNTER_SIG_23;
+column_counter_sig_1 <= COLUMN_COUNTER_SIG_24;
+column_counter_sig_2 <= COLUMN_COUNTER_SIG_25;
+column_counter_sig_3 <= COLUMN_COUNTER_SIG_26;
+column_counter_sig_4 <= COLUMN_COUNTER_SIG_27;
+column_counter_sig_5 <= COLUMN_COUNTER_SIG_28;
+column_counter_sig_6 <= COLUMN_COUNTER_SIG_29;
+column_counter_sig_7 <= COLUMN_COUNTER_SIG_30;
+column_counter_sig_8 <= COLUMN_COUNTER_SIG_31;
+column_counter_sig_9 <= COLUMN_COUNTER_SIG_32;
+vsync_counter_9 <= VSYNC_COUNTER_33;
+vsync_counter_8 <= VSYNC_COUNTER_34;
+vsync_counter_7 <= VSYNC_COUNTER_35;
+vsync_counter_6 <= VSYNC_COUNTER_36;
+vsync_counter_5 <= VSYNC_COUNTER_37;
+vsync_counter_4 <= VSYNC_COUNTER_38;
+vsync_counter_3 <= VSYNC_COUNTER_39;
+vsync_counter_2 <= VSYNC_COUNTER_40;
+vsync_counter_1 <= VSYNC_COUNTER_41;
+vsync_counter_0 <= VSYNC_COUNTER_42;
+hsync_counter_9 <= HSYNC_COUNTER_43;
+hsync_counter_8 <= HSYNC_COUNTER_44;
+hsync_counter_7 <= HSYNC_COUNTER_45;
+hsync_counter_6 <= HSYNC_COUNTER_46;
+hsync_counter_5 <= HSYNC_COUNTER_47;
+hsync_counter_4 <= HSYNC_COUNTER_48;
+hsync_counter_3 <= HSYNC_COUNTER_49;
+hsync_counter_2 <= HSYNC_COUNTER_50;
+hsync_counter_1 <= HSYNC_COUNTER_51;
+hsync_counter_0 <= HSYNC_COUNTER_52;
+d_set_vsync_counter <= D_SET_VSYNC_COUNTER_53;
+v_sync <= V_SYNC_54;
+h_sync <= H_SYNC_55;
+un6_dly_counter_0_x <= UN6_DLY_COUNTER_0_X_56;
+d_set_hsync_counter <= D_SET_HSYNC_COUNTER_57;
+end beh;
+
+--
+library ieee, stratix;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+use stratix.stratix_components.all;
+
+entity vga is
+port(
+clk_pin :  in std_logic;
+reset_pin :  in std_logic;
+r0_pin :  out std_logic;
+r1_pin :  out std_logic;
+r2_pin :  out std_logic;
+g0_pin :  out std_logic;
+g1_pin :  out std_logic;
+g2_pin :  out std_logic;
+b0_pin :  out std_logic;
+b1_pin :  out std_logic;
+hsync_pin :  out std_logic;
+vsync_pin :  out std_logic;
+seven_seg_pin : out std_logic_vector(13 downto 0);
+d_hsync :  out std_logic;
+d_vsync :  out std_logic;
+d_column_counter : out std_logic_vector(9 downto 0);
+d_line_counter : out std_logic_vector(8 downto 0);
+d_set_column_counter :  out std_logic;
+d_set_line_counter :  out std_logic;
+d_hsync_counter : out std_logic_vector(9 downto 0);
+d_vsync_counter : out std_logic_vector(9 downto 0);
+d_set_hsync_counter :  out std_logic;
+d_set_vsync_counter :  out std_logic;
+d_h_enable :  out std_logic;
+d_v_enable :  out std_logic;
+d_r :  out std_logic;
+d_g :  out std_logic;
+d_b :  out std_logic;
+d_hsync_state : out std_logic_vector(0 to 6);
+d_vsync_state : out std_logic_vector(0 to 6);
+d_state_clk :  out std_logic;
+d_toggle :  out std_logic;
+d_toggle_counter : out std_logic_vector(24 downto 0));
+end vga;
+
+architecture beh of vga is
+signal devclrn : std_logic := '1';
+signal devpor : std_logic := '1';
+signal devoe : std_logic := '0';
+signal DLY_COUNTER : std_logic_vector(1 downto 0);
+signal \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\ : std_logic_vector(9 downto 0);
+signal \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\ : std_logic_vector(8 downto 0);
+signal \VGA_DRIVER_UNIT.HSYNC_COUNTER\ : std_logic_vector(9 downto 0);
+signal \VGA_DRIVER_UNIT.VSYNC_COUNTER\ : std_logic_vector(9 downto 0);
+signal \VGA_DRIVER_UNIT.HSYNC_STATE\ : std_logic_vector(6 downto 0);
+signal \VGA_DRIVER_UNIT.VSYNC_STATE\ : std_logic_vector(6 downto 0);
+signal \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\ : std_logic_vector(24 downto 0);
+signal SEVEN_SEG_PINZ : std_logic_vector(13 downto 0);
+signal D_COLUMN_COUNTERZ : std_logic_vector(9 downto 0);
+signal D_LINE_COUNTERZ : std_logic_vector(8 downto 0);
+signal D_HSYNC_COUNTERZ : std_logic_vector(9 downto 0);
+signal D_VSYNC_COUNTERZ : std_logic_vector(9 downto 0);
+signal D_HSYNC_STATEZ : std_logic_vector(6 downto 0);
+signal D_VSYNC_STATEZ : std_logic_vector(6 downto 0);
+signal D_TOGGLE_COUNTERZ : std_logic_vector(24 downto 0);
+signal VCC : std_logic ;
+signal GND : std_logic ;
+signal \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\ : std_logic ;
+signal \VGA_DRIVER_UNIT.H_SYNC\ : std_logic ;
+signal \VGA_DRIVER_UNIT.V_SYNC\ : std_logic ;
+signal \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\ : std_logic ;
+signal \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\ : std_logic ;
+signal \VGA_DRIVER_UNIT.H_ENABLE_SIG\ : std_logic ;
+signal \VGA_DRIVER_UNIT.V_ENABLE_SIG\ : std_logic ;
+signal \VGA_CONTROL_UNIT.R\ : std_logic ;
+signal \VGA_CONTROL_UNIT.G\ : std_logic ;
+signal \VGA_CONTROL_UNIT.B\ : std_logic ;
+signal G_33 : std_logic ;
+signal \VGA_CONTROL_UNIT.TOGGLE_SIG\ : std_logic ;
+signal CLK_PIN_C : std_logic ;
+signal RESET_PIN_C : std_logic ;
+signal CLK_PIN_INTERNAL : std_logic ;
+signal RESET_PIN_INTERNAL : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_84_0 : std_logic ;
+signal N_85_0 : std_logic ;
+signal N_86_0 : std_logic ;
+signal N_87_0 : std_logic ;
+signal N_88_0 : std_logic ;
+signal N_89_0 : std_logic ;
+signal N_90_0 : std_logic ;
+signal N_91_0 : std_logic ;
+signal N_92_0 : std_logic ;
+signal N_93_0 : std_logic ;
+signal N_94_0 : std_logic ;
+signal N_95_0 : std_logic ;
+signal N_96_0 : std_logic ;
+signal N_97_0 : std_logic ;
+signal N_98_0 : std_logic ;
+signal N_99_0 : std_logic ;
+signal N_100_0 : std_logic ;
+signal N_101_0 : std_logic ;
+signal N_102_0 : std_logic ;
+signal N_103_0 : std_logic ;
+signal N_104_0 : std_logic ;
+signal N_105_0 : std_logic ;
+signal N_106_0 : std_logic ;
+signal N_107_0 : std_logic ;
+signal N_108_0 : std_logic ;
+signal N_109_0 : std_logic ;
+signal N_110_0 : std_logic ;
+signal N_111_0 : std_logic ;
+signal N_112_0 : std_logic ;
+signal N_113_0 : std_logic ;
+signal N_114_0 : std_logic ;
+signal N_115_0 : std_logic ;
+signal N_116_0 : std_logic ;
+signal N_117_0 : std_logic ;
+signal N_118 : std_logic ;
+signal N_119 : std_logic ;
+signal N_120 : std_logic ;
+signal N_121 : std_logic ;
+signal N_122 : std_logic ;
+signal N_123 : std_logic ;
+signal N_124 : std_logic ;
+signal N_125 : std_logic ;
+signal N_126 : std_logic ;
+signal N_127 : std_logic ;
+signal N_128 : std_logic ;
+signal N_129 : std_logic ;
+signal N_130 : std_logic ;
+signal N_131 : std_logic ;
+signal N_132 : std_logic ;
+signal N_133 : std_logic ;
+signal N_134 : std_logic ;
+signal N_135 : std_logic ;
+signal N_136 : std_logic ;
+signal N_137 : std_logic ;
+signal N_138 : std_logic ;
+signal N_139 : std_logic ;
+signal N_140 : std_logic ;
+signal N_141 : std_logic ;
+signal N_142 : std_logic ;
+signal N_143 : std_logic ;
+signal N_144 : std_logic ;
+signal N_145 : std_logic ;
+signal N_146 : std_logic ;
+signal N_147 : std_logic ;
+signal N_148 : std_logic ;
+signal N_149 : std_logic ;
+signal N_150 : std_logic ;
+signal N_151 : std_logic ;
+signal N_152 : std_logic ;
+signal N_153 : std_logic ;
+signal N_154 : std_logic ;
+signal N_155 : std_logic ;
+signal N_156 : std_logic ;
+signal N_157 : std_logic ;
+signal N_158 : std_logic ;
+signal N_159 : std_logic ;
+signal N_160 : std_logic ;
+signal N_161 : std_logic ;
+signal N_162 : std_logic ;
+signal N_163 : std_logic ;
+signal N_164 : std_logic ;
+signal N_165 : std_logic ;
+signal N_166 : std_logic ;
+signal N_167 : std_logic ;
+signal N_168 : std_logic ;
+signal N_169 : std_logic ;
+signal N_170 : std_logic ;
+signal N_171 : std_logic ;
+signal N_172 : std_logic ;
+signal N_173 : std_logic ;
+signal N_174 : std_logic ;
+signal N_175 : std_logic ;
+signal N_176 : std_logic ;
+signal N_177 : std_logic ;
+signal N_178 : std_logic ;
+signal N_179 : std_logic ;
+signal N_180 : std_logic ;
+signal N_181 : std_logic ;
+signal N_182 : std_logic ;
+signal N_183 : std_logic ;
+signal N_184 : std_logic ;
+signal N_185 : std_logic ;
+signal N_186 : std_logic ;
+signal N_187 : std_logic ;
+signal N_188 : std_logic ;
+signal N_189 : std_logic ;
+signal N_190 : std_logic ;
+signal N_191 : std_logic ;
+signal N_192 : std_logic ;
+signal N_193 : std_logic ;
+signal N_194 : std_logic ;
+signal N_195 : std_logic ;
+signal N_196 : std_logic ;
+signal N_197 : std_logic ;
+signal N_198 : std_logic ;
+signal R0_PINZ : std_logic ;
+signal R1_PINZ : std_logic ;
+signal R2_PINZ : std_logic ;
+signal G0_PINZ : std_logic ;
+signal G1_PINZ : std_logic ;
+signal G2_PINZ : std_logic ;
+signal B0_PINZ : std_logic ;
+signal B1_PINZ : std_logic ;
+signal HSYNC_PINZ : std_logic ;
+signal VSYNC_PINZ : std_logic ;
+signal D_HSYNCZ : std_logic ;
+signal D_VSYNCZ : std_logic ;
+signal D_SET_COLUMN_COUNTERZ : std_logic ;
+signal D_SET_LINE_COUNTERZ : std_logic ;
+signal D_SET_HSYNC_COUNTERZ : std_logic ;
+signal D_SET_VSYNC_COUNTERZ : std_logic ;
+signal D_H_ENABLEZ : std_logic ;
+signal D_V_ENABLEZ : std_logic ;
+signal D_RZ : std_logic ;
+signal D_GZ : std_logic ;
+signal D_BZ : std_logic ;
+signal D_STATE_CLKZ : std_logic ;
+signal D_TOGGLEZ : std_logic ;
+component vga_driver
+port(
+  line_counter_sig_0 :  out std_logic;
+  line_counter_sig_1 :  out std_logic;
+  line_counter_sig_2 :  out std_logic;
+  line_counter_sig_3 :  out std_logic;
+  line_counter_sig_4 :  out std_logic;
+  line_counter_sig_5 :  out std_logic;
+  line_counter_sig_6 :  out std_logic;
+  line_counter_sig_7 :  out std_logic;
+  line_counter_sig_8 :  out std_logic;
+  dly_counter_1 :  in std_logic;
+  dly_counter_0 :  in std_logic;
+  vsync_state_2 :  out std_logic;
+  vsync_state_5 :  out std_logic;
+  vsync_state_3 :  out std_logic;
+  vsync_state_6 :  out std_logic;
+  vsync_state_4 :  out std_logic;
+  vsync_state_1 :  out std_logic;
+  vsync_state_0 :  out std_logic;
+  hsync_state_2 :  out std_logic;
+  hsync_state_4 :  out std_logic;
+  hsync_state_0 :  out std_logic;
+  hsync_state_5 :  out std_logic;
+  hsync_state_1 :  out std_logic;
+  hsync_state_3 :  out std_logic;
+  hsync_state_6 :  out std_logic;
+  column_counter_sig_0 :  out std_logic;
+  column_counter_sig_1 :  out std_logic;
+  column_counter_sig_2 :  out std_logic;
+  column_counter_sig_3 :  out std_logic;
+  column_counter_sig_4 :  out std_logic;
+  column_counter_sig_5 :  out std_logic;
+  column_counter_sig_6 :  out std_logic;
+  column_counter_sig_7 :  out std_logic;
+  column_counter_sig_8 :  out std_logic;
+  column_counter_sig_9 :  out std_logic;
+  vsync_counter_9 :  out std_logic;
+  vsync_counter_8 :  out std_logic;
+  vsync_counter_7 :  out std_logic;
+  vsync_counter_6 :  out std_logic;
+  vsync_counter_5 :  out std_logic;
+  vsync_counter_4 :  out std_logic;
+  vsync_counter_3 :  out std_logic;
+  vsync_counter_2 :  out std_logic;
+  vsync_counter_1 :  out std_logic;
+  vsync_counter_0 :  out std_logic;
+  hsync_counter_9 :  out std_logic;
+  hsync_counter_8 :  out std_logic;
+  hsync_counter_7 :  out std_logic;
+  hsync_counter_6 :  out std_logic;
+  hsync_counter_5 :  out std_logic;
+  hsync_counter_4 :  out std_logic;
+  hsync_counter_3 :  out std_logic;
+  hsync_counter_2 :  out std_logic;
+  hsync_counter_1 :  out std_logic;
+  hsync_counter_0 :  out std_logic;
+  d_set_vsync_counter :  out std_logic;
+  v_sync :  out std_logic;
+  h_sync :  out std_logic;
+  h_enable_sig :  out std_logic;
+  v_enable_sig :  out std_logic;
+  reset_pin_c :  in std_logic;
+  un6_dly_counter_0_x :  out std_logic;
+  d_set_hsync_counter :  out std_logic;
+  clk_pin_c :  in std_logic  );
+end component;
+component vga_control
+port(
+  line_counter_sig_0 :  in std_logic;
+  line_counter_sig_2 :  in std_logic;
+  line_counter_sig_1 :  in std_logic;
+  line_counter_sig_3 :  in std_logic;
+  line_counter_sig_6 :  in std_logic;
+  line_counter_sig_5 :  in std_logic;
+  line_counter_sig_4 :  in std_logic;
+  line_counter_sig_7 :  in std_logic;
+  line_counter_sig_8 :  in std_logic;
+  column_counter_sig_0 :  in std_logic;
+  column_counter_sig_1 :  in std_logic;
+  column_counter_sig_2 :  in std_logic;
+  column_counter_sig_8 :  in std_logic;
+  column_counter_sig_3 :  in std_logic;
+  column_counter_sig_5 :  in std_logic;
+  column_counter_sig_4 :  in std_logic;
+  column_counter_sig_9 :  in std_logic;
+  column_counter_sig_7 :  in std_logic;
+  column_counter_sig_6 :  in std_logic;
+  toggle_counter_sig_0 :  out std_logic;
+  toggle_counter_sig_1 :  out std_logic;
+  toggle_counter_sig_2 :  out std_logic;
+  toggle_counter_sig_3 :  out std_logic;
+  toggle_counter_sig_4 :  out std_logic;
+  toggle_counter_sig_5 :  out std_logic;
+  toggle_counter_sig_6 :  out std_logic;
+  toggle_counter_sig_7 :  out std_logic;
+  toggle_counter_sig_8 :  out std_logic;
+  toggle_counter_sig_9 :  out std_logic;
+  toggle_counter_sig_10 :  out std_logic;
+  toggle_counter_sig_11 :  out std_logic;
+  toggle_counter_sig_12 :  out std_logic;
+  toggle_counter_sig_13 :  out std_logic;
+  toggle_counter_sig_14 :  out std_logic;
+  toggle_counter_sig_15 :  out std_logic;
+  toggle_counter_sig_16 :  out std_logic;
+  toggle_counter_sig_17 :  out std_logic;
+  toggle_counter_sig_18 :  out std_logic;
+  toggle_counter_sig_19 :  out std_logic;
+  toggle_counter_sig_20 :  out std_logic;
+  toggle_counter_sig_21 :  out std_logic;
+  toggle_counter_sig_22 :  out std_logic;
+  toggle_counter_sig_23 :  out std_logic;
+  toggle_counter_sig_24 :  out std_logic;
+  h_enable_sig :  in std_logic;
+  g :  out std_logic;
+  b :  out std_logic;
+  v_enable_sig :  in std_logic;
+  r :  out std_logic;
+  toggle_sig :  out std_logic;
+  un6_dly_counter_0_x :  in std_logic;
+  clk_pin_c :  in std_logic  );
+end component;
+begin
+VCC <= '1';
+GND <= '0';
+\DLY_COUNTER_1_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "a8a8")
+port map (
+regout => DLY_COUNTER(1),
+clk => CLK_PIN_C,
+dataa => RESET_PIN_C,
+datab => DLY_COUNTER(0),
+datac => DLY_COUNTER(1),
+	devpor => devpor,
+	devclrn => devclrn,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+\DLY_COUNTER_0_\: stratix_lcell generic map (
+    operation_mode => "normal",
+    output_mode => "reg_only",
+    synch_mode => "off",
+     sum_lutc_input => "datac",
+    lut_mask => "a2a2")
+port map (
+regout => DLY_COUNTER(0),
+clk => CLK_PIN_C,
+dataa => RESET_PIN_C,
+datab => DLY_COUNTER(0),
+datac => DLY_COUNTER(1),
+	devpor => devpor,
+	devclrn => devclrn,
+	datad => VCC,
+	aclr => GND,
+	sclr => GND,
+	sload => GND,
+	ena => VCC,
+	cin => GND,
+	inverta => GND,
+	aload => GND);
+RESET_PIN_IN: stratix_io generic map (
+    operation_mode => "input"
+    )
+port map (
+padio => N_2,
+combout => RESET_PIN_C,
+oe => GND,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+CLK_PIN_IN: stratix_io generic map (
+    operation_mode => "input"
+    )
+port map (
+padio => N_1,
+combout => CLK_PIN_C,
+oe => GND,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_24_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(24),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_23_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(23),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_22_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(22),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_21_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(21),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_20_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(20),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_19_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(19),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_18_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(18),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_17_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(17),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_16_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(16),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_15_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(15),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_14_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(14),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_13_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(13),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_12_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(12),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_11_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(11),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_10_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(10),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_9_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(9),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_8_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(8),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_7_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(7),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_6_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(6),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_5_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(5),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_4_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(4),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_3_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(3),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_2_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(2),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_1_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(1),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_TOGGLE_COUNTER_OUT_0_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLE_COUNTERZ(0),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_TOGGLE_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_TOGGLEZ,
+datain => \VGA_CONTROL_UNIT.TOGGLE_SIG\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_STATE_CLK_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_STATE_CLKZ,
+datain => G_33,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_STATE_OUT_0_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_STATEZ(0),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_STATE_OUT_1_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_STATEZ(1),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_STATE_OUT_2_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_STATEZ(2),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_STATE_OUT_3_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_STATEZ(3),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_STATE_OUT_4_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_STATEZ(4),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_STATE_OUT_5_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_STATEZ(5),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_STATE_OUT_6_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_STATEZ(6),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_STATE_OUT_0_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_STATEZ(0),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_STATE_OUT_1_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_STATEZ(1),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_STATE_OUT_2_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_STATEZ(2),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_STATE_OUT_3_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_STATEZ(3),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_STATE_OUT_4_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_STATEZ(4),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_STATE_OUT_5_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_STATEZ(5),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_STATE_OUT_6_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_STATEZ(6),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_B_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_BZ,
+datain => \VGA_CONTROL_UNIT.B\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_G_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_GZ,
+datain => \VGA_CONTROL_UNIT.G\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_R_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_RZ,
+datain => \VGA_CONTROL_UNIT.R\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_V_ENABLE_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_V_ENABLEZ,
+datain => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_H_ENABLE_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_H_ENABLEZ,
+datain => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_SET_VSYNC_COUNTER_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_SET_VSYNC_COUNTERZ,
+datain => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_SET_HSYNC_COUNTER_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_SET_HSYNC_COUNTERZ,
+datain => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_9_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(9),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_8_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(8),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_7_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(7),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_6_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(6),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_5_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(5),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_4_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(4),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_3_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(3),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_2_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(2),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_1_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(1),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_VSYNC_COUNTER_OUT_0_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNC_COUNTERZ(0),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_9_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(9),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_8_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(8),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_7_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(7),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_6_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(6),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_5_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(5),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_4_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(4),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_3_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(3),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_2_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(2),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_1_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(1),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_HSYNC_COUNTER_OUT_0_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNC_COUNTERZ(0),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_SET_LINE_COUNTER_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_SET_LINE_COUNTERZ,
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_SET_COLUMN_COUNTER_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_SET_COLUMN_COUNTERZ,
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_LINE_COUNTER_OUT_8_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_LINE_COUNTERZ(8),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_LINE_COUNTER_OUT_7_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_LINE_COUNTERZ(7),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_LINE_COUNTER_OUT_6_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_LINE_COUNTERZ(6),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_LINE_COUNTER_OUT_5_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_LINE_COUNTERZ(5),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_LINE_COUNTER_OUT_4_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_LINE_COUNTERZ(4),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_LINE_COUNTER_OUT_3_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_LINE_COUNTERZ(3),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_LINE_COUNTER_OUT_2_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_LINE_COUNTERZ(2),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_LINE_COUNTER_OUT_1_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_LINE_COUNTERZ(1),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_LINE_COUNTER_OUT_0_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_LINE_COUNTERZ(0),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_9_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(9),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_8_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(8),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_7_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(7),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_6_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(6),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_5_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(5),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_4_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(4),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_3_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(3),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_2_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(2),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_1_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(1),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\D_COLUMN_COUNTER_OUT_0_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_COLUMN_COUNTERZ(0),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_VSYNC_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_VSYNCZ,
+datain => \VGA_DRIVER_UNIT.V_SYNC\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+D_HSYNC_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => D_HSYNCZ,
+datain => \VGA_DRIVER_UNIT.H_SYNC\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_TRI_13_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(13),
+datain => VCC,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_OUT_12_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(12),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_OUT_11_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(11),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_OUT_10_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(10),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_OUT_9_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(9),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_OUT_8_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(8),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_OUT_7_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(7),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_TRI_6_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(6),
+datain => VCC,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_TRI_5_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(5),
+datain => VCC,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_TRI_4_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(4),
+datain => VCC,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_TRI_3_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(3),
+datain => VCC,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_OUT_2_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(2),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_OUT_1_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(1),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+\SEVEN_SEG_PIN_TRI_0_\: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => SEVEN_SEG_PINZ(0),
+datain => VCC,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+VSYNC_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => VSYNC_PINZ,
+datain => \VGA_DRIVER_UNIT.V_SYNC\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+HSYNC_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => HSYNC_PINZ,
+datain => \VGA_DRIVER_UNIT.H_SYNC\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+B1_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => B1_PINZ,
+datain => \VGA_CONTROL_UNIT.B\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+B0_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => B0_PINZ,
+datain => \VGA_CONTROL_UNIT.B\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+G2_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => G2_PINZ,
+datain => \VGA_CONTROL_UNIT.G\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+G1_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => G1_PINZ,
+datain => \VGA_CONTROL_UNIT.G\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+G0_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => G0_PINZ,
+datain => \VGA_CONTROL_UNIT.G\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+R2_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => R2_PINZ,
+datain => \VGA_CONTROL_UNIT.R\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+R1_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => R1_PINZ,
+datain => \VGA_CONTROL_UNIT.R\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+R0_PIN_OUT: stratix_io generic map (
+    operation_mode => "output"
+    )
+port map (
+padio => R0_PINZ,
+datain => \VGA_CONTROL_UNIT.R\,
+oe => VCC,
+	devpor => devpor,
+	devclrn => devclrn,
+	devoe => devoe,
+	outclkena => VCC,
+	inclkena => VCC,
+	areset => GND,
+	sreset => GND);
+G_33 <= CLK_PIN_C;
+VGA_DRIVER_UNIT: vga_driver port map (
+line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
+line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
+line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
+line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
+line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
+line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
+line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
+line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
+line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
+dly_counter_1 => DLY_COUNTER(1),
+dly_counter_0 => DLY_COUNTER(0),
+vsync_state_2 => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
+vsync_state_5 => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
+vsync_state_3 => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
+vsync_state_6 => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
+vsync_state_4 => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
+vsync_state_1 => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
+vsync_state_0 => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
+hsync_state_2 => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
+hsync_state_4 => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
+hsync_state_0 => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
+hsync_state_5 => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
+hsync_state_1 => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
+hsync_state_3 => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
+hsync_state_6 => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
+column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
+column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
+column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
+column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
+column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
+column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
+column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
+column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
+column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
+column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
+vsync_counter_9 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
+vsync_counter_8 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
+vsync_counter_7 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
+vsync_counter_6 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
+vsync_counter_5 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
+vsync_counter_4 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
+vsync_counter_3 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
+vsync_counter_2 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
+vsync_counter_1 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
+vsync_counter_0 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
+hsync_counter_9 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
+hsync_counter_8 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
+hsync_counter_7 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
+hsync_counter_6 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
+hsync_counter_5 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
+hsync_counter_4 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
+hsync_counter_3 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
+hsync_counter_2 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
+hsync_counter_1 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
+hsync_counter_0 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
+d_set_vsync_counter => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
+v_sync => \VGA_DRIVER_UNIT.V_SYNC\,
+h_sync => \VGA_DRIVER_UNIT.H_SYNC\,
+h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
+v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
+reset_pin_c => RESET_PIN_C,
+un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+d_set_hsync_counter => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
+clk_pin_c => CLK_PIN_C);
+VGA_CONTROL_UNIT: vga_control port map (
+line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
+line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
+line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
+line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
+line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
+line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
+line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
+line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
+line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
+column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
+column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
+column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
+column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
+column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
+column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
+column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
+column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
+column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
+column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
+toggle_counter_sig_0 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0),
+toggle_counter_sig_1 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1),
+toggle_counter_sig_2 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2),
+toggle_counter_sig_3 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3),
+toggle_counter_sig_4 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4),
+toggle_counter_sig_5 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5),
+toggle_counter_sig_6 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6),
+toggle_counter_sig_7 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7),
+toggle_counter_sig_8 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8),
+toggle_counter_sig_9 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9),
+toggle_counter_sig_10 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10),
+toggle_counter_sig_11 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11),
+toggle_counter_sig_12 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12),
+toggle_counter_sig_13 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13),
+toggle_counter_sig_14 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14),
+toggle_counter_sig_15 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15),
+toggle_counter_sig_16 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16),
+toggle_counter_sig_17 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17),
+toggle_counter_sig_18 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18),
+toggle_counter_sig_19 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19),
+toggle_counter_sig_20 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20),
+toggle_counter_sig_21 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21),
+toggle_counter_sig_22 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22),
+toggle_counter_sig_23 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23),
+toggle_counter_sig_24 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24),
+h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
+g => \VGA_CONTROL_UNIT.G\,
+b => \VGA_CONTROL_UNIT.B\,
+v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
+r => \VGA_CONTROL_UNIT.R\,
+toggle_sig => \VGA_CONTROL_UNIT.TOGGLE_SIG\,
+un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+clk_pin_c => CLK_PIN_C);
+N_1 <= CLK_PIN_INTERNAL;
+N_2 <= RESET_PIN_INTERNAL;
+N_84_0 <= R0_PINZ;
+N_85_0 <= R1_PINZ;
+N_86_0 <= R2_PINZ;
+N_87_0 <= G0_PINZ;
+N_88_0 <= G1_PINZ;
+N_89_0 <= G2_PINZ;
+N_90_0 <= B0_PINZ;
+N_91_0 <= B1_PINZ;
+N_92_0 <= HSYNC_PINZ;
+N_93_0 <= VSYNC_PINZ;
+N_94_0 <= SEVEN_SEG_PINZ(0);
+N_95_0 <= SEVEN_SEG_PINZ(1);
+N_96_0 <= SEVEN_SEG_PINZ(2);
+N_97_0 <= SEVEN_SEG_PINZ(3);
+N_98_0 <= SEVEN_SEG_PINZ(4);
+N_99_0 <= SEVEN_SEG_PINZ(5);
+N_100_0 <= SEVEN_SEG_PINZ(6);
+N_101_0 <= SEVEN_SEG_PINZ(7);
+N_102_0 <= SEVEN_SEG_PINZ(8);
+N_103_0 <= SEVEN_SEG_PINZ(9);
+N_104_0 <= SEVEN_SEG_PINZ(10);
+N_105_0 <= SEVEN_SEG_PINZ(11);
+N_106_0 <= SEVEN_SEG_PINZ(12);
+N_107_0 <= SEVEN_SEG_PINZ(13);
+N_108_0 <= D_HSYNCZ;
+N_109_0 <= D_VSYNCZ;
+N_110_0 <= D_COLUMN_COUNTERZ(0);
+N_111_0 <= D_COLUMN_COUNTERZ(1);
+N_112_0 <= D_COLUMN_COUNTERZ(2);
+N_113_0 <= D_COLUMN_COUNTERZ(3);
+N_114_0 <= D_COLUMN_COUNTERZ(4);
+N_115_0 <= D_COLUMN_COUNTERZ(5);
+N_116_0 <= D_COLUMN_COUNTERZ(6);
+N_117_0 <= D_COLUMN_COUNTERZ(7);
+N_118 <= D_COLUMN_COUNTERZ(8);
+N_119 <= D_COLUMN_COUNTERZ(9);
+N_120 <= D_LINE_COUNTERZ(0);
+N_121 <= D_LINE_COUNTERZ(1);
+N_122 <= D_LINE_COUNTERZ(2);
+N_123 <= D_LINE_COUNTERZ(3);
+N_124 <= D_LINE_COUNTERZ(4);
+N_125 <= D_LINE_COUNTERZ(5);
+N_126 <= D_LINE_COUNTERZ(6);
+N_127 <= D_LINE_COUNTERZ(7);
+N_128 <= D_LINE_COUNTERZ(8);
+N_129 <= D_SET_COLUMN_COUNTERZ;
+N_130 <= D_SET_LINE_COUNTERZ;
+N_131 <= D_HSYNC_COUNTERZ(0);
+N_132 <= D_HSYNC_COUNTERZ(1);
+N_133 <= D_HSYNC_COUNTERZ(2);
+N_134 <= D_HSYNC_COUNTERZ(3);
+N_135 <= D_HSYNC_COUNTERZ(4);
+N_136 <= D_HSYNC_COUNTERZ(5);
+N_137 <= D_HSYNC_COUNTERZ(6);
+N_138 <= D_HSYNC_COUNTERZ(7);
+N_139 <= D_HSYNC_COUNTERZ(8);
+N_140 <= D_HSYNC_COUNTERZ(9);
+N_141 <= D_VSYNC_COUNTERZ(0);
+N_142 <= D_VSYNC_COUNTERZ(1);
+N_143 <= D_VSYNC_COUNTERZ(2);
+N_144 <= D_VSYNC_COUNTERZ(3);
+N_145 <= D_VSYNC_COUNTERZ(4);
+N_146 <= D_VSYNC_COUNTERZ(5);
+N_147 <= D_VSYNC_COUNTERZ(6);
+N_148 <= D_VSYNC_COUNTERZ(7);
+N_149 <= D_VSYNC_COUNTERZ(8);
+N_150 <= D_VSYNC_COUNTERZ(9);
+N_151 <= D_SET_HSYNC_COUNTERZ;
+N_152 <= D_SET_VSYNC_COUNTERZ;
+N_153 <= D_H_ENABLEZ;
+N_154 <= D_V_ENABLEZ;
+N_155 <= D_RZ;
+N_156 <= D_GZ;
+N_157 <= D_BZ;
+N_158 <= D_HSYNC_STATEZ(6);
+N_159 <= D_HSYNC_STATEZ(5);
+N_160 <= D_HSYNC_STATEZ(4);
+N_161 <= D_HSYNC_STATEZ(3);
+N_162 <= D_HSYNC_STATEZ(2);
+N_163 <= D_HSYNC_STATEZ(1);
+N_164 <= D_HSYNC_STATEZ(0);
+N_165 <= D_VSYNC_STATEZ(6);
+N_166 <= D_VSYNC_STATEZ(5);
+N_167 <= D_VSYNC_STATEZ(4);
+N_168 <= D_VSYNC_STATEZ(3);
+N_169 <= D_VSYNC_STATEZ(2);
+N_170 <= D_VSYNC_STATEZ(1);
+N_171 <= D_VSYNC_STATEZ(0);
+N_172 <= D_STATE_CLKZ;
+N_173 <= D_TOGGLEZ;
+N_174 <= D_TOGGLE_COUNTERZ(0);
+N_175 <= D_TOGGLE_COUNTERZ(1);
+N_176 <= D_TOGGLE_COUNTERZ(2);
+N_177 <= D_TOGGLE_COUNTERZ(3);
+N_178 <= D_TOGGLE_COUNTERZ(4);
+N_179 <= D_TOGGLE_COUNTERZ(5);
+N_180 <= D_TOGGLE_COUNTERZ(6);
+N_181 <= D_TOGGLE_COUNTERZ(7);
+N_182 <= D_TOGGLE_COUNTERZ(8);
+N_183 <= D_TOGGLE_COUNTERZ(9);
+N_184 <= D_TOGGLE_COUNTERZ(10);
+N_185 <= D_TOGGLE_COUNTERZ(11);
+N_186 <= D_TOGGLE_COUNTERZ(12);
+N_187 <= D_TOGGLE_COUNTERZ(13);
+N_188 <= D_TOGGLE_COUNTERZ(14);
+N_189 <= D_TOGGLE_COUNTERZ(15);
+N_190 <= D_TOGGLE_COUNTERZ(16);
+N_191 <= D_TOGGLE_COUNTERZ(17);
+N_192 <= D_TOGGLE_COUNTERZ(18);
+N_193 <= D_TOGGLE_COUNTERZ(19);
+N_194 <= D_TOGGLE_COUNTERZ(20);
+N_195 <= D_TOGGLE_COUNTERZ(21);
+N_196 <= D_TOGGLE_COUNTERZ(22);
+N_197 <= D_TOGGLE_COUNTERZ(23);
+N_198 <= D_TOGGLE_COUNTERZ(24);
+r0_pin <= N_84_0;
+r1_pin <= N_85_0;
+r2_pin <= N_86_0;
+g0_pin <= N_87_0;
+g1_pin <= N_88_0;
+g2_pin <= N_89_0;
+b0_pin <= N_90_0;
+b1_pin <= N_91_0;
+hsync_pin <= N_92_0;
+vsync_pin <= N_93_0;
+seven_seg_pin(0) <= N_94_0;
+seven_seg_pin(1) <= N_95_0;
+seven_seg_pin(2) <= N_96_0;
+seven_seg_pin(3) <= N_97_0;
+seven_seg_pin(4) <= N_98_0;
+seven_seg_pin(5) <= N_99_0;
+seven_seg_pin(6) <= N_100_0;
+seven_seg_pin(7) <= N_101_0;
+seven_seg_pin(8) <= N_102_0;
+seven_seg_pin(9) <= N_103_0;
+seven_seg_pin(10) <= N_104_0;
+seven_seg_pin(11) <= N_105_0;
+seven_seg_pin(12) <= N_106_0;
+seven_seg_pin(13) <= N_107_0;
+d_hsync <= N_108_0;
+d_vsync <= N_109_0;
+d_column_counter(0) <= N_110_0;
+d_column_counter(1) <= N_111_0;
+d_column_counter(2) <= N_112_0;
+d_column_counter(3) <= N_113_0;
+d_column_counter(4) <= N_114_0;
+d_column_counter(5) <= N_115_0;
+d_column_counter(6) <= N_116_0;
+d_column_counter(7) <= N_117_0;
+d_column_counter(8) <= N_118;
+d_column_counter(9) <= N_119;
+d_line_counter(0) <= N_120;
+d_line_counter(1) <= N_121;
+d_line_counter(2) <= N_122;
+d_line_counter(3) <= N_123;
+d_line_counter(4) <= N_124;
+d_line_counter(5) <= N_125;
+d_line_counter(6) <= N_126;
+d_line_counter(7) <= N_127;
+d_line_counter(8) <= N_128;
+d_set_column_counter <= N_129;
+d_set_line_counter <= N_130;
+d_hsync_counter(0) <= N_131;
+d_hsync_counter(1) <= N_132;
+d_hsync_counter(2) <= N_133;
+d_hsync_counter(3) <= N_134;
+d_hsync_counter(4) <= N_135;
+d_hsync_counter(5) <= N_136;
+d_hsync_counter(6) <= N_137;
+d_hsync_counter(7) <= N_138;
+d_hsync_counter(8) <= N_139;
+d_hsync_counter(9) <= N_140;
+d_vsync_counter(0) <= N_141;
+d_vsync_counter(1) <= N_142;
+d_vsync_counter(2) <= N_143;
+d_vsync_counter(3) <= N_144;
+d_vsync_counter(4) <= N_145;
+d_vsync_counter(5) <= N_146;
+d_vsync_counter(6) <= N_147;
+d_vsync_counter(7) <= N_148;
+d_vsync_counter(8) <= N_149;
+d_vsync_counter(9) <= N_150;
+d_set_hsync_counter <= N_151;
+d_set_vsync_counter <= N_152;
+d_h_enable <= N_153;
+d_v_enable <= N_154;
+d_r <= N_155;
+d_g <= N_156;
+d_b <= N_157;
+d_hsync_state(6) <= N_158;
+d_hsync_state(5) <= N_159;
+d_hsync_state(4) <= N_160;
+d_hsync_state(3) <= N_161;
+d_hsync_state(2) <= N_162;
+d_hsync_state(1) <= N_163;
+d_hsync_state(0) <= N_164;
+d_vsync_state(6) <= N_165;
+d_vsync_state(5) <= N_166;
+d_vsync_state(4) <= N_167;
+d_vsync_state(3) <= N_168;
+d_vsync_state(2) <= N_169;
+d_vsync_state(1) <= N_170;
+d_vsync_state(0) <= N_171;
+d_state_clk <= N_172;
+d_toggle <= N_173;
+d_toggle_counter(0) <= N_174;
+d_toggle_counter(1) <= N_175;
+d_toggle_counter(2) <= N_176;
+d_toggle_counter(3) <= N_177;
+d_toggle_counter(4) <= N_178;
+d_toggle_counter(5) <= N_179;
+d_toggle_counter(6) <= N_180;
+d_toggle_counter(7) <= N_181;
+d_toggle_counter(8) <= N_182;
+d_toggle_counter(9) <= N_183;
+d_toggle_counter(10) <= N_184;
+d_toggle_counter(11) <= N_185;
+d_toggle_counter(12) <= N_186;
+d_toggle_counter(13) <= N_187;
+d_toggle_counter(14) <= N_188;
+d_toggle_counter(15) <= N_189;
+d_toggle_counter(16) <= N_190;
+d_toggle_counter(17) <= N_191;
+d_toggle_counter(18) <= N_192;
+d_toggle_counter(19) <= N_193;
+d_toggle_counter(20) <= N_194;
+d_toggle_counter(21) <= N_195;
+d_toggle_counter(22) <= N_196;
+d_toggle_counter(23) <= N_197;
+d_toggle_counter(24) <= N_198;
+CLK_PIN_INTERNAL <= clk_pin;
+RESET_PIN_INTERNAL <= reset_pin;
+end beh;
+
diff --git a/bsp2/Designflow/syn/rev_1/vga.vqm b/bsp2/Designflow/syn/rev_1/vga.vqm
new file mode 100644
index 0000000..94981be
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.vqm
@@ -0,0 +1,6206 @@
+//
+// Written by Synplify
+// Product Version "C-2009.06"
+// Program "Synplify Pro", Mapper "map450rc, Build 029R"
+// Wed Oct 21 17:26:36 2009
+//
+// Source file index table:
+// Object locations will have the form :
+// file 0 "noname"
+// file 1 "\/opt/synplify/fpga_c200906/lib/vhd/std.vhd "
+// file 2 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd "
+// file 3 "\/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd "
+// file 4 "\/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd "
+// file 5 "\/opt/synplify/fpga_c200906/lib/vhd/arith.vhd "
+// file 6 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd "
+// file 7 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd "
+// file 8 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd "
+// file 9 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd "
+// file 10 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd "
+// file 11 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd "
+// file 12 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd "
+// file 13 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd "
+
+// VQM4.1+ 
+module vga_driver (
+  line_counter_sig_0,
+  line_counter_sig_1,
+  line_counter_sig_2,
+  line_counter_sig_3,
+  line_counter_sig_4,
+  line_counter_sig_5,
+  line_counter_sig_6,
+  line_counter_sig_7,
+  line_counter_sig_8,
+  dly_counter_1,
+  dly_counter_0,
+  vsync_state_2,
+  vsync_state_5,
+  vsync_state_3,
+  vsync_state_6,
+  vsync_state_4,
+  vsync_state_1,
+  vsync_state_0,
+  hsync_state_2,
+  hsync_state_4,
+  hsync_state_0,
+  hsync_state_5,
+  hsync_state_1,
+  hsync_state_3,
+  hsync_state_6,
+  column_counter_sig_0,
+  column_counter_sig_1,
+  column_counter_sig_2,
+  column_counter_sig_3,
+  column_counter_sig_4,
+  column_counter_sig_5,
+  column_counter_sig_6,
+  column_counter_sig_7,
+  column_counter_sig_8,
+  column_counter_sig_9,
+  vsync_counter_9,
+  vsync_counter_8,
+  vsync_counter_7,
+  vsync_counter_6,
+  vsync_counter_5,
+  vsync_counter_4,
+  vsync_counter_3,
+  vsync_counter_2,
+  vsync_counter_1,
+  vsync_counter_0,
+  hsync_counter_9,
+  hsync_counter_8,
+  hsync_counter_7,
+  hsync_counter_6,
+  hsync_counter_5,
+  hsync_counter_4,
+  hsync_counter_3,
+  hsync_counter_2,
+  hsync_counter_1,
+  hsync_counter_0,
+  d_set_vsync_counter,
+  v_sync,
+  h_sync,
+  h_enable_sig,
+  v_enable_sig,
+  reset_pin_c,
+  un6_dly_counter_0_x,
+  d_set_hsync_counter,
+  clk_pin_c
+)
+;
+output line_counter_sig_0 ;
+output line_counter_sig_1 ;
+output line_counter_sig_2 ;
+output line_counter_sig_3 ;
+output line_counter_sig_4 ;
+output line_counter_sig_5 ;
+output line_counter_sig_6 ;
+output line_counter_sig_7 ;
+output line_counter_sig_8 ;
+input dly_counter_1 ;
+input dly_counter_0 ;
+output vsync_state_2 ;
+output vsync_state_5 ;
+output vsync_state_3 ;
+output vsync_state_6 ;
+output vsync_state_4 ;
+output vsync_state_1 ;
+output vsync_state_0 ;
+output hsync_state_2 ;
+output hsync_state_4 ;
+output hsync_state_0 ;
+output hsync_state_5 ;
+output hsync_state_1 ;
+output hsync_state_3 ;
+output hsync_state_6 ;
+output column_counter_sig_0 ;
+output column_counter_sig_1 ;
+output column_counter_sig_2 ;
+output column_counter_sig_3 ;
+output column_counter_sig_4 ;
+output column_counter_sig_5 ;
+output column_counter_sig_6 ;
+output column_counter_sig_7 ;
+output column_counter_sig_8 ;
+output column_counter_sig_9 ;
+output vsync_counter_9 ;
+output vsync_counter_8 ;
+output vsync_counter_7 ;
+output vsync_counter_6 ;
+output vsync_counter_5 ;
+output vsync_counter_4 ;
+output vsync_counter_3 ;
+output vsync_counter_2 ;
+output vsync_counter_1 ;
+output vsync_counter_0 ;
+output hsync_counter_9 ;
+output hsync_counter_8 ;
+output hsync_counter_7 ;
+output hsync_counter_6 ;
+output hsync_counter_5 ;
+output hsync_counter_4 ;
+output hsync_counter_3 ;
+output hsync_counter_2 ;
+output hsync_counter_1 ;
+output hsync_counter_0 ;
+output d_set_vsync_counter ;
+output v_sync ;
+output h_sync ;
+output h_enable_sig ;
+output v_enable_sig ;
+input reset_pin_c ;
+output un6_dly_counter_0_x ;
+output d_set_hsync_counter ;
+input clk_pin_c ;
+wire line_counter_sig_0 ;
+wire line_counter_sig_1 ;
+wire line_counter_sig_2 ;
+wire line_counter_sig_3 ;
+wire line_counter_sig_4 ;
+wire line_counter_sig_5 ;
+wire line_counter_sig_6 ;
+wire line_counter_sig_7 ;
+wire line_counter_sig_8 ;
+wire dly_counter_1 ;
+wire dly_counter_0 ;
+wire vsync_state_2 ;
+wire vsync_state_5 ;
+wire vsync_state_3 ;
+wire vsync_state_6 ;
+wire vsync_state_4 ;
+wire vsync_state_1 ;
+wire vsync_state_0 ;
+wire hsync_state_2 ;
+wire hsync_state_4 ;
+wire hsync_state_0 ;
+wire hsync_state_5 ;
+wire hsync_state_1 ;
+wire hsync_state_3 ;
+wire hsync_state_6 ;
+wire column_counter_sig_0 ;
+wire column_counter_sig_1 ;
+wire column_counter_sig_2 ;
+wire column_counter_sig_3 ;
+wire column_counter_sig_4 ;
+wire column_counter_sig_5 ;
+wire column_counter_sig_6 ;
+wire column_counter_sig_7 ;
+wire column_counter_sig_8 ;
+wire column_counter_sig_9 ;
+wire vsync_counter_9 ;
+wire vsync_counter_8 ;
+wire vsync_counter_7 ;
+wire vsync_counter_6 ;
+wire vsync_counter_5 ;
+wire vsync_counter_4 ;
+wire vsync_counter_3 ;
+wire vsync_counter_2 ;
+wire vsync_counter_1 ;
+wire vsync_counter_0 ;
+wire hsync_counter_9 ;
+wire hsync_counter_8 ;
+wire hsync_counter_7 ;
+wire hsync_counter_6 ;
+wire hsync_counter_5 ;
+wire hsync_counter_4 ;
+wire hsync_counter_3 ;
+wire hsync_counter_2 ;
+wire hsync_counter_1 ;
+wire hsync_counter_0 ;
+wire d_set_vsync_counter ;
+wire v_sync ;
+wire h_sync ;
+wire h_enable_sig ;
+wire v_enable_sig ;
+wire reset_pin_c ;
+wire un6_dly_counter_0_x ;
+wire d_set_hsync_counter ;
+wire clk_pin_c ;
+wire [8:0] hsync_counter_cout;
+wire [8:0] vsync_counter_cout;
+wire [9:1] un2_column_counter_next_combout;
+wire [9:1] un1_line_counter_sig_combout;
+wire [7:1] un1_line_counter_sig_cout;
+wire [1:1] un1_line_counter_sig_a_cout;
+wire [7:0] un2_column_counter_next_cout;
+wire hsync_counter_next_1_sqmuxa ;
+wire G_2_i ;
+wire un9_hsync_counterlt9 ;
+wire vsync_counter_next_1_sqmuxa ;
+wire G_16_i ;
+wire un9_vsync_counterlt9 ;
+wire un10_column_counter_siglto9 ;
+wire column_counter_next_0_sqmuxa_1_1 ;
+wire vsync_state_3_iv_0_0__g0_0_a3_0 ;
+wire vsync_state_next_2_sqmuxa ;
+wire un12_vsync_counter_7 ;
+wire un13_vsync_counter_4 ;
+wire un10_line_counter_siglto8 ;
+wire line_counter_next_0_sqmuxa_1_1 ;
+wire v_enable_sig_1_0_0_0_g0_i_o4 ;
+wire h_enable_sig_1_0_0_0_g0_i_o4 ;
+wire h_sync_1_0_0_0_g1 ;
+wire v_sync_1_0_0_0_g1 ;
+wire un14_vsync_counter_8 ;
+wire hsync_state_3_0_0_0__g0_0 ;
+wire un10_hsync_counter_3 ;
+wire un10_hsync_counter_1 ;
+wire un10_hsync_counter_4 ;
+wire un12_hsync_counter ;
+wire un11_hsync_counter_2 ;
+wire un11_hsync_counter_3 ;
+wire un13_hsync_counter ;
+wire vsync_state_next_1_sqmuxa_1 ;
+wire vsync_state_next_1_sqmuxa_3 ;
+wire un1_vsync_state_next_1_sqmuxa_0 ;
+wire hsync_state_next_1_sqmuxa_1 ;
+wire hsync_state_next_1_sqmuxa_2 ;
+wire un1_hsync_state_next_1_sqmuxa_0 ;
+wire un12_vsync_counter_6 ;
+wire un15_vsync_counter_4 ;
+wire vsync_state_next_1_sqmuxa_2 ;
+wire un10_line_counter_siglto5 ;
+wire un10_column_counter_siglt6 ;
+wire un13_hsync_counter_2 ;
+wire un13_hsync_counter_7 ;
+wire un9_hsync_counterlt9_3 ;
+wire un9_vsync_counterlt9_5 ;
+wire un9_vsync_counterlt9_6 ;
+wire un12_hsync_counter_3 ;
+wire un12_hsync_counter_4 ;
+wire un10_line_counter_siglt4_2 ;
+wire un15_vsync_counter_3 ;
+wire un13_vsync_counter_3 ;
+wire un10_column_counter_siglt6_4 ;
+wire un1_vsync_state_2_0 ;
+wire un1_hsync_state_3_0 ;
+wire VCC ;
+wire GND ;
+wire line_counter_next_0_sqmuxa_1_1_i ;
+wire column_counter_next_0_sqmuxa_1_1_i ;
+wire un9_vsync_counterlt9_i ;
+wire G_16_i_i ;
+wire un9_hsync_counterlt9_i ;
+wire G_2_i_i ;
+//@1:1
+  assign VCC = 1'b1;
+  assign GND = 1'b0;
+// @13:158
+  stratix_lcell hsync_counter_0_ (
+	.regout(hsync_counter_0),
+	.cout(hsync_counter_cout[0]),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_0),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_0_.operation_mode="arithmetic";
+defparam hsync_counter_0_.output_mode="reg_only";
+defparam hsync_counter_0_.lut_mask="55aa";
+defparam hsync_counter_0_.synch_mode="on";
+defparam hsync_counter_0_.sum_lutc_input="datac";
+// @13:158
+  stratix_lcell hsync_counter_1_ (
+	.regout(hsync_counter_1),
+	.cout(hsync_counter_cout[1]),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_1),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.cin(hsync_counter_cout[0]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_1_.cin_used="true";
+defparam hsync_counter_1_.operation_mode="arithmetic";
+defparam hsync_counter_1_.output_mode="reg_only";
+defparam hsync_counter_1_.lut_mask="5aa0";
+defparam hsync_counter_1_.synch_mode="on";
+defparam hsync_counter_1_.sum_lutc_input="cin";
+// @13:158
+  stratix_lcell hsync_counter_2_ (
+	.regout(hsync_counter_2),
+	.cout(hsync_counter_cout[2]),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_2),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.cin(hsync_counter_cout[1]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_2_.cin_used="true";
+defparam hsync_counter_2_.operation_mode="arithmetic";
+defparam hsync_counter_2_.output_mode="reg_only";
+defparam hsync_counter_2_.lut_mask="5aa0";
+defparam hsync_counter_2_.synch_mode="on";
+defparam hsync_counter_2_.sum_lutc_input="cin";
+// @13:158
+  stratix_lcell hsync_counter_3_ (
+	.regout(hsync_counter_3),
+	.cout(hsync_counter_cout[3]),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_3),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.cin(hsync_counter_cout[2]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_3_.cin_used="true";
+defparam hsync_counter_3_.operation_mode="arithmetic";
+defparam hsync_counter_3_.output_mode="reg_only";
+defparam hsync_counter_3_.lut_mask="5aa0";
+defparam hsync_counter_3_.synch_mode="on";
+defparam hsync_counter_3_.sum_lutc_input="cin";
+// @13:158
+  stratix_lcell hsync_counter_4_ (
+	.regout(hsync_counter_4),
+	.cout(hsync_counter_cout[4]),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_4),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.cin(hsync_counter_cout[3]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_4_.cin_used="true";
+defparam hsync_counter_4_.operation_mode="arithmetic";
+defparam hsync_counter_4_.output_mode="reg_only";
+defparam hsync_counter_4_.lut_mask="5aa0";
+defparam hsync_counter_4_.synch_mode="on";
+defparam hsync_counter_4_.sum_lutc_input="cin";
+// @13:158
+  stratix_lcell hsync_counter_5_ (
+	.regout(hsync_counter_5),
+	.cout(hsync_counter_cout[5]),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_5),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.cin(hsync_counter_cout[4]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_5_.cin_used="true";
+defparam hsync_counter_5_.operation_mode="arithmetic";
+defparam hsync_counter_5_.output_mode="reg_only";
+defparam hsync_counter_5_.lut_mask="5aa0";
+defparam hsync_counter_5_.synch_mode="on";
+defparam hsync_counter_5_.sum_lutc_input="cin";
+// @13:158
+  stratix_lcell hsync_counter_6_ (
+	.regout(hsync_counter_6),
+	.cout(hsync_counter_cout[6]),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_6),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.cin(hsync_counter_cout[5]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_6_.cin_used="true";
+defparam hsync_counter_6_.operation_mode="arithmetic";
+defparam hsync_counter_6_.output_mode="reg_only";
+defparam hsync_counter_6_.lut_mask="5aa0";
+defparam hsync_counter_6_.synch_mode="on";
+defparam hsync_counter_6_.sum_lutc_input="cin";
+// @13:158
+  stratix_lcell hsync_counter_7_ (
+	.regout(hsync_counter_7),
+	.cout(hsync_counter_cout[7]),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_7),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.cin(hsync_counter_cout[6]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_7_.cin_used="true";
+defparam hsync_counter_7_.operation_mode="arithmetic";
+defparam hsync_counter_7_.output_mode="reg_only";
+defparam hsync_counter_7_.lut_mask="5aa0";
+defparam hsync_counter_7_.synch_mode="on";
+defparam hsync_counter_7_.sum_lutc_input="cin";
+// @13:158
+  stratix_lcell hsync_counter_8_ (
+	.regout(hsync_counter_8),
+	.cout(hsync_counter_cout[8]),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_8),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.cin(hsync_counter_cout[7]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_8_.cin_used="true";
+defparam hsync_counter_8_.operation_mode="arithmetic";
+defparam hsync_counter_8_.output_mode="reg_only";
+defparam hsync_counter_8_.lut_mask="5aa0";
+defparam hsync_counter_8_.synch_mode="on";
+defparam hsync_counter_8_.sum_lutc_input="cin";
+// @13:158
+  stratix_lcell hsync_counter_9_ (
+	.regout(hsync_counter_9),
+	.clk(clk_pin_c),
+	.dataa(hsync_counter_9),
+	.datab(VCC),
+	.datac(hsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_2_i_i),
+	.sload(un9_hsync_counterlt9_i),
+	.ena(VCC),
+	.cin(hsync_counter_cout[8]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_9_.cin_used="true";
+defparam hsync_counter_9_.operation_mode="normal";
+defparam hsync_counter_9_.output_mode="reg_only";
+defparam hsync_counter_9_.lut_mask="5a5a";
+defparam hsync_counter_9_.synch_mode="on";
+defparam hsync_counter_9_.sum_lutc_input="cin";
+// @13:267
+  stratix_lcell vsync_counter_0_ (
+	.regout(vsync_counter_0),
+	.cout(vsync_counter_cout[0]),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_0),
+	.datab(d_set_hsync_counter),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_0_.operation_mode="arithmetic";
+defparam vsync_counter_0_.output_mode="reg_only";
+defparam vsync_counter_0_.lut_mask="6688";
+defparam vsync_counter_0_.synch_mode="on";
+defparam vsync_counter_0_.sum_lutc_input="datac";
+// @13:267
+  stratix_lcell vsync_counter_1_ (
+	.regout(vsync_counter_1),
+	.cout(vsync_counter_cout[1]),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_1),
+	.datab(VCC),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.cin(vsync_counter_cout[0]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_1_.cin_used="true";
+defparam vsync_counter_1_.operation_mode="arithmetic";
+defparam vsync_counter_1_.output_mode="reg_only";
+defparam vsync_counter_1_.lut_mask="5aa0";
+defparam vsync_counter_1_.synch_mode="on";
+defparam vsync_counter_1_.sum_lutc_input="cin";
+// @13:267
+  stratix_lcell vsync_counter_2_ (
+	.regout(vsync_counter_2),
+	.cout(vsync_counter_cout[2]),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_2),
+	.datab(VCC),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.cin(vsync_counter_cout[1]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_2_.cin_used="true";
+defparam vsync_counter_2_.operation_mode="arithmetic";
+defparam vsync_counter_2_.output_mode="reg_only";
+defparam vsync_counter_2_.lut_mask="5aa0";
+defparam vsync_counter_2_.synch_mode="on";
+defparam vsync_counter_2_.sum_lutc_input="cin";
+// @13:267
+  stratix_lcell vsync_counter_3_ (
+	.regout(vsync_counter_3),
+	.cout(vsync_counter_cout[3]),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_3),
+	.datab(VCC),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.cin(vsync_counter_cout[2]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_3_.cin_used="true";
+defparam vsync_counter_3_.operation_mode="arithmetic";
+defparam vsync_counter_3_.output_mode="reg_only";
+defparam vsync_counter_3_.lut_mask="5aa0";
+defparam vsync_counter_3_.synch_mode="on";
+defparam vsync_counter_3_.sum_lutc_input="cin";
+// @13:267
+  stratix_lcell vsync_counter_4_ (
+	.regout(vsync_counter_4),
+	.cout(vsync_counter_cout[4]),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_4),
+	.datab(VCC),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.cin(vsync_counter_cout[3]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_4_.cin_used="true";
+defparam vsync_counter_4_.operation_mode="arithmetic";
+defparam vsync_counter_4_.output_mode="reg_only";
+defparam vsync_counter_4_.lut_mask="5aa0";
+defparam vsync_counter_4_.synch_mode="on";
+defparam vsync_counter_4_.sum_lutc_input="cin";
+// @13:267
+  stratix_lcell vsync_counter_5_ (
+	.regout(vsync_counter_5),
+	.cout(vsync_counter_cout[5]),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_5),
+	.datab(VCC),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.cin(vsync_counter_cout[4]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_5_.cin_used="true";
+defparam vsync_counter_5_.operation_mode="arithmetic";
+defparam vsync_counter_5_.output_mode="reg_only";
+defparam vsync_counter_5_.lut_mask="5aa0";
+defparam vsync_counter_5_.synch_mode="on";
+defparam vsync_counter_5_.sum_lutc_input="cin";
+// @13:267
+  stratix_lcell vsync_counter_6_ (
+	.regout(vsync_counter_6),
+	.cout(vsync_counter_cout[6]),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_6),
+	.datab(VCC),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.cin(vsync_counter_cout[5]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_6_.cin_used="true";
+defparam vsync_counter_6_.operation_mode="arithmetic";
+defparam vsync_counter_6_.output_mode="reg_only";
+defparam vsync_counter_6_.lut_mask="5aa0";
+defparam vsync_counter_6_.synch_mode="on";
+defparam vsync_counter_6_.sum_lutc_input="cin";
+// @13:267
+  stratix_lcell vsync_counter_7_ (
+	.regout(vsync_counter_7),
+	.cout(vsync_counter_cout[7]),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_7),
+	.datab(VCC),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.cin(vsync_counter_cout[6]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_7_.cin_used="true";
+defparam vsync_counter_7_.operation_mode="arithmetic";
+defparam vsync_counter_7_.output_mode="reg_only";
+defparam vsync_counter_7_.lut_mask="5aa0";
+defparam vsync_counter_7_.synch_mode="on";
+defparam vsync_counter_7_.sum_lutc_input="cin";
+// @13:267
+  stratix_lcell vsync_counter_8_ (
+	.regout(vsync_counter_8),
+	.cout(vsync_counter_cout[8]),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_8),
+	.datab(VCC),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.cin(vsync_counter_cout[7]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_8_.cin_used="true";
+defparam vsync_counter_8_.operation_mode="arithmetic";
+defparam vsync_counter_8_.output_mode="reg_only";
+defparam vsync_counter_8_.lut_mask="5aa0";
+defparam vsync_counter_8_.synch_mode="on";
+defparam vsync_counter_8_.sum_lutc_input="cin";
+// @13:267
+  stratix_lcell vsync_counter_9_ (
+	.regout(vsync_counter_9),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_9),
+	.datab(VCC),
+	.datac(vsync_counter_next_1_sqmuxa),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(G_16_i_i),
+	.sload(un9_vsync_counterlt9_i),
+	.ena(VCC),
+	.cin(vsync_counter_cout[8]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_9_.cin_used="true";
+defparam vsync_counter_9_.operation_mode="normal";
+defparam vsync_counter_9_.output_mode="reg_only";
+defparam vsync_counter_9_.lut_mask="5a5a";
+defparam vsync_counter_9_.synch_mode="on";
+defparam vsync_counter_9_.sum_lutc_input="cin";
+// @13:97
+  stratix_lcell column_counter_sig_9_ (
+	.regout(column_counter_sig_9),
+	.clk(clk_pin_c),
+	.dataa(un2_column_counter_next_combout[9]),
+	.datab(un10_column_counter_siglto9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(column_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_9_.operation_mode="normal";
+defparam column_counter_sig_9_.output_mode="reg_only";
+defparam column_counter_sig_9_.lut_mask="bbbb";
+defparam column_counter_sig_9_.synch_mode="on";
+defparam column_counter_sig_9_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell column_counter_sig_8_ (
+	.regout(column_counter_sig_8),
+	.clk(clk_pin_c),
+	.dataa(un2_column_counter_next_combout[8]),
+	.datab(un10_column_counter_siglto9),
+	.datac(column_counter_next_0_sqmuxa_1_1),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_8_.operation_mode="normal";
+defparam column_counter_sig_8_.output_mode="reg_only";
+defparam column_counter_sig_8_.lut_mask="8080";
+defparam column_counter_sig_8_.synch_mode="off";
+defparam column_counter_sig_8_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell column_counter_sig_7_ (
+	.regout(column_counter_sig_7),
+	.clk(clk_pin_c),
+	.dataa(un2_column_counter_next_combout[7]),
+	.datab(un10_column_counter_siglto9),
+	.datac(column_counter_next_0_sqmuxa_1_1),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_7_.operation_mode="normal";
+defparam column_counter_sig_7_.output_mode="reg_only";
+defparam column_counter_sig_7_.lut_mask="8080";
+defparam column_counter_sig_7_.synch_mode="off";
+defparam column_counter_sig_7_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell column_counter_sig_6_ (
+	.regout(column_counter_sig_6),
+	.clk(clk_pin_c),
+	.dataa(un2_column_counter_next_combout[6]),
+	.datab(un10_column_counter_siglto9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(column_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_6_.operation_mode="normal";
+defparam column_counter_sig_6_.output_mode="reg_only";
+defparam column_counter_sig_6_.lut_mask="bbbb";
+defparam column_counter_sig_6_.synch_mode="on";
+defparam column_counter_sig_6_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell column_counter_sig_5_ (
+	.regout(column_counter_sig_5),
+	.clk(clk_pin_c),
+	.dataa(un2_column_counter_next_combout[5]),
+	.datab(un10_column_counter_siglto9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(column_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_5_.operation_mode="normal";
+defparam column_counter_sig_5_.output_mode="reg_only";
+defparam column_counter_sig_5_.lut_mask="bbbb";
+defparam column_counter_sig_5_.synch_mode="on";
+defparam column_counter_sig_5_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell column_counter_sig_4_ (
+	.regout(column_counter_sig_4),
+	.clk(clk_pin_c),
+	.dataa(un2_column_counter_next_combout[4]),
+	.datab(un10_column_counter_siglto9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(column_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_4_.operation_mode="normal";
+defparam column_counter_sig_4_.output_mode="reg_only";
+defparam column_counter_sig_4_.lut_mask="bbbb";
+defparam column_counter_sig_4_.synch_mode="on";
+defparam column_counter_sig_4_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell column_counter_sig_3_ (
+	.regout(column_counter_sig_3),
+	.clk(clk_pin_c),
+	.dataa(un2_column_counter_next_combout[3]),
+	.datab(un10_column_counter_siglto9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(column_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_3_.operation_mode="normal";
+defparam column_counter_sig_3_.output_mode="reg_only";
+defparam column_counter_sig_3_.lut_mask="bbbb";
+defparam column_counter_sig_3_.synch_mode="on";
+defparam column_counter_sig_3_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell column_counter_sig_2_ (
+	.regout(column_counter_sig_2),
+	.clk(clk_pin_c),
+	.dataa(un2_column_counter_next_combout[2]),
+	.datab(un10_column_counter_siglto9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(column_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_2_.operation_mode="normal";
+defparam column_counter_sig_2_.output_mode="reg_only";
+defparam column_counter_sig_2_.lut_mask="bbbb";
+defparam column_counter_sig_2_.synch_mode="on";
+defparam column_counter_sig_2_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell column_counter_sig_1_ (
+	.regout(column_counter_sig_1),
+	.clk(clk_pin_c),
+	.dataa(un2_column_counter_next_combout[1]),
+	.datab(un10_column_counter_siglto9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(column_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_1_.operation_mode="normal";
+defparam column_counter_sig_1_.output_mode="reg_only";
+defparam column_counter_sig_1_.lut_mask="bbbb";
+defparam column_counter_sig_1_.synch_mode="on";
+defparam column_counter_sig_1_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell column_counter_sig_0_ (
+	.regout(column_counter_sig_0),
+	.clk(clk_pin_c),
+	.dataa(column_counter_sig_0),
+	.datab(un10_column_counter_siglto9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(column_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_sig_0_.operation_mode="normal";
+defparam column_counter_sig_0_.output_mode="reg_only";
+defparam column_counter_sig_0_.lut_mask="7777";
+defparam column_counter_sig_0_.synch_mode="on";
+defparam column_counter_sig_0_.sum_lutc_input="datac";
+// @13:187
+  stratix_lcell hsync_state_6_ (
+	.regout(hsync_state_6),
+	.clk(clk_pin_c),
+	.dataa(VCC),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(un6_dly_counter_0_x),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_6_.operation_mode="normal";
+defparam hsync_state_6_.output_mode="reg_only";
+defparam hsync_state_6_.lut_mask="ff00";
+defparam hsync_state_6_.synch_mode="off";
+defparam hsync_state_6_.sum_lutc_input="datac";
+// @13:300
+  stratix_lcell vsync_state_0_ (
+	.regout(vsync_state_0),
+	.clk(clk_pin_c),
+	.dataa(vsync_state_0),
+	.datab(vsync_state_3_iv_0_0__g0_0_a3_0),
+	.datac(un6_dly_counter_0_x),
+	.datad(vsync_state_next_2_sqmuxa),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_0_.operation_mode="normal";
+defparam vsync_state_0_.output_mode="reg_only";
+defparam vsync_state_0_.lut_mask="0cae";
+defparam vsync_state_0_.synch_mode="off";
+defparam vsync_state_0_.sum_lutc_input="datac";
+// @13:300
+  stratix_lcell vsync_state_1_ (
+	.regout(vsync_state_1),
+	.clk(clk_pin_c),
+	.dataa(vsync_state_4),
+	.datab(un12_vsync_counter_7),
+	.datac(un13_vsync_counter_4),
+	.datad(un6_dly_counter_0_x),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_1_.operation_mode="normal";
+defparam vsync_state_1_.output_mode="reg_only";
+defparam vsync_state_1_.lut_mask="0080";
+defparam vsync_state_1_.synch_mode="off";
+defparam vsync_state_1_.sum_lutc_input="datac";
+// @13:300
+  stratix_lcell vsync_state_6_ (
+	.combout(un6_dly_counter_0_x),
+	.regout(vsync_state_6),
+	.clk(clk_pin_c),
+	.dataa(reset_pin_c),
+	.datab(dly_counter_0),
+	.datac(dly_counter_1),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_6_.operation_mode="normal";
+defparam vsync_state_6_.output_mode="reg_and_comb";
+defparam vsync_state_6_.lut_mask="7f7f";
+defparam vsync_state_6_.synch_mode="off";
+defparam vsync_state_6_.sum_lutc_input="datac";
+// @13:125
+  stratix_lcell line_counter_sig_8_ (
+	.regout(line_counter_sig_8),
+	.clk(clk_pin_c),
+	.dataa(un10_line_counter_siglto8),
+	.datab(un1_line_counter_sig_combout[9]),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(line_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_sig_8_.operation_mode="normal";
+defparam line_counter_sig_8_.output_mode="reg_only";
+defparam line_counter_sig_8_.lut_mask="dddd";
+defparam line_counter_sig_8_.synch_mode="on";
+defparam line_counter_sig_8_.sum_lutc_input="datac";
+// @13:125
+  stratix_lcell line_counter_sig_7_ (
+	.regout(line_counter_sig_7),
+	.clk(clk_pin_c),
+	.dataa(un10_line_counter_siglto8),
+	.datab(un1_line_counter_sig_combout[8]),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(line_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_sig_7_.operation_mode="normal";
+defparam line_counter_sig_7_.output_mode="reg_only";
+defparam line_counter_sig_7_.lut_mask="dddd";
+defparam line_counter_sig_7_.synch_mode="on";
+defparam line_counter_sig_7_.sum_lutc_input="datac";
+// @13:125
+  stratix_lcell line_counter_sig_6_ (
+	.regout(line_counter_sig_6),
+	.clk(clk_pin_c),
+	.dataa(un10_line_counter_siglto8),
+	.datab(un1_line_counter_sig_combout[7]),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(line_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_sig_6_.operation_mode="normal";
+defparam line_counter_sig_6_.output_mode="reg_only";
+defparam line_counter_sig_6_.lut_mask="dddd";
+defparam line_counter_sig_6_.synch_mode="on";
+defparam line_counter_sig_6_.sum_lutc_input="datac";
+// @13:125
+  stratix_lcell line_counter_sig_5_ (
+	.regout(line_counter_sig_5),
+	.clk(clk_pin_c),
+	.dataa(un10_line_counter_siglto8),
+	.datab(un1_line_counter_sig_combout[6]),
+	.datac(line_counter_next_0_sqmuxa_1_1),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_sig_5_.operation_mode="normal";
+defparam line_counter_sig_5_.output_mode="reg_only";
+defparam line_counter_sig_5_.lut_mask="8080";
+defparam line_counter_sig_5_.synch_mode="off";
+defparam line_counter_sig_5_.sum_lutc_input="datac";
+// @13:125
+  stratix_lcell line_counter_sig_4_ (
+	.regout(line_counter_sig_4),
+	.clk(clk_pin_c),
+	.dataa(un10_line_counter_siglto8),
+	.datab(un1_line_counter_sig_combout[5]),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(line_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_sig_4_.operation_mode="normal";
+defparam line_counter_sig_4_.output_mode="reg_only";
+defparam line_counter_sig_4_.lut_mask="dddd";
+defparam line_counter_sig_4_.synch_mode="on";
+defparam line_counter_sig_4_.sum_lutc_input="datac";
+// @13:125
+  stratix_lcell line_counter_sig_3_ (
+	.regout(line_counter_sig_3),
+	.clk(clk_pin_c),
+	.dataa(un10_line_counter_siglto8),
+	.datab(un1_line_counter_sig_combout[4]),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(line_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_sig_3_.operation_mode="normal";
+defparam line_counter_sig_3_.output_mode="reg_only";
+defparam line_counter_sig_3_.lut_mask="dddd";
+defparam line_counter_sig_3_.synch_mode="on";
+defparam line_counter_sig_3_.sum_lutc_input="datac";
+// @13:125
+  stratix_lcell line_counter_sig_2_ (
+	.regout(line_counter_sig_2),
+	.clk(clk_pin_c),
+	.dataa(un10_line_counter_siglto8),
+	.datab(un1_line_counter_sig_combout[3]),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(line_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_sig_2_.operation_mode="normal";
+defparam line_counter_sig_2_.output_mode="reg_only";
+defparam line_counter_sig_2_.lut_mask="dddd";
+defparam line_counter_sig_2_.synch_mode="on";
+defparam line_counter_sig_2_.sum_lutc_input="datac";
+// @13:125
+  stratix_lcell line_counter_sig_1_ (
+	.regout(line_counter_sig_1),
+	.clk(clk_pin_c),
+	.dataa(un10_line_counter_siglto8),
+	.datab(un1_line_counter_sig_combout[2]),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(line_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_sig_1_.operation_mode="normal";
+defparam line_counter_sig_1_.output_mode="reg_only";
+defparam line_counter_sig_1_.lut_mask="dddd";
+defparam line_counter_sig_1_.synch_mode="on";
+defparam line_counter_sig_1_.sum_lutc_input="datac";
+// @13:125
+  stratix_lcell line_counter_sig_0_ (
+	.regout(line_counter_sig_0),
+	.clk(clk_pin_c),
+	.dataa(un1_line_counter_sig_combout[1]),
+	.datab(un10_line_counter_siglto8),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(line_counter_next_0_sqmuxa_1_1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_sig_0_.operation_mode="normal";
+defparam line_counter_sig_0_.output_mode="reg_only";
+defparam line_counter_sig_0_.lut_mask="bbbb";
+defparam line_counter_sig_0_.synch_mode="on";
+defparam line_counter_sig_0_.sum_lutc_input="datac";
+// @13:187
+  stratix_lcell v_enable_sig_Z (
+	.regout(v_enable_sig),
+	.clk(clk_pin_c),
+	.dataa(hsync_state_3),
+	.datab(hsync_state_1),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(v_enable_sig_1_0_0_0_g0_i_o4),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam v_enable_sig_Z.operation_mode="normal";
+defparam v_enable_sig_Z.output_mode="reg_only";
+defparam v_enable_sig_Z.lut_mask="eeee";
+defparam v_enable_sig_Z.synch_mode="on";
+defparam v_enable_sig_Z.sum_lutc_input="datac";
+// @13:300
+  stratix_lcell h_enable_sig_Z (
+	.regout(h_enable_sig),
+	.clk(clk_pin_c),
+	.dataa(vsync_state_3),
+	.datab(vsync_state_1),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(h_enable_sig_1_0_0_0_g0_i_o4),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam h_enable_sig_Z.operation_mode="normal";
+defparam h_enable_sig_Z.output_mode="reg_only";
+defparam h_enable_sig_Z.lut_mask="eeee";
+defparam h_enable_sig_Z.synch_mode="on";
+defparam h_enable_sig_Z.sum_lutc_input="datac";
+// @13:187
+  stratix_lcell h_sync_Z (
+	.regout(h_sync),
+	.clk(clk_pin_c),
+	.dataa(reset_pin_c),
+	.datab(dly_counter_0),
+	.datac(dly_counter_1),
+	.datad(h_sync_1_0_0_0_g1),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam h_sync_Z.operation_mode="normal";
+defparam h_sync_Z.output_mode="reg_only";
+defparam h_sync_Z.lut_mask="ff7f";
+defparam h_sync_Z.synch_mode="off";
+defparam h_sync_Z.sum_lutc_input="datac";
+// @13:300
+  stratix_lcell v_sync_Z (
+	.regout(v_sync),
+	.clk(clk_pin_c),
+	.dataa(reset_pin_c),
+	.datab(dly_counter_0),
+	.datac(dly_counter_1),
+	.datad(v_sync_1_0_0_0_g1),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam v_sync_Z.operation_mode="normal";
+defparam v_sync_Z.output_mode="reg_only";
+defparam v_sync_Z.lut_mask="ff7f";
+defparam v_sync_Z.synch_mode="off";
+defparam v_sync_Z.sum_lutc_input="datac";
+// @13:300
+  stratix_lcell vsync_state_5_ (
+	.regout(vsync_state_5),
+	.clk(clk_pin_c),
+	.dataa(vsync_state_6),
+	.datab(vsync_state_0),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(vsync_state_next_2_sqmuxa),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_5_.operation_mode="normal";
+defparam vsync_state_5_.output_mode="reg_only";
+defparam vsync_state_5_.lut_mask="eeee";
+defparam vsync_state_5_.synch_mode="on";
+defparam vsync_state_5_.sum_lutc_input="datac";
+// @13:300
+  stratix_lcell vsync_state_4_ (
+	.regout(vsync_state_4),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_0),
+	.datab(vsync_counter_9),
+	.datac(vsync_state_5),
+	.datad(un14_vsync_counter_8),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(vsync_state_next_2_sqmuxa),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_4_.operation_mode="normal";
+defparam vsync_state_4_.output_mode="reg_only";
+defparam vsync_state_4_.lut_mask="2000";
+defparam vsync_state_4_.synch_mode="on";
+defparam vsync_state_4_.sum_lutc_input="datac";
+// @13:300
+  stratix_lcell vsync_state_3_ (
+	.regout(vsync_state_3),
+	.clk(clk_pin_c),
+	.dataa(vsync_state_1),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(vsync_state_next_2_sqmuxa),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_3_.operation_mode="normal";
+defparam vsync_state_3_.output_mode="reg_only";
+defparam vsync_state_3_.lut_mask="aaaa";
+defparam vsync_state_3_.synch_mode="on";
+defparam vsync_state_3_.sum_lutc_input="datac";
+// @13:300
+  stratix_lcell vsync_state_2_ (
+	.regout(vsync_state_2),
+	.clk(clk_pin_c),
+	.dataa(vsync_counter_0),
+	.datab(vsync_counter_9),
+	.datac(vsync_state_3),
+	.datad(un14_vsync_counter_8),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(vsync_state_next_2_sqmuxa),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_2_.operation_mode="normal";
+defparam vsync_state_2_.output_mode="reg_only";
+defparam vsync_state_2_.lut_mask="8000";
+defparam vsync_state_2_.synch_mode="on";
+defparam vsync_state_2_.sum_lutc_input="datac";
+// @13:187
+  stratix_lcell hsync_state_5_ (
+	.regout(hsync_state_5),
+	.clk(clk_pin_c),
+	.dataa(hsync_state_6),
+	.datab(hsync_state_0),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(hsync_state_3_0_0_0__g0_0),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_5_.operation_mode="normal";
+defparam hsync_state_5_.output_mode="reg_only";
+defparam hsync_state_5_.lut_mask="eeee";
+defparam hsync_state_5_.synch_mode="on";
+defparam hsync_state_5_.sum_lutc_input="datac";
+// @13:187
+  stratix_lcell hsync_state_4_ (
+	.regout(hsync_state_4),
+	.clk(clk_pin_c),
+	.dataa(hsync_state_5),
+	.datab(un10_hsync_counter_3),
+	.datac(un10_hsync_counter_1),
+	.datad(un10_hsync_counter_4),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(hsync_state_3_0_0_0__g0_0),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_4_.operation_mode="normal";
+defparam hsync_state_4_.output_mode="reg_only";
+defparam hsync_state_4_.lut_mask="8000";
+defparam hsync_state_4_.synch_mode="on";
+defparam hsync_state_4_.sum_lutc_input="datac";
+// @13:187
+  stratix_lcell hsync_state_3_ (
+	.regout(hsync_state_3),
+	.clk(clk_pin_c),
+	.dataa(hsync_state_1),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(hsync_state_3_0_0_0__g0_0),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_3_.operation_mode="normal";
+defparam hsync_state_3_.output_mode="reg_only";
+defparam hsync_state_3_.lut_mask="aaaa";
+defparam hsync_state_3_.synch_mode="on";
+defparam hsync_state_3_.sum_lutc_input="datac";
+// @13:187
+  stratix_lcell hsync_state_2_ (
+	.regout(hsync_state_2),
+	.clk(clk_pin_c),
+	.dataa(hsync_state_3),
+	.datab(un12_hsync_counter),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(hsync_state_3_0_0_0__g0_0),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_2_.operation_mode="normal";
+defparam hsync_state_2_.output_mode="reg_only";
+defparam hsync_state_2_.lut_mask="8888";
+defparam hsync_state_2_.synch_mode="on";
+defparam hsync_state_2_.sum_lutc_input="datac";
+// @13:187
+  stratix_lcell hsync_state_1_ (
+	.regout(hsync_state_1),
+	.clk(clk_pin_c),
+	.dataa(hsync_state_4),
+	.datab(un11_hsync_counter_2),
+	.datac(un10_hsync_counter_1),
+	.datad(un11_hsync_counter_3),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(hsync_state_3_0_0_0__g0_0),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_1_.operation_mode="normal";
+defparam hsync_state_1_.output_mode="reg_only";
+defparam hsync_state_1_.lut_mask="8000";
+defparam hsync_state_1_.synch_mode="on";
+defparam hsync_state_1_.sum_lutc_input="datac";
+// @13:187
+  stratix_lcell hsync_state_0_ (
+	.regout(hsync_state_0),
+	.clk(clk_pin_c),
+	.dataa(hsync_state_2),
+	.datab(un13_hsync_counter),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(un6_dly_counter_0_x),
+	.sload(GND),
+	.ena(hsync_state_3_0_0_0__g0_0),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_0_.operation_mode="normal";
+defparam hsync_state_0_.output_mode="reg_only";
+defparam hsync_state_0_.lut_mask="8888";
+defparam hsync_state_0_.synch_mode="on";
+defparam hsync_state_0_.sum_lutc_input="datac";
+// @13:97
+  stratix_lcell vsync_state_next_2_sqmuxa_cZ (
+	.combout(vsync_state_next_2_sqmuxa),
+	.clk(GND),
+	.dataa(un6_dly_counter_0_x),
+	.datab(vsync_state_next_1_sqmuxa_1),
+	.datac(vsync_state_next_1_sqmuxa_3),
+	.datad(un1_vsync_state_next_1_sqmuxa_0),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_next_2_sqmuxa_cZ.operation_mode="normal";
+defparam vsync_state_next_2_sqmuxa_cZ.output_mode="comb_only";
+defparam vsync_state_next_2_sqmuxa_cZ.lut_mask="aaab";
+defparam vsync_state_next_2_sqmuxa_cZ.synch_mode="off";
+defparam vsync_state_next_2_sqmuxa_cZ.sum_lutc_input="datac";
+  stratix_lcell hsync_state_3_0_0_0__g0_0_cZ (
+	.combout(hsync_state_3_0_0_0__g0_0),
+	.clk(GND),
+	.dataa(hsync_state_next_1_sqmuxa_1),
+	.datab(hsync_state_next_1_sqmuxa_2),
+	.datac(un6_dly_counter_0_x),
+	.datad(un1_hsync_state_next_1_sqmuxa_0),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_3_0_0_0__g0_0_cZ.operation_mode="normal";
+defparam hsync_state_3_0_0_0__g0_0_cZ.output_mode="comb_only";
+defparam hsync_state_3_0_0_0__g0_0_cZ.lut_mask="f0f1";
+defparam hsync_state_3_0_0_0__g0_0_cZ.synch_mode="off";
+defparam hsync_state_3_0_0_0__g0_0_cZ.sum_lutc_input="datac";
+// @13:206
+  stratix_lcell un1_hsync_state_next_1_sqmuxa_0_cZ (
+	.combout(un1_hsync_state_next_1_sqmuxa_0),
+	.clk(GND),
+	.dataa(hsync_state_2),
+	.datab(hsync_state_3),
+	.datac(un13_hsync_counter),
+	.datad(un12_hsync_counter),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.lut_mask="0ace";
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
+// @13:319
+  stratix_lcell un1_vsync_state_next_1_sqmuxa_0_cZ (
+	.combout(un1_vsync_state_next_1_sqmuxa_0),
+	.clk(GND),
+	.dataa(vsync_state_2),
+	.datab(un12_vsync_counter_6),
+	.datac(un15_vsync_counter_4),
+	.datad(vsync_state_next_1_sqmuxa_2),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.lut_mask="ff2a";
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
+  stratix_lcell vsync_state_3_iv_0_0__g0_0_a3_0_cZ (
+	.combout(vsync_state_3_iv_0_0__g0_0_a3_0),
+	.clk(GND),
+	.dataa(vsync_state_2),
+	.datab(un12_vsync_counter_6),
+	.datac(un15_vsync_counter_4),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.operation_mode="normal";
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.output_mode="comb_only";
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lut_mask="8080";
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.synch_mode="off";
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.sum_lutc_input="datac";
+// @13:139
+  stratix_lcell LINE_COUNT_next_un10_line_counter_siglto8 (
+	.combout(un10_line_counter_siglto8),
+	.clk(GND),
+	.dataa(line_counter_sig_6),
+	.datab(line_counter_sig_7),
+	.datac(line_counter_sig_8),
+	.datad(un10_line_counter_siglto5),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam LINE_COUNT_next_un10_line_counter_siglto8.operation_mode="normal";
+defparam LINE_COUNT_next_un10_line_counter_siglto8.output_mode="comb_only";
+defparam LINE_COUNT_next_un10_line_counter_siglto8.lut_mask="ff7f";
+defparam LINE_COUNT_next_un10_line_counter_siglto8.synch_mode="off";
+defparam LINE_COUNT_next_un10_line_counter_siglto8.sum_lutc_input="datac";
+// @10:161
+  stratix_lcell G_2 (
+	.combout(G_2_i),
+	.clk(GND),
+	.dataa(hsync_state_0),
+	.datab(hsync_state_6),
+	.datac(un9_hsync_counterlt9),
+	.datad(un6_dly_counter_0_x),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam G_2.operation_mode="normal";
+defparam G_2.output_mode="comb_only";
+defparam G_2.lut_mask="0f1f";
+defparam G_2.synch_mode="off";
+defparam G_2.sum_lutc_input="datac";
+// @13:326
+  stratix_lcell vsync_state_next_1_sqmuxa_1_cZ (
+	.combout(vsync_state_next_1_sqmuxa_1),
+	.clk(GND),
+	.dataa(vsync_counter_0),
+	.datab(vsync_counter_9),
+	.datac(vsync_state_5),
+	.datad(un14_vsync_counter_8),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
+defparam vsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
+defparam vsync_state_next_1_sqmuxa_1_cZ.lut_mask="d0f0";
+defparam vsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
+defparam vsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
+// @13:331
+  stratix_lcell vsync_state_next_1_sqmuxa_2_cZ (
+	.combout(vsync_state_next_1_sqmuxa_2),
+	.clk(GND),
+	.dataa(vsync_state_4),
+	.datab(un12_vsync_counter_7),
+	.datac(un13_vsync_counter_4),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
+defparam vsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
+defparam vsync_state_next_1_sqmuxa_2_cZ.lut_mask="2a2a";
+defparam vsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
+defparam vsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
+// @13:339
+  stratix_lcell vsync_state_next_1_sqmuxa_3_cZ (
+	.combout(vsync_state_next_1_sqmuxa_3),
+	.clk(GND),
+	.dataa(vsync_counter_0),
+	.datab(vsync_counter_9),
+	.datac(vsync_state_3),
+	.datad(un14_vsync_counter_8),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_state_next_1_sqmuxa_3_cZ.operation_mode="normal";
+defparam vsync_state_next_1_sqmuxa_3_cZ.output_mode="comb_only";
+defparam vsync_state_next_1_sqmuxa_3_cZ.lut_mask="70f0";
+defparam vsync_state_next_1_sqmuxa_3_cZ.synch_mode="off";
+defparam vsync_state_next_1_sqmuxa_3_cZ.sum_lutc_input="datac";
+// @10:161
+  stratix_lcell G_16 (
+	.combout(G_16_i),
+	.clk(GND),
+	.dataa(vsync_state_0),
+	.datab(vsync_state_6),
+	.datac(un9_vsync_counterlt9),
+	.datad(un6_dly_counter_0_x),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam G_16.operation_mode="normal";
+defparam G_16.output_mode="comb_only";
+defparam G_16.lut_mask="0f1f";
+defparam G_16.synch_mode="off";
+defparam G_16.sum_lutc_input="datac";
+// @13:111
+  stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglto9 (
+	.combout(un10_column_counter_siglto9),
+	.clk(GND),
+	.dataa(column_counter_sig_7),
+	.datab(column_counter_sig_8),
+	.datac(column_counter_sig_9),
+	.datad(un10_column_counter_siglt6),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.operation_mode="normal";
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.output_mode="comb_only";
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.lut_mask="1f0f";
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.synch_mode="off";
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.sum_lutc_input="datac";
+// @13:218
+  stratix_lcell hsync_state_next_1_sqmuxa_2_cZ (
+	.combout(hsync_state_next_1_sqmuxa_2),
+	.clk(GND),
+	.dataa(hsync_state_4),
+	.datab(un11_hsync_counter_2),
+	.datac(un10_hsync_counter_1),
+	.datad(un11_hsync_counter_3),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
+defparam hsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
+defparam hsync_state_next_1_sqmuxa_2_cZ.lut_mask="2aaa";
+defparam hsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
+defparam hsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
+// @13:213
+  stratix_lcell hsync_state_next_1_sqmuxa_1_cZ (
+	.combout(hsync_state_next_1_sqmuxa_1),
+	.clk(GND),
+	.dataa(hsync_state_5),
+	.datab(un10_hsync_counter_3),
+	.datac(un10_hsync_counter_1),
+	.datad(un10_hsync_counter_4),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
+defparam hsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
+defparam hsync_state_next_1_sqmuxa_1_cZ.lut_mask="2aaa";
+defparam hsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
+defparam hsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
+// @13:231
+  stratix_lcell HSYNC_FSM_next_un13_hsync_counter (
+	.combout(un13_hsync_counter),
+	.clk(GND),
+	.dataa(hsync_counter_6),
+	.datab(hsync_counter_7),
+	.datac(un13_hsync_counter_2),
+	.datad(un13_hsync_counter_7),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un13_hsync_counter.operation_mode="normal";
+defparam HSYNC_FSM_next_un13_hsync_counter.output_mode="comb_only";
+defparam HSYNC_FSM_next_un13_hsync_counter.lut_mask="1000";
+defparam HSYNC_FSM_next_un13_hsync_counter.synch_mode="off";
+defparam HSYNC_FSM_next_un13_hsync_counter.sum_lutc_input="datac";
+// @13:172
+  stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9 (
+	.combout(un9_hsync_counterlt9),
+	.clk(GND),
+	.dataa(hsync_counter_8),
+	.datab(hsync_counter_9),
+	.datac(un9_hsync_counterlt9_3),
+	.datad(un13_hsync_counter_7),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.operation_mode="normal";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.output_mode="comb_only";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.lut_mask="f7ff";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.synch_mode="off";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.sum_lutc_input="datac";
+// @13:281
+  stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9 (
+	.combout(un9_vsync_counterlt9),
+	.clk(GND),
+	.dataa(vsync_counter_4),
+	.datab(vsync_counter_5),
+	.datac(un9_vsync_counterlt9_5),
+	.datad(un9_vsync_counterlt9_6),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.operation_mode="normal";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.output_mode="comb_only";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.lut_mask="fff7";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.synch_mode="off";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.sum_lutc_input="datac";
+// @13:226
+  stratix_lcell HSYNC_FSM_next_un12_hsync_counter (
+	.combout(un12_hsync_counter),
+	.clk(GND),
+	.dataa(hsync_counter_0),
+	.datab(hsync_counter_1),
+	.datac(un12_hsync_counter_3),
+	.datad(un12_hsync_counter_4),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un12_hsync_counter.operation_mode="normal";
+defparam HSYNC_FSM_next_un12_hsync_counter.output_mode="comb_only";
+defparam HSYNC_FSM_next_un12_hsync_counter.lut_mask="8000";
+defparam HSYNC_FSM_next_un12_hsync_counter.synch_mode="off";
+defparam HSYNC_FSM_next_un12_hsync_counter.sum_lutc_input="datac";
+// @13:139
+  stratix_lcell LINE_COUNT_next_un10_line_counter_siglto5 (
+	.combout(un10_line_counter_siglto5),
+	.clk(GND),
+	.dataa(line_counter_sig_1),
+	.datab(line_counter_sig_2),
+	.datac(line_counter_sig_5),
+	.datad(un10_line_counter_siglt4_2),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam LINE_COUNT_next_un10_line_counter_siglto5.operation_mode="normal";
+defparam LINE_COUNT_next_un10_line_counter_siglto5.output_mode="comb_only";
+defparam LINE_COUNT_next_un10_line_counter_siglto5.lut_mask="0f07";
+defparam LINE_COUNT_next_un10_line_counter_siglto5.synch_mode="off";
+defparam LINE_COUNT_next_un10_line_counter_siglto5.sum_lutc_input="datac";
+// @13:344
+  stratix_lcell VSYNC_FSM_next_un15_vsync_counter_4 (
+	.combout(un15_vsync_counter_4),
+	.clk(GND),
+	.dataa(vsync_counter_1),
+	.datab(vsync_counter_4),
+	.datac(un15_vsync_counter_3),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_FSM_next_un15_vsync_counter_4.operation_mode="normal";
+defparam VSYNC_FSM_next_un15_vsync_counter_4.output_mode="comb_only";
+defparam VSYNC_FSM_next_un15_vsync_counter_4.lut_mask="1010";
+defparam VSYNC_FSM_next_un15_vsync_counter_4.synch_mode="off";
+defparam VSYNC_FSM_next_un15_vsync_counter_4.sum_lutc_input="datac";
+// @13:331
+  stratix_lcell VSYNC_FSM_next_un13_vsync_counter_4 (
+	.combout(un13_vsync_counter_4),
+	.clk(GND),
+	.dataa(vsync_counter_0),
+	.datab(vsync_counter_5),
+	.datac(un13_vsync_counter_3),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_FSM_next_un13_vsync_counter_4.operation_mode="normal";
+defparam VSYNC_FSM_next_un13_vsync_counter_4.output_mode="comb_only";
+defparam VSYNC_FSM_next_un13_vsync_counter_4.lut_mask="8080";
+defparam VSYNC_FSM_next_un13_vsync_counter_4.synch_mode="off";
+defparam VSYNC_FSM_next_un13_vsync_counter_4.sum_lutc_input="datac";
+// @13:111
+  stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6 (
+	.combout(un10_column_counter_siglt6),
+	.clk(GND),
+	.dataa(column_counter_sig_4),
+	.datab(column_counter_sig_6),
+	.datac(column_counter_sig_5),
+	.datad(un10_column_counter_siglt6_4),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.operation_mode="normal";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.output_mode="comb_only";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.lut_mask="ff7f";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.synch_mode="off";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.sum_lutc_input="datac";
+// @13:169
+  stratix_lcell hsync_counter_next_1_sqmuxa_cZ (
+	.combout(hsync_counter_next_1_sqmuxa),
+	.clk(GND),
+	.dataa(reset_pin_c),
+	.datab(dly_counter_0),
+	.datac(dly_counter_1),
+	.datad(d_set_hsync_counter),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam hsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
+defparam hsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
+defparam hsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
+defparam hsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
+defparam hsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
+// @13:339
+  stratix_lcell VSYNC_FSM_next_un14_vsync_counter_8 (
+	.combout(un14_vsync_counter_8),
+	.clk(GND),
+	.dataa(un12_vsync_counter_6),
+	.datab(un12_vsync_counter_7),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_FSM_next_un14_vsync_counter_8.operation_mode="normal";
+defparam VSYNC_FSM_next_un14_vsync_counter_8.output_mode="comb_only";
+defparam VSYNC_FSM_next_un14_vsync_counter_8.lut_mask="8888";
+defparam VSYNC_FSM_next_un14_vsync_counter_8.synch_mode="off";
+defparam VSYNC_FSM_next_un14_vsync_counter_8.sum_lutc_input="datac";
+// @13:139
+  stratix_lcell line_counter_next_0_sqmuxa_1_1_cZ (
+	.combout(line_counter_next_0_sqmuxa_1_1),
+	.clk(GND),
+	.dataa(reset_pin_c),
+	.datab(dly_counter_0),
+	.datac(dly_counter_1),
+	.datad(vsync_state_1),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam line_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
+defparam line_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
+defparam line_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
+defparam line_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
+defparam line_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
+  stratix_lcell v_sync_1_0_0_0_g1_cZ (
+	.combout(v_sync_1_0_0_0_g1),
+	.clk(GND),
+	.dataa(vsync_state_2),
+	.datab(v_sync),
+	.datac(vsync_state_4),
+	.datad(un1_vsync_state_2_0),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam v_sync_1_0_0_0_g1_cZ.operation_mode="normal";
+defparam v_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
+defparam v_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
+defparam v_sync_1_0_0_0_g1_cZ.synch_mode="off";
+defparam v_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
+  stratix_lcell h_enable_sig_1_0_0_0_g0_i_o4_cZ (
+	.combout(h_enable_sig_1_0_0_0_g0_i_o4),
+	.clk(GND),
+	.dataa(vsync_state_4),
+	.datab(vsync_state_5),
+	.datac(un6_dly_counter_0_x),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
+// @13:278
+  stratix_lcell vsync_counter_next_1_sqmuxa_cZ (
+	.combout(vsync_counter_next_1_sqmuxa),
+	.clk(GND),
+	.dataa(reset_pin_c),
+	.datab(dly_counter_0),
+	.datac(dly_counter_1),
+	.datad(d_set_vsync_counter),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam vsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
+defparam vsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
+defparam vsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
+defparam vsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
+defparam vsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
+  stratix_lcell v_enable_sig_1_0_0_0_g0_i_o4_cZ (
+	.combout(v_enable_sig_1_0_0_0_g0_i_o4),
+	.clk(GND),
+	.dataa(hsync_state_4),
+	.datab(hsync_state_5),
+	.datac(un6_dly_counter_0_x),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
+  stratix_lcell h_sync_1_0_0_0_g1_cZ (
+	.combout(h_sync_1_0_0_0_g1),
+	.clk(GND),
+	.dataa(hsync_state_2),
+	.datab(h_sync),
+	.datac(hsync_state_4),
+	.datad(un1_hsync_state_3_0),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam h_sync_1_0_0_0_g1_cZ.operation_mode="normal";
+defparam h_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
+defparam h_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
+defparam h_sync_1_0_0_0_g1_cZ.synch_mode="off";
+defparam h_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
+// @13:111
+  stratix_lcell column_counter_next_0_sqmuxa_1_1_cZ (
+	.combout(column_counter_next_0_sqmuxa_1_1),
+	.clk(GND),
+	.dataa(reset_pin_c),
+	.datab(dly_counter_0),
+	.datac(dly_counter_1),
+	.datad(hsync_state_1),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam column_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
+defparam column_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
+defparam column_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
+defparam column_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
+defparam column_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
+// @13:226
+  stratix_lcell HSYNC_FSM_next_un12_hsync_counter_4 (
+	.combout(un12_hsync_counter_4),
+	.clk(GND),
+	.dataa(hsync_counter_6),
+	.datab(hsync_counter_7),
+	.datac(hsync_counter_9),
+	.datad(hsync_counter_3),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un12_hsync_counter_4.operation_mode="normal";
+defparam HSYNC_FSM_next_un12_hsync_counter_4.output_mode="comb_only";
+defparam HSYNC_FSM_next_un12_hsync_counter_4.lut_mask="0010";
+defparam HSYNC_FSM_next_un12_hsync_counter_4.synch_mode="off";
+defparam HSYNC_FSM_next_un12_hsync_counter_4.sum_lutc_input="datac";
+// @13:226
+  stratix_lcell HSYNC_FSM_next_un12_hsync_counter_3 (
+	.combout(un12_hsync_counter_3),
+	.clk(GND),
+	.dataa(hsync_counter_2),
+	.datab(hsync_counter_8),
+	.datac(hsync_counter_4),
+	.datad(hsync_counter_5),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un12_hsync_counter_3.operation_mode="normal";
+defparam HSYNC_FSM_next_un12_hsync_counter_3.output_mode="comb_only";
+defparam HSYNC_FSM_next_un12_hsync_counter_3.lut_mask="0008";
+defparam HSYNC_FSM_next_un12_hsync_counter_3.synch_mode="off";
+defparam HSYNC_FSM_next_un12_hsync_counter_3.sum_lutc_input="datac";
+// @13:218
+  stratix_lcell HSYNC_FSM_next_un11_hsync_counter_3 (
+	.combout(un11_hsync_counter_3),
+	.clk(GND),
+	.dataa(hsync_counter_0),
+	.datab(hsync_counter_1),
+	.datac(hsync_counter_3),
+	.datad(hsync_counter_4),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un11_hsync_counter_3.operation_mode="normal";
+defparam HSYNC_FSM_next_un11_hsync_counter_3.output_mode="comb_only";
+defparam HSYNC_FSM_next_un11_hsync_counter_3.lut_mask="0008";
+defparam HSYNC_FSM_next_un11_hsync_counter_3.synch_mode="off";
+defparam HSYNC_FSM_next_un11_hsync_counter_3.sum_lutc_input="datac";
+// @13:218
+  stratix_lcell HSYNC_FSM_next_un11_hsync_counter_2 (
+	.combout(un11_hsync_counter_2),
+	.clk(GND),
+	.dataa(hsync_counter_2),
+	.datab(hsync_counter_7),
+	.datac(hsync_counter_6),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un11_hsync_counter_2.operation_mode="normal";
+defparam HSYNC_FSM_next_un11_hsync_counter_2.output_mode="comb_only";
+defparam HSYNC_FSM_next_un11_hsync_counter_2.lut_mask="0808";
+defparam HSYNC_FSM_next_un11_hsync_counter_2.synch_mode="off";
+defparam HSYNC_FSM_next_un11_hsync_counter_2.sum_lutc_input="datac";
+// @13:172
+  stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9_3 (
+	.combout(un9_hsync_counterlt9_3),
+	.clk(GND),
+	.dataa(hsync_counter_6),
+	.datab(hsync_counter_7),
+	.datac(hsync_counter_4),
+	.datad(hsync_counter_5),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.operation_mode="normal";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.output_mode="comb_only";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.lut_mask="7fff";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.synch_mode="off";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.sum_lutc_input="datac";
+// @13:231
+  stratix_lcell HSYNC_FSM_next_un13_hsync_counter_2 (
+	.combout(un13_hsync_counter_2),
+	.clk(GND),
+	.dataa(hsync_counter_8),
+	.datab(hsync_counter_9),
+	.datac(hsync_counter_4),
+	.datad(hsync_counter_5),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un13_hsync_counter_2.operation_mode="normal";
+defparam HSYNC_FSM_next_un13_hsync_counter_2.output_mode="comb_only";
+defparam HSYNC_FSM_next_un13_hsync_counter_2.lut_mask="0080";
+defparam HSYNC_FSM_next_un13_hsync_counter_2.synch_mode="off";
+defparam HSYNC_FSM_next_un13_hsync_counter_2.sum_lutc_input="datac";
+// @13:281
+  stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_6 (
+	.combout(un9_vsync_counterlt9_6),
+	.clk(GND),
+	.dataa(vsync_counter_2),
+	.datab(vsync_counter_3),
+	.datac(vsync_counter_0),
+	.datad(vsync_counter_1),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.operation_mode="normal";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.output_mode="comb_only";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.lut_mask="7fff";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.synch_mode="off";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.sum_lutc_input="datac";
+// @13:281
+  stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_5 (
+	.combout(un9_vsync_counterlt9_5),
+	.clk(GND),
+	.dataa(vsync_counter_8),
+	.datab(vsync_counter_9),
+	.datac(vsync_counter_6),
+	.datad(vsync_counter_7),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.operation_mode="normal";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.output_mode="comb_only";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.lut_mask="7fff";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.synch_mode="off";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.sum_lutc_input="datac";
+// @13:213
+  stratix_lcell HSYNC_FSM_next_un10_hsync_counter_4 (
+	.combout(un10_hsync_counter_4),
+	.clk(GND),
+	.dataa(hsync_counter_4),
+	.datab(hsync_counter_6),
+	.datac(hsync_counter_1),
+	.datad(hsync_counter_3),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un10_hsync_counter_4.operation_mode="normal";
+defparam HSYNC_FSM_next_un10_hsync_counter_4.output_mode="comb_only";
+defparam HSYNC_FSM_next_un10_hsync_counter_4.lut_mask="8000";
+defparam HSYNC_FSM_next_un10_hsync_counter_4.synch_mode="off";
+defparam HSYNC_FSM_next_un10_hsync_counter_4.sum_lutc_input="datac";
+// @13:213
+  stratix_lcell HSYNC_FSM_next_un10_hsync_counter_3 (
+	.combout(un10_hsync_counter_3),
+	.clk(GND),
+	.dataa(hsync_counter_0),
+	.datab(hsync_counter_7),
+	.datac(hsync_counter_2),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un10_hsync_counter_3.operation_mode="normal";
+defparam HSYNC_FSM_next_un10_hsync_counter_3.output_mode="comb_only";
+defparam HSYNC_FSM_next_un10_hsync_counter_3.lut_mask="0101";
+defparam HSYNC_FSM_next_un10_hsync_counter_3.synch_mode="off";
+defparam HSYNC_FSM_next_un10_hsync_counter_3.sum_lutc_input="datac";
+// @13:344
+  stratix_lcell VSYNC_FSM_next_un15_vsync_counter_3 (
+	.combout(un15_vsync_counter_3),
+	.clk(GND),
+	.dataa(vsync_counter_9),
+	.datab(vsync_counter_2),
+	.datac(vsync_counter_3),
+	.datad(vsync_counter_0),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_FSM_next_un15_vsync_counter_3.operation_mode="normal";
+defparam VSYNC_FSM_next_un15_vsync_counter_3.output_mode="comb_only";
+defparam VSYNC_FSM_next_un15_vsync_counter_3.lut_mask="0020";
+defparam VSYNC_FSM_next_un15_vsync_counter_3.synch_mode="off";
+defparam VSYNC_FSM_next_un15_vsync_counter_3.sum_lutc_input="datac";
+// @13:331
+  stratix_lcell VSYNC_FSM_next_un13_vsync_counter_3 (
+	.combout(un13_vsync_counter_3),
+	.clk(GND),
+	.dataa(vsync_counter_6),
+	.datab(vsync_counter_7),
+	.datac(vsync_counter_8),
+	.datad(vsync_counter_9),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_FSM_next_un13_vsync_counter_3.operation_mode="normal";
+defparam VSYNC_FSM_next_un13_vsync_counter_3.output_mode="comb_only";
+defparam VSYNC_FSM_next_un13_vsync_counter_3.lut_mask="0001";
+defparam VSYNC_FSM_next_un13_vsync_counter_3.synch_mode="off";
+defparam VSYNC_FSM_next_un13_vsync_counter_3.sum_lutc_input="datac";
+// @13:111
+  stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6_4 (
+	.combout(un10_column_counter_siglt6_4),
+	.clk(GND),
+	.dataa(column_counter_sig_2),
+	.datab(column_counter_sig_3),
+	.datac(column_counter_sig_0),
+	.datad(column_counter_sig_1),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.operation_mode="normal";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.output_mode="comb_only";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.lut_mask="7fff";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.synch_mode="off";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.sum_lutc_input="datac";
+// @13:139
+  stratix_lcell LINE_COUNT_next_un10_line_counter_siglt4_2 (
+	.combout(un10_line_counter_siglt4_2),
+	.clk(GND),
+	.dataa(line_counter_sig_3),
+	.datab(line_counter_sig_4),
+	.datac(line_counter_sig_0),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.operation_mode="normal";
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.output_mode="comb_only";
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.lut_mask="7f7f";
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.synch_mode="off";
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.sum_lutc_input="datac";
+// @13:213
+  stratix_lcell HSYNC_FSM_next_un10_hsync_counter_1 (
+	.combout(un10_hsync_counter_1),
+	.clk(GND),
+	.dataa(hsync_counter_5),
+	.datab(hsync_counter_8),
+	.datac(hsync_counter_9),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un10_hsync_counter_1.operation_mode="normal";
+defparam HSYNC_FSM_next_un10_hsync_counter_1.output_mode="comb_only";
+defparam HSYNC_FSM_next_un10_hsync_counter_1.lut_mask="0101";
+defparam HSYNC_FSM_next_un10_hsync_counter_1.synch_mode="off";
+defparam HSYNC_FSM_next_un10_hsync_counter_1.sum_lutc_input="datac";
+// @13:326
+  stratix_lcell VSYNC_FSM_next_un12_vsync_counter_6 (
+	.combout(un12_vsync_counter_6),
+	.clk(GND),
+	.dataa(vsync_counter_7),
+	.datab(vsync_counter_8),
+	.datac(vsync_counter_5),
+	.datad(vsync_counter_6),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_FSM_next_un12_vsync_counter_6.operation_mode="normal";
+defparam VSYNC_FSM_next_un12_vsync_counter_6.output_mode="comb_only";
+defparam VSYNC_FSM_next_un12_vsync_counter_6.lut_mask="0001";
+defparam VSYNC_FSM_next_un12_vsync_counter_6.synch_mode="off";
+defparam VSYNC_FSM_next_un12_vsync_counter_6.sum_lutc_input="datac";
+// @13:326
+  stratix_lcell VSYNC_FSM_next_un12_vsync_counter_7 (
+	.combout(un12_vsync_counter_7),
+	.clk(GND),
+	.dataa(vsync_counter_3),
+	.datab(vsync_counter_4),
+	.datac(vsync_counter_1),
+	.datad(vsync_counter_2),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam VSYNC_FSM_next_un12_vsync_counter_7.operation_mode="normal";
+defparam VSYNC_FSM_next_un12_vsync_counter_7.output_mode="comb_only";
+defparam VSYNC_FSM_next_un12_vsync_counter_7.lut_mask="0001";
+defparam VSYNC_FSM_next_un12_vsync_counter_7.synch_mode="off";
+defparam VSYNC_FSM_next_un12_vsync_counter_7.sum_lutc_input="datac";
+// @13:231
+  stratix_lcell HSYNC_FSM_next_un13_hsync_counter_7 (
+	.combout(un13_hsync_counter_7),
+	.clk(GND),
+	.dataa(hsync_counter_2),
+	.datab(hsync_counter_3),
+	.datac(hsync_counter_0),
+	.datad(hsync_counter_1),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam HSYNC_FSM_next_un13_hsync_counter_7.operation_mode="normal";
+defparam HSYNC_FSM_next_un13_hsync_counter_7.output_mode="comb_only";
+defparam HSYNC_FSM_next_un13_hsync_counter_7.lut_mask="8000";
+defparam HSYNC_FSM_next_un13_hsync_counter_7.synch_mode="off";
+defparam HSYNC_FSM_next_un13_hsync_counter_7.sum_lutc_input="datac";
+// @13:206
+  stratix_lcell un1_hsync_state_3_0_cZ (
+	.combout(un1_hsync_state_3_0),
+	.clk(GND),
+	.dataa(hsync_state_3),
+	.datab(hsync_state_1),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_hsync_state_3_0_cZ.operation_mode="normal";
+defparam un1_hsync_state_3_0_cZ.output_mode="comb_only";
+defparam un1_hsync_state_3_0_cZ.lut_mask="eeee";
+defparam un1_hsync_state_3_0_cZ.synch_mode="off";
+defparam un1_hsync_state_3_0_cZ.sum_lutc_input="datac";
+// @13:319
+  stratix_lcell un1_vsync_state_2_0_cZ (
+	.combout(un1_vsync_state_2_0),
+	.clk(GND),
+	.dataa(vsync_state_3),
+	.datab(vsync_state_1),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_vsync_state_2_0_cZ.operation_mode="normal";
+defparam un1_vsync_state_2_0_cZ.output_mode="comb_only";
+defparam un1_vsync_state_2_0_cZ.lut_mask="eeee";
+defparam un1_vsync_state_2_0_cZ.synch_mode="off";
+defparam un1_vsync_state_2_0_cZ.sum_lutc_input="datac";
+// @13:248
+  stratix_lcell d_set_hsync_counter_cZ (
+	.combout(d_set_hsync_counter),
+	.clk(GND),
+	.dataa(hsync_state_6),
+	.datab(hsync_state_0),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam d_set_hsync_counter_cZ.operation_mode="normal";
+defparam d_set_hsync_counter_cZ.output_mode="comb_only";
+defparam d_set_hsync_counter_cZ.lut_mask="eeee";
+defparam d_set_hsync_counter_cZ.synch_mode="off";
+defparam d_set_hsync_counter_cZ.sum_lutc_input="datac";
+// @13:361
+  stratix_lcell d_set_vsync_counter_cZ (
+	.combout(d_set_vsync_counter),
+	.clk(GND),
+	.dataa(vsync_state_6),
+	.datab(vsync_state_0),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam d_set_vsync_counter_cZ.operation_mode="normal";
+defparam d_set_vsync_counter_cZ.output_mode="comb_only";
+defparam d_set_vsync_counter_cZ.lut_mask="eeee";
+defparam d_set_vsync_counter_cZ.synch_mode="off";
+defparam d_set_vsync_counter_cZ.sum_lutc_input="datac";
+// @13:141
+  stratix_lcell un1_line_counter_sig_9_ (
+	.combout(un1_line_counter_sig_combout[9]),
+	.clk(GND),
+	.dataa(line_counter_sig_7),
+	.datab(line_counter_sig_8),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un1_line_counter_sig_cout[7]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_9_.cin_used="true";
+defparam un1_line_counter_sig_9_.operation_mode="normal";
+defparam un1_line_counter_sig_9_.output_mode="comb_only";
+defparam un1_line_counter_sig_9_.lut_mask="6c6c";
+defparam un1_line_counter_sig_9_.synch_mode="off";
+defparam un1_line_counter_sig_9_.sum_lutc_input="cin";
+// @13:141
+  stratix_lcell un1_line_counter_sig_8_ (
+	.combout(un1_line_counter_sig_combout[8]),
+	.clk(GND),
+	.dataa(line_counter_sig_7),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un1_line_counter_sig_cout[6]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_8_.cin_used="true";
+defparam un1_line_counter_sig_8_.operation_mode="normal";
+defparam un1_line_counter_sig_8_.output_mode="comb_only";
+defparam un1_line_counter_sig_8_.lut_mask="5a5a";
+defparam un1_line_counter_sig_8_.synch_mode="off";
+defparam un1_line_counter_sig_8_.sum_lutc_input="cin";
+// @13:141
+  stratix_lcell un1_line_counter_sig_7_ (
+	.combout(un1_line_counter_sig_combout[7]),
+	.cout(un1_line_counter_sig_cout[7]),
+	.clk(GND),
+	.dataa(line_counter_sig_5),
+	.datab(line_counter_sig_6),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un1_line_counter_sig_cout[5]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_7_.cin_used="true";
+defparam un1_line_counter_sig_7_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_7_.output_mode="comb_only";
+defparam un1_line_counter_sig_7_.lut_mask="6c80";
+defparam un1_line_counter_sig_7_.synch_mode="off";
+defparam un1_line_counter_sig_7_.sum_lutc_input="cin";
+// @13:141
+  stratix_lcell un1_line_counter_sig_6_ (
+	.combout(un1_line_counter_sig_combout[6]),
+	.cout(un1_line_counter_sig_cout[6]),
+	.clk(GND),
+	.dataa(line_counter_sig_5),
+	.datab(line_counter_sig_6),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un1_line_counter_sig_cout[4]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_6_.cin_used="true";
+defparam un1_line_counter_sig_6_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_6_.output_mode="comb_only";
+defparam un1_line_counter_sig_6_.lut_mask="5a80";
+defparam un1_line_counter_sig_6_.synch_mode="off";
+defparam un1_line_counter_sig_6_.sum_lutc_input="cin";
+// @13:141
+  stratix_lcell un1_line_counter_sig_5_ (
+	.combout(un1_line_counter_sig_combout[5]),
+	.cout(un1_line_counter_sig_cout[5]),
+	.clk(GND),
+	.dataa(line_counter_sig_3),
+	.datab(line_counter_sig_4),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un1_line_counter_sig_cout[3]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_5_.cin_used="true";
+defparam un1_line_counter_sig_5_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_5_.output_mode="comb_only";
+defparam un1_line_counter_sig_5_.lut_mask="6c80";
+defparam un1_line_counter_sig_5_.synch_mode="off";
+defparam un1_line_counter_sig_5_.sum_lutc_input="cin";
+// @13:141
+  stratix_lcell un1_line_counter_sig_4_ (
+	.combout(un1_line_counter_sig_combout[4]),
+	.cout(un1_line_counter_sig_cout[4]),
+	.clk(GND),
+	.dataa(line_counter_sig_3),
+	.datab(line_counter_sig_4),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un1_line_counter_sig_cout[2]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_4_.cin_used="true";
+defparam un1_line_counter_sig_4_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_4_.output_mode="comb_only";
+defparam un1_line_counter_sig_4_.lut_mask="5a80";
+defparam un1_line_counter_sig_4_.synch_mode="off";
+defparam un1_line_counter_sig_4_.sum_lutc_input="cin";
+// @13:141
+  stratix_lcell un1_line_counter_sig_3_ (
+	.combout(un1_line_counter_sig_combout[3]),
+	.cout(un1_line_counter_sig_cout[3]),
+	.clk(GND),
+	.dataa(line_counter_sig_1),
+	.datab(line_counter_sig_2),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un1_line_counter_sig_cout[1]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_3_.cin_used="true";
+defparam un1_line_counter_sig_3_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_3_.output_mode="comb_only";
+defparam un1_line_counter_sig_3_.lut_mask="6c80";
+defparam un1_line_counter_sig_3_.synch_mode="off";
+defparam un1_line_counter_sig_3_.sum_lutc_input="cin";
+// @13:141
+  stratix_lcell un1_line_counter_sig_2_ (
+	.combout(un1_line_counter_sig_combout[2]),
+	.cout(un1_line_counter_sig_cout[2]),
+	.clk(GND),
+	.dataa(line_counter_sig_1),
+	.datab(line_counter_sig_2),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un1_line_counter_sig_a_cout[1]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_2_.cin_used="true";
+defparam un1_line_counter_sig_2_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_2_.output_mode="comb_only";
+defparam un1_line_counter_sig_2_.lut_mask="5a80";
+defparam un1_line_counter_sig_2_.synch_mode="off";
+defparam un1_line_counter_sig_2_.sum_lutc_input="cin";
+// @13:141
+  stratix_lcell un1_line_counter_sig_a_1_ (
+	.cout(un1_line_counter_sig_a_cout[1]),
+	.clk(GND),
+	.dataa(d_set_hsync_counter),
+	.datab(line_counter_sig_0),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_a_1_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_a_1_.output_mode="comb_only";
+defparam un1_line_counter_sig_a_1_.lut_mask="0088";
+defparam un1_line_counter_sig_a_1_.synch_mode="off";
+defparam un1_line_counter_sig_a_1_.sum_lutc_input="datac";
+// @13:141
+  stratix_lcell un1_line_counter_sig_1_ (
+	.combout(un1_line_counter_sig_combout[1]),
+	.cout(un1_line_counter_sig_cout[1]),
+	.clk(GND),
+	.dataa(d_set_hsync_counter),
+	.datab(line_counter_sig_0),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un1_line_counter_sig_1_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_1_.output_mode="comb_only";
+defparam un1_line_counter_sig_1_.lut_mask="6688";
+defparam un1_line_counter_sig_1_.synch_mode="off";
+defparam un1_line_counter_sig_1_.sum_lutc_input="datac";
+// @13:112
+  stratix_lcell un2_column_counter_next_9_ (
+	.combout(un2_column_counter_next_combout[9]),
+	.clk(GND),
+	.dataa(column_counter_sig_8),
+	.datab(column_counter_sig_9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un2_column_counter_next_cout[7]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_9_.cin_used="true";
+defparam un2_column_counter_next_9_.operation_mode="normal";
+defparam un2_column_counter_next_9_.output_mode="comb_only";
+defparam un2_column_counter_next_9_.lut_mask="6c6c";
+defparam un2_column_counter_next_9_.synch_mode="off";
+defparam un2_column_counter_next_9_.sum_lutc_input="cin";
+// @13:112
+  stratix_lcell un2_column_counter_next_8_ (
+	.combout(un2_column_counter_next_combout[8]),
+	.clk(GND),
+	.dataa(column_counter_sig_8),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un2_column_counter_next_cout[6]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_8_.cin_used="true";
+defparam un2_column_counter_next_8_.operation_mode="normal";
+defparam un2_column_counter_next_8_.output_mode="comb_only";
+defparam un2_column_counter_next_8_.lut_mask="5a5a";
+defparam un2_column_counter_next_8_.synch_mode="off";
+defparam un2_column_counter_next_8_.sum_lutc_input="cin";
+// @13:112
+  stratix_lcell un2_column_counter_next_7_ (
+	.combout(un2_column_counter_next_combout[7]),
+	.cout(un2_column_counter_next_cout[7]),
+	.clk(GND),
+	.dataa(column_counter_sig_6),
+	.datab(column_counter_sig_7),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un2_column_counter_next_cout[5]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_7_.cin_used="true";
+defparam un2_column_counter_next_7_.operation_mode="arithmetic";
+defparam un2_column_counter_next_7_.output_mode="comb_only";
+defparam un2_column_counter_next_7_.lut_mask="6c80";
+defparam un2_column_counter_next_7_.synch_mode="off";
+defparam un2_column_counter_next_7_.sum_lutc_input="cin";
+// @13:112
+  stratix_lcell un2_column_counter_next_6_ (
+	.combout(un2_column_counter_next_combout[6]),
+	.cout(un2_column_counter_next_cout[6]),
+	.clk(GND),
+	.dataa(column_counter_sig_6),
+	.datab(column_counter_sig_7),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un2_column_counter_next_cout[4]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_6_.cin_used="true";
+defparam un2_column_counter_next_6_.operation_mode="arithmetic";
+defparam un2_column_counter_next_6_.output_mode="comb_only";
+defparam un2_column_counter_next_6_.lut_mask="5a80";
+defparam un2_column_counter_next_6_.synch_mode="off";
+defparam un2_column_counter_next_6_.sum_lutc_input="cin";
+// @13:112
+  stratix_lcell un2_column_counter_next_5_ (
+	.combout(un2_column_counter_next_combout[5]),
+	.cout(un2_column_counter_next_cout[5]),
+	.clk(GND),
+	.dataa(column_counter_sig_4),
+	.datab(column_counter_sig_5),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un2_column_counter_next_cout[3]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_5_.cin_used="true";
+defparam un2_column_counter_next_5_.operation_mode="arithmetic";
+defparam un2_column_counter_next_5_.output_mode="comb_only";
+defparam un2_column_counter_next_5_.lut_mask="6c80";
+defparam un2_column_counter_next_5_.synch_mode="off";
+defparam un2_column_counter_next_5_.sum_lutc_input="cin";
+// @13:112
+  stratix_lcell un2_column_counter_next_4_ (
+	.combout(un2_column_counter_next_combout[4]),
+	.cout(un2_column_counter_next_cout[4]),
+	.clk(GND),
+	.dataa(column_counter_sig_4),
+	.datab(column_counter_sig_5),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un2_column_counter_next_cout[2]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_4_.cin_used="true";
+defparam un2_column_counter_next_4_.operation_mode="arithmetic";
+defparam un2_column_counter_next_4_.output_mode="comb_only";
+defparam un2_column_counter_next_4_.lut_mask="5a80";
+defparam un2_column_counter_next_4_.synch_mode="off";
+defparam un2_column_counter_next_4_.sum_lutc_input="cin";
+// @13:112
+  stratix_lcell un2_column_counter_next_3_ (
+	.combout(un2_column_counter_next_combout[3]),
+	.cout(un2_column_counter_next_cout[3]),
+	.clk(GND),
+	.dataa(column_counter_sig_2),
+	.datab(column_counter_sig_3),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un2_column_counter_next_cout[1]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_3_.cin_used="true";
+defparam un2_column_counter_next_3_.operation_mode="arithmetic";
+defparam un2_column_counter_next_3_.output_mode="comb_only";
+defparam un2_column_counter_next_3_.lut_mask="6c80";
+defparam un2_column_counter_next_3_.synch_mode="off";
+defparam un2_column_counter_next_3_.sum_lutc_input="cin";
+// @13:112
+  stratix_lcell un2_column_counter_next_2_ (
+	.combout(un2_column_counter_next_combout[2]),
+	.cout(un2_column_counter_next_cout[2]),
+	.clk(GND),
+	.dataa(column_counter_sig_2),
+	.datab(column_counter_sig_3),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un2_column_counter_next_cout[0]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_2_.cin_used="true";
+defparam un2_column_counter_next_2_.operation_mode="arithmetic";
+defparam un2_column_counter_next_2_.output_mode="comb_only";
+defparam un2_column_counter_next_2_.lut_mask="5a80";
+defparam un2_column_counter_next_2_.synch_mode="off";
+defparam un2_column_counter_next_2_.sum_lutc_input="cin";
+// @13:112
+  stratix_lcell un2_column_counter_next_1_ (
+	.combout(un2_column_counter_next_combout[1]),
+	.cout(un2_column_counter_next_cout[1]),
+	.clk(GND),
+	.dataa(column_counter_sig_0),
+	.datab(column_counter_sig_1),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_1_.operation_mode="arithmetic";
+defparam un2_column_counter_next_1_.output_mode="comb_only";
+defparam un2_column_counter_next_1_.lut_mask="6688";
+defparam un2_column_counter_next_1_.synch_mode="off";
+defparam un2_column_counter_next_1_.sum_lutc_input="datac";
+// @13:112
+  stratix_lcell un2_column_counter_next_0_ (
+	.cout(un2_column_counter_next_cout[0]),
+	.clk(GND),
+	.dataa(column_counter_sig_0),
+	.datab(column_counter_sig_1),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_column_counter_next_0_.operation_mode="arithmetic";
+defparam un2_column_counter_next_0_.output_mode="comb_only";
+defparam un2_column_counter_next_0_.lut_mask="5588";
+defparam un2_column_counter_next_0_.synch_mode="off";
+defparam un2_column_counter_next_0_.sum_lutc_input="datac";
+  assign  line_counter_next_0_sqmuxa_1_1_i = ~ line_counter_next_0_sqmuxa_1_1;
+  assign  column_counter_next_0_sqmuxa_1_1_i = ~ column_counter_next_0_sqmuxa_1_1;
+  assign  un9_vsync_counterlt9_i = ~ un9_vsync_counterlt9;
+  assign  G_16_i_i = ~ G_16_i;
+  assign  un9_hsync_counterlt9_i = ~ un9_hsync_counterlt9;
+  assign  G_2_i_i = ~ G_2_i;
+endmodule /* vga_driver */
+
+// VQM4.1+ 
+module vga_control (
+  line_counter_sig_0,
+  line_counter_sig_2,
+  line_counter_sig_1,
+  line_counter_sig_3,
+  line_counter_sig_6,
+  line_counter_sig_5,
+  line_counter_sig_4,
+  line_counter_sig_7,
+  line_counter_sig_8,
+  column_counter_sig_0,
+  column_counter_sig_1,
+  column_counter_sig_2,
+  column_counter_sig_8,
+  column_counter_sig_3,
+  column_counter_sig_5,
+  column_counter_sig_4,
+  column_counter_sig_9,
+  column_counter_sig_7,
+  column_counter_sig_6,
+  toggle_counter_sig_0,
+  toggle_counter_sig_1,
+  toggle_counter_sig_2,
+  toggle_counter_sig_3,
+  toggle_counter_sig_4,
+  toggle_counter_sig_5,
+  toggle_counter_sig_6,
+  toggle_counter_sig_7,
+  toggle_counter_sig_8,
+  toggle_counter_sig_9,
+  toggle_counter_sig_10,
+  toggle_counter_sig_11,
+  toggle_counter_sig_12,
+  toggle_counter_sig_13,
+  toggle_counter_sig_14,
+  toggle_counter_sig_15,
+  toggle_counter_sig_16,
+  toggle_counter_sig_17,
+  toggle_counter_sig_18,
+  toggle_counter_sig_19,
+  toggle_counter_sig_20,
+  toggle_counter_sig_21,
+  toggle_counter_sig_22,
+  toggle_counter_sig_23,
+  toggle_counter_sig_24,
+  h_enable_sig,
+  g,
+  b,
+  v_enable_sig,
+  r,
+  toggle_sig,
+  un6_dly_counter_0_x,
+  clk_pin_c
+)
+;
+input line_counter_sig_0 ;
+input line_counter_sig_2 ;
+input line_counter_sig_1 ;
+input line_counter_sig_3 ;
+input line_counter_sig_6 ;
+input line_counter_sig_5 ;
+input line_counter_sig_4 ;
+input line_counter_sig_7 ;
+input line_counter_sig_8 ;
+input column_counter_sig_0 ;
+input column_counter_sig_1 ;
+input column_counter_sig_2 ;
+input column_counter_sig_8 ;
+input column_counter_sig_3 ;
+input column_counter_sig_5 ;
+input column_counter_sig_4 ;
+input column_counter_sig_9 ;
+input column_counter_sig_7 ;
+input column_counter_sig_6 ;
+output toggle_counter_sig_0 ;
+output toggle_counter_sig_1 ;
+output toggle_counter_sig_2 ;
+output toggle_counter_sig_3 ;
+output toggle_counter_sig_4 ;
+output toggle_counter_sig_5 ;
+output toggle_counter_sig_6 ;
+output toggle_counter_sig_7 ;
+output toggle_counter_sig_8 ;
+output toggle_counter_sig_9 ;
+output toggle_counter_sig_10 ;
+output toggle_counter_sig_11 ;
+output toggle_counter_sig_12 ;
+output toggle_counter_sig_13 ;
+output toggle_counter_sig_14 ;
+output toggle_counter_sig_15 ;
+output toggle_counter_sig_16 ;
+output toggle_counter_sig_17 ;
+output toggle_counter_sig_18 ;
+output toggle_counter_sig_19 ;
+output toggle_counter_sig_20 ;
+output toggle_counter_sig_21 ;
+output toggle_counter_sig_22 ;
+output toggle_counter_sig_23 ;
+output toggle_counter_sig_24 ;
+input h_enable_sig ;
+output g ;
+output b ;
+input v_enable_sig ;
+output r ;
+output toggle_sig ;
+input un6_dly_counter_0_x ;
+input clk_pin_c ;
+wire line_counter_sig_0 ;
+wire line_counter_sig_2 ;
+wire line_counter_sig_1 ;
+wire line_counter_sig_3 ;
+wire line_counter_sig_6 ;
+wire line_counter_sig_5 ;
+wire line_counter_sig_4 ;
+wire line_counter_sig_7 ;
+wire line_counter_sig_8 ;
+wire column_counter_sig_0 ;
+wire column_counter_sig_1 ;
+wire column_counter_sig_2 ;
+wire column_counter_sig_8 ;
+wire column_counter_sig_3 ;
+wire column_counter_sig_5 ;
+wire column_counter_sig_4 ;
+wire column_counter_sig_9 ;
+wire column_counter_sig_7 ;
+wire column_counter_sig_6 ;
+wire toggle_counter_sig_0 ;
+wire toggle_counter_sig_1 ;
+wire toggle_counter_sig_2 ;
+wire toggle_counter_sig_3 ;
+wire toggle_counter_sig_4 ;
+wire toggle_counter_sig_5 ;
+wire toggle_counter_sig_6 ;
+wire toggle_counter_sig_7 ;
+wire toggle_counter_sig_8 ;
+wire toggle_counter_sig_9 ;
+wire toggle_counter_sig_10 ;
+wire toggle_counter_sig_11 ;
+wire toggle_counter_sig_12 ;
+wire toggle_counter_sig_13 ;
+wire toggle_counter_sig_14 ;
+wire toggle_counter_sig_15 ;
+wire toggle_counter_sig_16 ;
+wire toggle_counter_sig_17 ;
+wire toggle_counter_sig_18 ;
+wire toggle_counter_sig_19 ;
+wire toggle_counter_sig_20 ;
+wire toggle_counter_sig_21 ;
+wire toggle_counter_sig_22 ;
+wire toggle_counter_sig_23 ;
+wire toggle_counter_sig_24 ;
+wire h_enable_sig ;
+wire g ;
+wire b ;
+wire v_enable_sig ;
+wire r ;
+wire toggle_sig ;
+wire un6_dly_counter_0_x ;
+wire clk_pin_c ;
+wire [18:1] toggle_counter_sig_cout;
+wire [0:0] un2_toggle_counter_next_cout;
+wire GND ;
+wire toggle_sig_0_0_0_g1 ;
+wire b_next_0_sqmuxa_7_4 ;
+wire b_next_0_sqmuxa_7_5 ;
+wire toggle_sig_0_0_0_g1_2 ;
+wire un1_toggle_counter_siglto18 ;
+wire un1_toggle_counter_siglto15 ;
+wire un5_v_enablelto5 ;
+wire b_next_0_sqmuxa_7_3 ;
+wire un13_v_enablelto6 ;
+wire b_next_0_sqmuxa_7_4_a ;
+wire un17_v_enablelto3 ;
+wire b_next_0_sqmuxa_7_2 ;
+wire un9_v_enablelto6 ;
+wire un1_toggle_counter_siglto12 ;
+wire un5_v_enablelt2 ;
+wire un1_toggle_counter_siglto9 ;
+wire un13_v_enablelto4_0 ;
+wire un9_v_enablelto4 ;
+wire un1_toggle_counter_siglt6 ;
+wire VCC ;
+wire toggle_sig_0_0_0_g1_i ;
+  assign VCC = 1'b1;
+//@1:1
+  assign GND = 1'b0;
+// @12:99
+  stratix_lcell toggle_counter_sig_24_ (
+	.regout(toggle_counter_sig_24),
+	.clk(clk_pin_c),
+	.dataa(VCC),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(GND),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_24_.operation_mode="normal";
+defparam toggle_counter_sig_24_.output_mode="reg_only";
+defparam toggle_counter_sig_24_.lut_mask="ff00";
+defparam toggle_counter_sig_24_.synch_mode="off";
+defparam toggle_counter_sig_24_.sum_lutc_input="datac";
+// @12:99
+  stratix_lcell toggle_counter_sig_23_ (
+	.regout(toggle_counter_sig_23),
+	.clk(clk_pin_c),
+	.dataa(VCC),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(GND),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_23_.operation_mode="normal";
+defparam toggle_counter_sig_23_.output_mode="reg_only";
+defparam toggle_counter_sig_23_.lut_mask="ff00";
+defparam toggle_counter_sig_23_.synch_mode="off";
+defparam toggle_counter_sig_23_.sum_lutc_input="datac";
+// @12:99
+  stratix_lcell toggle_counter_sig_22_ (
+	.regout(toggle_counter_sig_22),
+	.clk(clk_pin_c),
+	.dataa(VCC),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(GND),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_22_.operation_mode="normal";
+defparam toggle_counter_sig_22_.output_mode="reg_only";
+defparam toggle_counter_sig_22_.lut_mask="ff00";
+defparam toggle_counter_sig_22_.synch_mode="off";
+defparam toggle_counter_sig_22_.sum_lutc_input="datac";
+// @12:99
+  stratix_lcell toggle_counter_sig_21_ (
+	.regout(toggle_counter_sig_21),
+	.clk(clk_pin_c),
+	.dataa(VCC),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(GND),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_21_.operation_mode="normal";
+defparam toggle_counter_sig_21_.output_mode="reg_only";
+defparam toggle_counter_sig_21_.lut_mask="ff00";
+defparam toggle_counter_sig_21_.synch_mode="off";
+defparam toggle_counter_sig_21_.sum_lutc_input="datac";
+// @12:99
+  stratix_lcell toggle_counter_sig_20_ (
+	.regout(toggle_counter_sig_20),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_20),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[18]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_20_.cin_used="true";
+defparam toggle_counter_sig_20_.operation_mode="normal";
+defparam toggle_counter_sig_20_.output_mode="reg_only";
+defparam toggle_counter_sig_20_.lut_mask="5a5a";
+defparam toggle_counter_sig_20_.synch_mode="on";
+defparam toggle_counter_sig_20_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_19_ (
+	.regout(toggle_counter_sig_19),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_18),
+	.datab(toggle_counter_sig_19),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[17]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_19_.cin_used="true";
+defparam toggle_counter_sig_19_.operation_mode="normal";
+defparam toggle_counter_sig_19_.output_mode="reg_only";
+defparam toggle_counter_sig_19_.lut_mask="6c6c";
+defparam toggle_counter_sig_19_.synch_mode="on";
+defparam toggle_counter_sig_19_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_18_ (
+	.regout(toggle_counter_sig_18),
+	.cout(toggle_counter_sig_cout[18]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_18),
+	.datab(toggle_counter_sig_19),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[16]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_18_.cin_used="true";
+defparam toggle_counter_sig_18_.operation_mode="arithmetic";
+defparam toggle_counter_sig_18_.output_mode="reg_only";
+defparam toggle_counter_sig_18_.lut_mask="5a80";
+defparam toggle_counter_sig_18_.synch_mode="on";
+defparam toggle_counter_sig_18_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_17_ (
+	.regout(toggle_counter_sig_17),
+	.cout(toggle_counter_sig_cout[17]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_16),
+	.datab(toggle_counter_sig_17),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[15]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_17_.cin_used="true";
+defparam toggle_counter_sig_17_.operation_mode="arithmetic";
+defparam toggle_counter_sig_17_.output_mode="reg_only";
+defparam toggle_counter_sig_17_.lut_mask="6c80";
+defparam toggle_counter_sig_17_.synch_mode="on";
+defparam toggle_counter_sig_17_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_16_ (
+	.regout(toggle_counter_sig_16),
+	.cout(toggle_counter_sig_cout[16]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_16),
+	.datab(toggle_counter_sig_17),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[14]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_16_.cin_used="true";
+defparam toggle_counter_sig_16_.operation_mode="arithmetic";
+defparam toggle_counter_sig_16_.output_mode="reg_only";
+defparam toggle_counter_sig_16_.lut_mask="5a80";
+defparam toggle_counter_sig_16_.synch_mode="on";
+defparam toggle_counter_sig_16_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_15_ (
+	.regout(toggle_counter_sig_15),
+	.cout(toggle_counter_sig_cout[15]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_14),
+	.datab(toggle_counter_sig_15),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[13]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_15_.cin_used="true";
+defparam toggle_counter_sig_15_.operation_mode="arithmetic";
+defparam toggle_counter_sig_15_.output_mode="reg_only";
+defparam toggle_counter_sig_15_.lut_mask="6c80";
+defparam toggle_counter_sig_15_.synch_mode="on";
+defparam toggle_counter_sig_15_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_14_ (
+	.regout(toggle_counter_sig_14),
+	.cout(toggle_counter_sig_cout[14]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_14),
+	.datab(toggle_counter_sig_15),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[12]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_14_.cin_used="true";
+defparam toggle_counter_sig_14_.operation_mode="arithmetic";
+defparam toggle_counter_sig_14_.output_mode="reg_only";
+defparam toggle_counter_sig_14_.lut_mask="5a80";
+defparam toggle_counter_sig_14_.synch_mode="on";
+defparam toggle_counter_sig_14_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_13_ (
+	.regout(toggle_counter_sig_13),
+	.cout(toggle_counter_sig_cout[13]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_12),
+	.datab(toggle_counter_sig_13),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[11]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_13_.cin_used="true";
+defparam toggle_counter_sig_13_.operation_mode="arithmetic";
+defparam toggle_counter_sig_13_.output_mode="reg_only";
+defparam toggle_counter_sig_13_.lut_mask="6c80";
+defparam toggle_counter_sig_13_.synch_mode="on";
+defparam toggle_counter_sig_13_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_12_ (
+	.regout(toggle_counter_sig_12),
+	.cout(toggle_counter_sig_cout[12]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_12),
+	.datab(toggle_counter_sig_13),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[10]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_12_.cin_used="true";
+defparam toggle_counter_sig_12_.operation_mode="arithmetic";
+defparam toggle_counter_sig_12_.output_mode="reg_only";
+defparam toggle_counter_sig_12_.lut_mask="5a80";
+defparam toggle_counter_sig_12_.synch_mode="on";
+defparam toggle_counter_sig_12_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_11_ (
+	.regout(toggle_counter_sig_11),
+	.cout(toggle_counter_sig_cout[11]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_10),
+	.datab(toggle_counter_sig_11),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[9]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_11_.cin_used="true";
+defparam toggle_counter_sig_11_.operation_mode="arithmetic";
+defparam toggle_counter_sig_11_.output_mode="reg_only";
+defparam toggle_counter_sig_11_.lut_mask="6c80";
+defparam toggle_counter_sig_11_.synch_mode="on";
+defparam toggle_counter_sig_11_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_10_ (
+	.regout(toggle_counter_sig_10),
+	.cout(toggle_counter_sig_cout[10]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_10),
+	.datab(toggle_counter_sig_11),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[8]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_10_.cin_used="true";
+defparam toggle_counter_sig_10_.operation_mode="arithmetic";
+defparam toggle_counter_sig_10_.output_mode="reg_only";
+defparam toggle_counter_sig_10_.lut_mask="5a80";
+defparam toggle_counter_sig_10_.synch_mode="on";
+defparam toggle_counter_sig_10_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_9_ (
+	.regout(toggle_counter_sig_9),
+	.cout(toggle_counter_sig_cout[9]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_8),
+	.datab(toggle_counter_sig_9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[7]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_9_.cin_used="true";
+defparam toggle_counter_sig_9_.operation_mode="arithmetic";
+defparam toggle_counter_sig_9_.output_mode="reg_only";
+defparam toggle_counter_sig_9_.lut_mask="6c80";
+defparam toggle_counter_sig_9_.synch_mode="on";
+defparam toggle_counter_sig_9_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_8_ (
+	.regout(toggle_counter_sig_8),
+	.cout(toggle_counter_sig_cout[8]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_8),
+	.datab(toggle_counter_sig_9),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[6]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_8_.cin_used="true";
+defparam toggle_counter_sig_8_.operation_mode="arithmetic";
+defparam toggle_counter_sig_8_.output_mode="reg_only";
+defparam toggle_counter_sig_8_.lut_mask="5a80";
+defparam toggle_counter_sig_8_.synch_mode="on";
+defparam toggle_counter_sig_8_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_7_ (
+	.regout(toggle_counter_sig_7),
+	.cout(toggle_counter_sig_cout[7]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_6),
+	.datab(toggle_counter_sig_7),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[5]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_7_.cin_used="true";
+defparam toggle_counter_sig_7_.operation_mode="arithmetic";
+defparam toggle_counter_sig_7_.output_mode="reg_only";
+defparam toggle_counter_sig_7_.lut_mask="6c80";
+defparam toggle_counter_sig_7_.synch_mode="on";
+defparam toggle_counter_sig_7_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_6_ (
+	.regout(toggle_counter_sig_6),
+	.cout(toggle_counter_sig_cout[6]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_6),
+	.datab(toggle_counter_sig_7),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[4]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_6_.cin_used="true";
+defparam toggle_counter_sig_6_.operation_mode="arithmetic";
+defparam toggle_counter_sig_6_.output_mode="reg_only";
+defparam toggle_counter_sig_6_.lut_mask="5a80";
+defparam toggle_counter_sig_6_.synch_mode="on";
+defparam toggle_counter_sig_6_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_5_ (
+	.regout(toggle_counter_sig_5),
+	.cout(toggle_counter_sig_cout[5]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_4),
+	.datab(toggle_counter_sig_5),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[3]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_5_.cin_used="true";
+defparam toggle_counter_sig_5_.operation_mode="arithmetic";
+defparam toggle_counter_sig_5_.output_mode="reg_only";
+defparam toggle_counter_sig_5_.lut_mask="6c80";
+defparam toggle_counter_sig_5_.synch_mode="on";
+defparam toggle_counter_sig_5_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_4_ (
+	.regout(toggle_counter_sig_4),
+	.cout(toggle_counter_sig_cout[4]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_4),
+	.datab(toggle_counter_sig_5),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[2]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_4_.cin_used="true";
+defparam toggle_counter_sig_4_.operation_mode="arithmetic";
+defparam toggle_counter_sig_4_.output_mode="reg_only";
+defparam toggle_counter_sig_4_.lut_mask="5a80";
+defparam toggle_counter_sig_4_.synch_mode="on";
+defparam toggle_counter_sig_4_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_3_ (
+	.regout(toggle_counter_sig_3),
+	.cout(toggle_counter_sig_cout[3]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_2),
+	.datab(toggle_counter_sig_3),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(toggle_counter_sig_cout[1]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_3_.cin_used="true";
+defparam toggle_counter_sig_3_.operation_mode="arithmetic";
+defparam toggle_counter_sig_3_.output_mode="reg_only";
+defparam toggle_counter_sig_3_.lut_mask="6c80";
+defparam toggle_counter_sig_3_.synch_mode="on";
+defparam toggle_counter_sig_3_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_2_ (
+	.regout(toggle_counter_sig_2),
+	.cout(toggle_counter_sig_cout[2]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_2),
+	.datab(toggle_counter_sig_3),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.cin(un2_toggle_counter_next_cout[0]),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_2_.cin_used="true";
+defparam toggle_counter_sig_2_.operation_mode="arithmetic";
+defparam toggle_counter_sig_2_.output_mode="reg_only";
+defparam toggle_counter_sig_2_.lut_mask="5a80";
+defparam toggle_counter_sig_2_.synch_mode="on";
+defparam toggle_counter_sig_2_.sum_lutc_input="cin";
+// @12:99
+  stratix_lcell toggle_counter_sig_1_ (
+	.regout(toggle_counter_sig_1),
+	.cout(toggle_counter_sig_cout[1]),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_0),
+	.datab(toggle_counter_sig_1),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_1_.operation_mode="arithmetic";
+defparam toggle_counter_sig_1_.output_mode="reg_only";
+defparam toggle_counter_sig_1_.lut_mask="6688";
+defparam toggle_counter_sig_1_.synch_mode="on";
+defparam toggle_counter_sig_1_.sum_lutc_input="datac";
+// @12:99
+  stratix_lcell toggle_counter_sig_0_ (
+	.regout(toggle_counter_sig_0),
+	.clk(clk_pin_c),
+	.dataa(toggle_counter_sig_0),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(toggle_sig_0_0_0_g1_i),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_counter_sig_0_.operation_mode="normal";
+defparam toggle_counter_sig_0_.output_mode="reg_only";
+defparam toggle_counter_sig_0_.lut_mask="5555";
+defparam toggle_counter_sig_0_.synch_mode="on";
+defparam toggle_counter_sig_0_.sum_lutc_input="datac";
+// @12:99
+  stratix_lcell toggle_sig_Z (
+	.regout(toggle_sig),
+	.clk(clk_pin_c),
+	.dataa(toggle_sig),
+	.datab(toggle_sig_0_0_0_g1),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_sig_Z.operation_mode="normal";
+defparam toggle_sig_Z.output_mode="reg_only";
+defparam toggle_sig_Z.lut_mask="9999";
+defparam toggle_sig_Z.synch_mode="off";
+defparam toggle_sig_Z.sum_lutc_input="datac";
+// @12:60
+  stratix_lcell r_Z (
+	.regout(r),
+	.clk(clk_pin_c),
+	.dataa(toggle_sig),
+	.datab(v_enable_sig),
+	.datac(b_next_0_sqmuxa_7_4),
+	.datad(b_next_0_sqmuxa_7_5),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam r_Z.operation_mode="normal";
+defparam r_Z.output_mode="reg_only";
+defparam r_Z.lut_mask="8000";
+defparam r_Z.synch_mode="off";
+defparam r_Z.sum_lutc_input="datac";
+// @12:60
+  stratix_lcell b_Z (
+	.regout(b),
+	.clk(clk_pin_c),
+	.dataa(toggle_sig),
+	.datab(v_enable_sig),
+	.datac(b_next_0_sqmuxa_7_4),
+	.datad(b_next_0_sqmuxa_7_5),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam b_Z.operation_mode="normal";
+defparam b_Z.output_mode="reg_only";
+defparam b_Z.lut_mask="4000";
+defparam b_Z.synch_mode="off";
+defparam b_Z.sum_lutc_input="datac";
+// @12:60
+  stratix_lcell g_Z (
+	.regout(g),
+	.clk(clk_pin_c),
+	.dataa(VCC),
+	.datab(VCC),
+	.datac(VCC),
+	.datad(GND),
+	.aclr(un6_dly_counter_0_x),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam g_Z.operation_mode="normal";
+defparam g_Z.output_mode="reg_only";
+defparam g_Z.lut_mask="ff00";
+defparam g_Z.synch_mode="off";
+defparam g_Z.sum_lutc_input="datac";
+  stratix_lcell toggle_sig_0_0_0_g1_cZ (
+	.combout(toggle_sig_0_0_0_g1),
+	.clk(GND),
+	.dataa(toggle_counter_sig_19),
+	.datab(toggle_counter_sig_20),
+	.datac(toggle_sig_0_0_0_g1_2),
+	.datad(un1_toggle_counter_siglto18),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_sig_0_0_0_g1_cZ.operation_mode="normal";
+defparam toggle_sig_0_0_0_g1_cZ.output_mode="comb_only";
+defparam toggle_sig_0_0_0_g1_cZ.lut_mask="0703";
+defparam toggle_sig_0_0_0_g1_cZ.synch_mode="off";
+defparam toggle_sig_0_0_0_g1_cZ.sum_lutc_input="datac";
+// @12:111
+  stratix_lcell BLINKER_next_un1_toggle_counter_siglto18 (
+	.combout(un1_toggle_counter_siglto18),
+	.clk(GND),
+	.dataa(toggle_counter_sig_17),
+	.datab(toggle_counter_sig_18),
+	.datac(toggle_counter_sig_16),
+	.datad(un1_toggle_counter_siglto15),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglto18.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglto18.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglto18.lut_mask="7f77";
+defparam BLINKER_next_un1_toggle_counter_siglto18.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglto18.sum_lutc_input="datac";
+// @12:75
+  stratix_lcell b_next_0_sqmuxa_7_5_cZ (
+	.combout(b_next_0_sqmuxa_7_5),
+	.clk(GND),
+	.dataa(column_counter_sig_6),
+	.datab(column_counter_sig_7),
+	.datac(un5_v_enablelto5),
+	.datad(b_next_0_sqmuxa_7_3),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_5_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_5_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_5_cZ.lut_mask="7f00";
+defparam b_next_0_sqmuxa_7_5_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_5_cZ.sum_lutc_input="datac";
+// @12:75
+  stratix_lcell b_next_0_sqmuxa_7_4_cZ (
+	.combout(b_next_0_sqmuxa_7_4),
+	.clk(GND),
+	.dataa(line_counter_sig_8),
+	.datab(line_counter_sig_7),
+	.datac(un13_v_enablelto6),
+	.datad(b_next_0_sqmuxa_7_4_a),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_4_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_4_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_4_cZ.lut_mask="ef23";
+defparam b_next_0_sqmuxa_7_4_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_4_cZ.sum_lutc_input="datac";
+// @12:75
+  stratix_lcell b_next_0_sqmuxa_7_4_a_cZ (
+	.combout(b_next_0_sqmuxa_7_4_a),
+	.clk(GND),
+	.dataa(line_counter_sig_4),
+	.datab(line_counter_sig_5),
+	.datac(line_counter_sig_6),
+	.datad(un17_v_enablelto3),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_4_a_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_4_a_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_4_a_cZ.lut_mask="0f1f";
+defparam b_next_0_sqmuxa_7_4_a_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_4_a_cZ.sum_lutc_input="datac";
+// @12:75
+  stratix_lcell b_next_0_sqmuxa_7_3_cZ (
+	.combout(b_next_0_sqmuxa_7_3),
+	.clk(GND),
+	.dataa(column_counter_sig_7),
+	.datab(column_counter_sig_9),
+	.datac(b_next_0_sqmuxa_7_2),
+	.datad(un9_v_enablelto6),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_3_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_3_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_3_cZ.lut_mask="e0f0";
+defparam b_next_0_sqmuxa_7_3_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_3_cZ.sum_lutc_input="datac";
+// @12:111
+  stratix_lcell BLINKER_next_un1_toggle_counter_siglto15 (
+	.combout(un1_toggle_counter_siglto15),
+	.clk(GND),
+	.dataa(toggle_counter_sig_13),
+	.datab(toggle_counter_sig_14),
+	.datac(toggle_counter_sig_15),
+	.datad(un1_toggle_counter_siglto12),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglto15.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglto15.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglto15.lut_mask="ff7f";
+defparam BLINKER_next_un1_toggle_counter_siglto15.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglto15.sum_lutc_input="datac";
+// @12:75
+  stratix_lcell DRAW_SQUARE_next_un5_v_enablelto5 (
+	.combout(un5_v_enablelto5),
+	.clk(GND),
+	.dataa(column_counter_sig_4),
+	.datab(column_counter_sig_5),
+	.datac(column_counter_sig_3),
+	.datad(un5_v_enablelt2),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un5_v_enablelto5.operation_mode="normal";
+defparam DRAW_SQUARE_next_un5_v_enablelto5.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un5_v_enablelto5.lut_mask="feee";
+defparam DRAW_SQUARE_next_un5_v_enablelto5.synch_mode="off";
+defparam DRAW_SQUARE_next_un5_v_enablelto5.sum_lutc_input="datac";
+// @12:111
+  stratix_lcell BLINKER_next_un1_toggle_counter_siglto12 (
+	.combout(un1_toggle_counter_siglto12),
+	.clk(GND),
+	.dataa(toggle_counter_sig_10),
+	.datab(toggle_counter_sig_11),
+	.datac(toggle_counter_sig_12),
+	.datad(un1_toggle_counter_siglto9),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglto12.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglto12.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglto12.lut_mask="0100";
+defparam BLINKER_next_un1_toggle_counter_siglto12.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglto12.sum_lutc_input="datac";
+// @12:76
+  stratix_lcell DRAW_SQUARE_next_un13_v_enablelto6 (
+	.combout(un13_v_enablelto6),
+	.clk(GND),
+	.dataa(line_counter_sig_5),
+	.datab(line_counter_sig_6),
+	.datac(line_counter_sig_3),
+	.datad(un13_v_enablelto4_0),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un13_v_enablelto6.operation_mode="normal";
+defparam DRAW_SQUARE_next_un13_v_enablelto6.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un13_v_enablelto6.lut_mask="7f77";
+defparam DRAW_SQUARE_next_un13_v_enablelto6.synch_mode="off";
+defparam DRAW_SQUARE_next_un13_v_enablelto6.sum_lutc_input="datac";
+// @12:75
+  stratix_lcell DRAW_SQUARE_next_un9_v_enablelto6 (
+	.combout(un9_v_enablelto6),
+	.clk(GND),
+	.dataa(column_counter_sig_5),
+	.datab(column_counter_sig_6),
+	.datac(un9_v_enablelto4),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un9_v_enablelto6.operation_mode="normal";
+defparam DRAW_SQUARE_next_un9_v_enablelto6.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un9_v_enablelto6.lut_mask="f7f7";
+defparam DRAW_SQUARE_next_un9_v_enablelto6.synch_mode="off";
+defparam DRAW_SQUARE_next_un9_v_enablelto6.sum_lutc_input="datac";
+// @12:111
+  stratix_lcell BLINKER_next_un1_toggle_counter_siglto9 (
+	.combout(un1_toggle_counter_siglto9),
+	.clk(GND),
+	.dataa(toggle_counter_sig_8),
+	.datab(toggle_counter_sig_9),
+	.datac(toggle_counter_sig_7),
+	.datad(un1_toggle_counter_siglt6),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglto9.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglto9.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglto9.lut_mask="7f77";
+defparam BLINKER_next_un1_toggle_counter_siglto9.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglto9.sum_lutc_input="datac";
+// @12:76
+  stratix_lcell DRAW_SQUARE_next_un17_v_enablelto3 (
+	.combout(un17_v_enablelto3),
+	.clk(GND),
+	.dataa(line_counter_sig_1),
+	.datab(line_counter_sig_2),
+	.datac(line_counter_sig_0),
+	.datad(line_counter_sig_3),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un17_v_enablelto3.operation_mode="normal";
+defparam DRAW_SQUARE_next_un17_v_enablelto3.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un17_v_enablelto3.lut_mask="fe00";
+defparam DRAW_SQUARE_next_un17_v_enablelto3.synch_mode="off";
+defparam DRAW_SQUARE_next_un17_v_enablelto3.sum_lutc_input="datac";
+  stratix_lcell toggle_sig_0_0_0_g1_2_cZ (
+	.combout(toggle_sig_0_0_0_g1_2),
+	.clk(GND),
+	.dataa(toggle_counter_sig_23),
+	.datab(toggle_counter_sig_24),
+	.datac(toggle_counter_sig_21),
+	.datad(toggle_counter_sig_22),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam toggle_sig_0_0_0_g1_2_cZ.operation_mode="normal";
+defparam toggle_sig_0_0_0_g1_2_cZ.output_mode="comb_only";
+defparam toggle_sig_0_0_0_g1_2_cZ.lut_mask="fffe";
+defparam toggle_sig_0_0_0_g1_2_cZ.synch_mode="off";
+defparam toggle_sig_0_0_0_g1_2_cZ.sum_lutc_input="datac";
+// @12:75
+  stratix_lcell b_next_0_sqmuxa_7_2_cZ (
+	.combout(b_next_0_sqmuxa_7_2),
+	.clk(GND),
+	.dataa(column_counter_sig_8),
+	.datab(h_enable_sig),
+	.datac(column_counter_sig_9),
+	.datad(line_counter_sig_8),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_2_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_2_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_2_cZ.lut_mask="0004";
+defparam b_next_0_sqmuxa_7_2_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_2_cZ.sum_lutc_input="datac";
+// @12:75
+  stratix_lcell DRAW_SQUARE_next_un9_v_enablelto4 (
+	.combout(un9_v_enablelto4),
+	.clk(GND),
+	.dataa(column_counter_sig_3),
+	.datab(column_counter_sig_4),
+	.datac(column_counter_sig_2),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un9_v_enablelto4.operation_mode="normal";
+defparam DRAW_SQUARE_next_un9_v_enablelto4.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un9_v_enablelto4.lut_mask="0101";
+defparam DRAW_SQUARE_next_un9_v_enablelto4.synch_mode="off";
+defparam DRAW_SQUARE_next_un9_v_enablelto4.sum_lutc_input="datac";
+// @12:75
+  stratix_lcell DRAW_SQUARE_next_un5_v_enablelt2 (
+	.combout(un5_v_enablelt2),
+	.clk(GND),
+	.dataa(column_counter_sig_1),
+	.datab(column_counter_sig_2),
+	.datac(column_counter_sig_0),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un5_v_enablelt2.operation_mode="normal";
+defparam DRAW_SQUARE_next_un5_v_enablelt2.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un5_v_enablelt2.lut_mask="fefe";
+defparam DRAW_SQUARE_next_un5_v_enablelt2.synch_mode="off";
+defparam DRAW_SQUARE_next_un5_v_enablelt2.sum_lutc_input="datac";
+// @12:76
+  stratix_lcell DRAW_SQUARE_next_un13_v_enablelto4_0 (
+	.combout(un13_v_enablelto4_0),
+	.clk(GND),
+	.dataa(line_counter_sig_4),
+	.datab(line_counter_sig_2),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.operation_mode="normal";
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.lut_mask="1111";
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.synch_mode="off";
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.sum_lutc_input="datac";
+// @12:111
+  stratix_lcell BLINKER_next_un1_toggle_counter_siglt6 (
+	.combout(un1_toggle_counter_siglt6),
+	.clk(GND),
+	.dataa(toggle_counter_sig_6),
+	.datab(toggle_counter_sig_5),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglt6.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglt6.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglt6.lut_mask="7777";
+defparam BLINKER_next_un1_toggle_counter_siglt6.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglt6.sum_lutc_input="datac";
+// @12:115
+  stratix_lcell un2_toggle_counter_next_0_ (
+	.cout(un2_toggle_counter_next_cout[0]),
+	.clk(GND),
+	.dataa(toggle_counter_sig_0),
+	.datab(toggle_counter_sig_1),
+	.datac(VCC),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam un2_toggle_counter_next_0_.operation_mode="arithmetic";
+defparam un2_toggle_counter_next_0_.output_mode="comb_only";
+defparam un2_toggle_counter_next_0_.lut_mask="5588";
+defparam un2_toggle_counter_next_0_.synch_mode="off";
+defparam un2_toggle_counter_next_0_.sum_lutc_input="datac";
+  assign  toggle_sig_0_0_0_g1_i = ~ toggle_sig_0_0_0_g1;
+endmodule /* vga_control */
+
+// VQM4.1+ 
+module vga (
+  clk_pin,
+  reset_pin,
+  r0_pin,
+  r1_pin,
+  r2_pin,
+  g0_pin,
+  g1_pin,
+  g2_pin,
+  b0_pin,
+  b1_pin,
+  hsync_pin,
+  vsync_pin,
+  seven_seg_pin,
+  d_hsync,
+  d_vsync,
+  d_column_counter,
+  d_line_counter,
+  d_set_column_counter,
+  d_set_line_counter,
+  d_hsync_counter,
+  d_vsync_counter,
+  d_set_hsync_counter,
+  d_set_vsync_counter,
+  d_h_enable,
+  d_v_enable,
+  d_r,
+  d_g,
+  d_b,
+  d_hsync_state,
+  d_vsync_state,
+  d_state_clk,
+  d_toggle,
+  d_toggle_counter
+)
+;
+input clk_pin ;
+input reset_pin ;
+output r0_pin ;
+output r1_pin ;
+output r2_pin ;
+output g0_pin ;
+output g1_pin ;
+output g2_pin ;
+output b0_pin ;
+output b1_pin ;
+output hsync_pin ;
+output vsync_pin ;
+output [13:0] seven_seg_pin ;
+output d_hsync ;
+output d_vsync ;
+output [9:0] d_column_counter ;
+output [8:0] d_line_counter ;
+output d_set_column_counter ;
+output d_set_line_counter ;
+output [9:0] d_hsync_counter ;
+output [9:0] d_vsync_counter ;
+output d_set_hsync_counter ;
+output d_set_vsync_counter ;
+output d_h_enable ;
+output d_v_enable ;
+output d_r ;
+output d_g ;
+output d_b ;
+output [0:6] d_hsync_state ;
+output [0:6] d_vsync_state ;
+output d_state_clk ;
+output d_toggle ;
+output [24:0] d_toggle_counter ;
+wire clk_pin ;
+wire reset_pin ;
+wire r0_pin ;
+wire r1_pin ;
+wire r2_pin ;
+wire g0_pin ;
+wire g1_pin ;
+wire g2_pin ;
+wire b0_pin ;
+wire b1_pin ;
+wire hsync_pin ;
+wire vsync_pin ;
+wire d_hsync ;
+wire d_vsync ;
+wire d_set_column_counter ;
+wire d_set_line_counter ;
+wire d_set_hsync_counter ;
+wire d_set_vsync_counter ;
+wire d_h_enable ;
+wire d_v_enable ;
+wire d_r ;
+wire d_g ;
+wire d_b ;
+wire d_state_clk ;
+wire d_toggle ;
+wire [1:0] dly_counter;
+wire [9:0] vga_driver_unit_column_counter_sig;
+wire [8:0] vga_driver_unit_line_counter_sig;
+wire [9:0] vga_driver_unit_hsync_counter;
+wire [9:0] vga_driver_unit_vsync_counter;
+wire [6:0] vga_driver_unit_hsync_state;
+wire [6:0] vga_driver_unit_vsync_state;
+wire [24:0] vga_control_unit_toggle_counter_sig;
+wire VCC ;
+wire GND ;
+wire DELAY_RESET_next_un6_dly_counter_0_x ;
+wire vga_driver_unit_h_sync ;
+wire vga_driver_unit_v_sync ;
+wire vga_driver_unit_d_set_hsync_counter ;
+wire vga_driver_unit_d_set_vsync_counter ;
+wire vga_driver_unit_h_enable_sig ;
+wire vga_driver_unit_v_enable_sig ;
+wire vga_control_unit_r ;
+wire vga_control_unit_g ;
+wire vga_control_unit_b ;
+wire G_33 ;
+wire vga_control_unit_toggle_sig ;
+wire reset_pin_c ;
+//@1:1
+  assign VCC = 1'b1;
+//@1:1
+  assign GND = 1'b0;
+// @10:113
+  stratix_lcell dly_counter_1_ (
+	.regout(dly_counter[1]),
+	.clk(G_33),
+	.dataa(reset_pin_c),
+	.datab(dly_counter[0]),
+	.datac(dly_counter[1]),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam dly_counter_1_.operation_mode="normal";
+defparam dly_counter_1_.output_mode="reg_only";
+defparam dly_counter_1_.lut_mask="a8a8";
+defparam dly_counter_1_.synch_mode="off";
+defparam dly_counter_1_.sum_lutc_input="datac";
+// @10:113
+  stratix_lcell dly_counter_0_ (
+	.regout(dly_counter[0]),
+	.clk(G_33),
+	.dataa(reset_pin_c),
+	.datab(dly_counter[0]),
+	.datac(dly_counter[1]),
+	.datad(VCC),
+	.aclr(GND),
+	.sclr(GND),
+	.sload(GND),
+	.ena(VCC),
+	.inverta(GND),
+	.aload(GND),
+	.regcascin(GND)
+);
+defparam dly_counter_0_.operation_mode="normal";
+defparam dly_counter_0_.output_mode="reg_only";
+defparam dly_counter_0_.lut_mask="a2a2";
+defparam dly_counter_0_.synch_mode="off";
+defparam dly_counter_0_.sum_lutc_input="datac";
+// @6:42
+  stratix_io reset_pin_in (
+	.padio(reset_pin),
+	.combout(reset_pin_c),
+	.datain(GND),
+	.oe(GND),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam reset_pin_in.operation_mode = "input";
+// @6:41
+  stratix_io clk_pin_in (
+	.padio(clk_pin),
+	.combout(G_33),
+	.datain(GND),
+	.oe(GND),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam clk_pin_in.operation_mode = "input";
+// @6:66
+  stratix_io d_toggle_counter_out_24_ (
+	.padio(d_toggle_counter[24]),
+	.datain(vga_control_unit_toggle_counter_sig[24]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_24_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_23_ (
+	.padio(d_toggle_counter[23]),
+	.datain(vga_control_unit_toggle_counter_sig[23]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_23_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_22_ (
+	.padio(d_toggle_counter[22]),
+	.datain(vga_control_unit_toggle_counter_sig[22]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_22_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_21_ (
+	.padio(d_toggle_counter[21]),
+	.datain(vga_control_unit_toggle_counter_sig[21]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_21_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_20_ (
+	.padio(d_toggle_counter[20]),
+	.datain(vga_control_unit_toggle_counter_sig[20]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_20_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_19_ (
+	.padio(d_toggle_counter[19]),
+	.datain(vga_control_unit_toggle_counter_sig[19]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_19_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_18_ (
+	.padio(d_toggle_counter[18]),
+	.datain(vga_control_unit_toggle_counter_sig[18]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_18_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_17_ (
+	.padio(d_toggle_counter[17]),
+	.datain(vga_control_unit_toggle_counter_sig[17]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_17_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_16_ (
+	.padio(d_toggle_counter[16]),
+	.datain(vga_control_unit_toggle_counter_sig[16]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_16_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_15_ (
+	.padio(d_toggle_counter[15]),
+	.datain(vga_control_unit_toggle_counter_sig[15]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_15_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_14_ (
+	.padio(d_toggle_counter[14]),
+	.datain(vga_control_unit_toggle_counter_sig[14]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_14_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_13_ (
+	.padio(d_toggle_counter[13]),
+	.datain(vga_control_unit_toggle_counter_sig[13]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_13_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_12_ (
+	.padio(d_toggle_counter[12]),
+	.datain(vga_control_unit_toggle_counter_sig[12]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_12_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_11_ (
+	.padio(d_toggle_counter[11]),
+	.datain(vga_control_unit_toggle_counter_sig[11]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_11_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_10_ (
+	.padio(d_toggle_counter[10]),
+	.datain(vga_control_unit_toggle_counter_sig[10]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_10_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_9_ (
+	.padio(d_toggle_counter[9]),
+	.datain(vga_control_unit_toggle_counter_sig[9]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_9_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_8_ (
+	.padio(d_toggle_counter[8]),
+	.datain(vga_control_unit_toggle_counter_sig[8]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_8_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_7_ (
+	.padio(d_toggle_counter[7]),
+	.datain(vga_control_unit_toggle_counter_sig[7]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_7_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_6_ (
+	.padio(d_toggle_counter[6]),
+	.datain(vga_control_unit_toggle_counter_sig[6]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_6_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_5_ (
+	.padio(d_toggle_counter[5]),
+	.datain(vga_control_unit_toggle_counter_sig[5]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_5_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_4_ (
+	.padio(d_toggle_counter[4]),
+	.datain(vga_control_unit_toggle_counter_sig[4]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_4_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_3_ (
+	.padio(d_toggle_counter[3]),
+	.datain(vga_control_unit_toggle_counter_sig[3]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_3_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_2_ (
+	.padio(d_toggle_counter[2]),
+	.datain(vga_control_unit_toggle_counter_sig[2]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_2_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_1_ (
+	.padio(d_toggle_counter[1]),
+	.datain(vga_control_unit_toggle_counter_sig[1]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_1_.operation_mode = "output";
+// @6:66
+  stratix_io d_toggle_counter_out_0_ (
+	.padio(d_toggle_counter[0]),
+	.datain(vga_control_unit_toggle_counter_sig[0]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_counter_out_0_.operation_mode = "output";
+// @6:65
+  stratix_io d_toggle_out (
+	.padio(d_toggle),
+	.datain(vga_control_unit_toggle_sig),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_toggle_out.operation_mode = "output";
+// @6:64
+  stratix_io d_state_clk_out (
+	.padio(d_state_clk),
+	.datain(G_33),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_state_clk_out.operation_mode = "output";
+// @6:63
+  stratix_io d_vsync_state_out_0_ (
+	.padio(d_vsync_state[0]),
+	.datain(vga_driver_unit_vsync_state[0]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_state_out_0_.operation_mode = "output";
+// @6:63
+  stratix_io d_vsync_state_out_1_ (
+	.padio(d_vsync_state[1]),
+	.datain(vga_driver_unit_vsync_state[1]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_state_out_1_.operation_mode = "output";
+// @6:63
+  stratix_io d_vsync_state_out_2_ (
+	.padio(d_vsync_state[2]),
+	.datain(vga_driver_unit_vsync_state[2]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_state_out_2_.operation_mode = "output";
+// @6:63
+  stratix_io d_vsync_state_out_3_ (
+	.padio(d_vsync_state[3]),
+	.datain(vga_driver_unit_vsync_state[3]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_state_out_3_.operation_mode = "output";
+// @6:63
+  stratix_io d_vsync_state_out_4_ (
+	.padio(d_vsync_state[4]),
+	.datain(vga_driver_unit_vsync_state[4]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_state_out_4_.operation_mode = "output";
+// @6:63
+  stratix_io d_vsync_state_out_5_ (
+	.padio(d_vsync_state[5]),
+	.datain(vga_driver_unit_vsync_state[5]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_state_out_5_.operation_mode = "output";
+// @6:63
+  stratix_io d_vsync_state_out_6_ (
+	.padio(d_vsync_state[6]),
+	.datain(vga_driver_unit_vsync_state[6]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_state_out_6_.operation_mode = "output";
+// @6:62
+  stratix_io d_hsync_state_out_0_ (
+	.padio(d_hsync_state[0]),
+	.datain(vga_driver_unit_hsync_state[0]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_state_out_0_.operation_mode = "output";
+// @6:62
+  stratix_io d_hsync_state_out_1_ (
+	.padio(d_hsync_state[1]),
+	.datain(vga_driver_unit_hsync_state[1]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_state_out_1_.operation_mode = "output";
+// @6:62
+  stratix_io d_hsync_state_out_2_ (
+	.padio(d_hsync_state[2]),
+	.datain(vga_driver_unit_hsync_state[2]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_state_out_2_.operation_mode = "output";
+// @6:62
+  stratix_io d_hsync_state_out_3_ (
+	.padio(d_hsync_state[3]),
+	.datain(vga_driver_unit_hsync_state[3]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_state_out_3_.operation_mode = "output";
+// @6:62
+  stratix_io d_hsync_state_out_4_ (
+	.padio(d_hsync_state[4]),
+	.datain(vga_driver_unit_hsync_state[4]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_state_out_4_.operation_mode = "output";
+// @6:62
+  stratix_io d_hsync_state_out_5_ (
+	.padio(d_hsync_state[5]),
+	.datain(vga_driver_unit_hsync_state[5]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_state_out_5_.operation_mode = "output";
+// @6:62
+  stratix_io d_hsync_state_out_6_ (
+	.padio(d_hsync_state[6]),
+	.datain(vga_driver_unit_hsync_state[6]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_state_out_6_.operation_mode = "output";
+// @6:61
+  stratix_io d_b_out (
+	.padio(d_b),
+	.datain(vga_control_unit_b),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_b_out.operation_mode = "output";
+// @6:61
+  stratix_io d_g_out (
+	.padio(d_g),
+	.datain(vga_control_unit_g),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_g_out.operation_mode = "output";
+// @6:61
+  stratix_io d_r_out (
+	.padio(d_r),
+	.datain(vga_control_unit_r),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_r_out.operation_mode = "output";
+// @6:60
+  stratix_io d_v_enable_out (
+	.padio(d_v_enable),
+	.datain(vga_driver_unit_v_enable_sig),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_v_enable_out.operation_mode = "output";
+// @6:59
+  stratix_io d_h_enable_out (
+	.padio(d_h_enable),
+	.datain(vga_driver_unit_h_enable_sig),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_h_enable_out.operation_mode = "output";
+// @6:58
+  stratix_io d_set_vsync_counter_out (
+	.padio(d_set_vsync_counter),
+	.datain(vga_driver_unit_d_set_vsync_counter),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_set_vsync_counter_out.operation_mode = "output";
+// @6:58
+  stratix_io d_set_hsync_counter_out (
+	.padio(d_set_hsync_counter),
+	.datain(vga_driver_unit_d_set_hsync_counter),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_set_hsync_counter_out.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_9_ (
+	.padio(d_vsync_counter[9]),
+	.datain(vga_driver_unit_vsync_counter[9]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_9_.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_8_ (
+	.padio(d_vsync_counter[8]),
+	.datain(vga_driver_unit_vsync_counter[8]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_8_.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_7_ (
+	.padio(d_vsync_counter[7]),
+	.datain(vga_driver_unit_vsync_counter[7]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_7_.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_6_ (
+	.padio(d_vsync_counter[6]),
+	.datain(vga_driver_unit_vsync_counter[6]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_6_.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_5_ (
+	.padio(d_vsync_counter[5]),
+	.datain(vga_driver_unit_vsync_counter[5]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_5_.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_4_ (
+	.padio(d_vsync_counter[4]),
+	.datain(vga_driver_unit_vsync_counter[4]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_4_.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_3_ (
+	.padio(d_vsync_counter[3]),
+	.datain(vga_driver_unit_vsync_counter[3]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_3_.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_2_ (
+	.padio(d_vsync_counter[2]),
+	.datain(vga_driver_unit_vsync_counter[2]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_2_.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_1_ (
+	.padio(d_vsync_counter[1]),
+	.datain(vga_driver_unit_vsync_counter[1]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_1_.operation_mode = "output";
+// @6:57
+  stratix_io d_vsync_counter_out_0_ (
+	.padio(d_vsync_counter[0]),
+	.datain(vga_driver_unit_vsync_counter[0]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_counter_out_0_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_9_ (
+	.padio(d_hsync_counter[9]),
+	.datain(vga_driver_unit_hsync_counter[9]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_9_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_8_ (
+	.padio(d_hsync_counter[8]),
+	.datain(vga_driver_unit_hsync_counter[8]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_8_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_7_ (
+	.padio(d_hsync_counter[7]),
+	.datain(vga_driver_unit_hsync_counter[7]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_7_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_6_ (
+	.padio(d_hsync_counter[6]),
+	.datain(vga_driver_unit_hsync_counter[6]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_6_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_5_ (
+	.padio(d_hsync_counter[5]),
+	.datain(vga_driver_unit_hsync_counter[5]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_5_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_4_ (
+	.padio(d_hsync_counter[4]),
+	.datain(vga_driver_unit_hsync_counter[4]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_4_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_3_ (
+	.padio(d_hsync_counter[3]),
+	.datain(vga_driver_unit_hsync_counter[3]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_3_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_2_ (
+	.padio(d_hsync_counter[2]),
+	.datain(vga_driver_unit_hsync_counter[2]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_2_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_1_ (
+	.padio(d_hsync_counter[1]),
+	.datain(vga_driver_unit_hsync_counter[1]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_1_.operation_mode = "output";
+// @6:56
+  stratix_io d_hsync_counter_out_0_ (
+	.padio(d_hsync_counter[0]),
+	.datain(vga_driver_unit_hsync_counter[0]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_counter_out_0_.operation_mode = "output";
+// @6:55
+  stratix_io d_set_line_counter_out (
+	.padio(d_set_line_counter),
+	.datain(vga_driver_unit_vsync_state[1]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_set_line_counter_out.operation_mode = "output";
+// @6:55
+  stratix_io d_set_column_counter_out (
+	.padio(d_set_column_counter),
+	.datain(vga_driver_unit_hsync_state[1]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_set_column_counter_out.operation_mode = "output";
+// @6:54
+  stratix_io d_line_counter_out_8_ (
+	.padio(d_line_counter[8]),
+	.datain(vga_driver_unit_line_counter_sig[8]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_line_counter_out_8_.operation_mode = "output";
+// @6:54
+  stratix_io d_line_counter_out_7_ (
+	.padio(d_line_counter[7]),
+	.datain(vga_driver_unit_line_counter_sig[7]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_line_counter_out_7_.operation_mode = "output";
+// @6:54
+  stratix_io d_line_counter_out_6_ (
+	.padio(d_line_counter[6]),
+	.datain(vga_driver_unit_line_counter_sig[6]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_line_counter_out_6_.operation_mode = "output";
+// @6:54
+  stratix_io d_line_counter_out_5_ (
+	.padio(d_line_counter[5]),
+	.datain(vga_driver_unit_line_counter_sig[5]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_line_counter_out_5_.operation_mode = "output";
+// @6:54
+  stratix_io d_line_counter_out_4_ (
+	.padio(d_line_counter[4]),
+	.datain(vga_driver_unit_line_counter_sig[4]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_line_counter_out_4_.operation_mode = "output";
+// @6:54
+  stratix_io d_line_counter_out_3_ (
+	.padio(d_line_counter[3]),
+	.datain(vga_driver_unit_line_counter_sig[3]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_line_counter_out_3_.operation_mode = "output";
+// @6:54
+  stratix_io d_line_counter_out_2_ (
+	.padio(d_line_counter[2]),
+	.datain(vga_driver_unit_line_counter_sig[2]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_line_counter_out_2_.operation_mode = "output";
+// @6:54
+  stratix_io d_line_counter_out_1_ (
+	.padio(d_line_counter[1]),
+	.datain(vga_driver_unit_line_counter_sig[1]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_line_counter_out_1_.operation_mode = "output";
+// @6:54
+  stratix_io d_line_counter_out_0_ (
+	.padio(d_line_counter[0]),
+	.datain(vga_driver_unit_line_counter_sig[0]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_line_counter_out_0_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_9_ (
+	.padio(d_column_counter[9]),
+	.datain(vga_driver_unit_column_counter_sig[9]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_9_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_8_ (
+	.padio(d_column_counter[8]),
+	.datain(vga_driver_unit_column_counter_sig[8]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_8_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_7_ (
+	.padio(d_column_counter[7]),
+	.datain(vga_driver_unit_column_counter_sig[7]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_7_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_6_ (
+	.padio(d_column_counter[6]),
+	.datain(vga_driver_unit_column_counter_sig[6]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_6_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_5_ (
+	.padio(d_column_counter[5]),
+	.datain(vga_driver_unit_column_counter_sig[5]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_5_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_4_ (
+	.padio(d_column_counter[4]),
+	.datain(vga_driver_unit_column_counter_sig[4]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_4_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_3_ (
+	.padio(d_column_counter[3]),
+	.datain(vga_driver_unit_column_counter_sig[3]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_3_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_2_ (
+	.padio(d_column_counter[2]),
+	.datain(vga_driver_unit_column_counter_sig[2]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_2_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_1_ (
+	.padio(d_column_counter[1]),
+	.datain(vga_driver_unit_column_counter_sig[1]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_1_.operation_mode = "output";
+// @6:53
+  stratix_io d_column_counter_out_0_ (
+	.padio(d_column_counter[0]),
+	.datain(vga_driver_unit_column_counter_sig[0]),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_column_counter_out_0_.operation_mode = "output";
+// @6:52
+  stratix_io d_vsync_out (
+	.padio(d_vsync),
+	.datain(vga_driver_unit_v_sync),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_vsync_out.operation_mode = "output";
+// @6:52
+  stratix_io d_hsync_out (
+	.padio(d_hsync),
+	.datain(vga_driver_unit_h_sync),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam d_hsync_out.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_tri_13_ (
+	.padio(seven_seg_pin[13]),
+	.datain(VCC),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_tri_13_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_out_12_ (
+	.padio(seven_seg_pin[12]),
+	.datain(DELAY_RESET_next_un6_dly_counter_0_x),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_out_12_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_out_11_ (
+	.padio(seven_seg_pin[11]),
+	.datain(DELAY_RESET_next_un6_dly_counter_0_x),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_out_11_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_out_10_ (
+	.padio(seven_seg_pin[10]),
+	.datain(DELAY_RESET_next_un6_dly_counter_0_x),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_out_10_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_out_9_ (
+	.padio(seven_seg_pin[9]),
+	.datain(DELAY_RESET_next_un6_dly_counter_0_x),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_out_9_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_out_8_ (
+	.padio(seven_seg_pin[8]),
+	.datain(DELAY_RESET_next_un6_dly_counter_0_x),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_out_8_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_out_7_ (
+	.padio(seven_seg_pin[7]),
+	.datain(DELAY_RESET_next_un6_dly_counter_0_x),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_out_7_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_tri_6_ (
+	.padio(seven_seg_pin[6]),
+	.datain(VCC),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_tri_6_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_tri_5_ (
+	.padio(seven_seg_pin[5]),
+	.datain(VCC),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_tri_5_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_tri_4_ (
+	.padio(seven_seg_pin[4]),
+	.datain(VCC),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_tri_4_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_tri_3_ (
+	.padio(seven_seg_pin[3]),
+	.datain(VCC),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_tri_3_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_out_2_ (
+	.padio(seven_seg_pin[2]),
+	.datain(DELAY_RESET_next_un6_dly_counter_0_x),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_out_2_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_out_1_ (
+	.padio(seven_seg_pin[1]),
+	.datain(DELAY_RESET_next_un6_dly_counter_0_x),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_out_1_.operation_mode = "output";
+// @6:50
+  stratix_io seven_seg_pin_tri_0_ (
+	.padio(seven_seg_pin[0]),
+	.datain(VCC),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam seven_seg_pin_tri_0_.operation_mode = "output";
+// @6:48
+  stratix_io vsync_pin_out (
+	.padio(vsync_pin),
+	.datain(vga_driver_unit_v_sync),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam vsync_pin_out.operation_mode = "output";
+// @6:47
+  stratix_io hsync_pin_out (
+	.padio(hsync_pin),
+	.datain(vga_driver_unit_h_sync),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam hsync_pin_out.operation_mode = "output";
+// @6:46
+  stratix_io b1_pin_out (
+	.padio(b1_pin),
+	.datain(vga_control_unit_b),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam b1_pin_out.operation_mode = "output";
+// @6:46
+  stratix_io b0_pin_out (
+	.padio(b0_pin),
+	.datain(vga_control_unit_b),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam b0_pin_out.operation_mode = "output";
+// @6:45
+  stratix_io g2_pin_out (
+	.padio(g2_pin),
+	.datain(vga_control_unit_g),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam g2_pin_out.operation_mode = "output";
+// @6:45
+  stratix_io g1_pin_out (
+	.padio(g1_pin),
+	.datain(vga_control_unit_g),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam g1_pin_out.operation_mode = "output";
+// @6:45
+  stratix_io g0_pin_out (
+	.padio(g0_pin),
+	.datain(vga_control_unit_g),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam g0_pin_out.operation_mode = "output";
+// @6:44
+  stratix_io r2_pin_out (
+	.padio(r2_pin),
+	.datain(vga_control_unit_r),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam r2_pin_out.operation_mode = "output";
+// @6:44
+  stratix_io r1_pin_out (
+	.padio(r1_pin),
+	.datain(vga_control_unit_r),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam r1_pin_out.operation_mode = "output";
+// @6:44
+  stratix_io r0_pin_out (
+	.padio(r0_pin),
+	.datain(vga_control_unit_r),
+	.oe(VCC),
+	.outclk(GND),
+	.outclkena(VCC),
+	.inclk(GND),
+	.inclkena(VCC),
+	.areset(GND),
+	.sreset(GND)
+);
+defparam r0_pin_out.operation_mode = "output";
+//@6:41
+// @10:161
+  vga_driver vga_driver_unit (
+	.line_counter_sig_0(vga_driver_unit_line_counter_sig[0]),
+	.line_counter_sig_1(vga_driver_unit_line_counter_sig[1]),
+	.line_counter_sig_2(vga_driver_unit_line_counter_sig[2]),
+	.line_counter_sig_3(vga_driver_unit_line_counter_sig[3]),
+	.line_counter_sig_4(vga_driver_unit_line_counter_sig[4]),
+	.line_counter_sig_5(vga_driver_unit_line_counter_sig[5]),
+	.line_counter_sig_6(vga_driver_unit_line_counter_sig[6]),
+	.line_counter_sig_7(vga_driver_unit_line_counter_sig[7]),
+	.line_counter_sig_8(vga_driver_unit_line_counter_sig[8]),
+	.dly_counter_1(dly_counter[1]),
+	.dly_counter_0(dly_counter[0]),
+	.vsync_state_2(vga_driver_unit_vsync_state[2]),
+	.vsync_state_5(vga_driver_unit_vsync_state[5]),
+	.vsync_state_3(vga_driver_unit_vsync_state[3]),
+	.vsync_state_6(vga_driver_unit_vsync_state[6]),
+	.vsync_state_4(vga_driver_unit_vsync_state[4]),
+	.vsync_state_1(vga_driver_unit_vsync_state[1]),
+	.vsync_state_0(vga_driver_unit_vsync_state[0]),
+	.hsync_state_2(vga_driver_unit_hsync_state[2]),
+	.hsync_state_4(vga_driver_unit_hsync_state[4]),
+	.hsync_state_0(vga_driver_unit_hsync_state[0]),
+	.hsync_state_5(vga_driver_unit_hsync_state[5]),
+	.hsync_state_1(vga_driver_unit_hsync_state[1]),
+	.hsync_state_3(vga_driver_unit_hsync_state[3]),
+	.hsync_state_6(vga_driver_unit_hsync_state[6]),
+	.column_counter_sig_0(vga_driver_unit_column_counter_sig[0]),
+	.column_counter_sig_1(vga_driver_unit_column_counter_sig[1]),
+	.column_counter_sig_2(vga_driver_unit_column_counter_sig[2]),
+	.column_counter_sig_3(vga_driver_unit_column_counter_sig[3]),
+	.column_counter_sig_4(vga_driver_unit_column_counter_sig[4]),
+	.column_counter_sig_5(vga_driver_unit_column_counter_sig[5]),
+	.column_counter_sig_6(vga_driver_unit_column_counter_sig[6]),
+	.column_counter_sig_7(vga_driver_unit_column_counter_sig[7]),
+	.column_counter_sig_8(vga_driver_unit_column_counter_sig[8]),
+	.column_counter_sig_9(vga_driver_unit_column_counter_sig[9]),
+	.vsync_counter_9(vga_driver_unit_vsync_counter[9]),
+	.vsync_counter_8(vga_driver_unit_vsync_counter[8]),
+	.vsync_counter_7(vga_driver_unit_vsync_counter[7]),
+	.vsync_counter_6(vga_driver_unit_vsync_counter[6]),
+	.vsync_counter_5(vga_driver_unit_vsync_counter[5]),
+	.vsync_counter_4(vga_driver_unit_vsync_counter[4]),
+	.vsync_counter_3(vga_driver_unit_vsync_counter[3]),
+	.vsync_counter_2(vga_driver_unit_vsync_counter[2]),
+	.vsync_counter_1(vga_driver_unit_vsync_counter[1]),
+	.vsync_counter_0(vga_driver_unit_vsync_counter[0]),
+	.hsync_counter_9(vga_driver_unit_hsync_counter[9]),
+	.hsync_counter_8(vga_driver_unit_hsync_counter[8]),
+	.hsync_counter_7(vga_driver_unit_hsync_counter[7]),
+	.hsync_counter_6(vga_driver_unit_hsync_counter[6]),
+	.hsync_counter_5(vga_driver_unit_hsync_counter[5]),
+	.hsync_counter_4(vga_driver_unit_hsync_counter[4]),
+	.hsync_counter_3(vga_driver_unit_hsync_counter[3]),
+	.hsync_counter_2(vga_driver_unit_hsync_counter[2]),
+	.hsync_counter_1(vga_driver_unit_hsync_counter[1]),
+	.hsync_counter_0(vga_driver_unit_hsync_counter[0]),
+	.d_set_vsync_counter(vga_driver_unit_d_set_vsync_counter),
+	.v_sync(vga_driver_unit_v_sync),
+	.h_sync(vga_driver_unit_h_sync),
+	.h_enable_sig(vga_driver_unit_h_enable_sig),
+	.v_enable_sig(vga_driver_unit_v_enable_sig),
+	.reset_pin_c(reset_pin_c),
+	.un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
+	.d_set_hsync_counter(vga_driver_unit_d_set_hsync_counter),
+	.clk_pin_c(G_33)
+);
+// @10:186
+  vga_control vga_control_unit (
+	.line_counter_sig_0(vga_driver_unit_line_counter_sig[0]),
+	.line_counter_sig_2(vga_driver_unit_line_counter_sig[2]),
+	.line_counter_sig_1(vga_driver_unit_line_counter_sig[1]),
+	.line_counter_sig_3(vga_driver_unit_line_counter_sig[3]),
+	.line_counter_sig_6(vga_driver_unit_line_counter_sig[6]),
+	.line_counter_sig_5(vga_driver_unit_line_counter_sig[5]),
+	.line_counter_sig_4(vga_driver_unit_line_counter_sig[4]),
+	.line_counter_sig_7(vga_driver_unit_line_counter_sig[7]),
+	.line_counter_sig_8(vga_driver_unit_line_counter_sig[8]),
+	.column_counter_sig_0(vga_driver_unit_column_counter_sig[0]),
+	.column_counter_sig_1(vga_driver_unit_column_counter_sig[1]),
+	.column_counter_sig_2(vga_driver_unit_column_counter_sig[2]),
+	.column_counter_sig_8(vga_driver_unit_column_counter_sig[8]),
+	.column_counter_sig_3(vga_driver_unit_column_counter_sig[3]),
+	.column_counter_sig_5(vga_driver_unit_column_counter_sig[5]),
+	.column_counter_sig_4(vga_driver_unit_column_counter_sig[4]),
+	.column_counter_sig_9(vga_driver_unit_column_counter_sig[9]),
+	.column_counter_sig_7(vga_driver_unit_column_counter_sig[7]),
+	.column_counter_sig_6(vga_driver_unit_column_counter_sig[6]),
+	.toggle_counter_sig_0(vga_control_unit_toggle_counter_sig[0]),
+	.toggle_counter_sig_1(vga_control_unit_toggle_counter_sig[1]),
+	.toggle_counter_sig_2(vga_control_unit_toggle_counter_sig[2]),
+	.toggle_counter_sig_3(vga_control_unit_toggle_counter_sig[3]),
+	.toggle_counter_sig_4(vga_control_unit_toggle_counter_sig[4]),
+	.toggle_counter_sig_5(vga_control_unit_toggle_counter_sig[5]),
+	.toggle_counter_sig_6(vga_control_unit_toggle_counter_sig[6]),
+	.toggle_counter_sig_7(vga_control_unit_toggle_counter_sig[7]),
+	.toggle_counter_sig_8(vga_control_unit_toggle_counter_sig[8]),
+	.toggle_counter_sig_9(vga_control_unit_toggle_counter_sig[9]),
+	.toggle_counter_sig_10(vga_control_unit_toggle_counter_sig[10]),
+	.toggle_counter_sig_11(vga_control_unit_toggle_counter_sig[11]),
+	.toggle_counter_sig_12(vga_control_unit_toggle_counter_sig[12]),
+	.toggle_counter_sig_13(vga_control_unit_toggle_counter_sig[13]),
+	.toggle_counter_sig_14(vga_control_unit_toggle_counter_sig[14]),
+	.toggle_counter_sig_15(vga_control_unit_toggle_counter_sig[15]),
+	.toggle_counter_sig_16(vga_control_unit_toggle_counter_sig[16]),
+	.toggle_counter_sig_17(vga_control_unit_toggle_counter_sig[17]),
+	.toggle_counter_sig_18(vga_control_unit_toggle_counter_sig[18]),
+	.toggle_counter_sig_19(vga_control_unit_toggle_counter_sig[19]),
+	.toggle_counter_sig_20(vga_control_unit_toggle_counter_sig[20]),
+	.toggle_counter_sig_21(vga_control_unit_toggle_counter_sig[21]),
+	.toggle_counter_sig_22(vga_control_unit_toggle_counter_sig[22]),
+	.toggle_counter_sig_23(vga_control_unit_toggle_counter_sig[23]),
+	.toggle_counter_sig_24(vga_control_unit_toggle_counter_sig[24]),
+	.h_enable_sig(vga_driver_unit_h_enable_sig),
+	.g(vga_control_unit_g),
+	.b(vga_control_unit_b),
+	.v_enable_sig(vga_driver_unit_v_enable_sig),
+	.r(vga_control_unit_r),
+	.toggle_sig(vga_control_unit_toggle_sig),
+	.un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
+	.clk_pin_c(G_33)
+);
+endmodule /* vga */
+
diff --git a/bsp2/Designflow/syn/rev_1/vga.xrf b/bsp2/Designflow/syn/rev_1/vga.xrf
new file mode 100644
index 0000000..330b87d
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga.xrf
@@ -0,0 +1,343 @@
+vendor_name = Synplicity
+source_file = 0, noname, synplify
+source_file = 1, /opt/synplify/fpga_c200906/lib/vhd/std.vhd, synplify
+source_file = 2, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd, synplify
+source_file = 3, /opt/synplify/fpga_c200906/lib/vhd/std1164.vhd, synplify
+source_file = 4, /opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd, synplify
+source_file = 5, /opt/synplify/fpga_c200906/lib/vhd/arith.vhd, synplify
+source_file = 6, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd, synplify
+source_file = 7, /homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd, synplify
+source_file = 8, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd, synplify
+source_file = 9, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd, synplify
+source_file = 10, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd, synplify
+source_file = 11, /homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd, synplify
+source_file = 12, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd, synplify
+source_file = 13, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd, synplify
+design_name=vga
+instance = port, clk_pin, , vga, 6, 41:7:41:13
+instance = port, reset_pin, , vga, 6, 42:7:42:15
+instance = port, r0_pin, , vga, 6, 44:7:44:12
+instance = port, r1_pin, , vga, 6, 44:15:44:20
+instance = port, r2_pin, , vga, 6, 44:23:44:28
+instance = port, g0_pin, , vga, 6, 45:7:45:12
+instance = port, g1_pin, , vga, 6, 45:15:45:20
+instance = port, g2_pin, , vga, 6, 45:23:45:28
+instance = port, b0_pin, , vga, 6, 46:7:46:12
+instance = port, b1_pin, , vga, 6, 46:15:46:20
+instance = port, hsync_pin, , vga, 6, 47:7:47:15
+instance = port, vsync_pin, , vga, 6, 48:7:48:15
+instance = port, seven_seg_pin[13:0], , vga, 6, 50:7:50:19
+instance = port, d_hsync, , vga, 6, 52:7:52:13
+instance = port, d_vsync, , vga, 6, 52:16:52:22
+instance = port, d_column_counter[9:0], , vga, 6, 53:7:53:22
+instance = port, d_line_counter[8:0], , vga, 6, 54:7:54:20
+instance = port, d_set_column_counter, , vga, 6, 55:7:55:26
+instance = port, d_set_line_counter, , vga, 6, 55:29:55:46
+instance = port, d_hsync_counter[9:0], , vga, 6, 56:7:56:21
+instance = port, d_vsync_counter[9:0], , vga, 6, 57:7:57:21
+instance = port, d_set_hsync_counter, , vga, 6, 58:7:58:25
+instance = port, d_set_vsync_counter, , vga, 6, 58:28:58:46
+instance = port, d_h_enable, , vga, 6, 59:7:59:16
+instance = port, d_v_enable, , vga, 6, 60:7:60:16
+instance = port, d_r, , vga, 6, 61:7:61:9
+instance = port, d_g, , vga, 6, 61:12:61:14
+instance = port, d_b, , vga, 6, 61:17:61:19
+instance = port, d_hsync_state[0:6], , vga, 6, 62:7:62:19
+instance = port, d_vsync_state[0:6], , vga, 6, 63:7:63:19
+instance = port, d_state_clk, , vga, 6, 64:7:64:17
+instance = port, d_toggle, , vga, 6, 65:7:65:14
+instance = port, d_toggle_counter[24:0], , vga, 6, 66:7:66:22
+instance = comp, dly_counter_1_, , vga, 10, 113:4:113:5
+instance = comp, dly_counter_0_, , vga, 10, 113:4:113:5
+instance = comp, reset_pin_in, , vga, 6, 42:7:42:15
+instance = comp, clk_pin_in, , vga, 6, 41:7:41:13
+instance = comp, d_toggle_counter_out_24_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_23_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_22_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_21_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_20_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_19_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_18_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_17_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_16_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_15_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_14_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_13_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_12_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_11_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_10_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_9_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_8_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_7_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_6_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_5_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_4_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_3_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_2_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_1_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_0_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_out, , vga, 6, 65:7:65:14
+instance = comp, d_state_clk_out, , vga, 6, 64:7:64:17
+instance = comp, d_vsync_state_out_0_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_1_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_2_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_3_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_4_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_5_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_6_, , vga, 6, 63:7:63:19
+instance = comp, d_hsync_state_out_0_, , vga, 6, 62:7:62:19
+instance = comp, d_hsync_state_out_1_, , vga, 6, 62:7:62:19
+instance = comp, d_hsync_state_out_2_, , vga, 6, 62:7:62:19
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+instance = comp, d_g_out, , vga, 6, 61:12:61:14
+instance = comp, d_r_out, , vga, 6, 61:7:61:9
+instance = comp, d_v_enable_out, , vga, 6, 60:7:60:16
+instance = comp, d_h_enable_out, , vga, 6, 59:7:59:16
+instance = comp, d_set_vsync_counter_out, , vga, 6, 58:28:58:46
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+instance = comp, seven_seg_pin_tri_13_, , vga, 6, 50:7:50:19
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+instance = comp, b_Z, , vga_control, 12, 60:4:60:5
+instance = comp, g_Z, , vga_control, 12, 60:4:60:5
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+instance = comp, b_next_0_sqmuxa_7_5_cZ, , vga_control, 12, 75:10:76:60
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+instance = comp, BLINKER_next_un1_toggle_counter_siglto15, , vga_control, 12, 111:7:111:38
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+instance = comp, BLINKER_next_un1_toggle_counter_siglto12, , vga_control, 12, 111:7:111:38
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+instance = comp, line_counter_sig_4_, , vga_driver, 13, 125:4:125:5
+instance = comp, line_counter_sig_3_, , vga_driver, 13, 125:4:125:5
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+instance = comp, line_counter_sig_1_, , vga_driver, 13, 125:4:125:5
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+instance = comp, v_enable_sig_Z, , vga_driver, 13, 187:4:187:5
+instance = comp, h_enable_sig_Z, , vga_driver, 13, 300:4:300:5
+instance = comp, h_sync_Z, , vga_driver, 13, 187:4:187:5
+instance = comp, v_sync_Z, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_5_, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_4_, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_3_, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_2_, , vga_driver, 13, 300:4:300:5
+instance = comp, hsync_state_5_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_4_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_3_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_2_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_1_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_0_, , vga_driver, 13, 187:4:187:5
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+instance = comp, un1_vsync_state_next_1_sqmuxa_0_cZ, , vga_driver, 13, 319:4:319:7
+instance = comp, LINE_COUNT_next_un10_line_counter_siglto8, , vga_driver, 13, 139:9:139:40
+instance = comp, G_2, , vga_driver, 10, 161:0:161:14
+instance = comp, vsync_state_next_1_sqmuxa_1_cZ, , vga_driver, 13, 326:11:326:32
+instance = comp, vsync_state_next_1_sqmuxa_2_cZ, , vga_driver, 13, 331:11:331:33
+instance = comp, vsync_state_next_1_sqmuxa_3_cZ, , vga_driver, 13, 339:11:339:34
+instance = comp, G_16, , vga_driver, 10, 161:0:161:14
+instance = comp, COLUMN_COUNT_next_un10_column_counter_siglto9, , vga_driver, 13, 111:9:111:41
+instance = comp, hsync_state_next_1_sqmuxa_2_cZ, , vga_driver, 13, 218:11:218:33
+instance = comp, hsync_state_next_1_sqmuxa_1_cZ, , vga_driver, 13, 213:11:213:32
+instance = comp, HSYNC_FSM_next_un13_hsync_counter, , vga_driver, 13, 231:11:231:32
+instance = comp, HSYNC_COUNT_next_un9_hsync_counterlt9, , vga_driver, 13, 172:9:172:36
+instance = comp, VSYNC_COUNT_next_un9_vsync_counterlt9, , vga_driver, 13, 281:9:281:36
+instance = comp, HSYNC_FSM_next_un12_hsync_counter, , vga_driver, 13, 226:11:226:34
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+instance = comp, VSYNC_FSM_next_un15_vsync_counter_4, , vga_driver, 13, 344:11:344:32
+instance = comp, VSYNC_FSM_next_un13_vsync_counter_4, , vga_driver, 13, 331:11:331:33
+instance = comp, COLUMN_COUNT_next_un10_column_counter_siglt6, , vga_driver, 13, 111:9:111:41
+instance = comp, hsync_counter_next_1_sqmuxa_cZ, , vga_driver, 13, 169:7:169:32
+instance = comp, VSYNC_FSM_next_un14_vsync_counter_8, , vga_driver, 13, 339:11:339:34
+instance = comp, line_counter_next_0_sqmuxa_1_1_cZ, , vga_driver, 13, 139:9:139:40
+instance = comp, vsync_counter_next_1_sqmuxa_cZ, , vga_driver, 13, 278:7:278:32
+instance = comp, column_counter_next_0_sqmuxa_1_1_cZ, , vga_driver, 13, 111:9:111:41
+instance = comp, HSYNC_FSM_next_un12_hsync_counter_4, , vga_driver, 13, 226:11:226:34
+instance = comp, HSYNC_FSM_next_un12_hsync_counter_3, , vga_driver, 13, 226:11:226:34
+instance = comp, HSYNC_FSM_next_un11_hsync_counter_3, , vga_driver, 13, 218:11:218:33
+instance = comp, HSYNC_FSM_next_un11_hsync_counter_2, , vga_driver, 13, 218:11:218:33
+instance = comp, HSYNC_COUNT_next_un9_hsync_counterlt9_3, , vga_driver, 13, 172:9:172:36
+instance = comp, HSYNC_FSM_next_un13_hsync_counter_2, , vga_driver, 13, 231:11:231:32
+instance = comp, VSYNC_COUNT_next_un9_vsync_counterlt9_6, , vga_driver, 13, 281:9:281:36
+instance = comp, VSYNC_COUNT_next_un9_vsync_counterlt9_5, , vga_driver, 13, 281:9:281:36
+instance = comp, HSYNC_FSM_next_un10_hsync_counter_4, , vga_driver, 13, 213:11:213:32
+instance = comp, HSYNC_FSM_next_un10_hsync_counter_3, , vga_driver, 13, 213:11:213:32
+instance = comp, VSYNC_FSM_next_un15_vsync_counter_3, , vga_driver, 13, 344:11:344:32
+instance = comp, VSYNC_FSM_next_un13_vsync_counter_3, , vga_driver, 13, 331:11:331:33
+instance = comp, COLUMN_COUNT_next_un10_column_counter_siglt6_4, , vga_driver, 13, 111:9:111:41
+instance = comp, LINE_COUNT_next_un10_line_counter_siglt4_2, , vga_driver, 13, 139:9:139:40
+instance = comp, HSYNC_FSM_next_un10_hsync_counter_1, , vga_driver, 13, 213:11:213:32
+instance = comp, VSYNC_FSM_next_un12_vsync_counter_6, , vga_driver, 13, 326:11:326:32
+instance = comp, VSYNC_FSM_next_un12_vsync_counter_7, , vga_driver, 13, 326:11:326:32
+instance = comp, HSYNC_FSM_next_un13_hsync_counter_7, , vga_driver, 13, 231:11:231:32
+instance = comp, un1_hsync_state_3_0_cZ, , vga_driver, 13, 206:4:206:7
+instance = comp, un1_vsync_state_2_0_cZ, , vga_driver, 13, 319:4:319:7
+instance = comp, d_set_hsync_counter_cZ, , vga_driver, 13, 248:4:248:7
+instance = comp, d_set_vsync_counter_cZ, , vga_driver, 13, 361:4:361:7
+instance = comp, un1_line_counter_sig_9_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_8_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_7_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_6_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_5_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_4_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_3_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_2_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_a_1_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_1_, , vga_driver, 13, 141:31:141:52
+instance = comp, un2_column_counter_next_9_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_8_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_7_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_6_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_5_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_4_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_3_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_2_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_1_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_0_, , vga_driver, 13, 112:31:112:54
diff --git a/bsp2/Designflow/syn/rev_1/vga_cons.tcl b/bsp2/Designflow/syn/rev_1/vga_cons.tcl
new file mode 100644
index 0000000..43fc06f
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga_cons.tcl
@@ -0,0 +1,6 @@
+source "/opt/synplify/fpga_c200906/lib/altera/quartus_cons.tcl"
+syn_create_and_open_prj vga
+source $::quartus(binpath)/prj_asd_import.tcl
+syn_create_and_open_csf vga
+syn_handle_cons vga
+syn_compile_quartus
diff --git a/bsp2/Designflow/syn/rev_1/vga_rm.tcl b/bsp2/Designflow/syn/rev_1/vga_rm.tcl
new file mode 100644
index 0000000..b20c77f
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/vga_rm.tcl
@@ -0,0 +1,12 @@
+set_global_assignment -name TOP_LEVEL_ENTITY "|vga" -remove 
+set_global_assignment -name FAMILY -remove 
+set_global_assignment -name TAO_FILE "myresults.tao" -remove
+set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000" -remove 
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON -remove 
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF" -remove 
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF" -remove 
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "OFF" -remove 
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF" -remove 
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF" -remove 
+#set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY" -remove
+create_base_clock clk_pin_setting -fmax 25.175mhz -duty_cycle 50.00 -target clk_pin -disable
diff --git a/bsp2/Designflow/syn/vga.prd b/bsp2/Designflow/syn/vga.prd
new file mode 100644
index 0000000..1040ee9
--- /dev/null
+++ b/bsp2/Designflow/syn/vga.prd
@@ -0,0 +1,13 @@
+#-- Synplicity, Inc.
+#-- Version C-2009.06
+#-- Project file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/vga.prd
+#-- Written on Wed Oct 21 17:34:16 2009
+
+#
+### Watch Implementation type ###
+#
+watch_impl -all
+#
+### Watch Implementation properties ###
+#
+watch_prop -clear
diff --git a/bsp2/Designflow/syn/vga.prj b/bsp2/Designflow/syn/vga.prj
new file mode 100644
index 0000000..60b6f05
--- /dev/null
+++ b/bsp2/Designflow/syn/vga.prj
@@ -0,0 +1,71 @@
+#-- Synplicity, Inc.
+#-- Version C-2009.06
+#-- Project file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/vga.prj
+#-- Written on Wed Oct 21 17:34:16 2009
+
+
+#project files
+add_file -vhdl -lib work "../src/vga_pak.vhd"
+add_file -vhdl -lib work "../src/vga_ent.vhd"
+add_file -vhdl -lib work "../src/vga_arc.vhd"
+add_file -vhdl -lib work "../src/board_driver_ent.vhd"
+add_file -vhdl -lib work "../src/board_driver_arc.vhd"
+add_file -vhdl -lib work "../src/vga_control_ent.vhd"
+add_file -vhdl -lib work "../src/vga_control_arc.vhd"
+add_file -vhdl -lib work "../src/vga_driver_ent.vhd"
+add_file -vhdl -lib work "../src/vga_driver_arc.vhd"
+
+
+#implementation: "rev_1"
+impl -add rev_1 -type fpga
+
+#device options
+set_option -technology STRATIX
+set_option -part EP1S25
+set_option -package FC672
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "vga"
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# mapper_options
+set_option -frequency 25.175
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# Altera STRATIX
+set_option -run_prop_extract 1
+set_option -maxfan 500
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -quartus_version 9.0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./rev_1/vga.vqm"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "rev_1"
diff --git a/bsp2/transcript b/bsp2/transcript
new file mode 100644
index 0000000..c9be072
--- /dev/null
+++ b/bsp2/transcript
@@ -0,0 +1,13 @@
+# //  ModelSim SE 6.5b May 21 2009 Linux 2.6.18-128.2.1.el5
+# //
+# //  Copyright 1991-2009 Mentor Graphics Corporation
+# //              All Rights Reserved.
+# //
+# //  THIS WORK CONTAINS TRADE SECRET AND 
+# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
+# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
+# //  AND IS SUBJECT TO LICENSE TERMS.
+# //
+vmap -del stratix
+# ** Error: (vmap-20) Cannot access for writing file "/opt/modelsim/modeltech/linux/../modelsim.ini".
+# Permission denied. (errno = EACCES)
-- 
2.25.1