From: Bernhard Urban Date: Thu, 15 Oct 2009 18:05:21 +0000 (+0200) Subject: init aus gzip X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=commitdiff_plain;h=9eebf9222d8c3be13db2fbec66839a2be5260e56 init aus gzip --- 9eebf9222d8c3be13db2fbec66839a2be5260e56 diff --git a/bsp1/Angabe/dide_16.sof b/bsp1/Angabe/dide_16.sof new file mode 100644 index 0000000..db16564 Binary files /dev/null and b/bsp1/Angabe/dide_16.sof differ diff --git a/bsp1/Angabe/dide_16_1.txt b/bsp1/Angabe/dide_16_1.txt new file mode 100644 index 0000000..a696cc9 --- /dev/null +++ b/bsp1/Angabe/dide_16_1.txt @@ -0,0 +1 @@ +Koordinaten: (x,y) = (317,148) diff --git a/bsp1/Protokolle/DigitalDesign_prot.sty b/bsp1/Protokolle/DigitalDesign_prot.sty new file mode 100644 index 0000000..6cb3c1c --- /dev/null +++ b/bsp1/Protokolle/DigitalDesign_prot.sty @@ -0,0 +1,225 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% DigitalDesign_app.sty +% +% Babak Rahbaran +% (rahbaran@ecs.tuwien.ac.at) +% +% 14.07.03 +% +% Institut f"ur Technische Informatik (182/2) +% ECS Group +% Technische Universit"at Wien +% 1040 Treitlstr. 3, 2. Stk. +% (www.ecs.tuwien.ac.at) +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% packages +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\usepackage{fancyheadings} +\usepackage{german} +\usepackage{graphicx} +\usepackage[latin1]{inputenc} %------- Umlaute im Text + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% user-defined commands +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% typeset pin numbers +\newcommand{\pin}[1]{\emph{\textbf{#1}}\ } +\renewcommand{\chaptername}{Aufgabe} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% some size definitions and counter settings +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\oddsidemargin 1cm +\evensidemargin 1cm +\topmargin 0pt +\headsep 50pt +\textheight 21.5cm +\textwidth 14.1cm + +\renewcommand{\floatpagefraction}{0.9} +\renewcommand{\textfraction}{0.05} +\renewcommand{\topfraction}{1.0} +\renewcommand{\bottomfraction}{1.0} + +\setcounter{totalnumber}{3} +\setcounter{bottomnumber}{3} +\setcounter{topnumber}{3} + +\setlength{\unitlength}{1mm} +\setlength{\parindent}{6mm} +\setlength{\parskip}{12pt plus2pt minus2pt} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% define variables used on titlepage +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% heading +\def\headline#1{\gdef\@headline{#1}} +% group number +\def\groupnr#1{\gdef\@groupnr{#1}} +% authors +\def\vornamea#1{\gdef\@vornamea{#1}} +\def\nachnamea#1{\gdef\@nachnamea{#1}} +\def\matrikela#1{\gdef\@matrikela{#1}} +\def\emaila#1{\gdef\@emaila{#1}} + +\def\vornameb#1{\gdef\@vornameb{#1}} +\def\nachnameb#1{\gdef\@nachnameb{#1}} +\def\matrikelb#1{\gdef\@matrikelb{#1}} +\def\emailb#1{\gdef\@emailb{#1}} + +\def\vornamec#1{\gdef\@vornamec{#1}} +\def\nachnamec#1{\gdef\@nachnamec{#1}} +\def\matrikelc#1{\gdef\@matrikelc{#1}} +\def\emailc#1{\gdef\@emailc{#1}} + +%\def\vornamed#1{\gdef\@vornamed{#1}} +%\def\nachnamed#1{\gdef\@nachnamed{#1}} +%\def\matrikeld#1{\gdef\@matrikeld{#1}} +%\def\emaild#1{\gdef\@emaild{#1}} + +% address of department +\def\address#1{\gdef\@address{#1}} +% LVA-Nr. +\def\lvanr#1{\gdef\@aufgabe{#1}} + +\setcounter{footnote}{0} + +% initialize variables +\gdef\@headline{Digital Design LU} +\gdef\@title{P r o t o k o l l} + +\gdef\@groupnr{00} + +\gdef\@vornamea{Vorname1} +\gdef\@nachnamea{Nachname1} +\gdef\@matrikela{0000000} +\gdef\@emaila{a@æstudent.tuwien.ac.at} + +\gdef\@vornameb{Vorname2} +\gdef\@nachnameb{Nachname2} +\gdef\@matrikelb{0000000} +\gdef\@emailb{b@æstudent.tuwien.ac.at} + +\gdef\@vornamec{Vorname3} +\gdef\@nachnamec{Nachname3} +\gdef\@matrikelc{0000000} +\gdef\@emailc{c@student.tuwien.ac.at} + +%\gdef\@vornamed{Vorname4} +%\gdef\@nachnamed{Nachname4} +%\gdef\@matrikeld{0000000} +%\gdef\@emaild{d@student.tuwien.ac.at} + +\gdef\@aufgabe{zu Aufgabe 1} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% titlepage +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\def\maketitle{ +\begin{titlepage} + +% enlarge page +\setlength{\topmargin}{0pt} +\setlength{\headheight}{0pt} +\setlength{\headsep}{0pt} +\setlength{\footskip}{0pt} + +\let\footnotesize\small \let\footnoterule\relax \setcounter{page}{1} +\null +\vfill +\large +\vskip -4 cm + +\begin{center} +% heading +{\LARGE\bf \@headline \par} \vskip 2cm + +\vskip 1cm + +% title +{\Huge\bf\underline \@title \par} +\vskip 1cm +%{\Large \bf \@aufgabe \par} +\vskip 4cm + +\begin{flushright} +Gruppe \@groupnr \par +% authors +\@vornamea \ \@nachnamea, Matr. Nr. \@matrikela \par +{\small \@emaila \par} +\@vornameb \ \@nachnameb, Matr. Nr. \@matrikelb \par +{\small \@emailb \par} +\@vornamec \ \@nachnamec, Matr. Nr. \@matrikelc \par +{\small \@emailc \par} +%\@vornamed \ \@nachnamed, Matr. Nr. \@matrikeld \par +%{\small \@emaild \par} + +%\@authora \par +%\@authorb \par +%\@authorc \par +%\@authord \par +\vskip 1cm +Wien, am~\today{} +\end{flushright} +\end{center} \par +\vskip 1.5cm + +\end{titlepage} + +\setcounter{footnote}{0} +\let\thanks\relax +} % \def\maketitle + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\newenvironment{Ventry}[1]% +{\begin{list}{}{\renewcommand{\makelabel}[1]{\textbf{##1:}\hfill}% +\settowidth{\labelwidth}{\textbf{#1:}}% +\setlength{\leftmargin}{\labelwidth}% +\addtolength{\leftmargin}{\labelsep}}}% +{\end{list}} + +\newcommand{\tablesize}{\fontsize{8}{10}\selectfont} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% layout of non-title pages +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\pagenumbering{roman} +\setlength{\parskip}{5pt plus2pt minus2pt} + +\setlength{\parskip}{1mm} +\clearpage +\setlength{\parskip}{5pt plus2pt minus2pt} + +\pagestyle{fancy} +\renewcommand{\chaptermark}[1]{\markboth{\thechapter\ #1}{}} +\renewcommand{\sectionmark}[1]{\markright{\thesection\ #1}{}} +\addtolength{\headheight}{2pt} + +\pagenumbering{arabic} +\setcounter{page} {1} diff --git a/bsp1/Protokolle/DigitalDesign_prot.tex b/bsp1/Protokolle/DigitalDesign_prot.tex new file mode 100644 index 0000000..acbdaed --- /dev/null +++ b/bsp1/Protokolle/DigitalDesign_prot.tex @@ -0,0 +1,36 @@ + +\documentclass[12pt,a4paper,titlepage,oneside]{report} + + +\usepackage{DigitalDesign_prot} +\sloppy + + +\begin{document} +% create titlepage +\maketitle + +% tables and lists +%\tableofcontents +%\newpage +%\listoffigures +%\newpage +%\listoftables +%\newpage + +% chapters +\input{chapter1} +\input{chapter2} +\input{chapter3} +\input{chapter4} + +% appendices +%\appendix +%\input{app1} + +% bibliography +%\bibliographystyle{alpha} +%\nocite{*} +%\bibliography{DigitalDesign} + +\end{document} diff --git a/bsp1/Protokolle/chapter1.tex b/bsp1/Protokolle/chapter1.tex new file mode 100644 index 0000000..27f796e --- /dev/null +++ b/bsp1/Protokolle/chapter1.tex @@ -0,0 +1,10 @@ +\chapter{Logikanalysator} + + +\begin{itemize} +\item Frequenz HSYNC = Hz +\item Frequenz VSYNC = Hz +\item Farbe Pixel = (r,g,b) +\item Farbe Hintergrund = (r,g,b) +\item x-Koordinate = +\end{itemize} diff --git a/bsp1/Protokolle/chapter2.tex b/bsp1/Protokolle/chapter2.tex new file mode 100644 index 0000000..a8ddc1a --- /dev/null +++ b/bsp1/Protokolle/chapter2.tex @@ -0,0 +1,6 @@ +\chapter{Design-Flow} + +\begin{itemize} +\item Blinkfrequenz = Hz +\end{itemize} + diff --git a/bsp1/Protokolle/chapter3.tex b/bsp1/Protokolle/chapter3.tex new file mode 100644 index 0000000..c6bbec2 --- /dev/null +++ b/bsp1/Protokolle/chapter3.tex @@ -0,0 +1 @@ +\chapter{VHDL} diff --git a/bsp1/Protokolle/chapter4.tex b/bsp1/Protokolle/chapter4.tex new file mode 100644 index 0000000..4b1b7cc --- /dev/null +++ b/bsp1/Protokolle/chapter4.tex @@ -0,0 +1,13 @@ +\chapter{Simulation und Test} + +\begin{itemize} +\item File Syntaxfehler: +\item Zeilennummer Syntaxfehler: + +\item File Semantikfehler 1: +\item Zeilennummer Semantikfehler 1: + +\item File Semantikfehler 2: +\item Zeilennummer Semantikfehler 2: +\end{itemize} + diff --git a/bsp1/Protokolle/prot_1.txt b/bsp1/Protokolle/prot_1.txt new file mode 100644 index 0000000..91a8a82 --- /dev/null +++ b/bsp1/Protokolle/prot_1.txt @@ -0,0 +1,6 @@ + +Frequenz HSYNC = ___ ___ Hz +Frequenz VSYNC = ___ ___ Hz +Farbe Pixel = (r,g,b) +Farbe Hintergrund = (r,g,b) +x-Koordinate = ___ ___ diff --git a/bsp1/Protokolle/prot_2.txt b/bsp1/Protokolle/prot_2.txt new file mode 100644 index 0000000..da24c18 --- /dev/null +++ b/bsp1/Protokolle/prot_2.txt @@ -0,0 +1 @@ +blinker_max = ___ ___ diff --git a/bsp1/Protokolle/prot_4.txt b/bsp1/Protokolle/prot_4.txt new file mode 100644 index 0000000..d45603d --- /dev/null +++ b/bsp1/Protokolle/prot_4.txt @@ -0,0 +1,9 @@ +File Syntaxfehler: ___ ___ +Zeilennummer Syntaxfehler: ___ ___ + +File Semantikfehler 1: ___ ___ +Zeilennummer Semantikfehler 1: ___ ___ + +File Semantikfehler 2: ___ ___ +Zeilennummer Semantikfehler 2: ___ ___ + diff --git a/bsp2/Angabe/board_driver_arc.vhd b/bsp2/Angabe/board_driver_arc.vhd new file mode 100644 index 0000000..7636a37 --- /dev/null +++ b/bsp2/Angabe/board_driver_arc.vhd @@ -0,0 +1,102 @@ +------------------------------------------------------------------------------- +-- Title : board_driver architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : board_driver.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: display number on 7-segment display +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + + +architecture behav of board_driver is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + + signal display_value : std_logic_vector(2*BCD_WIDTH-1 downto 0); + signal ten_value : std_logic_vector(BCD_WIDTH-1 downto 0); + signal one_value : std_logic_vector(BCD_WIDTH-1 downto 0); + signal digit_left : std_logic_vector(SEG_WIDTH-1 downto 0); + signal digit_right : std_logic_vector(SEG_WIDTH-1 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- generate control data + ----------------------------------------------------------------------------- + + + display_value <= "00000001"; -- vector of two BCD coded numbers to be displayed + one_value <= display_value(BCD_WIDTH-1 downto 0); -- BCD number to be displayed in right digit + ten_value <= display_value(2*BCD_WIDTH-1 downto BCD_WIDTH); -- BCD number to be displayed in left digit + + + SEG_DATA: process(reset, one_value, ten_value) + begin + if (reset = RES_ACT) then -- upon reset + digit_left <= DIGIT_OFF; -- ... switch off display + digit_right <= DIGIT_OFF; + else -- during operation + case one_value is -- ...display "one" position according + when "0000" => digit_right <= DIGIT_ZERO; -- ...to translation table + when "0001" => digit_right <= DIGIT_ONE; + when "0010" => digit_right <= DIGIT_TWO; + when "0011" => digit_right <= DIGIT_THREE; + when "0100" => digit_right <= DIGIT_FOUR; + when "0101" => digit_right <= DIGIT_FIVE; + when "0110" => digit_right <= DIGIT_SIX; + when "0111" => digit_right <= DIGIT_SEVEN; + when "1000" => digit_right <= DIGIT_EIGHT; + when "1001" => digit_right <= DIGIT_NINE; + when others => digit_right <= DIGIT_F; -- use "F" as overflow + end case; + + case ten_value is -- same for "ten" position + when "0000" => digit_left <= DIGIT_ZERO; + when "0001" => digit_left <= DIGIT_ONE; + when "0010" => digit_left <= DIGIT_TWO; + when "0011" => digit_left <= DIGIT_THREE; + when "0100" => digit_left <= DIGIT_FOUR; + when "0101" => digit_left <= DIGIT_FIVE; + when "0110" => digit_left <= DIGIT_SIX; + when "0111" => digit_left <= DIGIT_SEVEN; + when "1000" => digit_left <= DIGIT_EIGHT; + when "1001" => digit_left <= DIGIT_NINE; + when others => digit_left <= DIGIT_F; + end case; + end if; + end process; + + +-- combine the two digits to one bus + seven_seg(SEG_WIDTH-1 downto 0) <= digit_right; + seven_seg(2*SEG_WIDTH-1 downto SEG_WIDTH) <= digit_left; + +end behav; diff --git a/bsp2/Angabe/board_driver_ent.vhd b/bsp2/Angabe/board_driver_ent.vhd new file mode 100644 index 0000000..17e5cf7 --- /dev/null +++ b/bsp2/Angabe/board_driver_ent.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- Title : board_driver entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : board_driver_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: display number on 7-segment display +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + +entity board_driver is + + port ( + reset : in std_logic; + seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0) + ); +end board_driver; diff --git a/bsp2/Angabe/dide_16_2.txt b/bsp2/Angabe/dide_16_2.txt new file mode 100644 index 0000000..29c2cf3 --- /dev/null +++ b/bsp2/Angabe/dide_16_2.txt @@ -0,0 +1 @@ +Periodendauer: 0.12 Sekunden diff --git a/bsp2/Angabe/vga.hex b/bsp2/Angabe/vga.hex new file mode 100644 index 0000000..b3c05bd --- /dev/null +++ b/bsp2/Angabe/vga.hex @@ -0,0 +1,4097 @@ +:010000001ce3 +:010001001ce2 +:010002001ce1 +:010003001ce0 +:010004001cdf +:010005001cde +:010006001cdd +:010007001cdc +:010008001cdb +:010009001cda +:01000a001cd9 +:01000b001cd8 +:01000c001cd7 +:01000d001cd6 +:01000e001cd5 +:01000f001cd4 +:010010001cd3 +:010011001cd2 +:010012001cd1 +:010013001cd0 +:010014001ccf +:010015001cce +:010016001ccd +:010017001ccc +:010018001ccb +:010019001cca +:01001a001cc9 +:01001b001cc8 +:01001c001cc7 +:01001d001cc6 +:01001e001cc5 +:01001f001cc4 +:010020001cc3 +:010021001cc2 +:010022001cc1 +:010023001cc0 +:010024001cbf +:010025001cbe +:010026001cbd +:010027001cbc +:010028001cbb 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+:010fe300e02d +:010fe400e02c +:010fe500e02b +:010fe600e02a +:010fe700e029 +:010fe800e028 +:010fe900e027 +:010fea00e026 +:010feb00e025 +:010fec00e024 +:010fed00e023 +:010fee00e022 +:010fef00e021 +:010ff000e020 +:010ff100e01f +:010ff200e01e +:010ff300e01d +:010ff400e01c +:010ff500e01b +:010ff600e01a +:010ff700e019 +:010ff800e018 +:010ff900e017 +:010ffa00e016 +:010ffb00e015 +:010ffc00e014 +:010ffd00e013 +:010ffe00e012 +:010fff00e011 +:00000001ff diff --git a/bsp2/Angabe/vga_arc.vhd b/bsp2/Angabe/vga_arc.vhd new file mode 100644 index 0000000..3d2d158 --- /dev/null +++ b/bsp2/Angabe/vga_arc.vhd @@ -0,0 +1,223 @@ + ------------------------------------------------------------------------------- +-- Title : vga architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: arch of top level module, the sub-modules are connected here +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; -- include package + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + +------------------------------------------------------------------------------- +-- component declarations for the modules +------------------------------------------------------------------------------- + + component vga_driver + port ( + clk : in std_logic; + reset : in std_logic; + column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : out std_logic; + v_enable : out std_logic; + hsync : out std_logic; + vsync : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter : out std_logic; + d_set_vsync_counter : out std_logic; + d_set_column_counter : out std_logic; + d_set_line_counter : out std_logic); + end component; + + + component vga_control + port ( + clk : in std_logic; + reset : in std_logic; + column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : in std_logic; + v_enable : in std_logic; + toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + toggle : out std_logic; + r, g, b : out std_logic + ); + end component; + + + component board_driver + port ( + reset : in std_logic; + seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0)); + end component; + + +-- declare signals needed for internal wiring of these components later + signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal h_enable_sig : std_logic; + signal v_enable_sig : std_logic; + signal r_sig, g_sig, b_sig : std_logic; + signal hsync_sig, vsync_sig : std_logic; + +-- declare signals needed for prolongation of reset + signal dly_counter : std_logic_vector(1 downto 0); + signal dly_counter_next : std_logic_vector(1 downto 0); + constant MAX_DLY : std_logic_vector(1 downto 0) := "11"; + signal reset_dly : std_logic; -- + signal safe_reset : std_logic; + + +------------------------------------------------------------------------------- +-- prolong duration of reset to prevent glitches at power-up +------------------------------------------------------------------------------- + +begin + + DELAY_RESET_syn : process(clk_pin) -- synchronous capture + begin + if clk_pin'event and clk_pin = '1' then -- upon rising clock + dly_counter <= dly_counter_next; -- ... capture new counter value + end if; + end process; + + DELAY_RESET_next : process(dly_counter, reset_pin) -- next state logic + begin + if reset_pin = RES_ACT then -- upon reset + dly_counter_next <= (others => '0'); -- ...clear dly counter + elsif dly_counter < MAX_DLY then -- if no oflo + dly_counter_next <= dly_counter + '1'; -- ...increment dly counter + else + dly_counter_next <= dly_counter; -- freeze dly counter when oflo + end if; + end process; + + DELAY_RESET_out: process(dly_counter) + begin + if dly_counter < MAX_DLY then -- until dly counter reaches maximum + reset_dly <= RES_ACT; -- ...activate delayed reset signal + else -- upon counter oflo + reset_dly <= not(RES_ACT); -- ...finally deactivate delayed reset + end if; + end process; + + + + COMBINE_RESET: process(reset_pin, reset_dly) -- generate "safe" reset signal + begin + if reset_pin = RES_ACT or reset_dly = RES_ACT then -- ...by combining delayed reset with non-delayed reset input + safe_reset <= RES_ACT; + else + safe_reset <= not(RES_ACT); + end if; + end process; + + +------------------------------------------------------------------------------- +-- instantiate the components and connect to internal and external signals +------------------------------------------------------------------------------- + + +board_driver_unit : board_driver + port map ( + reset => safe_reset, + seven_seg => seven_seg_pin); + + +vga_driver_unit : vga_driver + port map ( + clk => clk_pin, + reset => safe_reset, + column_counter => column_counter_sig, + line_counter => line_counter_sig, + h_enable => h_enable_sig, + v_enable => v_enable_sig, + hsync => hsync_sig, + vsync => vsync_sig, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter); + +-- make the wiring for hsync and vsync pins +-- (pin is output only => internal _sig version required to allow readback of signal) + vsync_pin <= vsync_sig; + hsync_pin <= hsync_sig; + + + vga_control_unit : vga_control + port map ( + clk => clk_pin, + reset => safe_reset, + column_counter => column_counter_sig, + line_counter => line_counter_sig, + h_enable => h_enable_sig, + v_enable => v_enable_sig, + toggle_counter => d_toggle_counter, + toggle => d_toggle, + r => r_sig, + g => g_sig, + b => b_sig); + +-- make the wiring for RGB pins: drive all pins for same color from one source ("8 color mode") + r0_pin <= r_sig; r1_pin <= r_sig; r2_pin <= r_sig; + g0_pin <= g_sig; g1_pin <= g_sig; g2_pin <= g_sig; + b0_pin <= b_sig; b1_pin <= b_sig; + + +-- make extra pin connections for debug signals + d_hsync <= hsync_sig; -- make duplicate of signal for debug connector + d_vsync <= vsync_sig; -- make duplicate of signal for debug connector + d_column_counter <= column_counter_sig; + d_line_counter <= line_counter_sig; + d_h_enable <= h_enable_sig; + d_v_enable <= v_enable_sig; + d_r <= r_sig; + d_g <= g_sig; + d_b <= b_sig; + d_state_clk <= clk_pin; -- make duplicate of signal for debug connector + + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp2/Angabe/vga_beh_tb.vhd b/bsp2/Angabe/vga_beh_tb.vhd new file mode 100644 index 0000000..9530bed --- /dev/null +++ b/bsp2/Angabe/vga_beh_tb.vhd @@ -0,0 +1,194 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_tb is + +end vga_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture behaviour of vga_tb is + + constant cc : time := 39.7 ns; -- test clock period + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : hsync_state_type; + signal d_vsync_state : vsync_state_type; + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk_pin <= '1'; + wait for cc/2; + clk_pin <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk_pin = '1' and clk_pin'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + +end behaviour; + + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_beh of vga_tb is + for behaviour + for vga_unit : vga use entity work.vga(behav); + end for; + end for; +end vga_conf_beh; + + diff --git a/bsp2/Angabe/vga_control_arc.vhd b/bsp2/Angabe/vga_control_arc.vhd new file mode 100644 index 0000000..7f78d72 --- /dev/null +++ b/bsp2/Angabe/vga_control_arc.vhd @@ -0,0 +1,128 @@ +------------------------------------------------------------------------------- +-- Title : vga_control architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga_control is + + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + + -- signal and constant declarations + signal r_next, g_next, b_next : std_logic; -- auxiliary signals for next state logic + signal toggle_sig : std_logic; -- auxiliary signal to allow read back of toggle + signal toggle_counter_sig : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal to allow read back of blinker + signal toggle_next : std_logic; -- auxiliary signal for next state logic + signal toggle_counter_next : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal for next state logic + constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "1100000000010001111011000"; + -- define half period of toggle frequency in clock ticks + +begin + ----------------------------------------------------------------------------- + -- draw rectangle on screen + ----------------------------------------------------------------------------- + + DRAW_SQUARE_syn: process(clk, reset) + begin + if (reset = RES_ACT) then -- draw black screen upon reset + r <= COLR_OFF; + g <= COLR_OFF; + b <= COLR_OFF; + elsif (clk'event and clk = '1') then -- synchronous capture + r <= r_next; + g <= g_next; + b <= b_next; + end if; + end process; + + + DRAW_SQUARE_next: process (column_counter, line_counter, v_enable, h_enable, toggle_sig) + begin + if v_enable = ENABLE and h_enable = ENABLE then + if (column_counter >= X_MIN and column_counter <= X_MAX and -- if pixel within the rectangle borders + line_counter >= Y_MIN and line_counter <= Y_MAX) then + r_next <= toggle_sig; -- ...red + g_next <= COLR_OFF; -- ...green + b_next <= not toggle_sig; -- ...blue + else -- if somewhere else on screen... + r_next <= COLR_OFF; + g_next <= COLR_OFF; -- ... draw background color + b_next <= COLR_OFF; + end if; + else -- if out of screen... + r_next <= COLR_OFF; + g_next <= COLR_OFF; -- ... do not activate any color + b_next <= COLR_OFF; -- (black screen) + end if; + end process; + + + ----------------------------------------------------------------------------- + -- control blinking of rectangle + ----------------------------------------------------------------------------- + + BLINKER_syn: process(clk, reset) + begin + if (reset = RES_ACT) then -- asyn reset + toggle_counter_sig <= (others => '0'); + toggle_sig <= COLR_OFF; + elsif(clk'event and clk = '1') then -- synchronous capture + toggle_counter_sig <= toggle_counter_next; + toggle_sig <= toggle_next; + end if; + end process; + + + BLINKER_next : process(toggle_counter_sig, toggle_sig) + begin + if toggle_counter_sig >= HALFPERIOD then -- after half period ... + toggle_counter_next <= (others => '0'); -- ... clear counter + toggle_next <= not(toggle_sig); -- ... and toggle colour. + else -- before half period ... + toggle_counter_next <= toggle_counter_sig + '1'; -- ... increment counter + toggle_next <= toggle_sig; -- ... and hold colour + end if; + end process; + + +-- assign auxiliary signals to module outputs +toggle <= toggle_sig; +toggle_counter <= toggle_counter_sig; + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp2/Angabe/vga_control_ent.vhd b/bsp2/Angabe/vga_control_ent.vhd new file mode 100644 index 0000000..2ff5a0a --- /dev/null +++ b/bsp2/Angabe/vga_control_ent.vhd @@ -0,0 +1,53 @@ +------------------------------------------------------------------------------- +-- Title : vga_control entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + + +entity vga_control is + port(clk : in std_logic; + reset : in std_logic; + column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); + toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + toggle : out std_logic; + line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + v_enable : in std_logic; + h_enable : in std_logic; + r, g, b : out std_logic + ); + +end vga_control; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp2/Angabe/vga_driver_arc.vhd b/bsp2/Angabe/vga_driver_arc.vhd new file mode 100644 index 0000000..1b89ac1 --- /dev/null +++ b/bsp2/Angabe/vga_driver_arc.vhd @@ -0,0 +1,402 @@ +------------------------------------------------------------------------------- +-- Title : vga_driver architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_driver.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-01-24 +------------------------------------------------------------------------------- +-- Description: generate hsync and vsync +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-01-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga_driver is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + constant TIME_A : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100011111"; + constant TIME_B : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0001011010"; + constant TIME_BC : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0010000111"; + constant TIME_BCD : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100000111"; + + constant TIME_O : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000001000"; + constant TIME_P : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000000001"; + constant TIME_PQ : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000100001"; + constant TIME_PQR : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000000001"; + + signal h_sync : std_logic; + signal h_sync_next : std_logic; + + signal hsync_state : hsync_state_type; + signal hsync_state_next : hsync_state_type; + + signal h_enable_sig : std_logic; + signal h_enable_next : std_logic; + + signal set_hsync_counter : std_logic; + signal hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal hsync_counter_next : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + constant HSYN_CNT_MAX : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1111111111"; + + signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal column_counter_next : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal set_column_counter : std_logic; + + signal v_sync : std_logic; + signal v_sync_next : std_logic; + + signal vsync_state : vsync_state_type; + signal vsync_state_next : vsync_state_type; + + signal v_enable_sig : std_logic; + signal v_enable_next : std_logic; + + signal set_vsync_counter : std_logic; + signal vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal vsync_counter_next : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + constant VSYN_CNT_MAX : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1111111111"; + + signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal line_counter_next : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal set_line_counter : std_logic; + + + +begin + +---------------------------------------------------------------------------- +-- Column_Counter [0..639]: calculates column number for next pixel to be displayed +---------------------------------------------------------------------------- + + COLUMN_COUNT_syn: process(clk, reset, column_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + column_counter_sig <= (others => '0'); + else + column_counter_sig <= column_counter_next; -- synchronous capture + end if; + end if; + end process; + + COLUMN_COUNT_next: process(set_column_counter, column_counter_sig) + begin + if set_column_counter = ENABLE then -- reset counter + column_counter_next <= (others => '0'); + else + if column_counter_sig < RIGHT_BORDER then + column_counter_next <= column_counter_sig + '1'; -- increment column + else + column_counter_next <= RIGHT_BORDER; -- ... but do not count beyond right border + end if; + end if; + end process; + +---------------------------------------------------------------------------- +-- Line_counter [0..479]: calculates line number for next pixel to be displayed +---------------------------------------------------------------------------- + + LINE_COUNT_syn: process(clk, reset, line_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + line_counter_sig <= (others => '0'); + else + line_counter_sig <= line_counter_next; -- synchronous capture + end if; + end if; + end process; + + LINE_COUNT_next: process(set_line_counter, line_counter_sig, set_hsync_counter) + begin + if set_line_counter = ENABLE then -- reset counter + line_counter_next <= (others => '0'); + else + if line_counter_sig < BOTTOM_BORDER then + if set_hsync_counter = '1' then -- when enabled + line_counter_next <= line_counter_sig + '1'; -- ... increment line + else + line_counter_next <= line_counter_sig; + end if; + else + line_counter_next <= BOTTOM_BORDER; -- ... but do not count below bottom + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- Hsync_Counter: generates time base for HSYNC State Machine +---------------------------------------------------------------------------- + + HSYNC_COUNT_syn: process(clk, reset, hsync_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + hsync_counter <= (others => '0'); + else + hsync_counter <= hsync_counter_next; -- synchronous capture + end if; + end if; + end process; + + HSYNC_COUNT_next: process(set_hsync_counter, hsync_counter) + begin + if set_hsync_counter = ENABLE then -- reset counter + hsync_counter_next <= (others => '0'); + else + if hsync_counter < HSYN_CNT_MAX then + hsync_counter_next <= hsync_counter + '1'; -- increment time + else + hsync_counter_next <= HSYN_CNT_MAX; -- ... but do not count beyond max period + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- HSYNC STATE MACHINE: generates hsync signal and controls hsync counter & column counter +---------------------------------------------------------------------------- + + HSYNC_FSM_syn: process (clk, reset) -- synchronous capture + begin + if clk'event and clk = '1' then + if reset = RES_ACT then + hsync_state <= RESET_STATE; + h_sync <= '1'; + v_enable_sig <= not(ENABLE); + else + hsync_state <= hsync_state_next; + h_sync <= h_sync_next; + v_enable_sig <= v_enable_next; + end if; + end if; + end process; + + HSYNC_FSM_next : process(hsync_state, hsync_counter, h_sync, v_enable_sig) -- next-state logic + begin -- default assignments + hsync_state_next <= hsync_state; -- ... hold current state + h_sync_next <= h_sync; -- ... and values + v_enable_next <= v_enable_sig; + + case hsync_state is + when RESET_STATE => + h_sync_next <= '0'; -- next signal values are defined here + v_enable_next <= not(ENABLE); + hsync_state_next <= B_STATE; -- ... as well as state transitions + when B_STATE => + h_sync_next <= '0'; + if hsync_counter = TIME_B then + hsync_state_next <= C_STATE; + end if; + when C_STATE => + h_sync_next <= '1'; + if hsync_counter = TIME_BC then + hsync_state_next <= pre_D_STATE; + end if; + when pre_D_STATE => + v_enable_next <= ENABLE; + hsync_state_next <= D_STATE; + when D_STATE => + v_enable_next <= ENABLE; + if hsync_counter = TIME_BCD then + hsync_state_next <= E_STATE; + end if; + when E_STATE => + v_enable_next <= not(ENABLE); + if hsync_counter = TIME_A then + hsync_state_next <= pre_B_STATE; + end if; + when pre_B_STATE => + h_sync_next <= '0'; + v_enable_next <= not(ENABLE); + hsync_state_next <= B_STATE; + when others => + null; + end case; + end process; + + HSYNC_FSM_out : process(hsync_state) -- output logic + begin + set_hsync_counter <= not(ENABLE); -- default assignments + set_column_counter <= not(ENABLE); + + case hsync_state is + when RESET_STATE => -- outputs for each state are defined here + set_hsync_counter <= ENABLE; + when pre_D_STATE => + set_column_counter <= ENABLE; + when pre_B_STATE => + set_hsync_counter <= ENABLE; + when others => + null; + end case; + end process; + + +---------------------------------------------------------------------------- +-- Vsync_Counter: generates time base for VSYNC State Machine +---------------------------------------------------------------------------- + + VSYNC_COUNT_syn: process(clk, reset, vsync_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + vsync_counter <= (others => '0'); + else + vsync_counter <= vsync_counter_next; -- synchronous capture + end if; + end if; + end process; + + VSYNC_COUNT_next: process(set_vsync_counter, vsync_counter, set_hsync_counter) + begin + if set_vsync_counter = ENABLE then -- reset counter + vsync_counter_next <= (others => '0'); + else + if vsync_counter < VSYN_CNT_MAX then + if set_hsync_counter = '1' then -- if enabled + vsync_counter_next <= vsync_counter + '1'; -- ... increment time + else + vsync_counter_next <= vsync_counter; + end if; + else + vsync_counter_next <= VSYN_CNT_MAX; -- ... but do not count beyond max period + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- VSYNC STATE MACHINE: generates vsync signal and controls vsync counter & line counter +---------------------------------------------------------------------------- + + VSYNC_FSM_syn : process (clk, reset) -- synchronous capture + begin + if clk'event and clk = '1' then + if reset = RES_ACT then + vsync_state <= RESET_STATE; + v_sync <= '1'; + h_enable_sig <= not(ENABLE); + else + vsync_state <= vsync_state_next; + v_sync <= v_sync_next; + h_enable_sig <= h_enable_next; + end if; + end if; + end process; + + VSYNC_FSM_next : process(vsync_state, vsync_counter, v_sync, h_enable_sig) + begin -- next state logic + vsync_state_next <= vsync_state; -- default assignments + v_sync_next <= v_sync; + h_enable_next <= h_enable_sig; + + case vsync_state is -- state transitions and next signals are defined here + when RESET_STATE => + v_sync_next <= '0'; + h_enable_next <= not(ENABLE); + vsync_state_next <= P_STATE; + when P_STATE => + v_sync_next <= '0'; + if vsync_counter = time_p then + vsync_state_next <= Q_STATE; + end if; + when Q_STATE => + v_sync_next <= '1'; + if vsync_counter = time_pq then + vsync_state_next <= pre_R_STATE; + end if; + when pre_R_STATE => + h_enable_next <= ENABLE; + vsync_state_next <= R_STATE; + when R_STATE => + h_enable_next <= ENABLE; + if vsync_counter = time_pqr then + vsync_state_next <= S_STATE; + end if; + when S_STATE => + h_enable_next <= not(ENABLE); + if vsync_counter = time_o then + vsync_state_next <= pre_P_STATE; + end if; + when pre_P_STATE => + v_sync_next <= '0'; + h_enable_next <= not(ENABLE); + vsync_state_next <= P_STATE; + when others => + null; + end case; + end process; + + VSYNC_FSM_out : process(vsync_state) + begin -- output logic + set_vsync_counter <= not(ENABLE); -- output values for each state defined here + set_line_counter <= not(ENABLE); + + case vsync_state is + when RESET_STATE => + set_vsync_counter <= ENABLE; + when pre_R_STATE => + set_line_counter <= ENABLE; + when pre_P_STATE => + set_vsync_counter <= ENABLE; + when others => + null; + end case; + end process; + + + +-- signal wiring for entity (introduced _sig to allow readback of output signals) + + column_counter <= column_counter_sig; + v_enable <= v_enable_sig; + line_counter <= line_counter_sig; + h_enable <= h_enable_sig; + + + hsync <= h_sync; + vsync <= v_sync; + + ----------------------------------------------------------------------------- + -- debug signals + ----------------------------------------------------------------------------- + d_hsync_state <= hsync_state; + d_vsync_state <= vsync_state; + d_hsync_counter <= hsync_counter; + d_vsync_counter <= vsync_counter; + d_set_hsync_counter <= set_hsync_counter; + d_set_vsync_counter <= set_vsync_counter; + d_set_column_counter <= set_column_counter; + d_set_line_counter <= set_line_counter; + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp2/Angabe/vga_driver_ent.vhd b/bsp2/Angabe/vga_driver_ent.vhd new file mode 100644 index 0000000..f4c00be --- /dev/null +++ b/bsp2/Angabe/vga_driver_ent.vhd @@ -0,0 +1,60 @@ +------------------------------------------------------------------------------- +-- Title : vga_driver entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_driver_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generate vsync and hsync +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + + +entity vga_driver is + port(clk : in std_logic; + reset : in std_logic; + column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : out std_logic; + v_enable : out std_logic; + hsync, vsync : out std_logic; + + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter : out std_logic; + d_set_vsync_counter : out std_logic; + d_set_column_counter : out std_logic; + d_set_line_counter : out std_logic + ); + +end vga_driver; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp2/Angabe/vga_ent.vhd b/bsp2/Angabe/vga_ent.vhd new file mode 100644 index 0000000..a32ebc0 --- /dev/null +++ b/bsp2/Angabe/vga_ent.vhd @@ -0,0 +1,73 @@ +------------------------------------------------------------------------------- +-- Title : vga entitiy +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: entity of top level module, external pins defined here +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + +entity vga is + port( +-- input pins from PCB board + clk_pin : in std_logic; -- clock pin + reset_pin : in std_logic; -- reset pins (from switch) +-- output pins to RGB connector / VGA screen + r0_pin, r1_pin, r2_pin : out std_logic; -- to RGB connector "red" + g0_pin, g1_pin, g2_pin : out std_logic; -- to RGB connector "green" + b0_pin, b1_pin : out std_logic; -- to RGB connector "blue" + hsync_pin : out std_logic; -- to RGB connector "Hsync" + vsync_pin : out std_logic; -- to RGB connector "Vsync" +-- output pins to 7-segment display + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); +-- output pins provided for debugging only / logic analyzer + d_hsync, d_vsync : out std_logic; -- copy of hsync_pin, vsync_pin + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0) + ); + +end vga; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp2/Angabe/vga_pak.vhd b/bsp2/Angabe/vga_pak.vhd new file mode 100644 index 0000000..61c8adf --- /dev/null +++ b/bsp2/Angabe/vga_pak.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------- +-- Title : vga package +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_pak.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-08-19 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: definitions of global constants and enumerated types +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-08-19 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + + +------------------------------------------------------------------------------- +-- PACKAGE +------------------------------------------------------------------------------- + +package vga_pak is + + constant RES_ACT : std_logic := '0'; -- define reset active LO + constant ENABLE : std_logic := '1'; -- define diverse enable HI + constant COLR_ON : std_logic := '1'; -- define VGA color on as HI + constant COLR_OFF : std_logic := '0'; -- define VGA color off as LO + constant SEG_WIDTH : integer := 7; -- display has 7 segments + constant BCD_WIDTH : integer := 4; -- BCD number has 4 bit + constant TOG_CNT_WIDTH : integer := 25; -- bitwidth of counter that controls blinking + + constant COL_CNT_WIDTH : integer := 10; -- width of the column counter + constant LINE_CNT_WIDTH : integer := 9; -- width of the line counter + constant HSYN_CNT_WIDTH : integer := 10; -- width of the h-sync counter + constant VSYN_CNT_WIDTH : integer := 10; -- width of the v-sync counter + + constant RIGHT_BORDER: std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "1001111111"; -- 640 columns (0...639) + constant BOTTOM_BORDER: std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "111011111"; -- 480 lines (0...479) + + -- define coordinates of rectangle + constant X_MIN : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0001100100"; -- 100 + constant X_MAX : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0011001000"; -- 200 + constant Y_MIN : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "001100100"; + constant Y_MAX : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "011001000"; + + -- define emumerated types for state machines + type hsync_state_type is (RESET_STATE, B_STATE, C_STATE, D_STATE, E_STATE, + pre_D_STATE, pre_B_STATE); + type vsync_state_type is (RESET_STATE, P_STATE, Q_STATE, R_STATE, S_STATE, + pre_R_STATE, pre_P_STATE); + + -- Definitions for 7-segment display gfedcba + constant DIGIT_ZERO : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000000"; + constant DIGIT_ONE : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111001"; + constant DIGIT_TWO : std_logic_vector(SEG_WIDTH-1 downto 0) := "0100100"; + constant DIGIT_THREE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110000"; + constant DIGIT_FOUR : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011001"; + constant DIGIT_FIVE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0010010"; + constant DIGIT_SIX : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000010"; + constant DIGIT_SEVEN : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111000"; + constant DIGIT_EIGHT : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000000"; + constant DIGIT_NINE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011000"; + constant DIGIT_MINUS : std_logic_vector(SEG_WIDTH-1 downto 0) := "0111111"; + constant DIGIT_A : std_logic_vector(SEG_WIDTH-1 downto 0) := "0001000"; + constant DIGIT_B : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000011"; + constant DIGIT_C : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110001"; + constant DIGIT_D : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000010"; + constant DIGIT_E : std_logic_vector(SEG_WIDTH-1 downto 0) := "1001111"; + constant DIGIT_F : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000111"; + constant DIGIT_OFF : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111111"; + +end package; diff --git a/bsp2/Angabe/vga_pll.bdf b/bsp2/Angabe/vga_pll.bdf new file mode 100755 index 0000000..906c435 --- /dev/null +++ b/bsp2/Angabe/vga_pll.bdf @@ -0,0 +1,847 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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512)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 200 528)(line_width 1)) + ) +) +(symbol + (rect 416 56 512 152) + (text "vpll" (rect 5 0 22 12)(font "Arial" )) + (text "inst1" (rect 8 80 31 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inclk0" (rect 0 0 28 12)(font "Arial" )) + (text "inclk0" (rect 21 27 49 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 96 32) + (output) + (text "c0" (rect 0 0 11 12)(font "Arial" )) + (text "c0" (rect 64 27 75 39)(font "Arial" )) + (line (pt 96 32)(pt 80 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 80 80)(line_width 1)) + ) +) +(connector + (pt 512 88) + (pt 712 88) +) diff --git a/bsp2/Angabe/vga_pll.tcl b/bsp2/Angabe/vga_pll.tcl new file mode 100755 index 0000000..c260434 --- /dev/null +++ b/bsp2/Angabe/vga_pll.tcl @@ -0,0 +1,184 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: vga_pll.tcl +# Generated on: Fri Sep 29 09:31:24 2006 + +# Load Quartus II Tcl Project package +package require ::quartus::project +package require ::quartus::flow + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "vga_pll"]} { + puts "Project vga_pll is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists vga_pll]} { + project_open -cmp vga_pll vga_pll + } else { + project_new -cmp vga_pll vga_pll + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + catch { set_global_assignment -name FAMILY Stratix } result + catch { set_global_assignment -name DEVICE EP1S25F672C6 } result + catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result + catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result + catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result + catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result + catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result + catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result + catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result + catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result + catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result + catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result + catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result + catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result + + set_location_assignment PIN_E24 -to b0_pin + set_location_assignment PIN_T6 -to b1_pin + set_location_assignment PIN_N3 -to board_clk + set_location_assignment PIN_E23 -to g0_pin + set_location_assignment PIN_T5 -to g1_pin + set_location_assignment PIN_T24 -to g2_pin + set_location_assignment PIN_F1 -to hsync_pin + set_location_assignment PIN_E22 -to r0_pin + set_location_assignment PIN_T4 -to r1_pin + set_location_assignment PIN_T7 -to r2_pin + set_location_assignment PIN_A5 -to reset + set_location_assignment PIN_F2 -to vsync_pin + set_location_assignment PIN_Y5 -to d_hsync_state[0] + set_location_assignment PIN_F19 -to d_hsync_state[1] + set_location_assignment PIN_F17 -to d_hsync_state[2] + set_location_assignment PIN_Y2 -to d_hsync_state[3] + set_location_assignment PIN_F10 -to d_hsync_state[4] + set_location_assignment PIN_F9 -to d_hsync_state[5] + set_location_assignment PIN_F6 -to d_hsync_state[6] + set_location_assignment PIN_H4 -to d_hsync_counter[0] + set_location_assignment PIN_G25 -to d_hsync_counter[7] + set_location_assignment PIN_G22 -to d_hsync_counter[8] + set_location_assignment PIN_G18 -to d_hsync_counter[9] + set_location_assignment PIN_F5 -to d_vsync_state[0] + set_location_assignment PIN_F4 -to d_vsync_state[1] + set_location_assignment PIN_F3 -to d_vsync_state[2] + set_location_assignment PIN_M19 -to d_vsync_state[3] + set_location_assignment PIN_M18 -to d_vsync_state[4] + set_location_assignment PIN_M7 -to d_vsync_state[5] + set_location_assignment PIN_M4 -to d_vsync_state[6] + set_location_assignment PIN_G9 -to d_vsync_counter[0] + set_location_assignment PIN_G6 -to d_vsync_counter[7] + set_location_assignment PIN_G4 -to d_vsync_counter[8] + set_location_assignment PIN_G2 -to d_vsync_counter[9] + set_location_assignment PIN_K6 -to d_line_counter[0] + set_location_assignment PIN_K4 -to d_line_counter[1] + set_location_assignment PIN_J22 -to d_line_counter[2] + set_location_assignment PIN_M9 -to d_line_counter[3] + set_location_assignment PIN_M8 -to d_line_counter[4] + set_location_assignment PIN_M6 -to d_line_counter[5] + set_location_assignment PIN_M5 -to d_line_counter[6] + set_location_assignment PIN_L24 -to d_line_counter[7] + set_location_assignment PIN_L25 -to d_line_counter[8] + set_location_assignment PIN_L23 -to d_column_counter[0] + set_location_assignment PIN_L22 -to d_column_counter[1] + set_location_assignment PIN_L21 -to d_column_counter[2] + set_location_assignment PIN_L20 -to d_column_counter[3] + set_location_assignment PIN_L6 -to d_column_counter[4] + set_location_assignment PIN_L4 -to d_column_counter[5] + set_location_assignment PIN_L2 -to d_column_counter[6] + set_location_assignment PIN_K23 -to d_column_counter[7] + set_location_assignment PIN_K19 -to d_column_counter[8] + set_location_assignment PIN_K5 -to d_column_counter[9] + set_location_assignment PIN_L7 -to d_hsync + set_location_assignment PIN_L5 -to d_vsync + set_location_assignment PIN_F26 -to d_set_hsync_counter + set_location_assignment PIN_F24 -to d_set_vsync_counter + set_location_assignment PIN_F21 -to d_set_line_counter + set_location_assignment PIN_Y23 -to d_set_column_counter + set_location_assignment PIN_L3 -to d_r + set_location_assignment PIN_K24 -to d_g + set_location_assignment PIN_K20 -to d_b + set_location_assignment PIN_H18 -to d_v_enable + set_location_assignment PIN_J21 -to d_h_enable + set_location_assignment PIN_R8 -to seven_seg_pin[0] + set_location_assignment PIN_R9 -to seven_seg_pin[1] + set_location_assignment PIN_R19 -to seven_seg_pin[2] + set_location_assignment PIN_R20 -to seven_seg_pin[3] + set_location_assignment PIN_R21 -to seven_seg_pin[4] + set_location_assignment PIN_R22 -to seven_seg_pin[5] + set_location_assignment PIN_R23 -to seven_seg_pin[6] + set_location_assignment PIN_Y11 -to seven_seg_pin[7] + set_location_assignment PIN_N7 -to seven_seg_pin[8] + set_location_assignment PIN_N8 -to seven_seg_pin[9] + set_location_assignment PIN_R4 -to seven_seg_pin[10] + set_location_assignment PIN_R6 -to seven_seg_pin[11] + set_location_assignment PIN_AA11 -to seven_seg_pin[12] + set_location_assignment PIN_T2 -to seven_seg_pin[13] + set_location_assignment PIN_K3 -to d_state_clk + set_location_assignment PIN_H3 -to d_toggle + set_location_assignment PIN_H26 -to d_toggle_counter[0] + set_location_assignment PIN_G24 -to d_toggle_counter[15] + set_location_assignment PIN_G23 -to d_toggle_counter[16] + set_location_assignment PIN_G21 -to d_toggle_counter[17] + set_location_assignment PIN_G20 -to d_toggle_counter[18] + set_location_assignment PIN_G5 -to d_toggle_counter[19] + set_location_assignment PIN_G3 -to d_toggle_counter[20] + set_location_assignment PIN_G1 -to d_toggle_counter[21] + set_location_assignment PIN_F25 -to d_toggle_counter[22] + set_location_assignment PIN_F23 -to d_toggle_counter[23] + set_location_assignment PIN_T19 -to d_toggle_counter[24] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin + + + # Commit assignments + export_assignments + +execute_flow -compile + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/bsp2/Angabe/vga_pos_tb.vhd b/bsp2/Angabe/vga_pos_tb.vhd new file mode 100644 index 0000000..ebcff70 --- /dev/null +++ b/bsp2/Angabe/vga_pos_tb.vhd @@ -0,0 +1,198 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pos_tb is + +end vga_pos_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pos_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(1000000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pos of vga_pos_tb is + for structure + for vga_unit : vga use entity work.vga(structure); + end for; + end for; +end vga_conf_pos; + + + diff --git a/bsp2/Angabe/vga_pre_tb.vhd b/bsp2/Angabe/vga_pre_tb.vhd new file mode 100644 index 0000000..dc010f7 --- /dev/null +++ b/bsp2/Angabe/vga_pre_tb.vhd @@ -0,0 +1,197 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pre_tb is + +end vga_pre_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pre_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pre of vga_pre_tb is + for structure + for vga_unit : vga use entity work.vga(beh); + end for; + end for; +end vga_conf_pre; + + + diff --git a/bsp2/Angabe/vpll.bsf b/bsp2/Angabe/vpll.bsf new file mode 100644 index 0000000..63c3118 --- /dev/null +++ b/bsp2/Angabe/vpll.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2004 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 112 112) + (text "vpll" (rect 5 0 22 12)(font "Arial" )) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inclk0" (rect 0 0 28 12)(font "Arial" )) + (text "inclk0" (rect 21 27 49 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 96 32) + (output) + (text "c0" (rect 0 0 11 12)(font "Arial" )) + (text "c0" (rect 64 27 75 39)(font "Arial" )) + (line (pt 96 32)(pt 80 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 80 80)(line_width 1)) + ) +) diff --git a/bsp2/Angabe/vpll.vhd b/bsp2/Angabe/vpll.vhd new file mode 100644 index 0000000..dbb347f --- /dev/null +++ b/bsp2/Angabe/vpll.vhd @@ -0,0 +1,274 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: vpll.vhd +-- Megafunction Name(s): +-- altpll +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 4.1 Build 181 06/29/2004 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2004 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY vpll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; +-- pllena : IN STD_LOGIC := '1'; +-- areset : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC +-- locked : OUT STD_LOGIC + ); +END vpll; + + +ARCHITECTURE SYN OF vpll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (3 DOWNTO 0); + +signal pllena_int : std_logic; +signal areset_int : std_logic; +signal locked : std_logic; + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_duty_cycle : NATURAL; + lpm_type : STRING; + clk0_multiply_by : NATURAL; + invalid_lock_multiplier : NATURAL; + inclk0_input_frequency : NATURAL; + gate_lock_signal : STRING; + clk0_divide_by : NATURAL; + pll_type : STRING; + valid_lock_multiplier : NATURAL; + clk0_time_delay : STRING; + spread_frequency : NATURAL; + intended_device_family : STRING; + operation_mode : STRING; + compensate_clock : STRING; + clk0_phase_shift : STRING + ); + PORT ( + clkena : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + pllena : IN STD_LOGIC ; + extclkena : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + locked : OUT STD_LOGIC ; + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire3_bv(0 DOWNTO 0) <= "0"; + sub_wire3 <= To_stdlogicvector(sub_wire3_bv); + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= NOT(To_stdlogicvector(sub_wire5_bv)); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + locked <= sub_wire2; + sub_wire4 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire5(0 DOWNTO 0); + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire3(0 DOWNTO 0) & sub_wire6; + sub_wire8 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0); + +areset_int <= '0'; +pllena_int <= '1'; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_duty_cycle => 50, + lpm_type => "altpll", + clk0_multiply_by => 5435, + invalid_lock_multiplier => 5, + inclk0_input_frequency => 30003, + gate_lock_signal => "NO", + clk0_divide_by => 6666, + pll_type => "AUTO", + valid_lock_multiplier => 1, + clk0_time_delay => "0", + spread_frequency => 0, + intended_device_family => "Stratix", + operation_mode => "NORMAL", + compensate_clock => "CLK0", + clk0_phase_shift => "0" + ) + PORT MAP ( + clkena => sub_wire4, + inclk => sub_wire7, + pllena => pllena_int, + extclkena => sub_wire8, + areset => areset_int, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.175" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix" +-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5435" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6666" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" +-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE FALSE diff --git a/bsp2/Protokolle/DigitalDesign_prot.sty b/bsp2/Protokolle/DigitalDesign_prot.sty new file mode 100644 index 0000000..6cb3c1c --- /dev/null +++ b/bsp2/Protokolle/DigitalDesign_prot.sty @@ -0,0 +1,225 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% DigitalDesign_app.sty +% +% Babak Rahbaran +% (rahbaran@ecs.tuwien.ac.at) +% +% 14.07.03 +% +% Institut f"ur Technische Informatik (182/2) +% ECS Group +% Technische Universit"at Wien +% 1040 Treitlstr. 3, 2. Stk. +% (www.ecs.tuwien.ac.at) +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% packages +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\usepackage{fancyheadings} +\usepackage{german} +\usepackage{graphicx} +\usepackage[latin1]{inputenc} %------- Umlaute im Text + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% user-defined commands +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% typeset pin numbers +\newcommand{\pin}[1]{\emph{\textbf{#1}}\ } +\renewcommand{\chaptername}{Aufgabe} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% some size definitions and counter settings +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\oddsidemargin 1cm +\evensidemargin 1cm +\topmargin 0pt +\headsep 50pt +\textheight 21.5cm +\textwidth 14.1cm + +\renewcommand{\floatpagefraction}{0.9} +\renewcommand{\textfraction}{0.05} +\renewcommand{\topfraction}{1.0} +\renewcommand{\bottomfraction}{1.0} + +\setcounter{totalnumber}{3} +\setcounter{bottomnumber}{3} +\setcounter{topnumber}{3} + +\setlength{\unitlength}{1mm} +\setlength{\parindent}{6mm} +\setlength{\parskip}{12pt plus2pt minus2pt} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% define variables used on titlepage +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% heading +\def\headline#1{\gdef\@headline{#1}} +% group number +\def\groupnr#1{\gdef\@groupnr{#1}} +% authors +\def\vornamea#1{\gdef\@vornamea{#1}} +\def\nachnamea#1{\gdef\@nachnamea{#1}} +\def\matrikela#1{\gdef\@matrikela{#1}} +\def\emaila#1{\gdef\@emaila{#1}} + +\def\vornameb#1{\gdef\@vornameb{#1}} +\def\nachnameb#1{\gdef\@nachnameb{#1}} +\def\matrikelb#1{\gdef\@matrikelb{#1}} +\def\emailb#1{\gdef\@emailb{#1}} + +\def\vornamec#1{\gdef\@vornamec{#1}} +\def\nachnamec#1{\gdef\@nachnamec{#1}} +\def\matrikelc#1{\gdef\@matrikelc{#1}} +\def\emailc#1{\gdef\@emailc{#1}} + +%\def\vornamed#1{\gdef\@vornamed{#1}} +%\def\nachnamed#1{\gdef\@nachnamed{#1}} +%\def\matrikeld#1{\gdef\@matrikeld{#1}} +%\def\emaild#1{\gdef\@emaild{#1}} + +% address of department +\def\address#1{\gdef\@address{#1}} +% LVA-Nr. +\def\lvanr#1{\gdef\@aufgabe{#1}} + +\setcounter{footnote}{0} + +% initialize variables +\gdef\@headline{Digital Design LU} +\gdef\@title{P r o t o k o l l} + +\gdef\@groupnr{00} + +\gdef\@vornamea{Vorname1} +\gdef\@nachnamea{Nachname1} +\gdef\@matrikela{0000000} +\gdef\@emaila{a@æstudent.tuwien.ac.at} + +\gdef\@vornameb{Vorname2} +\gdef\@nachnameb{Nachname2} +\gdef\@matrikelb{0000000} +\gdef\@emailb{b@æstudent.tuwien.ac.at} + +\gdef\@vornamec{Vorname3} +\gdef\@nachnamec{Nachname3} +\gdef\@matrikelc{0000000} +\gdef\@emailc{c@student.tuwien.ac.at} + +%\gdef\@vornamed{Vorname4} +%\gdef\@nachnamed{Nachname4} +%\gdef\@matrikeld{0000000} +%\gdef\@emaild{d@student.tuwien.ac.at} + +\gdef\@aufgabe{zu Aufgabe 1} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% titlepage +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\def\maketitle{ +\begin{titlepage} + +% enlarge page +\setlength{\topmargin}{0pt} +\setlength{\headheight}{0pt} +\setlength{\headsep}{0pt} +\setlength{\footskip}{0pt} + +\let\footnotesize\small \let\footnoterule\relax \setcounter{page}{1} +\null +\vfill +\large +\vskip -4 cm + +\begin{center} +% heading +{\LARGE\bf \@headline \par} \vskip 2cm + +\vskip 1cm + +% title +{\Huge\bf\underline \@title \par} +\vskip 1cm +%{\Large \bf \@aufgabe \par} +\vskip 4cm + +\begin{flushright} +Gruppe \@groupnr \par +% authors +\@vornamea \ \@nachnamea, Matr. Nr. \@matrikela \par +{\small \@emaila \par} +\@vornameb \ \@nachnameb, Matr. Nr. \@matrikelb \par +{\small \@emailb \par} +\@vornamec \ \@nachnamec, Matr. Nr. \@matrikelc \par +{\small \@emailc \par} +%\@vornamed \ \@nachnamed, Matr. Nr. \@matrikeld \par +%{\small \@emaild \par} + +%\@authora \par +%\@authorb \par +%\@authorc \par +%\@authord \par +\vskip 1cm +Wien, am~\today{} +\end{flushright} +\end{center} \par +\vskip 1.5cm + +\end{titlepage} + +\setcounter{footnote}{0} +\let\thanks\relax +} % \def\maketitle + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\newenvironment{Ventry}[1]% +{\begin{list}{}{\renewcommand{\makelabel}[1]{\textbf{##1:}\hfill}% +\settowidth{\labelwidth}{\textbf{#1:}}% +\setlength{\leftmargin}{\labelwidth}% +\addtolength{\leftmargin}{\labelsep}}}% +{\end{list}} + +\newcommand{\tablesize}{\fontsize{8}{10}\selectfont} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% layout of non-title pages +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\pagenumbering{roman} +\setlength{\parskip}{5pt plus2pt minus2pt} + +\setlength{\parskip}{1mm} +\clearpage +\setlength{\parskip}{5pt plus2pt minus2pt} + +\pagestyle{fancy} +\renewcommand{\chaptermark}[1]{\markboth{\thechapter\ #1}{}} +\renewcommand{\sectionmark}[1]{\markright{\thesection\ #1}{}} +\addtolength{\headheight}{2pt} + +\pagenumbering{arabic} +\setcounter{page} {1} diff --git a/bsp2/Protokolle/DigitalDesign_prot.tex b/bsp2/Protokolle/DigitalDesign_prot.tex new file mode 100644 index 0000000..acbdaed --- /dev/null +++ b/bsp2/Protokolle/DigitalDesign_prot.tex @@ -0,0 +1,36 @@ + +\documentclass[12pt,a4paper,titlepage,oneside]{report} + + +\usepackage{DigitalDesign_prot} +\sloppy + + +\begin{document} +% create titlepage +\maketitle + +% tables and lists +%\tableofcontents +%\newpage +%\listoffigures +%\newpage +%\listoftables +%\newpage + +% chapters +\input{chapter1} +\input{chapter2} +\input{chapter3} +\input{chapter4} + +% appendices +%\appendix +%\input{app1} + +% bibliography +%\bibliographystyle{alpha} +%\nocite{*} +%\bibliography{DigitalDesign} + +\end{document} diff --git a/bsp2/Protokolle/chapter1.tex b/bsp2/Protokolle/chapter1.tex new file mode 100644 index 0000000..27f796e --- /dev/null +++ b/bsp2/Protokolle/chapter1.tex @@ -0,0 +1,10 @@ +\chapter{Logikanalysator} + + +\begin{itemize} +\item Frequenz HSYNC = Hz +\item Frequenz VSYNC = Hz +\item Farbe Pixel = (r,g,b) +\item Farbe Hintergrund = (r,g,b) +\item x-Koordinate = +\end{itemize} diff --git a/bsp2/Protokolle/chapter2.tex b/bsp2/Protokolle/chapter2.tex new file mode 100644 index 0000000..a8ddc1a --- /dev/null +++ b/bsp2/Protokolle/chapter2.tex @@ -0,0 +1,6 @@ +\chapter{Design-Flow} + +\begin{itemize} +\item Blinkfrequenz = Hz +\end{itemize} + diff --git a/bsp2/Protokolle/chapter3.tex b/bsp2/Protokolle/chapter3.tex new file mode 100644 index 0000000..c6bbec2 --- /dev/null +++ b/bsp2/Protokolle/chapter3.tex @@ -0,0 +1 @@ +\chapter{VHDL} diff --git a/bsp2/Protokolle/chapter4.tex b/bsp2/Protokolle/chapter4.tex new file mode 100644 index 0000000..4b1b7cc --- /dev/null +++ b/bsp2/Protokolle/chapter4.tex @@ -0,0 +1,13 @@ +\chapter{Simulation und Test} + +\begin{itemize} +\item File Syntaxfehler: +\item Zeilennummer Syntaxfehler: + +\item File Semantikfehler 1: +\item Zeilennummer Semantikfehler 1: + +\item File Semantikfehler 2: +\item Zeilennummer Semantikfehler 2: +\end{itemize} + diff --git a/bsp2/Protokolle/prot_1.txt b/bsp2/Protokolle/prot_1.txt new file mode 100644 index 0000000..91a8a82 --- /dev/null +++ b/bsp2/Protokolle/prot_1.txt @@ -0,0 +1,6 @@ + +Frequenz HSYNC = ___ ___ Hz +Frequenz VSYNC = ___ ___ Hz +Farbe Pixel = (r,g,b) +Farbe Hintergrund = (r,g,b) +x-Koordinate = ___ ___ diff --git a/bsp2/Protokolle/prot_2.txt b/bsp2/Protokolle/prot_2.txt new file mode 100644 index 0000000..da24c18 --- /dev/null +++ b/bsp2/Protokolle/prot_2.txt @@ -0,0 +1 @@ +blinker_max = ___ ___ diff --git a/bsp2/Protokolle/prot_4.txt b/bsp2/Protokolle/prot_4.txt new file mode 100644 index 0000000..d45603d --- /dev/null +++ b/bsp2/Protokolle/prot_4.txt @@ -0,0 +1,9 @@ +File Syntaxfehler: ___ ___ +Zeilennummer Syntaxfehler: ___ ___ + +File Semantikfehler 1: ___ ___ +Zeilennummer Semantikfehler 1: ___ ___ + +File Semantikfehler 2: ___ ___ +Zeilennummer Semantikfehler 2: ___ ___ + diff --git a/bsp3/Angabe/board_driver_arc.vhd b/bsp3/Angabe/board_driver_arc.vhd new file mode 100644 index 0000000..7636a37 --- /dev/null +++ b/bsp3/Angabe/board_driver_arc.vhd @@ -0,0 +1,102 @@ +------------------------------------------------------------------------------- +-- Title : board_driver architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : board_driver.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: display number on 7-segment display +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + + +architecture behav of board_driver is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + + signal display_value : std_logic_vector(2*BCD_WIDTH-1 downto 0); + signal ten_value : std_logic_vector(BCD_WIDTH-1 downto 0); + signal one_value : std_logic_vector(BCD_WIDTH-1 downto 0); + signal digit_left : std_logic_vector(SEG_WIDTH-1 downto 0); + signal digit_right : std_logic_vector(SEG_WIDTH-1 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- generate control data + ----------------------------------------------------------------------------- + + + display_value <= "00000001"; -- vector of two BCD coded numbers to be displayed + one_value <= display_value(BCD_WIDTH-1 downto 0); -- BCD number to be displayed in right digit + ten_value <= display_value(2*BCD_WIDTH-1 downto BCD_WIDTH); -- BCD number to be displayed in left digit + + + SEG_DATA: process(reset, one_value, ten_value) + begin + if (reset = RES_ACT) then -- upon reset + digit_left <= DIGIT_OFF; -- ... switch off display + digit_right <= DIGIT_OFF; + else -- during operation + case one_value is -- ...display "one" position according + when "0000" => digit_right <= DIGIT_ZERO; -- ...to translation table + when "0001" => digit_right <= DIGIT_ONE; + when "0010" => digit_right <= DIGIT_TWO; + when "0011" => digit_right <= DIGIT_THREE; + when "0100" => digit_right <= DIGIT_FOUR; + when "0101" => digit_right <= DIGIT_FIVE; + when "0110" => digit_right <= DIGIT_SIX; + when "0111" => digit_right <= DIGIT_SEVEN; + when "1000" => digit_right <= DIGIT_EIGHT; + when "1001" => digit_right <= DIGIT_NINE; + when others => digit_right <= DIGIT_F; -- use "F" as overflow + end case; + + case ten_value is -- same for "ten" position + when "0000" => digit_left <= DIGIT_ZERO; + when "0001" => digit_left <= DIGIT_ONE; + when "0010" => digit_left <= DIGIT_TWO; + when "0011" => digit_left <= DIGIT_THREE; + when "0100" => digit_left <= DIGIT_FOUR; + when "0101" => digit_left <= DIGIT_FIVE; + when "0110" => digit_left <= DIGIT_SIX; + when "0111" => digit_left <= DIGIT_SEVEN; + when "1000" => digit_left <= DIGIT_EIGHT; + when "1001" => digit_left <= DIGIT_NINE; + when others => digit_left <= DIGIT_F; + end case; + end if; + end process; + + +-- combine the two digits to one bus + seven_seg(SEG_WIDTH-1 downto 0) <= digit_right; + seven_seg(2*SEG_WIDTH-1 downto SEG_WIDTH) <= digit_left; + +end behav; diff --git a/bsp3/Angabe/board_driver_ent.vhd b/bsp3/Angabe/board_driver_ent.vhd new file mode 100644 index 0000000..17e5cf7 --- /dev/null +++ b/bsp3/Angabe/board_driver_ent.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- Title : board_driver entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : board_driver_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: display number on 7-segment display +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + +entity board_driver is + + port ( + reset : in std_logic; + seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0) + ); +end board_driver; diff --git a/bsp3/Angabe/dide_16_3.txt b/bsp3/Angabe/dide_16_3.txt new file mode 100644 index 0000000..8af1bbb --- /dev/null +++ b/bsp3/Angabe/dide_16_3.txt @@ -0,0 +1,4 @@ +Anzahl der Streifen: 3 +Breite Streifen 1: 67 Pixel Farbe: (r,g,b) = (0,0,1) +Breite Streifen 2: 65 Pixel Farbe: (r,g,b) = (0,1,1) +Breite Streifen 3: 136 Pixel Farbe: (r,g,b) = (1,0,1) diff --git a/bsp3/Angabe/vga_arc.vhd b/bsp3/Angabe/vga_arc.vhd new file mode 100755 index 0000000..1723f58 --- /dev/null +++ b/bsp3/Angabe/vga_arc.vhd @@ -0,0 +1,219 @@ + ------------------------------------------------------------------------------- +-- Title : vga architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: arch of top level module, the sub-modules are connected here +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; -- include package + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + +------------------------------------------------------------------------------- +-- component declarations for the modules +------------------------------------------------------------------------------- + + component vga_driver + port ( + clk : in std_logic; + reset : in std_logic; + column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : out std_logic; + v_enable : out std_logic; + hsync : out std_logic; + vsync : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter : out std_logic; + d_set_vsync_counter : out std_logic; + d_set_column_counter : out std_logic; + d_set_line_counter : out std_logic); + end component; + + + component vga_control + port ( + clk : in std_logic; + reset : in std_logic; + column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : in std_logic; + v_enable : in std_logic; + r, g, b : out std_logic + ); + end component; + + + component board_driver + port ( + reset : in std_logic; + seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0)); + end component; + + +-- declare signals needed for internal wiring of these components later + signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal h_enable_sig : std_logic; + signal v_enable_sig : std_logic; + signal r_sig, g_sig, b_sig : std_logic; + signal hsync_sig, vsync_sig : std_logic; + +-- declare signals needed for prolongation of reset + signal dly_counter : std_logic_vector(1 downto 0); + signal dly_counter_next : std_logic_vector(1 downto 0); + constant MAX_DLY : std_logic_vector(1 downto 0) := "11"; + signal reset_dly : std_logic; -- + signal safe_reset : std_logic; + + +------------------------------------------------------------------------------- +-- prolong duration of reset to prevent glitches at power-up +------------------------------------------------------------------------------- + +begin + + DELAY_RESET_syn : process(clk_pin) -- synchronous capture + begin + if clk_pin'event and clk_pin = '1' then -- upon rising clock + dly_counter <= dly_counter_next; -- ... capture new counter value + end if; + end process; + + DELAY_RESET_next : process(dly_counter, reset_pin) -- next state logic + begin + if reset_pin = RES_ACT then -- upon reset + dly_counter_next <= (others => '0'); -- ...clear dly counter + elsif dly_counter < MAX_DLY then -- if no oflo + dly_counter_next <= dly_counter + '1'; -- ...increment dly counter + else + dly_counter_next <= dly_counter; -- freeze dly counter when oflo + end if; + end process; + + DELAY_RESET_out: process(dly_counter) + begin + if dly_counter < MAX_DLY then -- until dly counter reaches maximum + reset_dly <= RES_ACT; -- ...activate delayed reset signal + else -- upon counter oflo + reset_dly <= not(RES_ACT); -- ...finally deactivate delayed reset + end if; + end process; + + + + COMBINE_RESET: process(reset_pin, reset_dly) -- generate "safe" reset signal + begin + if reset_pin = RES_ACT or reset_dly = RES_ACT then -- ...by combining delayed reset with non-delayed reset input + safe_reset <= RES_ACT; + else + safe_reset <= not(RES_ACT); + end if; + end process; + + +------------------------------------------------------------------------------- +-- instantiate the components and connect to internal and external signals +------------------------------------------------------------------------------- + + +board_driver_unit : board_driver + port map ( + reset => safe_reset, + seven_seg => seven_seg_pin); + + +vga_driver_unit : vga_driver + port map ( + clk => clk_pin, + reset => safe_reset, + column_counter => column_counter_sig, + line_counter => line_counter_sig, + h_enable => h_enable_sig, + v_enable => v_enable_sig, + hsync => hsync_sig, + vsync => vsync_sig, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter); + +-- make the wiring for hsync and vsync pins +-- (pin is output only => internal _sig version required to allow readback of signal) + vsync_pin <= vsync_sig; + hsync_pin <= hsync_sig; + + + vga_control_unit : vga_control + port map ( + clk => clk_pin, + reset => safe_reset, + column_counter => column_counter_sig, + line_counter => line_counter_sig, + h_enable => h_enable_sig, + v_enable => v_enable_sig, + r => r_sig, + g => g_sig, + b => b_sig); + +-- make the wiring for RGB pins: drive all pins for same color from one source ("8 color mode") + r0_pin <= r_sig; r1_pin <= r_sig; r2_pin <= r_sig; + g0_pin <= g_sig; g1_pin <= g_sig; g2_pin <= g_sig; + b0_pin <= b_sig; b1_pin <= b_sig; + + +-- make extra pin connections for debug signals + d_hsync <= hsync_sig; -- make duplicate of signal for debug connector + d_vsync <= vsync_sig; -- make duplicate of signal for debug connector + d_column_counter <= column_counter_sig; + d_line_counter <= line_counter_sig; + d_h_enable <= h_enable_sig; + d_v_enable <= v_enable_sig; + d_r <= r_sig; + d_g <= g_sig; + d_b <= b_sig; + d_state_clk <= clk_pin; -- make duplicate of signal for debug connector + + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp3/Angabe/vga_beh_tb.vhd b/bsp3/Angabe/vga_beh_tb.vhd new file mode 100644 index 0000000..4a4ba09 --- /dev/null +++ b/bsp3/Angabe/vga_beh_tb.vhd @@ -0,0 +1,189 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-11-21 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_tb is + +end vga_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture behaviour of vga_tb is + + constant cc : time := 39.7 ns; -- test clock period + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : hsync_state_type; + signal d_vsync_state : vsync_state_type; + signal d_state_clk : std_logic; + + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk); + + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk_pin <= '1'; + wait for cc/2; + clk_pin <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk_pin = '1' and clk_pin'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + +end behaviour; + + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_beh of vga_tb is + for behaviour + for vga_unit : vga use entity work.vga(behav); + end for; + end for; +end vga_conf_beh; + + diff --git a/bsp3/Angabe/vga_beh_tb.vhd~ b/bsp3/Angabe/vga_beh_tb.vhd~ new file mode 100644 index 0000000..9530bed --- /dev/null +++ b/bsp3/Angabe/vga_beh_tb.vhd~ @@ -0,0 +1,194 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_tb is + +end vga_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture behaviour of vga_tb is + + constant cc : time := 39.7 ns; -- test clock period + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : hsync_state_type; + signal d_vsync_state : vsync_state_type; + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk_pin <= '1'; + wait for cc/2; + clk_pin <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk_pin = '1' and clk_pin'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + +end behaviour; + + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_beh of vga_tb is + for behaviour + for vga_unit : vga use entity work.vga(behav); + end for; + end for; +end vga_conf_beh; + + diff --git a/bsp3/Angabe/vga_control_arc.vhd b/bsp3/Angabe/vga_control_arc.vhd new file mode 100644 index 0000000..0c4425b --- /dev/null +++ b/bsp3/Angabe/vga_control_arc.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- Title : vga_control architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga_control is + + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + + +begin + + r <= COLR_OFF; + g <= COLR_OFF; + b <= COLR_OFF; + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp3/Angabe/vga_control_ent.vhd b/bsp3/Angabe/vga_control_ent.vhd new file mode 100644 index 0000000..5fce16a --- /dev/null +++ b/bsp3/Angabe/vga_control_ent.vhd @@ -0,0 +1,51 @@ +------------------------------------------------------------------------------- +-- Title : vga_control entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + + +entity vga_control is + port(clk : in std_logic; + reset : in std_logic; + column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + v_enable : in std_logic; + h_enable : in std_logic; + r, g, b : out std_logic + ); + +end vga_control; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp3/Angabe/vga_driver_arc.vhd b/bsp3/Angabe/vga_driver_arc.vhd new file mode 100644 index 0000000..1b89ac1 --- /dev/null +++ b/bsp3/Angabe/vga_driver_arc.vhd @@ -0,0 +1,402 @@ +------------------------------------------------------------------------------- +-- Title : vga_driver architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_driver.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-01-24 +------------------------------------------------------------------------------- +-- Description: generate hsync and vsync +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-01-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga_driver is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + constant TIME_A : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100011111"; + constant TIME_B : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0001011010"; + constant TIME_BC : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0010000111"; + constant TIME_BCD : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100000111"; + + constant TIME_O : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000001000"; + constant TIME_P : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000000001"; + constant TIME_PQ : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000100001"; + constant TIME_PQR : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000000001"; + + signal h_sync : std_logic; + signal h_sync_next : std_logic; + + signal hsync_state : hsync_state_type; + signal hsync_state_next : hsync_state_type; + + signal h_enable_sig : std_logic; + signal h_enable_next : std_logic; + + signal set_hsync_counter : std_logic; + signal hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal hsync_counter_next : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + constant HSYN_CNT_MAX : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1111111111"; + + signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal column_counter_next : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal set_column_counter : std_logic; + + signal v_sync : std_logic; + signal v_sync_next : std_logic; + + signal vsync_state : vsync_state_type; + signal vsync_state_next : vsync_state_type; + + signal v_enable_sig : std_logic; + signal v_enable_next : std_logic; + + signal set_vsync_counter : std_logic; + signal vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal vsync_counter_next : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + constant VSYN_CNT_MAX : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1111111111"; + + signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal line_counter_next : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal set_line_counter : std_logic; + + + +begin + +---------------------------------------------------------------------------- +-- Column_Counter [0..639]: calculates column number for next pixel to be displayed +---------------------------------------------------------------------------- + + COLUMN_COUNT_syn: process(clk, reset, column_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + column_counter_sig <= (others => '0'); + else + column_counter_sig <= column_counter_next; -- synchronous capture + end if; + end if; + end process; + + COLUMN_COUNT_next: process(set_column_counter, column_counter_sig) + begin + if set_column_counter = ENABLE then -- reset counter + column_counter_next <= (others => '0'); + else + if column_counter_sig < RIGHT_BORDER then + column_counter_next <= column_counter_sig + '1'; -- increment column + else + column_counter_next <= RIGHT_BORDER; -- ... but do not count beyond right border + end if; + end if; + end process; + +---------------------------------------------------------------------------- +-- Line_counter [0..479]: calculates line number for next pixel to be displayed +---------------------------------------------------------------------------- + + LINE_COUNT_syn: process(clk, reset, line_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + line_counter_sig <= (others => '0'); + else + line_counter_sig <= line_counter_next; -- synchronous capture + end if; + end if; + end process; + + LINE_COUNT_next: process(set_line_counter, line_counter_sig, set_hsync_counter) + begin + if set_line_counter = ENABLE then -- reset counter + line_counter_next <= (others => '0'); + else + if line_counter_sig < BOTTOM_BORDER then + if set_hsync_counter = '1' then -- when enabled + line_counter_next <= line_counter_sig + '1'; -- ... increment line + else + line_counter_next <= line_counter_sig; + end if; + else + line_counter_next <= BOTTOM_BORDER; -- ... but do not count below bottom + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- Hsync_Counter: generates time base for HSYNC State Machine +---------------------------------------------------------------------------- + + HSYNC_COUNT_syn: process(clk, reset, hsync_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + hsync_counter <= (others => '0'); + else + hsync_counter <= hsync_counter_next; -- synchronous capture + end if; + end if; + end process; + + HSYNC_COUNT_next: process(set_hsync_counter, hsync_counter) + begin + if set_hsync_counter = ENABLE then -- reset counter + hsync_counter_next <= (others => '0'); + else + if hsync_counter < HSYN_CNT_MAX then + hsync_counter_next <= hsync_counter + '1'; -- increment time + else + hsync_counter_next <= HSYN_CNT_MAX; -- ... but do not count beyond max period + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- HSYNC STATE MACHINE: generates hsync signal and controls hsync counter & column counter +---------------------------------------------------------------------------- + + HSYNC_FSM_syn: process (clk, reset) -- synchronous capture + begin + if clk'event and clk = '1' then + if reset = RES_ACT then + hsync_state <= RESET_STATE; + h_sync <= '1'; + v_enable_sig <= not(ENABLE); + else + hsync_state <= hsync_state_next; + h_sync <= h_sync_next; + v_enable_sig <= v_enable_next; + end if; + end if; + end process; + + HSYNC_FSM_next : process(hsync_state, hsync_counter, h_sync, v_enable_sig) -- next-state logic + begin -- default assignments + hsync_state_next <= hsync_state; -- ... hold current state + h_sync_next <= h_sync; -- ... and values + v_enable_next <= v_enable_sig; + + case hsync_state is + when RESET_STATE => + h_sync_next <= '0'; -- next signal values are defined here + v_enable_next <= not(ENABLE); + hsync_state_next <= B_STATE; -- ... as well as state transitions + when B_STATE => + h_sync_next <= '0'; + if hsync_counter = TIME_B then + hsync_state_next <= C_STATE; + end if; + when C_STATE => + h_sync_next <= '1'; + if hsync_counter = TIME_BC then + hsync_state_next <= pre_D_STATE; + end if; + when pre_D_STATE => + v_enable_next <= ENABLE; + hsync_state_next <= D_STATE; + when D_STATE => + v_enable_next <= ENABLE; + if hsync_counter = TIME_BCD then + hsync_state_next <= E_STATE; + end if; + when E_STATE => + v_enable_next <= not(ENABLE); + if hsync_counter = TIME_A then + hsync_state_next <= pre_B_STATE; + end if; + when pre_B_STATE => + h_sync_next <= '0'; + v_enable_next <= not(ENABLE); + hsync_state_next <= B_STATE; + when others => + null; + end case; + end process; + + HSYNC_FSM_out : process(hsync_state) -- output logic + begin + set_hsync_counter <= not(ENABLE); -- default assignments + set_column_counter <= not(ENABLE); + + case hsync_state is + when RESET_STATE => -- outputs for each state are defined here + set_hsync_counter <= ENABLE; + when pre_D_STATE => + set_column_counter <= ENABLE; + when pre_B_STATE => + set_hsync_counter <= ENABLE; + when others => + null; + end case; + end process; + + +---------------------------------------------------------------------------- +-- Vsync_Counter: generates time base for VSYNC State Machine +---------------------------------------------------------------------------- + + VSYNC_COUNT_syn: process(clk, reset, vsync_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + vsync_counter <= (others => '0'); + else + vsync_counter <= vsync_counter_next; -- synchronous capture + end if; + end if; + end process; + + VSYNC_COUNT_next: process(set_vsync_counter, vsync_counter, set_hsync_counter) + begin + if set_vsync_counter = ENABLE then -- reset counter + vsync_counter_next <= (others => '0'); + else + if vsync_counter < VSYN_CNT_MAX then + if set_hsync_counter = '1' then -- if enabled + vsync_counter_next <= vsync_counter + '1'; -- ... increment time + else + vsync_counter_next <= vsync_counter; + end if; + else + vsync_counter_next <= VSYN_CNT_MAX; -- ... but do not count beyond max period + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- VSYNC STATE MACHINE: generates vsync signal and controls vsync counter & line counter +---------------------------------------------------------------------------- + + VSYNC_FSM_syn : process (clk, reset) -- synchronous capture + begin + if clk'event and clk = '1' then + if reset = RES_ACT then + vsync_state <= RESET_STATE; + v_sync <= '1'; + h_enable_sig <= not(ENABLE); + else + vsync_state <= vsync_state_next; + v_sync <= v_sync_next; + h_enable_sig <= h_enable_next; + end if; + end if; + end process; + + VSYNC_FSM_next : process(vsync_state, vsync_counter, v_sync, h_enable_sig) + begin -- next state logic + vsync_state_next <= vsync_state; -- default assignments + v_sync_next <= v_sync; + h_enable_next <= h_enable_sig; + + case vsync_state is -- state transitions and next signals are defined here + when RESET_STATE => + v_sync_next <= '0'; + h_enable_next <= not(ENABLE); + vsync_state_next <= P_STATE; + when P_STATE => + v_sync_next <= '0'; + if vsync_counter = time_p then + vsync_state_next <= Q_STATE; + end if; + when Q_STATE => + v_sync_next <= '1'; + if vsync_counter = time_pq then + vsync_state_next <= pre_R_STATE; + end if; + when pre_R_STATE => + h_enable_next <= ENABLE; + vsync_state_next <= R_STATE; + when R_STATE => + h_enable_next <= ENABLE; + if vsync_counter = time_pqr then + vsync_state_next <= S_STATE; + end if; + when S_STATE => + h_enable_next <= not(ENABLE); + if vsync_counter = time_o then + vsync_state_next <= pre_P_STATE; + end if; + when pre_P_STATE => + v_sync_next <= '0'; + h_enable_next <= not(ENABLE); + vsync_state_next <= P_STATE; + when others => + null; + end case; + end process; + + VSYNC_FSM_out : process(vsync_state) + begin -- output logic + set_vsync_counter <= not(ENABLE); -- output values for each state defined here + set_line_counter <= not(ENABLE); + + case vsync_state is + when RESET_STATE => + set_vsync_counter <= ENABLE; + when pre_R_STATE => + set_line_counter <= ENABLE; + when pre_P_STATE => + set_vsync_counter <= ENABLE; + when others => + null; + end case; + end process; + + + +-- signal wiring for entity (introduced _sig to allow readback of output signals) + + column_counter <= column_counter_sig; + v_enable <= v_enable_sig; + line_counter <= line_counter_sig; + h_enable <= h_enable_sig; + + + hsync <= h_sync; + vsync <= v_sync; + + ----------------------------------------------------------------------------- + -- debug signals + ----------------------------------------------------------------------------- + d_hsync_state <= hsync_state; + d_vsync_state <= vsync_state; + d_hsync_counter <= hsync_counter; + d_vsync_counter <= vsync_counter; + d_set_hsync_counter <= set_hsync_counter; + d_set_vsync_counter <= set_vsync_counter; + d_set_column_counter <= set_column_counter; + d_set_line_counter <= set_line_counter; + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp3/Angabe/vga_driver_ent.vhd b/bsp3/Angabe/vga_driver_ent.vhd new file mode 100644 index 0000000..f4c00be --- /dev/null +++ b/bsp3/Angabe/vga_driver_ent.vhd @@ -0,0 +1,60 @@ +------------------------------------------------------------------------------- +-- Title : vga_driver entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_driver_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generate vsync and hsync +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + + +entity vga_driver is + port(clk : in std_logic; + reset : in std_logic; + column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : out std_logic; + v_enable : out std_logic; + hsync, vsync : out std_logic; + + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter : out std_logic; + d_set_vsync_counter : out std_logic; + d_set_column_counter : out std_logic; + d_set_line_counter : out std_logic + ); + +end vga_driver; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp3/Angabe/vga_ent.vhd b/bsp3/Angabe/vga_ent.vhd new file mode 100644 index 0000000..32256bb --- /dev/null +++ b/bsp3/Angabe/vga_ent.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- Title : vga entitiy +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: entity of top level module, external pins defined here +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + +entity vga is + port( +-- input pins from PCB board + clk_pin : in std_logic; -- clock pin + reset_pin : in std_logic; -- reset pins (from switch) +-- output pins to RGB connector / VGA screen + r0_pin, r1_pin, r2_pin : out std_logic; -- to RGB connector "red" + g0_pin, g1_pin, g2_pin : out std_logic; -- to RGB connector "green" + b0_pin, b1_pin : out std_logic; -- to RGB connector "blue" + hsync_pin : out std_logic; -- to RGB connector "Hsync" + vsync_pin : out std_logic; -- to RGB connector "Vsync" +-- output pins to 7-segment display + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); +-- output pins provided for debugging only / logic analyzer + d_hsync, d_vsync : out std_logic; -- copy of hsync_pin, vsync_pin + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic + ); + +end vga; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp3/Angabe/vga_pak.vhd b/bsp3/Angabe/vga_pak.vhd new file mode 100644 index 0000000..7f59eab --- /dev/null +++ b/bsp3/Angabe/vga_pak.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------- +-- Title : vga package +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_pak.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-08-19 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: definitions of global constants and enumerated types +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-08-19 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + + +------------------------------------------------------------------------------- +-- PACKAGE +------------------------------------------------------------------------------- + +package vga_pak is + + constant RES_ACT : std_logic := '0'; -- define reset active LO + constant ENABLE : std_logic := '1'; -- define diverse enable HI + constant COLR_ON : std_logic := '1'; -- define VGA color on as HI + constant COLR_OFF : std_logic := '0'; -- define VGA color off as LO + constant SEG_WIDTH : integer := 7; -- display has 7 segments + constant BCD_WIDTH : integer := 4; -- BCD number has 4 bit + constant TOG_CNT_WIDTH : integer := 25; -- bitwidth of counter that controls blinking + + constant COL_CNT_WIDTH : integer := 10; -- width of the column counter + constant LINE_CNT_WIDTH : integer := 9; -- width of the line counter + constant HSYN_CNT_WIDTH : integer := 10; -- width of the h-sync counter + constant VSYN_CNT_WIDTH : integer := 10; -- width of the v-sync counter + + constant RIGHT_BORDER: std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "1001111111"; -- 640 columns (0...639) + constant BOTTOM_BORDER: std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "111011111"; -- 480 lines (0...479) + + -- define coordinates of rectangle + constant X_MIN : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0001100100"; -- 100 + constant X_MAX : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0011001000"; -- 200 + constant Y_MIN : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "001100100"; + constant Y_MAX : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "011001000"; + + -- define emumerated types for state machines + type hsync_state_type is (RESET_STATE, B_STATE, C_STATE, D_STATE, E_STATE, + pre_D_STATE, pre_B_STATE); + type vsync_state_type is (RESET_STATE, P_STATE, Q_STATE, R_STATE, S_STATE, + pre_R_STATE, pre_P_STATE); + + -- Definitions for 7-segment display gfedcba + constant DIGIT_ZERO : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000000"; + constant DIGIT_ONE : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111001"; + constant DIGIT_TWO : std_logic_vector(SEG_WIDTH-1 downto 0) := "0100100"; + constant DIGIT_THREE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110000"; + constant DIGIT_FOUR : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011001"; + constant DIGIT_FIVE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0010010"; + constant DIGIT_SIX : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000010"; + constant DIGIT_SEVEN : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111000"; + constant DIGIT_EIGHT : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000000"; + constant DIGIT_NINE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011000"; + constant DIGIT_MINUS : std_logic_vector(SEG_WIDTH-1 downto 0) := "0111111"; + constant DIGIT_A : std_logic_vector(SEG_WIDTH-1 downto 0) := "0001000"; + constant DIGIT_B : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000011"; + constant DIGIT_C : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110001"; + constant DIGIT_D : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000010"; + constant DIGIT_E : std_logic_vector(SEG_WIDTH-1 downto 0) := "1001111"; + constant DIGIT_F : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000111"; + constant DIGIT_OFF : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111111"; + +end package; diff --git a/bsp3/Angabe/vga_pll.bdf b/bsp3/Angabe/vga_pll.bdf new file mode 100755 index 0000000..414cf76 --- /dev/null +++ b/bsp3/Angabe/vga_pll.bdf @@ -0,0 +1,799 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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1348 672)) +) +(pin + (output) + (rect 912 208 1088 224) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "hsync_pin" (rect 90 0 140 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)(line_width 1)) + (line (pt 52 4)(pt 78 4)(line_width 1)) + (line (pt 52 12)(pt 78 12)(line_width 1)) + (line (pt 52 12)(pt 52 4)(line_width 1)) + (line (pt 78 4)(pt 82 8)(line_width 1)) + (line (pt 82 8)(pt 78 12)(line_width 1)) + (line (pt 78 12)(pt 82 8)(line_width 1)) + ) + (annotation_block (location)(rect 872 528 920 544)) +) +(pin + (output) + (rect 912 224 1088 240) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "vsync_pin" (rect 90 0 141 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)(line_width 1)) + (line (pt 52 4)(pt 78 4)(line_width 1)) + (line (pt 52 12)(pt 78 12)(line_width 1)) + (line (pt 52 12)(pt 52 4)(line_width 1)) + (line (pt 78 4)(pt 82 8)(line_width 1)) + (line (pt 82 8)(pt 78 12)(line_width 1)) + (line (pt 78 12)(pt 82 8)(line_width 1)) + ) + (annotation_block (location)(rect 872 544 920 560)) +) +(symbol + (rect 696 56 912 568) + (text "vga" (rect 5 0 23 12)(font "Arial" )) + (text "inst" (rect 8 496 25 508)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk_pin" (rect 0 0 34 12)(font "Arial" )) + (text "clk_pin" (rect 21 27 55 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "reset_pin" (rect 0 0 44 12)(font "Arial" )) + (text "reset_pin" (rect 21 43 65 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 216 32) + (output) + (text "r0_pin" (rect 0 0 29 12)(font "Arial" )) + (text "r0_pin" (rect 166 27 195 39)(font "Arial" )) + (line (pt 216 32)(pt 200 32)(line_width 1)) + ) + (port + (pt 216 48) + (output) + (text "r1_pin" (rect 0 0 29 12)(font "Arial" )) + (text "r1_pin" (rect 166 43 195 55)(font "Arial" )) + (line (pt 216 48)(pt 200 48)(line_width 1)) + ) + (port + (pt 216 64) + (output) + (text "r2_pin" (rect 0 0 29 12)(font "Arial" )) + (text "r2_pin" (rect 166 59 195 71)(font "Arial" )) + (line (pt 216 64)(pt 200 64)(line_width 1)) + ) + (port + (pt 216 80) + (output) + (text "g0_pin" (rect 0 0 31 12)(font "Arial" )) + (text "g0_pin" (rect 164 75 195 87)(font "Arial" )) + (line (pt 216 80)(pt 200 80)(line_width 1)) + ) + (port + (pt 216 96) + (output) + (text "g1_pin" (rect 0 0 31 12)(font "Arial" )) + (text "g1_pin" (rect 164 91 195 103)(font "Arial" )) + (line (pt 216 96)(pt 200 96)(line_width 1)) + ) + (port + (pt 216 112) + (output) + (text "g2_pin" (rect 0 0 31 12)(font "Arial" )) + (text "g2_pin" (rect 164 107 195 119)(font "Arial" )) + (line (pt 216 112)(pt 200 112)(line_width 1)) + ) + (port + (pt 216 128) + (output) + (text "b0_pin" (rect 0 0 31 12)(font "Arial" )) + (text "b0_pin" (rect 164 123 195 135)(font "Arial" )) + (line (pt 216 128)(pt 200 128)(line_width 1)) + ) + (port + (pt 216 144) + (output) + (text "b1_pin" (rect 0 0 31 12)(font "Arial" )) + (text "b1_pin" (rect 164 139 195 151)(font "Arial" )) + (line (pt 216 144)(pt 200 144)(line_width 1)) + ) + (port + (pt 216 160) + (output) + (text "hsync_pin" (rect 0 0 50 12)(font "Arial" )) + (text "hsync_pin" (rect 145 155 195 167)(font "Arial" )) + (line (pt 216 160)(pt 200 160)(line_width 1)) + ) + (port + (pt 216 176) + (output) + (text "vsync_pin" (rect 0 0 51 12)(font "Arial" )) + (text "vsync_pin" (rect 144 171 195 183)(font "Arial" )) + (line (pt 216 176)(pt 200 176)(line_width 1)) + ) + (port + (pt 216 192) + (output) + (text "seven_seg_pin[13..0]" (rect 0 0 106 12)(font "Arial" )) + (text "seven_seg_pin[13..0]" (rect 89 187 195 199)(font "Arial" )) + (line (pt 216 192)(pt 200 192)(line_width 3)) + ) + (port + (pt 216 208) + (output) + (text "d_hsync" (rect 0 0 42 12)(font "Arial" )) + (text "d_hsync" (rect 153 203 195 215)(font "Arial" )) + (line (pt 216 208)(pt 200 208)(line_width 1)) + ) + (port + (pt 216 224) + (output) + (text "d_vsync" (rect 0 0 43 12)(font "Arial" )) + (text "d_vsync" (rect 152 219 195 231)(font "Arial" )) + (line (pt 216 224)(pt 200 224)(line_width 1)) + ) + (port + (pt 216 240) + (output) + (text "d_column_counter[9..0]" (rect 0 0 115 12)(font "Arial" )) + (text "d_column_counter[9..0]" (rect 80 235 195 247)(font "Arial" )) + (line (pt 216 240)(pt 200 240)(line_width 3)) + ) + (port + (pt 216 256) + (output) + (text "d_line_counter[8..0]" (rect 0 0 96 12)(font "Arial" )) + (text "d_line_counter[8..0]" (rect 99 251 195 263)(font "Arial" )) + (line (pt 216 256)(pt 200 256)(line_width 3)) + ) + (port + (pt 216 272) + (output) + (text "d_set_column_counter" (rect 0 0 110 12)(font "Arial" )) + (text "d_set_column_counter" (rect 85 267 195 279)(font "Arial" )) + (line (pt 216 272)(pt 200 272)(line_width 1)) + ) + (port + (pt 216 288) + (output) + (text "d_set_line_counter" (rect 0 0 92 12)(font "Arial" )) + (text "d_set_line_counter" (rect 103 283 195 295)(font "Arial" )) + (line (pt 216 288)(pt 200 288)(line_width 1)) + ) + (port + (pt 216 304) + (output) + (text "d_hsync_counter[9..0]" (rect 0 0 110 12)(font "Arial" )) + (text "d_hsync_counter[9..0]" (rect 85 299 195 311)(font "Arial" )) + (line (pt 216 304)(pt 200 304)(line_width 3)) + ) + (port + (pt 216 320) + (output) + (text "d_vsync_counter[9..0]" (rect 0 0 112 12)(font "Arial" )) + (text "d_vsync_counter[9..0]" (rect 83 315 195 327)(font "Arial" )) + (line (pt 216 320)(pt 200 320)(line_width 3)) + ) + (port + (pt 216 336) + (output) + (text "d_set_hsync_counter" (rect 0 0 106 12)(font "Arial" )) + (text "d_set_hsync_counter" (rect 89 331 195 343)(font "Arial" )) + (line (pt 216 336)(pt 200 336)(line_width 1)) + ) + (port + (pt 216 352) + (output) + (text "d_set_vsync_counter" (rect 0 0 107 12)(font "Arial" )) + (text "d_set_vsync_counter" (rect 88 347 195 359)(font "Arial" )) + (line (pt 216 352)(pt 200 352)(line_width 1)) + ) + (port + (pt 216 368) + (output) + (text "d_h_enable" (rect 0 0 55 12)(font "Arial" )) + (text "d_h_enable" (rect 140 363 195 375)(font "Arial" )) + (line (pt 216 368)(pt 200 368)(line_width 1)) + ) + (port + (pt 216 384) + (output) + (text "d_v_enable" (rect 0 0 56 12)(font "Arial" )) + (text "d_v_enable" (rect 139 379 195 391)(font "Arial" )) + (line (pt 216 384)(pt 200 384)(line_width 1)) + ) + (port + (pt 216 400) + (output) + (text "d_r" (rect 0 0 15 12)(font "Arial" )) + (text "d_r" (rect 180 395 195 407)(font "Arial" )) + (line (pt 216 400)(pt 200 400)(line_width 1)) + ) + (port + (pt 216 416) + (output) + (text "d_g" (rect 0 0 17 12)(font "Arial" )) + (text "d_g" (rect 178 411 195 423)(font "Arial" )) + (line (pt 216 416)(pt 200 416)(line_width 1)) + ) + (port + (pt 216 432) + (output) + (text "d_b" (rect 0 0 17 12)(font "Arial" )) + (text "d_b" (rect 178 427 195 439)(font "Arial" )) + (line (pt 216 432)(pt 200 432)(line_width 1)) + ) + (port + (pt 216 448) + (output) + (text "d_hsync_state[0..6]" (rect 0 0 99 12)(font "Arial" )) + (text "d_hsync_state[0..6]" (rect 96 443 195 455)(font "Arial" )) + (line (pt 216 448)(pt 200 448)(line_width 3)) + ) + (port + (pt 216 464) + (output) + (text "d_vsync_state[0..6]" (rect 0 0 100 12)(font "Arial" )) + (text "d_vsync_state[0..6]" (rect 95 459 195 471)(font "Arial" )) + (line (pt 216 464)(pt 200 464)(line_width 3)) + ) + (port + (pt 216 480) + (output) + (text "d_state_clk" (rect 0 0 56 12)(font "Arial" )) + (text "d_state_clk" (rect 139 475 195 487)(font "Arial" )) + (line (pt 216 480)(pt 200 480)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 200 496)(line_width 1)) + ) +) +(symbol + (rect 408 56 504 152) + (text "vpll" (rect 5 0 22 12)(font "Arial" )) + (text "inst1" (rect 8 80 31 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inclk0" (rect 0 0 28 12)(font "Arial" )) + (text "inclk0" (rect 21 27 49 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 96 32) + (output) + (text "c0" (rect 0 0 11 12)(font "Arial" )) + (text "c0" (rect 64 27 75 39)(font "Arial" )) + (line (pt 96 32)(pt 80 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 80 80)(line_width 1)) + ) +) +(connector + (pt 696 88) + (pt 504 88) +) diff --git a/bsp3/Angabe/vga_pll.tcl b/bsp3/Angabe/vga_pll.tcl new file mode 100755 index 0000000..aa73503 --- /dev/null +++ b/bsp3/Angabe/vga_pll.tcl @@ -0,0 +1,172 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: vga_pll.tcl +# Generated on: Fri Sep 29 09:31:24 2006 + +# Load Quartus II Tcl Project package +package require ::quartus::project +package require ::quartus::flow + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "vga_pll"]} { + puts "Project vga_pll is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists vga_pll]} { + project_open -cmp vga_pll vga_pll + } else { + project_new -cmp vga_pll vga_pll + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + catch { set_global_assignment -name FAMILY Stratix } result + catch { set_global_assignment -name DEVICE EP1S25F672C6 } result + catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result + catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result + catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result + catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result + catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result + catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result + catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result + catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result + catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result + catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result + catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result + catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result + + set_location_assignment PIN_E24 -to b0_pin + set_location_assignment PIN_T6 -to b1_pin + set_location_assignment PIN_N3 -to board_clk + set_location_assignment PIN_E23 -to g0_pin + set_location_assignment PIN_T5 -to g1_pin + set_location_assignment PIN_T24 -to g2_pin + set_location_assignment PIN_F1 -to hsync_pin + set_location_assignment PIN_E22 -to r0_pin + set_location_assignment PIN_T4 -to r1_pin + set_location_assignment PIN_T7 -to r2_pin + set_location_assignment PIN_A5 -to reset + set_location_assignment PIN_F2 -to vsync_pin + set_location_assignment PIN_Y5 -to d_hsync_state[0] + set_location_assignment PIN_F19 -to d_hsync_state[1] + set_location_assignment PIN_F17 -to d_hsync_state[2] + set_location_assignment PIN_Y2 -to d_hsync_state[3] + set_location_assignment PIN_F10 -to d_hsync_state[4] + set_location_assignment PIN_F9 -to d_hsync_state[5] + set_location_assignment PIN_F6 -to d_hsync_state[6] + set_location_assignment PIN_H4 -to d_hsync_counter[0] + set_location_assignment PIN_G25 -to d_hsync_counter[7] + set_location_assignment PIN_G22 -to d_hsync_counter[8] + set_location_assignment PIN_G18 -to d_hsync_counter[9] + set_location_assignment PIN_F5 -to d_vsync_state[0] + set_location_assignment PIN_F4 -to d_vsync_state[1] + set_location_assignment PIN_F3 -to d_vsync_state[2] + set_location_assignment PIN_M19 -to d_vsync_state[3] + set_location_assignment PIN_M18 -to d_vsync_state[4] + set_location_assignment PIN_M7 -to d_vsync_state[5] + set_location_assignment PIN_M4 -to d_vsync_state[6] + set_location_assignment PIN_G9 -to d_vsync_counter[0] + set_location_assignment PIN_G6 -to d_vsync_counter[7] + set_location_assignment PIN_G4 -to d_vsync_counter[8] + set_location_assignment PIN_G2 -to d_vsync_counter[9] + set_location_assignment PIN_K6 -to d_line_counter[0] + set_location_assignment PIN_K4 -to d_line_counter[1] + set_location_assignment PIN_J22 -to d_line_counter[2] + set_location_assignment PIN_M9 -to d_line_counter[3] + set_location_assignment PIN_M8 -to d_line_counter[4] + set_location_assignment PIN_M6 -to d_line_counter[5] + set_location_assignment PIN_M5 -to d_line_counter[6] + set_location_assignment PIN_L24 -to d_line_counter[7] + set_location_assignment PIN_L25 -to d_line_counter[8] + set_location_assignment PIN_L23 -to d_column_counter[0] + set_location_assignment PIN_L22 -to d_column_counter[1] + set_location_assignment PIN_L21 -to d_column_counter[2] + set_location_assignment PIN_L20 -to d_column_counter[3] + set_location_assignment PIN_L6 -to d_column_counter[4] + set_location_assignment PIN_L4 -to d_column_counter[5] + set_location_assignment PIN_L2 -to d_column_counter[6] + set_location_assignment PIN_K23 -to d_column_counter[7] + set_location_assignment PIN_K19 -to d_column_counter[8] + set_location_assignment PIN_K5 -to d_column_counter[9] + set_location_assignment PIN_L7 -to d_hsync + set_location_assignment PIN_L5 -to d_vsync + set_location_assignment PIN_F26 -to d_set_hsync_counter + set_location_assignment PIN_F24 -to d_set_vsync_counter + set_location_assignment PIN_F21 -to d_set_line_counter + set_location_assignment PIN_Y23 -to d_set_column_counter + set_location_assignment PIN_L3 -to d_r + set_location_assignment PIN_K24 -to d_g + set_location_assignment PIN_K20 -to d_b + set_location_assignment PIN_H18 -to d_v_enable + set_location_assignment PIN_J21 -to d_h_enable + set_location_assignment PIN_R8 -to seven_seg_pin[0] + set_location_assignment PIN_R9 -to seven_seg_pin[1] + set_location_assignment PIN_R19 -to seven_seg_pin[2] + set_location_assignment PIN_R20 -to seven_seg_pin[3] + set_location_assignment PIN_R21 -to seven_seg_pin[4] + set_location_assignment PIN_R22 -to seven_seg_pin[5] + set_location_assignment PIN_R23 -to seven_seg_pin[6] + set_location_assignment PIN_Y11 -to seven_seg_pin[7] + set_location_assignment PIN_N7 -to seven_seg_pin[8] + set_location_assignment PIN_N8 -to seven_seg_pin[9] + set_location_assignment PIN_R4 -to seven_seg_pin[10] + set_location_assignment PIN_R6 -to seven_seg_pin[11] + set_location_assignment PIN_AA11 -to seven_seg_pin[12] + set_location_assignment PIN_T2 -to seven_seg_pin[13] + set_location_assignment PIN_K3 -to d_state_clk + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin + + + # Commit assignments + export_assignments + +execute_flow -compile + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/bsp3/Angabe/vga_pos_tb.vhd b/bsp3/Angabe/vga_pos_tb.vhd new file mode 100644 index 0000000..4c314d8 --- /dev/null +++ b/bsp3/Angabe/vga_pos_tb.vhd @@ -0,0 +1,192 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-11-21 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pos_tb is + +end vga_pos_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pos_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk); + + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(1000000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pos of vga_pos_tb is + for structure + for vga_unit : vga use entity work.vga(structure); + end for; + end for; +end vga_conf_pos; + + + diff --git a/bsp3/Angabe/vga_pos_tb.vhd~ b/bsp3/Angabe/vga_pos_tb.vhd~ new file mode 100644 index 0000000..ebcff70 --- /dev/null +++ b/bsp3/Angabe/vga_pos_tb.vhd~ @@ -0,0 +1,198 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pos_tb is + +end vga_pos_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pos_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(1000000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pos of vga_pos_tb is + for structure + for vga_unit : vga use entity work.vga(structure); + end for; + end for; +end vga_conf_pos; + + + diff --git a/bsp3/Angabe/vga_pre_tb.vhd b/bsp3/Angabe/vga_pre_tb.vhd new file mode 100644 index 0000000..d3dd745 --- /dev/null +++ b/bsp3/Angabe/vga_pre_tb.vhd @@ -0,0 +1,191 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-11-21 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pre_tb is + +end vga_pre_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pre_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pre of vga_pre_tb is + for structure + for vga_unit : vga use entity work.vga(beh); + end for; + end for; +end vga_conf_pre; + + + diff --git a/bsp3/Angabe/vga_pre_tb.vhd~ b/bsp3/Angabe/vga_pre_tb.vhd~ new file mode 100644 index 0000000..dc010f7 --- /dev/null +++ b/bsp3/Angabe/vga_pre_tb.vhd~ @@ -0,0 +1,197 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pre_tb is + +end vga_pre_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pre_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pre of vga_pre_tb is + for structure + for vga_unit : vga use entity work.vga(beh); + end for; + end for; +end vga_conf_pre; + + + diff --git a/bsp3/Angabe/vpll.bsf b/bsp3/Angabe/vpll.bsf new file mode 100644 index 0000000..63c3118 --- /dev/null +++ b/bsp3/Angabe/vpll.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2004 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 112 112) + (text "vpll" (rect 5 0 22 12)(font "Arial" )) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inclk0" (rect 0 0 28 12)(font "Arial" )) + (text "inclk0" (rect 21 27 49 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 96 32) + (output) + (text "c0" (rect 0 0 11 12)(font "Arial" )) + (text "c0" (rect 64 27 75 39)(font "Arial" )) + (line (pt 96 32)(pt 80 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 80 80)(line_width 1)) + ) +) diff --git a/bsp3/Angabe/vpll.vhd b/bsp3/Angabe/vpll.vhd new file mode 100644 index 0000000..dbb347f --- /dev/null +++ b/bsp3/Angabe/vpll.vhd @@ -0,0 +1,274 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: vpll.vhd +-- Megafunction Name(s): +-- altpll +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 4.1 Build 181 06/29/2004 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2004 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY vpll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; +-- pllena : IN STD_LOGIC := '1'; +-- areset : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC +-- locked : OUT STD_LOGIC + ); +END vpll; + + +ARCHITECTURE SYN OF vpll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (3 DOWNTO 0); + +signal pllena_int : std_logic; +signal areset_int : std_logic; +signal locked : std_logic; + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_duty_cycle : NATURAL; + lpm_type : STRING; + clk0_multiply_by : NATURAL; + invalid_lock_multiplier : NATURAL; + inclk0_input_frequency : NATURAL; + gate_lock_signal : STRING; + clk0_divide_by : NATURAL; + pll_type : STRING; + valid_lock_multiplier : NATURAL; + clk0_time_delay : STRING; + spread_frequency : NATURAL; + intended_device_family : STRING; + operation_mode : STRING; + compensate_clock : STRING; + clk0_phase_shift : STRING + ); + PORT ( + clkena : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + pllena : IN STD_LOGIC ; + extclkena : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + locked : OUT STD_LOGIC ; + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire3_bv(0 DOWNTO 0) <= "0"; + sub_wire3 <= To_stdlogicvector(sub_wire3_bv); + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= NOT(To_stdlogicvector(sub_wire5_bv)); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + locked <= sub_wire2; + sub_wire4 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire5(0 DOWNTO 0); + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire3(0 DOWNTO 0) & sub_wire6; + sub_wire8 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0); + +areset_int <= '0'; +pllena_int <= '1'; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_duty_cycle => 50, + lpm_type => "altpll", + clk0_multiply_by => 5435, + invalid_lock_multiplier => 5, + inclk0_input_frequency => 30003, + gate_lock_signal => "NO", + clk0_divide_by => 6666, + pll_type => "AUTO", + valid_lock_multiplier => 1, + clk0_time_delay => "0", + spread_frequency => 0, + intended_device_family => "Stratix", + operation_mode => "NORMAL", + compensate_clock => "CLK0", + clk0_phase_shift => "0" + ) + PORT MAP ( + clkena => sub_wire4, + inclk => sub_wire7, + pllena => pllena_int, + extclkena => sub_wire8, + areset => areset_int, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.175" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix" +-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5435" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6666" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" +-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE FALSE diff --git a/bsp3/Protokolle/DigitalDesign_prot.sty b/bsp3/Protokolle/DigitalDesign_prot.sty new file mode 100644 index 0000000..6cb3c1c --- /dev/null +++ b/bsp3/Protokolle/DigitalDesign_prot.sty @@ -0,0 +1,225 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% DigitalDesign_app.sty +% +% Babak Rahbaran +% (rahbaran@ecs.tuwien.ac.at) +% +% 14.07.03 +% +% Institut f"ur Technische Informatik (182/2) +% ECS Group +% Technische Universit"at Wien +% 1040 Treitlstr. 3, 2. Stk. +% (www.ecs.tuwien.ac.at) +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% packages +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\usepackage{fancyheadings} +\usepackage{german} +\usepackage{graphicx} +\usepackage[latin1]{inputenc} %------- Umlaute im Text + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% user-defined commands +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% typeset pin numbers +\newcommand{\pin}[1]{\emph{\textbf{#1}}\ } +\renewcommand{\chaptername}{Aufgabe} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% some size definitions and counter settings +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\oddsidemargin 1cm +\evensidemargin 1cm +\topmargin 0pt +\headsep 50pt +\textheight 21.5cm +\textwidth 14.1cm + +\renewcommand{\floatpagefraction}{0.9} +\renewcommand{\textfraction}{0.05} +\renewcommand{\topfraction}{1.0} +\renewcommand{\bottomfraction}{1.0} + +\setcounter{totalnumber}{3} +\setcounter{bottomnumber}{3} +\setcounter{topnumber}{3} + +\setlength{\unitlength}{1mm} +\setlength{\parindent}{6mm} +\setlength{\parskip}{12pt plus2pt minus2pt} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% define variables used on titlepage +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% heading +\def\headline#1{\gdef\@headline{#1}} +% group number +\def\groupnr#1{\gdef\@groupnr{#1}} +% authors +\def\vornamea#1{\gdef\@vornamea{#1}} +\def\nachnamea#1{\gdef\@nachnamea{#1}} +\def\matrikela#1{\gdef\@matrikela{#1}} +\def\emaila#1{\gdef\@emaila{#1}} + +\def\vornameb#1{\gdef\@vornameb{#1}} +\def\nachnameb#1{\gdef\@nachnameb{#1}} +\def\matrikelb#1{\gdef\@matrikelb{#1}} +\def\emailb#1{\gdef\@emailb{#1}} + +\def\vornamec#1{\gdef\@vornamec{#1}} +\def\nachnamec#1{\gdef\@nachnamec{#1}} +\def\matrikelc#1{\gdef\@matrikelc{#1}} +\def\emailc#1{\gdef\@emailc{#1}} + +%\def\vornamed#1{\gdef\@vornamed{#1}} +%\def\nachnamed#1{\gdef\@nachnamed{#1}} +%\def\matrikeld#1{\gdef\@matrikeld{#1}} +%\def\emaild#1{\gdef\@emaild{#1}} + +% address of department +\def\address#1{\gdef\@address{#1}} +% LVA-Nr. +\def\lvanr#1{\gdef\@aufgabe{#1}} + +\setcounter{footnote}{0} + +% initialize variables +\gdef\@headline{Digital Design LU} +\gdef\@title{P r o t o k o l l} + +\gdef\@groupnr{00} + +\gdef\@vornamea{Vorname1} +\gdef\@nachnamea{Nachname1} +\gdef\@matrikela{0000000} +\gdef\@emaila{a@æstudent.tuwien.ac.at} + +\gdef\@vornameb{Vorname2} +\gdef\@nachnameb{Nachname2} +\gdef\@matrikelb{0000000} +\gdef\@emailb{b@æstudent.tuwien.ac.at} + +\gdef\@vornamec{Vorname3} +\gdef\@nachnamec{Nachname3} +\gdef\@matrikelc{0000000} +\gdef\@emailc{c@student.tuwien.ac.at} + +%\gdef\@vornamed{Vorname4} +%\gdef\@nachnamed{Nachname4} +%\gdef\@matrikeld{0000000} +%\gdef\@emaild{d@student.tuwien.ac.at} + +\gdef\@aufgabe{zu Aufgabe 1} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% titlepage +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\def\maketitle{ +\begin{titlepage} + +% enlarge page +\setlength{\topmargin}{0pt} +\setlength{\headheight}{0pt} +\setlength{\headsep}{0pt} +\setlength{\footskip}{0pt} + +\let\footnotesize\small \let\footnoterule\relax \setcounter{page}{1} +\null +\vfill +\large +\vskip -4 cm + +\begin{center} +% heading +{\LARGE\bf \@headline \par} \vskip 2cm + +\vskip 1cm + +% title +{\Huge\bf\underline \@title \par} +\vskip 1cm +%{\Large \bf \@aufgabe \par} +\vskip 4cm + +\begin{flushright} +Gruppe \@groupnr \par +% authors +\@vornamea \ \@nachnamea, Matr. Nr. \@matrikela \par +{\small \@emaila \par} +\@vornameb \ \@nachnameb, Matr. Nr. \@matrikelb \par +{\small \@emailb \par} +\@vornamec \ \@nachnamec, Matr. Nr. \@matrikelc \par +{\small \@emailc \par} +%\@vornamed \ \@nachnamed, Matr. Nr. \@matrikeld \par +%{\small \@emaild \par} + +%\@authora \par +%\@authorb \par +%\@authorc \par +%\@authord \par +\vskip 1cm +Wien, am~\today{} +\end{flushright} +\end{center} \par +\vskip 1.5cm + +\end{titlepage} + +\setcounter{footnote}{0} +\let\thanks\relax +} % \def\maketitle + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\newenvironment{Ventry}[1]% +{\begin{list}{}{\renewcommand{\makelabel}[1]{\textbf{##1:}\hfill}% +\settowidth{\labelwidth}{\textbf{#1:}}% +\setlength{\leftmargin}{\labelwidth}% +\addtolength{\leftmargin}{\labelsep}}}% +{\end{list}} + +\newcommand{\tablesize}{\fontsize{8}{10}\selectfont} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% layout of non-title pages +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\pagenumbering{roman} +\setlength{\parskip}{5pt plus2pt minus2pt} + +\setlength{\parskip}{1mm} +\clearpage +\setlength{\parskip}{5pt plus2pt minus2pt} + +\pagestyle{fancy} +\renewcommand{\chaptermark}[1]{\markboth{\thechapter\ #1}{}} +\renewcommand{\sectionmark}[1]{\markright{\thesection\ #1}{}} +\addtolength{\headheight}{2pt} + +\pagenumbering{arabic} +\setcounter{page} {1} diff --git a/bsp3/Protokolle/DigitalDesign_prot.tex b/bsp3/Protokolle/DigitalDesign_prot.tex new file mode 100644 index 0000000..acbdaed --- /dev/null +++ b/bsp3/Protokolle/DigitalDesign_prot.tex @@ -0,0 +1,36 @@ + +\documentclass[12pt,a4paper,titlepage,oneside]{report} + + +\usepackage{DigitalDesign_prot} +\sloppy + + +\begin{document} +% create titlepage +\maketitle + +% tables and lists +%\tableofcontents +%\newpage +%\listoffigures +%\newpage +%\listoftables +%\newpage + +% chapters +\input{chapter1} +\input{chapter2} +\input{chapter3} +\input{chapter4} + +% appendices +%\appendix +%\input{app1} + +% bibliography +%\bibliographystyle{alpha} +%\nocite{*} +%\bibliography{DigitalDesign} + +\end{document} diff --git a/bsp3/Protokolle/chapter1.tex b/bsp3/Protokolle/chapter1.tex new file mode 100644 index 0000000..27f796e --- /dev/null +++ b/bsp3/Protokolle/chapter1.tex @@ -0,0 +1,10 @@ +\chapter{Logikanalysator} + + +\begin{itemize} +\item Frequenz HSYNC = Hz +\item Frequenz VSYNC = Hz +\item Farbe Pixel = (r,g,b) +\item Farbe Hintergrund = (r,g,b) +\item x-Koordinate = +\end{itemize} diff --git a/bsp3/Protokolle/chapter2.tex b/bsp3/Protokolle/chapter2.tex new file mode 100644 index 0000000..a8ddc1a --- /dev/null +++ b/bsp3/Protokolle/chapter2.tex @@ -0,0 +1,6 @@ +\chapter{Design-Flow} + +\begin{itemize} +\item Blinkfrequenz = Hz +\end{itemize} + diff --git a/bsp3/Protokolle/chapter3.tex b/bsp3/Protokolle/chapter3.tex new file mode 100644 index 0000000..c6bbec2 --- /dev/null +++ b/bsp3/Protokolle/chapter3.tex @@ -0,0 +1 @@ +\chapter{VHDL} diff --git a/bsp3/Protokolle/chapter4.tex b/bsp3/Protokolle/chapter4.tex new file mode 100644 index 0000000..4b1b7cc --- /dev/null +++ b/bsp3/Protokolle/chapter4.tex @@ -0,0 +1,13 @@ +\chapter{Simulation und Test} + +\begin{itemize} +\item File Syntaxfehler: +\item Zeilennummer Syntaxfehler: + +\item File Semantikfehler 1: +\item Zeilennummer Semantikfehler 1: + +\item File Semantikfehler 2: +\item Zeilennummer Semantikfehler 2: +\end{itemize} + diff --git a/bsp3/Protokolle/prot_1.txt b/bsp3/Protokolle/prot_1.txt new file mode 100644 index 0000000..91a8a82 --- /dev/null +++ b/bsp3/Protokolle/prot_1.txt @@ -0,0 +1,6 @@ + +Frequenz HSYNC = ___ ___ Hz +Frequenz VSYNC = ___ ___ Hz +Farbe Pixel = (r,g,b) +Farbe Hintergrund = (r,g,b) +x-Koordinate = ___ ___ diff --git a/bsp3/Protokolle/prot_2.txt b/bsp3/Protokolle/prot_2.txt new file mode 100644 index 0000000..da24c18 --- /dev/null +++ b/bsp3/Protokolle/prot_2.txt @@ -0,0 +1 @@ +blinker_max = ___ ___ diff --git a/bsp3/Protokolle/prot_4.txt b/bsp3/Protokolle/prot_4.txt new file mode 100644 index 0000000..d45603d --- /dev/null +++ b/bsp3/Protokolle/prot_4.txt @@ -0,0 +1,9 @@ +File Syntaxfehler: ___ ___ +Zeilennummer Syntaxfehler: ___ ___ + +File Semantikfehler 1: ___ ___ +Zeilennummer Semantikfehler 1: ___ ___ + +File Semantikfehler 2: ___ ___ +Zeilennummer Semantikfehler 2: ___ ___ + diff --git a/bsp4/Angabe/board_driver_arc.vhd b/bsp4/Angabe/board_driver_arc.vhd new file mode 100644 index 0000000..7636a37 --- /dev/null +++ b/bsp4/Angabe/board_driver_arc.vhd @@ -0,0 +1,102 @@ +------------------------------------------------------------------------------- +-- Title : board_driver architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : board_driver.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: display number on 7-segment display +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + + +architecture behav of board_driver is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + + signal display_value : std_logic_vector(2*BCD_WIDTH-1 downto 0); + signal ten_value : std_logic_vector(BCD_WIDTH-1 downto 0); + signal one_value : std_logic_vector(BCD_WIDTH-1 downto 0); + signal digit_left : std_logic_vector(SEG_WIDTH-1 downto 0); + signal digit_right : std_logic_vector(SEG_WIDTH-1 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- generate control data + ----------------------------------------------------------------------------- + + + display_value <= "00000001"; -- vector of two BCD coded numbers to be displayed + one_value <= display_value(BCD_WIDTH-1 downto 0); -- BCD number to be displayed in right digit + ten_value <= display_value(2*BCD_WIDTH-1 downto BCD_WIDTH); -- BCD number to be displayed in left digit + + + SEG_DATA: process(reset, one_value, ten_value) + begin + if (reset = RES_ACT) then -- upon reset + digit_left <= DIGIT_OFF; -- ... switch off display + digit_right <= DIGIT_OFF; + else -- during operation + case one_value is -- ...display "one" position according + when "0000" => digit_right <= DIGIT_ZERO; -- ...to translation table + when "0001" => digit_right <= DIGIT_ONE; + when "0010" => digit_right <= DIGIT_TWO; + when "0011" => digit_right <= DIGIT_THREE; + when "0100" => digit_right <= DIGIT_FOUR; + when "0101" => digit_right <= DIGIT_FIVE; + when "0110" => digit_right <= DIGIT_SIX; + when "0111" => digit_right <= DIGIT_SEVEN; + when "1000" => digit_right <= DIGIT_EIGHT; + when "1001" => digit_right <= DIGIT_NINE; + when others => digit_right <= DIGIT_F; -- use "F" as overflow + end case; + + case ten_value is -- same for "ten" position + when "0000" => digit_left <= DIGIT_ZERO; + when "0001" => digit_left <= DIGIT_ONE; + when "0010" => digit_left <= DIGIT_TWO; + when "0011" => digit_left <= DIGIT_THREE; + when "0100" => digit_left <= DIGIT_FOUR; + when "0101" => digit_left <= DIGIT_FIVE; + when "0110" => digit_left <= DIGIT_SIX; + when "0111" => digit_left <= DIGIT_SEVEN; + when "1000" => digit_left <= DIGIT_EIGHT; + when "1001" => digit_left <= DIGIT_NINE; + when others => digit_left <= DIGIT_F; + end case; + end if; + end process; + + +-- combine the two digits to one bus + seven_seg(SEG_WIDTH-1 downto 0) <= digit_right; + seven_seg(2*SEG_WIDTH-1 downto SEG_WIDTH) <= digit_left; + +end behav; diff --git a/bsp4/Angabe/board_driver_ent.vhd b/bsp4/Angabe/board_driver_ent.vhd new file mode 100644 index 0000000..17e5cf7 --- /dev/null +++ b/bsp4/Angabe/board_driver_ent.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- Title : board_driver entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : board_driver_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: display number on 7-segment display +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + +entity board_driver is + + port ( + reset : in std_logic; + seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0) + ); +end board_driver; diff --git a/bsp4/Angabe/dide_16_4.txt b/bsp4/Angabe/dide_16_4.txt new file mode 100644 index 0000000..36d5855 --- /dev/null +++ b/bsp4/Angabe/dide_16_4.txt @@ -0,0 +1,3 @@ +Blinkfrequenz: 12 Hz +Farbe 1: (r,g,b) = (0,0,0) +Farbe 2: (r,g,b) = (0,0,1) diff --git a/bsp4/Angabe/vga.hex b/bsp4/Angabe/vga.hex new file mode 100644 index 0000000..b3c05bd --- /dev/null +++ b/bsp4/Angabe/vga.hex @@ -0,0 +1,4097 @@ +:010000001ce3 +:010001001ce2 +:010002001ce1 +:010003001ce0 +:010004001cdf +:010005001cde +:010006001cdd +:010007001cdc +:010008001cdb +:010009001cda +:01000a001cd9 +:01000b001cd8 +:01000c001cd7 +:01000d001cd6 +:01000e001cd5 +:01000f001cd4 +:010010001cd3 +:010011001cd2 +:010012001cd1 +:010013001cd0 +:010014001ccf +:010015001cce +:010016001ccd +:010017001ccc +:010018001ccb +:010019001cca +:01001a001cc9 +:01001b001cc8 +:01001c001cc7 +:01001d001cc6 +:01001e001cc5 +:01001f001cc4 +:010020001cc3 +:010021001cc2 +:010022001cc1 +:010023001cc0 +:010024001cbf +:010025001cbe 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2006-02-24 +------------------------------------------------------------------------------- +-- Description: arch of top level module, the sub-modules are connected here +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; -- include package + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + +------------------------------------------------------------------------------- +-- component declarations for the modules +------------------------------------------------------------------------------- + + component vga_driver + port ( + clk : in std_logic; + reset : in std_logic; + column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : out std_logic; + v_enable : out std_logic; + hsync : out std_logic; + vsync : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter : out std_logic; + d_set_vsync_counter : out std_logic; + d_set_column_counter : out std_logic; + d_set_line_counter : out std_logic); + end component; + + + component vga_control + port ( + clk : in std_logic; + reset : in std_logic; + column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : in std_logic; + v_enable : in std_logic; + toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + toggle : out std_logic; + r, g, b : out std_logic + ); + end component; + + + component board_driver + port ( + reset : in std_logic; + seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0)); + end component; + + +-- declare signals needed for internal wiring of these components later + signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal h_enable_sig : std_logic; + signal v_enable_sig : std_logic; + signal r_sig, g_sig, b_sig : std_logic; + signal hsync_sig, vsync_sig : std_logic; + +-- declare signals needed for prolongation of reset + signal dly_counter : std_logic_vector(1 downto 0); + signal dly_counter_next : std_logic_vector(1 downto 0); + constant MAX_DLY : std_logic_vector(1 downto 0) := "11"; + signal reset_dly : std_logic; -- + signal safe_reset : std_logic; + + +------------------------------------------------------------------------------- +-- prolong duration of reset to prevent glitches at power-up +------------------------------------------------------------------------------- + +begin + + DELAY_RESET_syn : process(clk_pin) -- synchronous capture + begin + if clk_pin'event and clk_pin = '1' then -- upon rising clock + dly_counter <= dly_counter_next; -- ... capture new counter value + end if; + end process; + + DELAY_RESET_next : process(dly_counter, reset_pin) -- next state logic + begin + if reset_pin = RES_ACT then -- upon reset + dly_counter_next <= (others => '0'); -- ...clear dly counter + elsif dly_counter < MAX_DLY then -- if no oflo + dly_counter_next <= dly_counter + '1'; -- ...increment dly counter + else + dly_counter_next <= dly_counter; -- freeze dly counter when oflo + end if; + end process; + + DELAY_RESET_out: process(dly_counter) + begin + if dly_counter < MAX_DLY then -- until dly counter reaches maximum + reset_dly <= RES_ACT; -- ...activate delayed reset signal + else -- upon counter oflo + reset_dly <= not(RES_ACT); -- ...finally deactivate delayed reset + end if; + end process; + + + + COMBINE_RESET: process(reset_pin, reset_dly) -- generate "safe" reset signal + begin + if reset_pin = RES_ACT or reset_dly = RES_ACT then -- ...by combining delayed reset with non-delayed reset input + safe_reset <= RES_ACT; + else + safe_reset <= not(RES_ACT); + end if; + end process; + + +------------------------------------------------------------------------------- +-- instantiate the components and connect to internal and external signals +------------------------------------------------------------------------------- + + +board_driver_unit : board_driver + port map ( + reset => safe_reset, + seven_seg => seven_seg_pin); + + +vga_driver_unit : vga_driver + port map ( + clk => clk_pin, + reset => safe_reset, + column_counter => column_counter_sig, + line_counter => line_counter_sig, + h_enable => h_enable_sig, + v_enable => v_enable_sig, + hsync => hsync_sig, + vsync => vsync_sig, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter); + +-- make the wiring for hsync and vsync pins +-- (pin is output only => internal _sig version required to allow readback of signal) + vsync_pin <= vsync_sig; + hsync_pin <= hsync_sig; + + + vga_control_unit : vga_control + port map ( + clk => clk_pin, + reset => safe_reset, + column_counter => column_counter_sig, + line_counter => line_counter_sig, + h_enable => h_enable_sig, + v_enable => v_enable_sig, + toggle_counter => d_toggle_counter, + toggle => d_toggle, + r => r_sig, + g => g_sig, + b => b_sig); + +-- make the wiring for RGB pins: drive all pins for same color from one source ("8 color mode") + r0_pin <= r_sig; r1_pin <= r_sig; r2_pin <= r_sig; + g0_pin <= g_sig; g1_pin <= g_sig; g2_pin <= g_sig; + b0_pin <= b_sig; b1_pin <= b_sig; + + +-- make extra pin connections for debug signals + d_hsync <= hsync_sig; -- make duplicate of signal for debug connector + d_vsync <= vsync_sig; -- make duplicate of signal for debug connector + d_column_counter <= column_counter_sig; + d_line_counter <= line_counter_sig; + d_h_enable <= h_enable_sig; + d_v_enable <= v_enable_sig; + d_r <= r_sig; + d_g <= g_sig; + d_b <= b_sig; + d_state_clk <= clk_pin; -- make duplicate of signal for debug connector + + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp4/Angabe/vga_beh_tb.vhd b/bsp4/Angabe/vga_beh_tb.vhd new file mode 100644 index 0000000..c7e990d --- /dev/null +++ b/bsp4/Angabe/vga_beh_tb.vhd @@ -0,0 +1,194 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2007-09-13 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_tb is + +end vga_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture behaviour of vga_tb is + + constant cc : time := 39.7 ns; -- test clock period + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : hsync_state_type; + signal d_vsync_state : vsync_state_type; + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk_pin <= '1'; + wait for cc/2; + clk_pin <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk_pin = '1' and clk_pin'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + +end behaviour; + + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_beh of vga_tb is + for behaviour + for vga_unit : vga use entity work.vga(behav); + end for; + end for; +end vga_conf_beh; + + diff --git a/bsp4/Angabe/vga_control_arc.vhd b/bsp4/Angabe/vga_control_arc.vhd new file mode 100644 index 0000000..7f78d72 --- /dev/null +++ b/bsp4/Angabe/vga_control_arc.vhd @@ -0,0 +1,128 @@ +------------------------------------------------------------------------------- +-- Title : vga_control architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga_control is + + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + + -- signal and constant declarations + signal r_next, g_next, b_next : std_logic; -- auxiliary signals for next state logic + signal toggle_sig : std_logic; -- auxiliary signal to allow read back of toggle + signal toggle_counter_sig : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal to allow read back of blinker + signal toggle_next : std_logic; -- auxiliary signal for next state logic + signal toggle_counter_next : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal for next state logic + constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "1100000000010001111011000"; + -- define half period of toggle frequency in clock ticks + +begin + ----------------------------------------------------------------------------- + -- draw rectangle on screen + ----------------------------------------------------------------------------- + + DRAW_SQUARE_syn: process(clk, reset) + begin + if (reset = RES_ACT) then -- draw black screen upon reset + r <= COLR_OFF; + g <= COLR_OFF; + b <= COLR_OFF; + elsif (clk'event and clk = '1') then -- synchronous capture + r <= r_next; + g <= g_next; + b <= b_next; + end if; + end process; + + + DRAW_SQUARE_next: process (column_counter, line_counter, v_enable, h_enable, toggle_sig) + begin + if v_enable = ENABLE and h_enable = ENABLE then + if (column_counter >= X_MIN and column_counter <= X_MAX and -- if pixel within the rectangle borders + line_counter >= Y_MIN and line_counter <= Y_MAX) then + r_next <= toggle_sig; -- ...red + g_next <= COLR_OFF; -- ...green + b_next <= not toggle_sig; -- ...blue + else -- if somewhere else on screen... + r_next <= COLR_OFF; + g_next <= COLR_OFF; -- ... draw background color + b_next <= COLR_OFF; + end if; + else -- if out of screen... + r_next <= COLR_OFF; + g_next <= COLR_OFF; -- ... do not activate any color + b_next <= COLR_OFF; -- (black screen) + end if; + end process; + + + ----------------------------------------------------------------------------- + -- control blinking of rectangle + ----------------------------------------------------------------------------- + + BLINKER_syn: process(clk, reset) + begin + if (reset = RES_ACT) then -- asyn reset + toggle_counter_sig <= (others => '0'); + toggle_sig <= COLR_OFF; + elsif(clk'event and clk = '1') then -- synchronous capture + toggle_counter_sig <= toggle_counter_next; + toggle_sig <= toggle_next; + end if; + end process; + + + BLINKER_next : process(toggle_counter_sig, toggle_sig) + begin + if toggle_counter_sig >= HALFPERIOD then -- after half period ... + toggle_counter_next <= (others => '0'); -- ... clear counter + toggle_next <= not(toggle_sig); -- ... and toggle colour. + else -- before half period ... + toggle_counter_next <= toggle_counter_sig + '1'; -- ... increment counter + toggle_next <= toggle_sig; -- ... and hold colour + end if; + end process; + + +-- assign auxiliary signals to module outputs +toggle <= toggle_sig; +toggle_counter <= toggle_counter_sig; + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp4/Angabe/vga_control_ent.vhd b/bsp4/Angabe/vga_control_ent.vhd new file mode 100644 index 0000000..2ff5a0a --- /dev/null +++ b/bsp4/Angabe/vga_control_ent.vhd @@ -0,0 +1,53 @@ +------------------------------------------------------------------------------- +-- Title : vga_control entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + + +entity vga_control is + port(clk : in std_logic; + reset : in std_logic; + column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); + toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + toggle : out std_logic; + line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + v_enable : in std_logic; + h_enable : in std_logic; + r, g, b : out std_logic + ); + +end vga_control; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp4/Angabe/vga_driver_arc.vhd b/bsp4/Angabe/vga_driver_arc.vhd new file mode 100644 index 0000000..02aec99 --- /dev/null +++ b/bsp4/Angabe/vga_driver_arc.vhd @@ -0,0 +1,402 @@ +------------------------------------------------------------------------------- +-- Title : vga_driver architecture +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_driver.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2007-09-13 +------------------------------------------------------------------------------- +-- Description: generate hsync and vsync +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-01-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- + +architecture behav of vga_driver is + + attribute syn_preserve : boolean; + attribute syn_preserve of behav : architecture is true; + + constant TIME_A : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100011111"; + constant TIME_B : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0001011010"; + constant TIME_BC : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0010000111"; + constant TIME_BCD : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100000111"; + + constant TIME_O : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000001000"; + constant TIME_P : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000000001"; + constant TIME_PQ : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000100001"; + constant TIME_PQR : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000000001"; + + signal h_sync : std_logic; + signal h_sync_next : std_logic; + + signal hsync_state : hsync_state_type; + signal hsync_state_next : hsync_state_type; + + signal h_enable_sig : std_logic; + signal h_enable_next : std_logic; + + signal set_hsync_counter : std_logic; + signal hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal hsync_counter_next : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + constant HSYN_CNT_MAX : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1111111111"; + + signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal column_counter_next : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal set_column_counter : std_logic; + + signal v_sync : std_logic; + signal v_sync_next : std_logic; + + signal vsync_state : vsync_state_type; + signal vsync_state_next : vsync_state_type; + + signal v_enable_sig : std_logic; + signal v_enable_next : std_logic; + + signal set_vsync_counter : std_logic; + signal vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal vsync_counter_next : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + constant VSYN_CNT_MAX : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1111111111"; + + signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal line_counter_next : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal set_line_counter : std_logic; + + + +begin + +---------------------------------------------------------------------------- +-- Column_Counter [0..639]: calculates column number for next pixel to be displayed +---------------------------------------------------------------------------- + + COLUMN_COUNT_syn: process(clk, reset, column_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + column_counter_sig <= (others => '0'); + else + column_counter_sig <= column_counter_next; -- synchronous capture + end if; + end if; + end process; + + COLUMN_COUNT_next: process(set_column_counter, column_counter_sig) + begin + if set_column_counter = ENABLE then -- reset counter + column_counter_next <= (others => '0'); + else + if column_counter_sig < RIGHT_BORDER then + column_counter_next <= column_counter_sig + '1'; -- increment column + else + column_counter_next <= RIGHT_BORDER; -- ... but do not count beyond right border + end if; + end if; + end process; + +---------------------------------------------------------------------------- +-- Line_counter [0..479]: calculates line number for next pixel to be displayed +---------------------------------------------------------------------------- + + LINE_COUNT_syn: process(clk, reset, line_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + line_counter_sig <= (others => '0'); + else + line_counter_sig <= line_counter_next; -- synchronous capture + end if; + end if; + end process; + + LINE_COUNT_next: process(set_line_counter, line_counter_sig, set_hsync_counter) + begin + if set_line_counter = ENABLE then -- reset counter + line_counter_next <= (others => '0'); + else + if line_counter_sig < BOTTOM_BORDER then + if set_hsync_counter = '1' then -- when enabled + line_counter_next <= line_counter_sig + '1'; -- ... increment line + else + line_counter_next <= line_counter_sig; + end if; + else + line_counter_next <= BOTTOM_BORDER; -- ... but do not count below bottom + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- Hsync_Counter: generates time base for HSYNC State Machine +---------------------------------------------------------------------------- + + HSYNC_COUNT_syn: process(clk, reset, hsync_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + hsync_counter <= (others => '0'); + else + hsync_counter <= hsync_counter_next; -- synchronous capture + end if; + end if; + end process; + + HSYNC_COUNT_next: process(set_hsync_counter, hsync_counter) + begin + if set_hsync_counter = ENABLE then -- reset counter + hsync_counter_next <= (others => '0'); + else + if hsync_counter < HSYN_CNT_MAX then + hsync_counter_next <= hsync_counter + '1'; -- increment time + else + hsync_counter_next <= HSYN_CNT_MAX; -- ... but do not count beyond max period + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- HSYNC STATE MACHINE: generates hsync signal and controls hsync counter & column counter +---------------------------------------------------------------------------- + + HSYNC_FSM_syn: process (clk, reset) -- synchronous capture + begin + if clk'event and clk = '1' then + if reset = RES_ACT then + hsync_state <= RESET_STATE; + h_sync <= '1'; + v_enable_sig <= not(ENABLE); + else + hsync_state <= hsync_state_next; + h_sync <= h_sync_next; + v_enable_sig <= v_enable_next; + end if; + end if; + end process; + + HSYNC_FSM_next : process(hsync_state, hsync_counter, h_sync, v_enable_sig) -- next-state logic + begin -- default assignments + hsync_state_next <= hsync_state; -- ... hold current state + h_sync_next <= h_sync; -- ... and values + v_enable_next <= v_enable_sig; + + case hsync_state is + when RESET_STATE => + h_sync_next <= '0'; -- next signal values are defined here + v_enable_next <= not(ENABLE); + hsync_state_next <= B_STATE; -- ... as well as state transitions + when B_STATE => + h_sync_next <= '0'; + if hsync_counter = TIME_B then + hsync_state_next <= C_STATE; + end if; + when D_STATE => + h_sync_next <= '1'; + if hsync_counter = TIME_BC then + hsync_state_next <= pre_D_STATE; + end if; + when pre_D_STATE => + v_enable_next <= ENABLE; + hsync_state_next <= D_STATE; + when C_STATE => + v_enable_next <= ENABLE; + if hsync_counter = TIME_BCD then + hsync_state_next <= E_STATE; + end if; + when E_STATE => + v_enable_next <= not(ENABLE); + if hsync_counter = TIME_A then + hsync_state_next <= pre_B_STATE; + end if; + when pre_B_STATE => + h_sync_next <= '0'; + v_enable_next <= not(ENABLE); + hsync_state_next <= B_STATE; + when others => + null; + end case; + end process; + + HSYNC_FSM_out : process(hsync_state) -- output logic + begin + set_hsync_counter <= not(ENABLE); -- default assignments + set_column_counter <= not(ENABLE); + + case hsync_state is + when RESET_STATE => -- outputs for each state are defined here + set_hsync_counter <= ENABLE; + when pre_D_STATE => + set_column_counter <= ENABLE; + when pre_B_STATE => + set_hsync_counter <= ENABLE; + when others => + null; + end case; + end process; + + +---------------------------------------------------------------------------- +-- Vsync_Counter: generates time base for VSYNC State Machine +---------------------------------------------------------------------------- + + VSYNC_COUNT_syn: process(clk, reset, vsync_counter_next) + begin + if clk'event and clk = '1' then + if reset = RES_ACT then -- synchronous reset + vsync_counter <= (others => '0'); + else + vsync_counter <= vsync_counter_next; -- synchronous capture + end if; + end if; + end process; + + VSYNC_COUNT_next: process(set_vsync_counter, vsync_counter, set_hsync_counter) + begin + if set_vsync_counter = ENABLE then -- reset counter + vsync_counter_next <= (others => '0'); + else + if vsync_counter < VSYN_CNT_MAX then + if set_hsync_counter = '1' then -- if enabled + vsync_counter_next <= vsync_counter + '1'; -- ... increment time + else + vsync_counter_next <= vsync_counter; + end if; + else + vsync_counter_next <= VSYN_CNT_MAX; -- ... but do not count beyond max period + end if; + end if; + end process; + + +---------------------------------------------------------------------------- +-- VSYNC STATE MACHINE: generates vsync signal and controls vsync counter & line counter +---------------------------------------------------------------------------- + + VSYNC_FSM_syn : process (clk, reset) -- synchronous capture + begin + if clk'event and clk = '1' then + if reset = RES_ACT then + vsync_state <= RESET_STATE; + v_sync <= '1'; + h_enable_sig <= not(ENABLE); + else + vsync_state <= vsync_state_next; + v_sync <= v_sync_next; + h_enable_sig <= h_enable_next; + end if; + end if; + end process; + + VSYNC_FSM_next : process(vsync_state, vsync_counter, v_sync, h_enable_sig) + begin -- next state logic + vsync_state_next <= vsync_state; -- default assignments + v_sync_next <= v_sync; + h_enable_next <= h_enable_sig; + + case vsync_state is -- state transitions and next signals are defined here + when RESET_STATE => + v_sync_next <= '0'; + h_enable_next <= not(ENABLE); + vsync_state_next <= P_STATE; + when P_STATE => + v_sync_next <= '0'; + if vsync_counter = time_p then + vsync_state_next <= Q_STATE; + end if; + when Q_STATE => + v_sync_next <= '1'; + if vsync_counter = time_pq then + vsync_state_next <= pre_R_STATE; + end if; + when pre_R_STATE => + h_enable_next <= ENABLE; + vsync_state_next <= R_STATE; + when R_STATE => + h_enable_next <= ENABLE; + if vsync_counter = time_pqr then + vsync_state_next <= S_STATE; + end if; + when S_STATE => + h_enable_next <= not(ENABLE); + if vsync_counter = time_o then + vsync_state_next <= pre_P_STATE; + end if; + when pre_P_STATE => + v_sync_next <= '0'; + h_enable_next <= not(ENABLE); + vsync_state_next <= P_STATE; + when others => + null; + end case; + end process; + + VSYNC_FSM_out : process(vsync_state) + begin -- output logic + set_vsync_counter <= not(ENABLE); -- output values for each state defined here + set_line_counter <= not(ENABLE); + + case vsync_state is + when RESET_STATE => + set_vsync_counter <= ENABLE; + when pre_R_STATE => + set_line_counter <= ENABLE; + when pre_P_STATE => + set_vsync_counter <= ENABLE; + when others => + null; + end case; + end process; + + + +-- signal wiring for entity (introduced _sig to allow readback of output signals) + + column_counter <= column_counter_sig; + v_enable <= v_enable_sig; + line_counter <= line_counter_sig; + h_enable <= h_enable_sig; + + + hsync <= h_sync; + vsync <= v_sync; + + ----------------------------------------------------------------------------- + -- debug signals + ----------------------------------------------------------------------------- + d_hsync_state <= hsync_state; + d_vsync_state <= vsync_state; + d_hsync_counter <= hsync_counter; + d_vsync_counter <= vsync_counter; + d_set_hsync_counter <= set_hsync_counter; + d_set_vsync_counter <= set_vsync_counter; + d_set_column_counter <= set_column_counter; + d_set_line_counter <= set_line_counter; + +end behav; + +------------------------------------------------------------------------------- +-- END ARCHITECTURE +------------------------------------------------------------------------------- diff --git a/bsp4/Angabe/vga_driver_ent.vhd b/bsp4/Angabe/vga_driver_ent.vhd new file mode 100644 index 0000000..f4c00be --- /dev/null +++ b/bsp4/Angabe/vga_driver_ent.vhd @@ -0,0 +1,60 @@ +------------------------------------------------------------------------------- +-- Title : vga_driver entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_driver_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generate vsync and hsync +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + + +entity vga_driver is + port(clk : in std_logic; + reset : in std_logic; + column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + h_enable : out std_logic; + v_enable : out std_logic; + hsync, vsync : out std_logic; + + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter : out std_logic; + d_set_vsync_counter : out std_logic; + d_set_column_counter : out std_logic; + d_set_line_counter : out std_logic + ); + +end vga_driver; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp4/Angabe/vga_ent.vhd b/bsp4/Angabe/vga_ent.vhd new file mode 100644 index 0000000..b16b96a --- /dev/null +++ b/bsp4/Angabe/vga_ent.vhd @@ -0,0 +1,73 @@ +------------------------------------------------------------------------------- +-- Title : vga entitiy +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2007-09-13 +------------------------------------------------------------------------------- +-- Description: entity of top level module, external pins defined here +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + +entity vga is + port( + input pins from PCB board + clk_pin : in std_logic; -- clock pin + reset_pin : in std_logic; -- reset pins (from switch) +-- output pins to RGB connector / VGA screen + r0_pin, r1_pin, r2_pin : out std_logic; -- to RGB connector "red" + g0_pin, g1_pin, g2_pin : out std_logic; -- to RGB connector "green" + b0_pin, b1_pin : out std_logic; -- to RGB connector "blue" + hsync_pin : out std_logic; -- to RGB connector "Hsync" + vsync_pin : out std_logic; -- to RGB connector "Vsync" +-- output pins to 7-segment display + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); +-- output pins provided for debugging only / logic analyzer + d_hsync, d_vsync : out std_logic; -- copy of hsync_pin, vsync_pin + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0) + ); + +end vga; + +------------------------------------------------------------------------------- +-- END ENTITY +------------------------------------------------------------------------------- diff --git a/bsp4/Angabe/vga_pak.vhd b/bsp4/Angabe/vga_pak.vhd new file mode 100644 index 0000000..61c8adf --- /dev/null +++ b/bsp4/Angabe/vga_pak.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------- +-- Title : vga package +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_pak.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-08-19 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: definitions of global constants and enumerated types +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-08-19 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + + +------------------------------------------------------------------------------- +-- PACKAGE +------------------------------------------------------------------------------- + +package vga_pak is + + constant RES_ACT : std_logic := '0'; -- define reset active LO + constant ENABLE : std_logic := '1'; -- define diverse enable HI + constant COLR_ON : std_logic := '1'; -- define VGA color on as HI + constant COLR_OFF : std_logic := '0'; -- define VGA color off as LO + constant SEG_WIDTH : integer := 7; -- display has 7 segments + constant BCD_WIDTH : integer := 4; -- BCD number has 4 bit + constant TOG_CNT_WIDTH : integer := 25; -- bitwidth of counter that controls blinking + + constant COL_CNT_WIDTH : integer := 10; -- width of the column counter + constant LINE_CNT_WIDTH : integer := 9; -- width of the line counter + constant HSYN_CNT_WIDTH : integer := 10; -- width of the h-sync counter + constant VSYN_CNT_WIDTH : integer := 10; -- width of the v-sync counter + + constant RIGHT_BORDER: std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "1001111111"; -- 640 columns (0...639) + constant BOTTOM_BORDER: std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "111011111"; -- 480 lines (0...479) + + -- define coordinates of rectangle + constant X_MIN : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0001100100"; -- 100 + constant X_MAX : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0011001000"; -- 200 + constant Y_MIN : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "001100100"; + constant Y_MAX : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "011001000"; + + -- define emumerated types for state machines + type hsync_state_type is (RESET_STATE, B_STATE, C_STATE, D_STATE, E_STATE, + pre_D_STATE, pre_B_STATE); + type vsync_state_type is (RESET_STATE, P_STATE, Q_STATE, R_STATE, S_STATE, + pre_R_STATE, pre_P_STATE); + + -- Definitions for 7-segment display gfedcba + constant DIGIT_ZERO : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000000"; + constant DIGIT_ONE : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111001"; + constant DIGIT_TWO : std_logic_vector(SEG_WIDTH-1 downto 0) := "0100100"; + constant DIGIT_THREE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110000"; + constant DIGIT_FOUR : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011001"; + constant DIGIT_FIVE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0010010"; + constant DIGIT_SIX : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000010"; + constant DIGIT_SEVEN : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111000"; + constant DIGIT_EIGHT : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000000"; + constant DIGIT_NINE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011000"; + constant DIGIT_MINUS : std_logic_vector(SEG_WIDTH-1 downto 0) := "0111111"; + constant DIGIT_A : std_logic_vector(SEG_WIDTH-1 downto 0) := "0001000"; + constant DIGIT_B : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000011"; + constant DIGIT_C : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110001"; + constant DIGIT_D : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000010"; + constant DIGIT_E : std_logic_vector(SEG_WIDTH-1 downto 0) := "1001111"; + constant DIGIT_F : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000111"; + constant DIGIT_OFF : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111111"; + +end package; diff --git a/bsp4/Angabe/vga_pll.bdf b/bsp4/Angabe/vga_pll.bdf new file mode 100755 index 0000000..906c435 --- /dev/null +++ b/bsp4/Angabe/vga_pll.bdf @@ -0,0 +1,847 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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512)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 200 528)(line_width 1)) + ) +) +(symbol + (rect 416 56 512 152) + (text "vpll" (rect 5 0 22 12)(font "Arial" )) + (text "inst1" (rect 8 80 31 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inclk0" (rect 0 0 28 12)(font "Arial" )) + (text "inclk0" (rect 21 27 49 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 96 32) + (output) + (text "c0" (rect 0 0 11 12)(font "Arial" )) + (text "c0" (rect 64 27 75 39)(font "Arial" )) + (line (pt 96 32)(pt 80 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 80 80)(line_width 1)) + ) +) +(connector + (pt 512 88) + (pt 712 88) +) diff --git a/bsp4/Angabe/vga_pll.tcl b/bsp4/Angabe/vga_pll.tcl new file mode 100755 index 0000000..c260434 --- /dev/null +++ b/bsp4/Angabe/vga_pll.tcl @@ -0,0 +1,184 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: vga_pll.tcl +# Generated on: Fri Sep 29 09:31:24 2006 + +# Load Quartus II Tcl Project package +package require ::quartus::project +package require ::quartus::flow + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "vga_pll"]} { + puts "Project vga_pll is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists vga_pll]} { + project_open -cmp vga_pll vga_pll + } else { + project_new -cmp vga_pll vga_pll + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + catch { set_global_assignment -name FAMILY Stratix } result + catch { set_global_assignment -name DEVICE EP1S25F672C6 } result + catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result + catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result + catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result + catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result + catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result + catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result + catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result + catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result + catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result + catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result + catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result + catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result + + set_location_assignment PIN_E24 -to b0_pin + set_location_assignment PIN_T6 -to b1_pin + set_location_assignment PIN_N3 -to board_clk + set_location_assignment PIN_E23 -to g0_pin + set_location_assignment PIN_T5 -to g1_pin + set_location_assignment PIN_T24 -to g2_pin + set_location_assignment PIN_F1 -to hsync_pin + set_location_assignment PIN_E22 -to r0_pin + set_location_assignment PIN_T4 -to r1_pin + set_location_assignment PIN_T7 -to r2_pin + set_location_assignment PIN_A5 -to reset + set_location_assignment PIN_F2 -to vsync_pin + set_location_assignment PIN_Y5 -to d_hsync_state[0] + set_location_assignment PIN_F19 -to d_hsync_state[1] + set_location_assignment PIN_F17 -to d_hsync_state[2] + set_location_assignment PIN_Y2 -to d_hsync_state[3] + set_location_assignment PIN_F10 -to d_hsync_state[4] + set_location_assignment PIN_F9 -to d_hsync_state[5] + set_location_assignment PIN_F6 -to d_hsync_state[6] + set_location_assignment PIN_H4 -to d_hsync_counter[0] + set_location_assignment PIN_G25 -to d_hsync_counter[7] + set_location_assignment PIN_G22 -to d_hsync_counter[8] + set_location_assignment PIN_G18 -to d_hsync_counter[9] + set_location_assignment PIN_F5 -to d_vsync_state[0] + set_location_assignment PIN_F4 -to d_vsync_state[1] + set_location_assignment PIN_F3 -to d_vsync_state[2] + set_location_assignment PIN_M19 -to d_vsync_state[3] + set_location_assignment PIN_M18 -to d_vsync_state[4] + set_location_assignment PIN_M7 -to d_vsync_state[5] + set_location_assignment PIN_M4 -to d_vsync_state[6] + set_location_assignment PIN_G9 -to d_vsync_counter[0] + set_location_assignment PIN_G6 -to d_vsync_counter[7] + set_location_assignment PIN_G4 -to d_vsync_counter[8] + set_location_assignment PIN_G2 -to d_vsync_counter[9] + set_location_assignment PIN_K6 -to d_line_counter[0] + set_location_assignment PIN_K4 -to d_line_counter[1] + set_location_assignment PIN_J22 -to d_line_counter[2] + set_location_assignment PIN_M9 -to d_line_counter[3] + set_location_assignment PIN_M8 -to d_line_counter[4] + set_location_assignment PIN_M6 -to d_line_counter[5] + set_location_assignment PIN_M5 -to d_line_counter[6] + set_location_assignment PIN_L24 -to d_line_counter[7] + set_location_assignment PIN_L25 -to d_line_counter[8] + set_location_assignment PIN_L23 -to d_column_counter[0] + set_location_assignment PIN_L22 -to d_column_counter[1] + set_location_assignment PIN_L21 -to d_column_counter[2] + set_location_assignment PIN_L20 -to d_column_counter[3] + set_location_assignment PIN_L6 -to d_column_counter[4] + set_location_assignment PIN_L4 -to d_column_counter[5] + set_location_assignment PIN_L2 -to d_column_counter[6] + set_location_assignment PIN_K23 -to d_column_counter[7] + set_location_assignment PIN_K19 -to d_column_counter[8] + set_location_assignment PIN_K5 -to d_column_counter[9] + set_location_assignment PIN_L7 -to d_hsync + set_location_assignment PIN_L5 -to d_vsync + set_location_assignment PIN_F26 -to d_set_hsync_counter + set_location_assignment PIN_F24 -to d_set_vsync_counter + set_location_assignment PIN_F21 -to d_set_line_counter + set_location_assignment PIN_Y23 -to d_set_column_counter + set_location_assignment PIN_L3 -to d_r + set_location_assignment PIN_K24 -to d_g + set_location_assignment PIN_K20 -to d_b + set_location_assignment PIN_H18 -to d_v_enable + set_location_assignment PIN_J21 -to d_h_enable + set_location_assignment PIN_R8 -to seven_seg_pin[0] + set_location_assignment PIN_R9 -to seven_seg_pin[1] + set_location_assignment PIN_R19 -to seven_seg_pin[2] + set_location_assignment PIN_R20 -to seven_seg_pin[3] + set_location_assignment PIN_R21 -to seven_seg_pin[4] + set_location_assignment PIN_R22 -to seven_seg_pin[5] + set_location_assignment PIN_R23 -to seven_seg_pin[6] + set_location_assignment PIN_Y11 -to seven_seg_pin[7] + set_location_assignment PIN_N7 -to seven_seg_pin[8] + set_location_assignment PIN_N8 -to seven_seg_pin[9] + set_location_assignment PIN_R4 -to seven_seg_pin[10] + set_location_assignment PIN_R6 -to seven_seg_pin[11] + set_location_assignment PIN_AA11 -to seven_seg_pin[12] + set_location_assignment PIN_T2 -to seven_seg_pin[13] + set_location_assignment PIN_K3 -to d_state_clk + set_location_assignment PIN_H3 -to d_toggle + set_location_assignment PIN_H26 -to d_toggle_counter[0] + set_location_assignment PIN_G24 -to d_toggle_counter[15] + set_location_assignment PIN_G23 -to d_toggle_counter[16] + set_location_assignment PIN_G21 -to d_toggle_counter[17] + set_location_assignment PIN_G20 -to d_toggle_counter[18] + set_location_assignment PIN_G5 -to d_toggle_counter[19] + set_location_assignment PIN_G3 -to d_toggle_counter[20] + set_location_assignment PIN_G1 -to d_toggle_counter[21] + set_location_assignment PIN_F25 -to d_toggle_counter[22] + set_location_assignment PIN_F23 -to d_toggle_counter[23] + set_location_assignment PIN_T19 -to d_toggle_counter[24] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin + + + # Commit assignments + export_assignments + +execute_flow -compile + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/bsp4/Angabe/vga_pos_tb.vhd b/bsp4/Angabe/vga_pos_tb.vhd new file mode 100644 index 0000000..ebcff70 --- /dev/null +++ b/bsp4/Angabe/vga_pos_tb.vhd @@ -0,0 +1,198 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pos_tb is + +end vga_pos_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pos_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(1000000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pos of vga_pos_tb is + for structure + for vga_unit : vga use entity work.vga(structure); + end for; + end for; +end vga_conf_pos; + + + diff --git a/bsp4/Angabe/vga_pre_tb.vhd b/bsp4/Angabe/vga_pre_tb.vhd new file mode 100644 index 0000000..dc010f7 --- /dev/null +++ b/bsp4/Angabe/vga_pre_tb.vhd @@ -0,0 +1,197 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2006-09-29 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_pre_tb is + +end vga_pre_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture structure of vga_pre_tb is + + constant cc : time := 39.7 ns; -- test clock period + + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out std_logic_vector(0 to 6); + d_vsync_state : out std_logic_vector(0 to 6); + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : std_logic_vector(0 to 6); + signal d_vsync_state : std_logic_vector(0 to 6); + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + signal clk : std_logic; + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk <= '1'; + wait for cc/2; + clk <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk = '1' and clk'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + + clk_pin <= clk; + +end structure; + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_pre of vga_pre_tb is + for structure + for vga_unit : vga use entity work.vga(beh); + end for; + end for; +end vga_conf_pre; + + + diff --git a/bsp4/Angabe/vpll.bsf b/bsp4/Angabe/vpll.bsf new file mode 100644 index 0000000..63c3118 --- /dev/null +++ b/bsp4/Angabe/vpll.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2004 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 112 112) + (text "vpll" (rect 5 0 22 12)(font "Arial" )) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inclk0" (rect 0 0 28 12)(font "Arial" )) + (text "inclk0" (rect 21 27 49 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 96 32) + (output) + (text "c0" (rect 0 0 11 12)(font "Arial" )) + (text "c0" (rect 64 27 75 39)(font "Arial" )) + (line (pt 96 32)(pt 80 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 80 80)(line_width 1)) + ) +) diff --git a/bsp4/Angabe/vpll.vhd b/bsp4/Angabe/vpll.vhd new file mode 100644 index 0000000..dbb347f --- /dev/null +++ b/bsp4/Angabe/vpll.vhd @@ -0,0 +1,274 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: vpll.vhd +-- Megafunction Name(s): +-- altpll +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 4.1 Build 181 06/29/2004 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2004 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY vpll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; +-- pllena : IN STD_LOGIC := '1'; +-- areset : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC +-- locked : OUT STD_LOGIC + ); +END vpll; + + +ARCHITECTURE SYN OF vpll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (3 DOWNTO 0); + +signal pllena_int : std_logic; +signal areset_int : std_logic; +signal locked : std_logic; + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_duty_cycle : NATURAL; + lpm_type : STRING; + clk0_multiply_by : NATURAL; + invalid_lock_multiplier : NATURAL; + inclk0_input_frequency : NATURAL; + gate_lock_signal : STRING; + clk0_divide_by : NATURAL; + pll_type : STRING; + valid_lock_multiplier : NATURAL; + clk0_time_delay : STRING; + spread_frequency : NATURAL; + intended_device_family : STRING; + operation_mode : STRING; + compensate_clock : STRING; + clk0_phase_shift : STRING + ); + PORT ( + clkena : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + pllena : IN STD_LOGIC ; + extclkena : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + locked : OUT STD_LOGIC ; + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire3_bv(0 DOWNTO 0) <= "0"; + sub_wire3 <= To_stdlogicvector(sub_wire3_bv); + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= NOT(To_stdlogicvector(sub_wire5_bv)); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + locked <= sub_wire2; + sub_wire4 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire5(0 DOWNTO 0); + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire3(0 DOWNTO 0) & sub_wire6; + sub_wire8 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0); + +areset_int <= '0'; +pllena_int <= '1'; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_duty_cycle => 50, + lpm_type => "altpll", + clk0_multiply_by => 5435, + invalid_lock_multiplier => 5, + inclk0_input_frequency => 30003, + gate_lock_signal => "NO", + clk0_divide_by => 6666, + pll_type => "AUTO", + valid_lock_multiplier => 1, + clk0_time_delay => "0", + spread_frequency => 0, + intended_device_family => "Stratix", + operation_mode => "NORMAL", + compensate_clock => "CLK0", + clk0_phase_shift => "0" + ) + PORT MAP ( + clkena => sub_wire4, + inclk => sub_wire7, + pllena => pllena_int, + extclkena => sub_wire8, + areset => areset_int, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.175" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix" +-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5435" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6666" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" +-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE FALSE diff --git a/bsp4/Protokolle/DigitalDesign_prot.sty b/bsp4/Protokolle/DigitalDesign_prot.sty new file mode 100644 index 0000000..6cb3c1c --- /dev/null +++ b/bsp4/Protokolle/DigitalDesign_prot.sty @@ -0,0 +1,225 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% DigitalDesign_app.sty +% +% Babak Rahbaran +% (rahbaran@ecs.tuwien.ac.at) +% +% 14.07.03 +% +% Institut f"ur Technische Informatik (182/2) +% ECS Group +% Technische Universit"at Wien +% 1040 Treitlstr. 3, 2. Stk. +% (www.ecs.tuwien.ac.at) +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% packages +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\usepackage{fancyheadings} +\usepackage{german} +\usepackage{graphicx} +\usepackage[latin1]{inputenc} %------- Umlaute im Text + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% user-defined commands +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% typeset pin numbers +\newcommand{\pin}[1]{\emph{\textbf{#1}}\ } +\renewcommand{\chaptername}{Aufgabe} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% some size definitions and counter settings +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\oddsidemargin 1cm +\evensidemargin 1cm +\topmargin 0pt +\headsep 50pt +\textheight 21.5cm +\textwidth 14.1cm + +\renewcommand{\floatpagefraction}{0.9} +\renewcommand{\textfraction}{0.05} +\renewcommand{\topfraction}{1.0} +\renewcommand{\bottomfraction}{1.0} + +\setcounter{totalnumber}{3} +\setcounter{bottomnumber}{3} +\setcounter{topnumber}{3} + +\setlength{\unitlength}{1mm} +\setlength{\parindent}{6mm} +\setlength{\parskip}{12pt plus2pt minus2pt} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% define variables used on titlepage +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% heading +\def\headline#1{\gdef\@headline{#1}} +% group number +\def\groupnr#1{\gdef\@groupnr{#1}} +% authors +\def\vornamea#1{\gdef\@vornamea{#1}} +\def\nachnamea#1{\gdef\@nachnamea{#1}} +\def\matrikela#1{\gdef\@matrikela{#1}} +\def\emaila#1{\gdef\@emaila{#1}} + +\def\vornameb#1{\gdef\@vornameb{#1}} +\def\nachnameb#1{\gdef\@nachnameb{#1}} +\def\matrikelb#1{\gdef\@matrikelb{#1}} +\def\emailb#1{\gdef\@emailb{#1}} + +\def\vornamec#1{\gdef\@vornamec{#1}} +\def\nachnamec#1{\gdef\@nachnamec{#1}} +\def\matrikelc#1{\gdef\@matrikelc{#1}} +\def\emailc#1{\gdef\@emailc{#1}} + +%\def\vornamed#1{\gdef\@vornamed{#1}} +%\def\nachnamed#1{\gdef\@nachnamed{#1}} +%\def\matrikeld#1{\gdef\@matrikeld{#1}} +%\def\emaild#1{\gdef\@emaild{#1}} + +% address of department +\def\address#1{\gdef\@address{#1}} +% LVA-Nr. +\def\lvanr#1{\gdef\@aufgabe{#1}} + +\setcounter{footnote}{0} + +% initialize variables +\gdef\@headline{Digital Design LU} +\gdef\@title{P r o t o k o l l} + +\gdef\@groupnr{00} + +\gdef\@vornamea{Vorname1} +\gdef\@nachnamea{Nachname1} +\gdef\@matrikela{0000000} +\gdef\@emaila{a@æstudent.tuwien.ac.at} + +\gdef\@vornameb{Vorname2} +\gdef\@nachnameb{Nachname2} +\gdef\@matrikelb{0000000} +\gdef\@emailb{b@æstudent.tuwien.ac.at} + +\gdef\@vornamec{Vorname3} +\gdef\@nachnamec{Nachname3} +\gdef\@matrikelc{0000000} +\gdef\@emailc{c@student.tuwien.ac.at} + +%\gdef\@vornamed{Vorname4} +%\gdef\@nachnamed{Nachname4} +%\gdef\@matrikeld{0000000} +%\gdef\@emaild{d@student.tuwien.ac.at} + +\gdef\@aufgabe{zu Aufgabe 1} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% titlepage +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\def\maketitle{ +\begin{titlepage} + +% enlarge page +\setlength{\topmargin}{0pt} +\setlength{\headheight}{0pt} +\setlength{\headsep}{0pt} +\setlength{\footskip}{0pt} + +\let\footnotesize\small \let\footnoterule\relax \setcounter{page}{1} +\null +\vfill +\large +\vskip -4 cm + +\begin{center} +% heading +{\LARGE\bf \@headline \par} \vskip 2cm + +\vskip 1cm + +% title +{\Huge\bf\underline \@title \par} +\vskip 1cm +%{\Large \bf \@aufgabe \par} +\vskip 4cm + +\begin{flushright} +Gruppe \@groupnr \par +% authors +\@vornamea \ \@nachnamea, Matr. Nr. \@matrikela \par +{\small \@emaila \par} +\@vornameb \ \@nachnameb, Matr. Nr. \@matrikelb \par +{\small \@emailb \par} +\@vornamec \ \@nachnamec, Matr. Nr. \@matrikelc \par +{\small \@emailc \par} +%\@vornamed \ \@nachnamed, Matr. Nr. \@matrikeld \par +%{\small \@emaild \par} + +%\@authora \par +%\@authorb \par +%\@authorc \par +%\@authord \par +\vskip 1cm +Wien, am~\today{} +\end{flushright} +\end{center} \par +\vskip 1.5cm + +\end{titlepage} + +\setcounter{footnote}{0} +\let\thanks\relax +} % \def\maketitle + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\newenvironment{Ventry}[1]% +{\begin{list}{}{\renewcommand{\makelabel}[1]{\textbf{##1:}\hfill}% +\settowidth{\labelwidth}{\textbf{#1:}}% +\setlength{\leftmargin}{\labelwidth}% +\addtolength{\leftmargin}{\labelsep}}}% +{\end{list}} + +\newcommand{\tablesize}{\fontsize{8}{10}\selectfont} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% layout of non-title pages +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\pagenumbering{roman} +\setlength{\parskip}{5pt plus2pt minus2pt} + +\setlength{\parskip}{1mm} +\clearpage +\setlength{\parskip}{5pt plus2pt minus2pt} + +\pagestyle{fancy} +\renewcommand{\chaptermark}[1]{\markboth{\thechapter\ #1}{}} +\renewcommand{\sectionmark}[1]{\markright{\thesection\ #1}{}} +\addtolength{\headheight}{2pt} + +\pagenumbering{arabic} +\setcounter{page} {1} diff --git a/bsp4/Protokolle/DigitalDesign_prot.tex b/bsp4/Protokolle/DigitalDesign_prot.tex new file mode 100644 index 0000000..acbdaed --- /dev/null +++ b/bsp4/Protokolle/DigitalDesign_prot.tex @@ -0,0 +1,36 @@ + +\documentclass[12pt,a4paper,titlepage,oneside]{report} + + +\usepackage{DigitalDesign_prot} +\sloppy + + +\begin{document} +% create titlepage +\maketitle + +% tables and lists +%\tableofcontents +%\newpage +%\listoffigures +%\newpage +%\listoftables +%\newpage + +% chapters +\input{chapter1} +\input{chapter2} +\input{chapter3} +\input{chapter4} + +% appendices +%\appendix +%\input{app1} + +% bibliography +%\bibliographystyle{alpha} +%\nocite{*} +%\bibliography{DigitalDesign} + +\end{document} diff --git a/bsp4/Protokolle/chapter1.tex b/bsp4/Protokolle/chapter1.tex new file mode 100644 index 0000000..27f796e --- /dev/null +++ b/bsp4/Protokolle/chapter1.tex @@ -0,0 +1,10 @@ +\chapter{Logikanalysator} + + +\begin{itemize} +\item Frequenz HSYNC = Hz +\item Frequenz VSYNC = Hz +\item Farbe Pixel = (r,g,b) +\item Farbe Hintergrund = (r,g,b) +\item x-Koordinate = +\end{itemize} diff --git a/bsp4/Protokolle/chapter2.tex b/bsp4/Protokolle/chapter2.tex new file mode 100644 index 0000000..a8ddc1a --- /dev/null +++ b/bsp4/Protokolle/chapter2.tex @@ -0,0 +1,6 @@ +\chapter{Design-Flow} + +\begin{itemize} +\item Blinkfrequenz = Hz +\end{itemize} + diff --git a/bsp4/Protokolle/chapter3.tex b/bsp4/Protokolle/chapter3.tex new file mode 100644 index 0000000..c6bbec2 --- /dev/null +++ b/bsp4/Protokolle/chapter3.tex @@ -0,0 +1 @@ +\chapter{VHDL} diff --git a/bsp4/Protokolle/chapter4.tex b/bsp4/Protokolle/chapter4.tex new file mode 100644 index 0000000..4b1b7cc --- /dev/null +++ b/bsp4/Protokolle/chapter4.tex @@ -0,0 +1,13 @@ +\chapter{Simulation und Test} + +\begin{itemize} +\item File Syntaxfehler: +\item Zeilennummer Syntaxfehler: + +\item File Semantikfehler 1: +\item Zeilennummer Semantikfehler 1: + +\item File Semantikfehler 2: +\item Zeilennummer Semantikfehler 2: +\end{itemize} + diff --git a/bsp4/Protokolle/prot_1.txt b/bsp4/Protokolle/prot_1.txt new file mode 100644 index 0000000..91a8a82 --- /dev/null +++ b/bsp4/Protokolle/prot_1.txt @@ -0,0 +1,6 @@ + +Frequenz HSYNC = ___ ___ Hz +Frequenz VSYNC = ___ ___ Hz +Farbe Pixel = (r,g,b) +Farbe Hintergrund = (r,g,b) +x-Koordinate = ___ ___ diff --git a/bsp4/Protokolle/prot_2.txt b/bsp4/Protokolle/prot_2.txt new file mode 100644 index 0000000..da24c18 --- /dev/null +++ b/bsp4/Protokolle/prot_2.txt @@ -0,0 +1 @@ +blinker_max = ___ ___ diff --git a/bsp4/Protokolle/prot_4.txt b/bsp4/Protokolle/prot_4.txt new file mode 100644 index 0000000..d45603d --- /dev/null +++ b/bsp4/Protokolle/prot_4.txt @@ -0,0 +1,9 @@ +File Syntaxfehler: ___ ___ +Zeilennummer Syntaxfehler: ___ ___ + +File Semantikfehler 1: ___ ___ +Zeilennummer Semantikfehler 1: ___ ___ + +File Semantikfehler 2: ___ ___ +Zeilennummer Semantikfehler 2: ___ ___ +