--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus II " "Info: Running Quartus II Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:45:00 2009 " "Info: Processing started: Wed Oct 28 14:45:00 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll --generate_symbol=/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll --generate_symbol=/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus II " "Info: Quartus II Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "176 " "Info: Peak virtual memory: 176 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:45:03 2009 " "Info: Processing ended: Wed Oct 28 14:45:03 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:55:16 2009 " "Info: Processing started: Wed Oct 28 14:55:16 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "269 " "Info: Peak virtual memory: 269 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:55:34 2009 " "Info: Processing ended: Wed Oct 28 14:55:34 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Info: Total CPU time (on all processors): 00:00:18" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="vga_pll">
+ </PROJECT>
+</LOG_ROOT>
--- /dev/null
+<kpt_db name="vga_pll.cmp" kpt_version="1.1">
+ <key_points_set type="reference" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transition" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transformed" hier_sep="|">
+ </key_points_set>
+ <transformations_set hier_sep="|">
+ </transformations_set>
+</kpt_db>
--- /dev/null
+Quartus_Version = Version 9.0 Build 132 02/25/2009 SJ Full Version
+Version_Index = 167805952
+Creation_Time = Wed Oct 28 14:44:43 2009
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:55:40 2009 " "Info: Processing started: Wed Oct 28 14:55:40 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "vga_pll.vo vga_pll_v.sdo /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/simulation/modelsim/ simulation " "Info: Generated files \"vga_pll.vo\" and \"vga_pll_v.sdo\" in directory \"/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/simulation/modelsim/\" for EDA simulation tool" { } { } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Peak virtual memory: 162 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:55:41 2009 " "Info: Processing ended: Wed Oct 28 14:55:41 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:54:43 2009 " "Info: Processing started: Wed Oct 28 14:54:43 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "vga_pll EP1S25F672C6 " "Info: Selected device EP1S25F672C6 for design \"vga_pll\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 vpll:inst1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"vpll:inst1\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd" 121 0 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 56 416 512 152 "inst1" "" } } } } } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F672C6 " "Info: Device EP1S10F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F672C6 " "Info: Device EP1S20F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE " "Info: Device EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ F16 " "Info: Pin ~DATA0~ is reserved at location F16" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { ~DATA0~ } } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 117 " "Warning: No exact pin location assignment(s) for 26 pins of 117 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[6\] " "Info: Pin d_hsync_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[6] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[6\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5391 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[5\] " "Info: Pin d_hsync_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[5] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[5\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5404 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[4\] " "Info: Pin d_hsync_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[4] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[4\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5417 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[3\] " "Info: Pin d_hsync_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[3] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[3\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5430 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[2\] " "Info: Pin d_hsync_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[2] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[2\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5443 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[1\] " "Info: Pin d_hsync_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[1] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[1\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5456 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[14\] " "Info: Pin d_toggle_counter\[14\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[14] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4728 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[13\] " "Info: Pin d_toggle_counter\[13\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[13] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4741 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[12\] " "Info: Pin d_toggle_counter\[12\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[12] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4754 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[11\] " "Info: Pin d_toggle_counter\[11\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[11] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4767 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[10\] " "Info: Pin d_toggle_counter\[10\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[10] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4780 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[9\] " "Info: Pin d_toggle_counter\[9\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[9] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4793 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[8\] " "Info: Pin d_toggle_counter\[8\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[8] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4806 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[7\] " "Info: Pin d_toggle_counter\[7\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[7] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4819 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[6\] " "Info: Pin d_toggle_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4832 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[5\] " "Info: Pin d_toggle_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4845 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[4\] " "Info: Pin d_toggle_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4858 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[3\] " "Info: Pin d_toggle_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4871 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[2\] " "Info: Pin d_toggle_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[2] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4884 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[1\] " "Info: Pin d_toggle_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[1] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4897 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[6\] " "Info: Pin d_vsync_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[6] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[6\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5261 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[5\] " "Info: Pin d_vsync_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[5] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[5\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5274 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[4\] " "Info: Pin d_vsync_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[4] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[4\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5287 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[3\] " "Info: Pin d_vsync_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[3] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[3\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5300 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[2\] " "Info: Pin d_vsync_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[2] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[2\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5313 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[1\] " "Info: Pin d_vsync_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[1] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[1\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5326 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "vpll:inst1\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"vpll:inst1\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "vpll:inst1\|altpll:altpll_component\|_clk0 31 38 0 -18 " "Info: Implementing clock multiplication of 31, clock division of 38, and phase shift of 0 degrees (-18 ps) for vpll:inst1\|altpll:altpll_component\|_clk0 port" { } { } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd" 121 0 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 56 416 512 152 "inst1" "" } } } } } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "vpll:inst1\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"vpll:inst1\|altpll:altpll_component\|_clk0\" to use global clock" { } { { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "vpll:inst1\|altpll:altpll_component\|_clk0" } } } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 56 416 512 152 "inst1" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 592 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0 "" 0 -1} } { } 0 0 "Promoted PLL clock signals" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x Global clock " "Info: Automatically promoted some destinations of signal \"vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|hsync_state_6_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_6_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 116 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_0_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_0_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 109 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_1_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_1_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 108 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|v_enable_sig_Z " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|v_enable_sig_Z\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 151 22 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_Z " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_Z\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 150 22 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_5_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_5_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 104 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_4_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_4_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_3_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_3_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 105 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_2_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_2_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 103 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" { } { } 0 0 "Limited to %1!d! non-global destinations" 0 0 "" 0 -1} } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Start inferring scan chains for DSP blocks" { } { } 1 0 "Start inferring scan chains for DSP blocks" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Inferring scan chains for DSP blocks is complete" { } { } 1 0 "Inferring scan chains for DSP blocks is complete" 1 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "26 unused 3.3V 0 26 0 " "Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 0 input, 26 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 11 50 " "Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 11 total pin(s) used -- 50 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 31 28 " "Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 31 total pin(s) used -- 28 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 6 48 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 6 total pin(s) used -- 48 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 8 48 " "Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used -- 48 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 26 33 " "Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used -- 33 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 8 53 " "Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used -- 53 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 57 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 57 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 2 52 " "Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used -- 52 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use undetermined 0 6 " "Info: I/O bank number 11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Info: Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3 register vga:inst\|vga_control:vga_control_unit\|r 29.678 ns " "Info: Slack time is 29.678 ns between source register \"vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3\" and destination register \"vga:inst\|vga_control:vga_control_unit\|r\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.591 ns + Largest register register " "Info: + Largest register to register requirement is 36.591 ns" { } { } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.138 ns Shortest register " "Info: Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_control:vga_control_unit\|r 2 REG Unassigned 4 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst\|vga_control:vga_control_unit\|r'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.138 ns Longest register " "Info: Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_control:vga_control_unit\|r 2 REG Unassigned 4 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst\|vga_control:vga_control_unit\|r'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.138 ns Shortest register " "Info: Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3 2 REG Unassigned 10 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 10; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 95 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.138 ns Longest register " "Info: Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3 2 REG Unassigned 10 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 10; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 95 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns " "Info: Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 95 28 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns " "Info: Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.913 ns - Longest register register " "Info: - Longest register to register delay is 6.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3 1 REG Unassigned 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 10; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 95 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.087 ns) 1.093 ns vga:inst\|vga_control:vga_control_unit\|un17_v_enablelto3 2 COMB Unassigned 1 " "Info: 2: + IC(1.006 ns) + CELL(0.087 ns) = 1.093 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|un17_v_enablelto3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.093 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 vga:inst|vga_control:vga_control_unit|un17_v_enablelto3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3295 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.825 ns) + CELL(0.087 ns) 3.005 ns vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4_a 3 COMB Unassigned 1 " "Info: 3: + IC(1.825 ns) + CELL(0.087 ns) = 3.005 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4_a'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.912 ns" { vga:inst|vga_control:vga_control_unit|un17_v_enablelto3 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3294 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 3.519 ns vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4 4 COMB Unassigned 2 " "Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 3.519 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3286 27 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.030 ns) + CELL(0.364 ns) 6.913 ns vga:inst\|vga_control:vga_control_unit\|r 5 REG Unassigned 4 " "Info: 5: + IC(3.030 ns) + CELL(0.364 ns) = 6.913 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst\|vga_control:vga_control_unit\|r'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.394 ns" { vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.625 ns ( 9.04 % ) " "Info: Total cell delay = 0.625 ns ( 9.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.288 ns ( 90.96 % ) " "Info: Total interconnect delay = 6.288 ns ( 90.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.913 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 vga:inst|vga_control:vga_control_unit|un17_v_enablelto3 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.913 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 vga:inst|vga_control:vga_control_unit|un17_v_enablelto3 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.913 ns register register " "Info: Estimated most critical path is register to register delay of 6.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3 1 REG LAB_X21_Y42 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y42; Fanout = 10; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 95 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.087 ns) 1.093 ns vga:inst\|vga_control:vga_control_unit\|un17_v_enablelto3 2 COMB LAB_X18_Y42 1 " "Info: 2: + IC(1.006 ns) + CELL(0.087 ns) = 1.093 ns; Loc. = LAB_X18_Y42; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|un17_v_enablelto3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.093 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 vga:inst|vga_control:vga_control_unit|un17_v_enablelto3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3295 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.825 ns) + CELL(0.087 ns) 3.005 ns vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4_a 3 COMB LAB_X28_Y35 1 " "Info: 3: + IC(1.825 ns) + CELL(0.087 ns) = 3.005 ns; Loc. = LAB_X28_Y35; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4_a'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.912 ns" { vga:inst|vga_control:vga_control_unit|un17_v_enablelto3 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3294 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 3.519 ns vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4 4 COMB LAB_X28_Y35 2 " "Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 3.519 ns; Loc. = LAB_X28_Y35; Fanout = 2; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3286 27 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.030 ns) + CELL(0.364 ns) 6.913 ns vga:inst\|vga_control:vga_control_unit\|r 5 REG LAB_X72_Y6 4 " "Info: 5: + IC(3.030 ns) + CELL(0.364 ns) = 6.913 ns; Loc. = LAB_X72_Y6; Fanout = 4; REG Node = 'vga:inst\|vga_control:vga_control_unit\|r'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.394 ns" { vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.625 ns ( 9.04 % ) " "Info: Total cell delay = 0.625 ns ( 9.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.288 ns ( 90.96 % ) " "Info: Total interconnect delay = 6.288 ns ( 90.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.913 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 vga:inst|vga_control:vga_control_unit|un17_v_enablelto3 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X22_Y36 X33_Y47 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X22_Y36 to location X33_Y47" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "14 " "Warning: Following 14 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_g GND " "Info: Pin d_g has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_g } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_g" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5144 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_g } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "g0_pin GND " "Info: Pin g0_pin has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { g0_pin } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "g0_pin" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6041 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { g0_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "g1_pin GND " "Info: Pin g1_pin has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { g1_pin } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "g1_pin" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6028 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { g1_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "g2_pin GND " "Info: Pin g2_pin has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { g2_pin } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "g2_pin" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6015 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { g2_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_toggle_counter\[24\] GND " "Info: Pin d_toggle_counter\[24\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[24] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_toggle_counter\[24\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4598 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_toggle_counter\[23\] GND " "Info: Pin d_toggle_counter\[23\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[23] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_toggle_counter\[23\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4611 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_toggle_counter\[22\] GND " "Info: Pin d_toggle_counter\[22\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[22] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_toggle_counter\[22\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4624 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_toggle_counter\[21\] GND " "Info: Pin d_toggle_counter\[21\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[21] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_toggle_counter\[21\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4637 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[13\] GND " "Info: Pin seven_seg_pin\[13\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[13] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[13\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5781 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[6\] GND " "Info: Pin seven_seg_pin\[6\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[6] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[6\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5872 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[5\] GND " "Info: Pin seven_seg_pin\[5\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[5] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[5\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5885 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[4\] GND " "Info: Pin seven_seg_pin\[4\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[4] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[4\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5898 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[3\] GND " "Info: Pin seven_seg_pin\[3\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[3] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[3\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5911 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[0\] GND " "Info: Pin seven_seg_pin\[0\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[0] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[0\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5950 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/vga_pll.fit.smsg " "Info: Generated suppressed messages file /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/vga_pll.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "320 " "Info: Peak virtual memory: 320 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:55:12 2009 " "Info: Processing ended: Wed Oct 28 14:55:12 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Info: Elapsed time: 00:00:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:29 " "Info: Total CPU time (on all processors): 00:00:29" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+|vga_pll
+d_hsync <= vga:inst.d_hsync
+board_clk => vpll:inst1.inclk0
+reset => vga:inst.reset_pin
+d_vsync <= vga:inst.d_vsync
+d_set_column_counter <= vga:inst.d_set_column_counter
+d_set_line_counter <= vga:inst.d_set_line_counter
+d_set_hsync_counter <= vga:inst.d_set_hsync_counter
+d_set_vsync_counter <= vga:inst.d_set_vsync_counter
+d_r <= vga:inst.d_r
+d_g <= vga:inst.d_g
+d_b <= vga:inst.d_b
+d_h_enable <= vga:inst.d_h_enable
+d_v_enable <= vga:inst.d_v_enable
+d_state_clk <= vga:inst.d_state_clk
+d_toggle <= vga:inst.d_toggle
+r0_pin <= vga:inst.r0_pin
+r1_pin <= vga:inst.r1_pin
+r2_pin <= vga:inst.r2_pin
+g0_pin <= vga:inst.g0_pin
+g1_pin <= vga:inst.g1_pin
+g2_pin <= vga:inst.g2_pin
+b0_pin <= vga:inst.b0_pin
+b1_pin <= vga:inst.b1_pin
+hsync_pin <= vga:inst.hsync_pin
+vsync_pin <= vga:inst.vsync_pin
+d_column_counter[0] <= vga:inst.d_column_counter[0]
+d_column_counter[1] <= vga:inst.d_column_counter[1]
+d_column_counter[2] <= vga:inst.d_column_counter[2]
+d_column_counter[3] <= vga:inst.d_column_counter[3]
+d_column_counter[4] <= vga:inst.d_column_counter[4]
+d_column_counter[5] <= vga:inst.d_column_counter[5]
+d_column_counter[6] <= vga:inst.d_column_counter[6]
+d_column_counter[7] <= vga:inst.d_column_counter[7]
+d_column_counter[8] <= vga:inst.d_column_counter[8]
+d_column_counter[9] <= vga:inst.d_column_counter[9]
+d_hsync_counter[0] <= vga:inst.d_hsync_counter[0]
+d_hsync_counter[1] <= vga:inst.d_hsync_counter[1]
+d_hsync_counter[2] <= vga:inst.d_hsync_counter[2]
+d_hsync_counter[3] <= vga:inst.d_hsync_counter[3]
+d_hsync_counter[4] <= vga:inst.d_hsync_counter[4]
+d_hsync_counter[5] <= vga:inst.d_hsync_counter[5]
+d_hsync_counter[6] <= vga:inst.d_hsync_counter[6]
+d_hsync_counter[7] <= vga:inst.d_hsync_counter[7]
+d_hsync_counter[8] <= vga:inst.d_hsync_counter[8]
+d_hsync_counter[9] <= vga:inst.d_hsync_counter[9]
+d_hsync_state[6] <= vga:inst.d_hsync_state[6]
+d_hsync_state[5] <= vga:inst.d_hsync_state[5]
+d_hsync_state[4] <= vga:inst.d_hsync_state[4]
+d_hsync_state[3] <= vga:inst.d_hsync_state[3]
+d_hsync_state[2] <= vga:inst.d_hsync_state[2]
+d_hsync_state[1] <= vga:inst.d_hsync_state[1]
+d_hsync_state[0] <= vga:inst.d_hsync_state[0]
+d_line_counter[0] <= vga:inst.d_line_counter[0]
+d_line_counter[1] <= vga:inst.d_line_counter[1]
+d_line_counter[2] <= vga:inst.d_line_counter[2]
+d_line_counter[3] <= vga:inst.d_line_counter[3]
+d_line_counter[4] <= vga:inst.d_line_counter[4]
+d_line_counter[5] <= vga:inst.d_line_counter[5]
+d_line_counter[6] <= vga:inst.d_line_counter[6]
+d_line_counter[7] <= vga:inst.d_line_counter[7]
+d_line_counter[8] <= vga:inst.d_line_counter[8]
+d_toggle_counter[0] <= vga:inst.d_toggle_counter[0]
+d_toggle_counter[1] <= vga:inst.d_toggle_counter[1]
+d_toggle_counter[2] <= vga:inst.d_toggle_counter[2]
+d_toggle_counter[3] <= vga:inst.d_toggle_counter[3]
+d_toggle_counter[4] <= vga:inst.d_toggle_counter[4]
+d_toggle_counter[5] <= vga:inst.d_toggle_counter[5]
+d_toggle_counter[6] <= vga:inst.d_toggle_counter[6]
+d_toggle_counter[7] <= vga:inst.d_toggle_counter[7]
+d_toggle_counter[8] <= vga:inst.d_toggle_counter[8]
+d_toggle_counter[9] <= vga:inst.d_toggle_counter[9]
+d_toggle_counter[10] <= vga:inst.d_toggle_counter[10]
+d_toggle_counter[11] <= vga:inst.d_toggle_counter[11]
+d_toggle_counter[12] <= vga:inst.d_toggle_counter[12]
+d_toggle_counter[13] <= vga:inst.d_toggle_counter[13]
+d_toggle_counter[14] <= vga:inst.d_toggle_counter[14]
+d_toggle_counter[15] <= vga:inst.d_toggle_counter[15]
+d_toggle_counter[16] <= vga:inst.d_toggle_counter[16]
+d_toggle_counter[17] <= vga:inst.d_toggle_counter[17]
+d_toggle_counter[18] <= vga:inst.d_toggle_counter[18]
+d_toggle_counter[19] <= vga:inst.d_toggle_counter[19]
+d_toggle_counter[20] <= vga:inst.d_toggle_counter[20]
+d_toggle_counter[21] <= vga:inst.d_toggle_counter[21]
+d_toggle_counter[22] <= vga:inst.d_toggle_counter[22]
+d_toggle_counter[23] <= vga:inst.d_toggle_counter[23]
+d_toggle_counter[24] <= vga:inst.d_toggle_counter[24]
+d_vsync_counter[0] <= vga:inst.d_vsync_counter[0]
+d_vsync_counter[1] <= vga:inst.d_vsync_counter[1]
+d_vsync_counter[2] <= vga:inst.d_vsync_counter[2]
+d_vsync_counter[3] <= vga:inst.d_vsync_counter[3]
+d_vsync_counter[4] <= vga:inst.d_vsync_counter[4]
+d_vsync_counter[5] <= vga:inst.d_vsync_counter[5]
+d_vsync_counter[6] <= vga:inst.d_vsync_counter[6]
+d_vsync_counter[7] <= vga:inst.d_vsync_counter[7]
+d_vsync_counter[8] <= vga:inst.d_vsync_counter[8]
+d_vsync_counter[9] <= vga:inst.d_vsync_counter[9]
+d_vsync_state[6] <= vga:inst.d_vsync_state[6]
+d_vsync_state[5] <= vga:inst.d_vsync_state[5]
+d_vsync_state[4] <= vga:inst.d_vsync_state[4]
+d_vsync_state[3] <= vga:inst.d_vsync_state[3]
+d_vsync_state[2] <= vga:inst.d_vsync_state[2]
+d_vsync_state[1] <= vga:inst.d_vsync_state[1]
+d_vsync_state[0] <= vga:inst.d_vsync_state[0]
+seven_seg_pin[0] <= vga:inst.seven_seg_pin[0]
+seven_seg_pin[1] <= vga:inst.seven_seg_pin[1]
+seven_seg_pin[2] <= vga:inst.seven_seg_pin[2]
+seven_seg_pin[3] <= vga:inst.seven_seg_pin[3]
+seven_seg_pin[4] <= vga:inst.seven_seg_pin[4]
+seven_seg_pin[5] <= vga:inst.seven_seg_pin[5]
+seven_seg_pin[6] <= vga:inst.seven_seg_pin[6]
+seven_seg_pin[7] <= vga:inst.seven_seg_pin[7]
+seven_seg_pin[8] <= vga:inst.seven_seg_pin[8]
+seven_seg_pin[9] <= vga:inst.seven_seg_pin[9]
+seven_seg_pin[10] <= vga:inst.seven_seg_pin[10]
+seven_seg_pin[11] <= vga:inst.seven_seg_pin[11]
+seven_seg_pin[12] <= vga:inst.seven_seg_pin[12]
+seven_seg_pin[13] <= vga:inst.seven_seg_pin[13]
+
+
+|vga_pll|vga:inst
+clk_pin => clk_pin_in.PADIO
+reset_pin => reset_pin_in.PADIO
+r0_pin <= r0_pin_out.PADIO
+r1_pin <= r1_pin_out.PADIO
+r2_pin <= r2_pin_out.PADIO
+g0_pin <= g0_pin_out.PADIO
+g1_pin <= g1_pin_out.PADIO
+g2_pin <= g2_pin_out.PADIO
+b0_pin <= b0_pin_out.PADIO
+b1_pin <= b1_pin_out.PADIO
+hsync_pin <= hsync_pin_out.PADIO
+vsync_pin <= vsync_pin_out.PADIO
+seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO
+seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO
+seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO
+seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO
+seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO
+seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO
+seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO
+seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO
+seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO
+seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO
+seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO
+seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO
+seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO
+seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO
+d_hsync <= d_hsync_out.PADIO
+d_vsync <= d_vsync_out.PADIO
+d_column_counter[0] <= d_column_counter_out_0_.PADIO
+d_column_counter[1] <= d_column_counter_out_1_.PADIO
+d_column_counter[2] <= d_column_counter_out_2_.PADIO
+d_column_counter[3] <= d_column_counter_out_3_.PADIO
+d_column_counter[4] <= d_column_counter_out_4_.PADIO
+d_column_counter[5] <= d_column_counter_out_5_.PADIO
+d_column_counter[6] <= d_column_counter_out_6_.PADIO
+d_column_counter[7] <= d_column_counter_out_7_.PADIO
+d_column_counter[8] <= d_column_counter_out_8_.PADIO
+d_column_counter[9] <= d_column_counter_out_9_.PADIO
+d_line_counter[0] <= d_line_counter_out_0_.PADIO
+d_line_counter[1] <= d_line_counter_out_1_.PADIO
+d_line_counter[2] <= d_line_counter_out_2_.PADIO
+d_line_counter[3] <= d_line_counter_out_3_.PADIO
+d_line_counter[4] <= d_line_counter_out_4_.PADIO
+d_line_counter[5] <= d_line_counter_out_5_.PADIO
+d_line_counter[6] <= d_line_counter_out_6_.PADIO
+d_line_counter[7] <= d_line_counter_out_7_.PADIO
+d_line_counter[8] <= d_line_counter_out_8_.PADIO
+d_set_column_counter <= d_set_column_counter_out.PADIO
+d_set_line_counter <= d_set_line_counter_out.PADIO
+d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO
+d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO
+d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO
+d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO
+d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO
+d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO
+d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO
+d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO
+d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO
+d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO
+d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO
+d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO
+d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO
+d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO
+d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO
+d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO
+d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO
+d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO
+d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO
+d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO
+d_set_hsync_counter <= d_set_hsync_counter_out.PADIO
+d_set_vsync_counter <= d_set_vsync_counter_out.PADIO
+d_h_enable <= d_h_enable_out.PADIO
+d_v_enable <= d_v_enable_out.PADIO
+d_r <= d_r_out.PADIO
+d_g <= d_g_out.PADIO
+d_b <= d_b_out.PADIO
+d_hsync_state[6] <= d_hsync_state_out_6_.PADIO
+d_hsync_state[5] <= d_hsync_state_out_5_.PADIO
+d_hsync_state[4] <= d_hsync_state_out_4_.PADIO
+d_hsync_state[3] <= d_hsync_state_out_3_.PADIO
+d_hsync_state[2] <= d_hsync_state_out_2_.PADIO
+d_hsync_state[1] <= d_hsync_state_out_1_.PADIO
+d_hsync_state[0] <= d_hsync_state_out_0_.PADIO
+d_vsync_state[6] <= d_vsync_state_out_6_.PADIO
+d_vsync_state[5] <= d_vsync_state_out_5_.PADIO
+d_vsync_state[4] <= d_vsync_state_out_4_.PADIO
+d_vsync_state[3] <= d_vsync_state_out_3_.PADIO
+d_vsync_state[2] <= d_vsync_state_out_2_.PADIO
+d_vsync_state[1] <= d_vsync_state_out_1_.PADIO
+d_vsync_state[0] <= d_vsync_state_out_0_.PADIO
+d_state_clk <= d_state_clk_out.PADIO
+d_toggle <= d_toggle_out.PADIO
+d_toggle_counter[0] <= d_toggle_counter_out_0_.PADIO
+d_toggle_counter[1] <= d_toggle_counter_out_1_.PADIO
+d_toggle_counter[2] <= d_toggle_counter_out_2_.PADIO
+d_toggle_counter[3] <= d_toggle_counter_out_3_.PADIO
+d_toggle_counter[4] <= d_toggle_counter_out_4_.PADIO
+d_toggle_counter[5] <= d_toggle_counter_out_5_.PADIO
+d_toggle_counter[6] <= d_toggle_counter_out_6_.PADIO
+d_toggle_counter[7] <= d_toggle_counter_out_7_.PADIO
+d_toggle_counter[8] <= d_toggle_counter_out_8_.PADIO
+d_toggle_counter[9] <= d_toggle_counter_out_9_.PADIO
+d_toggle_counter[10] <= d_toggle_counter_out_10_.PADIO
+d_toggle_counter[11] <= d_toggle_counter_out_11_.PADIO
+d_toggle_counter[12] <= d_toggle_counter_out_12_.PADIO
+d_toggle_counter[13] <= d_toggle_counter_out_13_.PADIO
+d_toggle_counter[14] <= d_toggle_counter_out_14_.PADIO
+d_toggle_counter[15] <= d_toggle_counter_out_15_.PADIO
+d_toggle_counter[16] <= d_toggle_counter_out_16_.PADIO
+d_toggle_counter[17] <= d_toggle_counter_out_17_.PADIO
+d_toggle_counter[18] <= d_toggle_counter_out_18_.PADIO
+d_toggle_counter[19] <= d_toggle_counter_out_19_.PADIO
+d_toggle_counter[20] <= d_toggle_counter_out_20_.PADIO
+d_toggle_counter[21] <= d_toggle_counter_out_21_.PADIO
+d_toggle_counter[22] <= d_toggle_counter_out_22_.PADIO
+d_toggle_counter[23] <= d_toggle_counter_out_23_.PADIO
+d_toggle_counter[24] <= d_toggle_counter_out_24_.PADIO
+
+
+|vga_pll|vga:inst|vga_driver:vga_driver_unit
+line_counter_sig_0 <= line_counter_sig_0_.REGOUT
+line_counter_sig_1 <= line_counter_sig_1_.REGOUT
+line_counter_sig_2 <= line_counter_sig_2_.REGOUT
+line_counter_sig_3 <= line_counter_sig_3_.REGOUT
+line_counter_sig_4 <= line_counter_sig_4_.REGOUT
+line_counter_sig_5 <= line_counter_sig_5_.REGOUT
+line_counter_sig_6 <= line_counter_sig_6_.REGOUT
+line_counter_sig_7 <= line_counter_sig_7_.REGOUT
+line_counter_sig_8 <= line_counter_sig_8_.REGOUT
+dly_counter_1 => vsync_state_6_.DATAC
+dly_counter_1 => h_sync_Z.DATAC
+dly_counter_1 => v_sync_Z.DATAC
+dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC
+dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC
+dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC
+dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC
+dly_counter_0 => vsync_state_6_.DATAB
+dly_counter_0 => h_sync_Z.DATAB
+dly_counter_0 => v_sync_Z.DATAB
+dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB
+dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB
+dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB
+dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB
+vsync_state_2 <= vsync_state_2_.REGOUT
+vsync_state_5 <= vsync_state_5_.REGOUT
+vsync_state_3 <= vsync_state_3_.REGOUT
+vsync_state_6 <= vsync_state_6_.REGOUT
+vsync_state_4 <= vsync_state_4_.REGOUT
+vsync_state_1 <= vsync_state_1_.REGOUT
+vsync_state_0 <= vsync_state_0_.REGOUT
+hsync_state_2 <= hsync_state_2_.REGOUT
+hsync_state_4 <= hsync_state_4_.REGOUT
+hsync_state_0 <= hsync_state_0_.REGOUT
+hsync_state_5 <= hsync_state_5_.REGOUT
+hsync_state_1 <= hsync_state_1_.REGOUT
+hsync_state_3 <= hsync_state_3_.REGOUT
+hsync_state_6 <= hsync_state_6_.REGOUT
+column_counter_sig_0 <= column_counter_sig_0_.REGOUT
+column_counter_sig_1 <= column_counter_sig_1_.REGOUT
+column_counter_sig_2 <= column_counter_sig_2_.REGOUT
+column_counter_sig_3 <= column_counter_sig_3_.REGOUT
+column_counter_sig_4 <= column_counter_sig_4_.REGOUT
+column_counter_sig_5 <= column_counter_sig_5_.REGOUT
+column_counter_sig_6 <= column_counter_sig_6_.REGOUT
+column_counter_sig_7 <= column_counter_sig_7_.REGOUT
+column_counter_sig_8 <= column_counter_sig_8_.REGOUT
+column_counter_sig_9 <= column_counter_sig_9_.REGOUT
+vsync_counter_9 <= vsync_counter_9_.REGOUT
+vsync_counter_8 <= vsync_counter_8_.REGOUT
+vsync_counter_7 <= vsync_counter_7_.REGOUT
+vsync_counter_6 <= vsync_counter_6_.REGOUT
+vsync_counter_5 <= vsync_counter_5_.REGOUT
+vsync_counter_4 <= vsync_counter_4_.REGOUT
+vsync_counter_3 <= vsync_counter_3_.REGOUT
+vsync_counter_2 <= vsync_counter_2_.REGOUT
+vsync_counter_1 <= vsync_counter_1_.REGOUT
+vsync_counter_0 <= vsync_counter_0_.REGOUT
+hsync_counter_9 <= hsync_counter_9_.REGOUT
+hsync_counter_8 <= hsync_counter_8_.REGOUT
+hsync_counter_7 <= hsync_counter_7_.REGOUT
+hsync_counter_6 <= hsync_counter_6_.REGOUT
+hsync_counter_5 <= hsync_counter_5_.REGOUT
+hsync_counter_4 <= hsync_counter_4_.REGOUT
+hsync_counter_3 <= hsync_counter_3_.REGOUT
+hsync_counter_2 <= hsync_counter_2_.REGOUT
+hsync_counter_1 <= hsync_counter_1_.REGOUT
+hsync_counter_0 <= hsync_counter_0_.REGOUT
+d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT
+v_sync <= v_sync_Z.REGOUT
+h_sync <= h_sync_Z.REGOUT
+h_enable_sig <= h_enable_sig_Z.REGOUT
+v_enable_sig <= v_enable_sig_Z.REGOUT
+reset_pin_c => vsync_state_6_.DATAA
+reset_pin_c => h_sync_Z.DATAA
+reset_pin_c => v_sync_Z.DATAA
+reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA
+reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA
+reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA
+reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA
+un6_dly_counter_0_x <= vsync_state_6_.COMBOUT
+d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT
+clk_pin_c => hsync_counter_0_.CLK
+clk_pin_c => hsync_counter_1_.CLK
+clk_pin_c => hsync_counter_2_.CLK
+clk_pin_c => hsync_counter_3_.CLK
+clk_pin_c => hsync_counter_4_.CLK
+clk_pin_c => hsync_counter_5_.CLK
+clk_pin_c => hsync_counter_6_.CLK
+clk_pin_c => hsync_counter_7_.CLK
+clk_pin_c => hsync_counter_8_.CLK
+clk_pin_c => hsync_counter_9_.CLK
+clk_pin_c => vsync_counter_0_.CLK
+clk_pin_c => vsync_counter_1_.CLK
+clk_pin_c => vsync_counter_2_.CLK
+clk_pin_c => vsync_counter_3_.CLK
+clk_pin_c => vsync_counter_4_.CLK
+clk_pin_c => vsync_counter_5_.CLK
+clk_pin_c => vsync_counter_6_.CLK
+clk_pin_c => vsync_counter_7_.CLK
+clk_pin_c => vsync_counter_8_.CLK
+clk_pin_c => vsync_counter_9_.CLK
+clk_pin_c => column_counter_sig_9_.CLK
+clk_pin_c => column_counter_sig_8_.CLK
+clk_pin_c => column_counter_sig_7_.CLK
+clk_pin_c => column_counter_sig_6_.CLK
+clk_pin_c => column_counter_sig_5_.CLK
+clk_pin_c => column_counter_sig_4_.CLK
+clk_pin_c => column_counter_sig_3_.CLK
+clk_pin_c => column_counter_sig_2_.CLK
+clk_pin_c => column_counter_sig_1_.CLK
+clk_pin_c => column_counter_sig_0_.CLK
+clk_pin_c => hsync_state_6_.CLK
+clk_pin_c => vsync_state_0_.CLK
+clk_pin_c => vsync_state_1_.CLK
+clk_pin_c => vsync_state_6_.CLK
+clk_pin_c => line_counter_sig_8_.CLK
+clk_pin_c => line_counter_sig_7_.CLK
+clk_pin_c => line_counter_sig_6_.CLK
+clk_pin_c => line_counter_sig_5_.CLK
+clk_pin_c => line_counter_sig_4_.CLK
+clk_pin_c => line_counter_sig_3_.CLK
+clk_pin_c => line_counter_sig_2_.CLK
+clk_pin_c => line_counter_sig_1_.CLK
+clk_pin_c => line_counter_sig_0_.CLK
+clk_pin_c => v_enable_sig_Z.CLK
+clk_pin_c => h_enable_sig_Z.CLK
+clk_pin_c => h_sync_Z.CLK
+clk_pin_c => v_sync_Z.CLK
+clk_pin_c => vsync_state_5_.CLK
+clk_pin_c => vsync_state_4_.CLK
+clk_pin_c => vsync_state_3_.CLK
+clk_pin_c => vsync_state_2_.CLK
+clk_pin_c => hsync_state_5_.CLK
+clk_pin_c => hsync_state_4_.CLK
+clk_pin_c => hsync_state_3_.CLK
+clk_pin_c => hsync_state_2_.CLK
+clk_pin_c => hsync_state_1_.CLK
+clk_pin_c => hsync_state_0_.CLK
+
+
+|vga_pll|vga:inst|vga_control:vga_control_unit
+line_counter_sig_0 => DRAW_SQUARE_next_un17_v_enablelto3.DATAC
+line_counter_sig_2 => DRAW_SQUARE_next_un17_v_enablelto3.DATAB
+line_counter_sig_2 => DRAW_SQUARE_next_un13_v_enablelto4_0.DATAB
+line_counter_sig_1 => DRAW_SQUARE_next_un17_v_enablelto3.DATAA
+line_counter_sig_3 => DRAW_SQUARE_next_un13_v_enablelto6.DATAC
+line_counter_sig_3 => DRAW_SQUARE_next_un17_v_enablelto3.DATAD
+line_counter_sig_6 => b_next_0_sqmuxa_7_4_a_cZ.DATAC
+line_counter_sig_6 => DRAW_SQUARE_next_un13_v_enablelto6.DATAB
+line_counter_sig_5 => b_next_0_sqmuxa_7_4_a_cZ.DATAB
+line_counter_sig_5 => DRAW_SQUARE_next_un13_v_enablelto6.DATAA
+line_counter_sig_4 => b_next_0_sqmuxa_7_4_a_cZ.DATAA
+line_counter_sig_4 => DRAW_SQUARE_next_un13_v_enablelto4_0.DATAA
+line_counter_sig_7 => b_next_0_sqmuxa_7_4_cZ.DATAB
+line_counter_sig_8 => b_next_0_sqmuxa_7_4_cZ.DATAA
+line_counter_sig_8 => b_next_0_sqmuxa_7_2_cZ.DATAD
+column_counter_sig_0 => DRAW_SQUARE_next_un5_v_enablelt2.DATAC
+column_counter_sig_1 => DRAW_SQUARE_next_un5_v_enablelt2.DATAA
+column_counter_sig_2 => DRAW_SQUARE_next_un9_v_enablelto4.DATAC
+column_counter_sig_2 => DRAW_SQUARE_next_un5_v_enablelt2.DATAB
+column_counter_sig_8 => b_next_0_sqmuxa_7_2_cZ.DATAA
+column_counter_sig_3 => DRAW_SQUARE_next_un5_v_enablelto5.DATAC
+column_counter_sig_3 => DRAW_SQUARE_next_un9_v_enablelto4.DATAA
+column_counter_sig_5 => DRAW_SQUARE_next_un5_v_enablelto5.DATAB
+column_counter_sig_5 => DRAW_SQUARE_next_un9_v_enablelto6.DATAA
+column_counter_sig_4 => DRAW_SQUARE_next_un5_v_enablelto5.DATAA
+column_counter_sig_4 => DRAW_SQUARE_next_un9_v_enablelto4.DATAB
+column_counter_sig_9 => b_next_0_sqmuxa_7_3_cZ.DATAB
+column_counter_sig_9 => b_next_0_sqmuxa_7_2_cZ.DATAC
+column_counter_sig_7 => b_next_0_sqmuxa_7_5_cZ.DATAB
+column_counter_sig_7 => b_next_0_sqmuxa_7_3_cZ.DATAA
+column_counter_sig_6 => b_next_0_sqmuxa_7_5_cZ.DATAA
+column_counter_sig_6 => DRAW_SQUARE_next_un9_v_enablelto6.DATAB
+toggle_counter_sig_0 <= toggle_counter_sig_0_.REGOUT
+toggle_counter_sig_1 <= toggle_counter_sig_1_.REGOUT
+toggle_counter_sig_2 <= toggle_counter_sig_2_.REGOUT
+toggle_counter_sig_3 <= toggle_counter_sig_3_.REGOUT
+toggle_counter_sig_4 <= toggle_counter_sig_4_.REGOUT
+toggle_counter_sig_5 <= toggle_counter_sig_5_.REGOUT
+toggle_counter_sig_6 <= toggle_counter_sig_6_.REGOUT
+toggle_counter_sig_7 <= toggle_counter_sig_7_.REGOUT
+toggle_counter_sig_8 <= toggle_counter_sig_8_.REGOUT
+toggle_counter_sig_9 <= toggle_counter_sig_9_.REGOUT
+toggle_counter_sig_10 <= toggle_counter_sig_10_.REGOUT
+toggle_counter_sig_11 <= toggle_counter_sig_11_.REGOUT
+toggle_counter_sig_12 <= toggle_counter_sig_12_.REGOUT
+toggle_counter_sig_13 <= toggle_counter_sig_13_.REGOUT
+toggle_counter_sig_14 <= toggle_counter_sig_14_.REGOUT
+toggle_counter_sig_15 <= toggle_counter_sig_15_.REGOUT
+toggle_counter_sig_16 <= toggle_counter_sig_16_.REGOUT
+toggle_counter_sig_17 <= toggle_counter_sig_17_.REGOUT
+toggle_counter_sig_18 <= toggle_counter_sig_18_.REGOUT
+toggle_counter_sig_19 <= toggle_counter_sig_19_.REGOUT
+toggle_counter_sig_20 <= toggle_counter_sig_20_.REGOUT
+toggle_counter_sig_21 <= toggle_counter_sig_21_.REGOUT
+toggle_counter_sig_22 <= toggle_counter_sig_22_.REGOUT
+toggle_counter_sig_23 <= toggle_counter_sig_23_.REGOUT
+toggle_counter_sig_24 <= toggle_counter_sig_24_.REGOUT
+h_enable_sig => b_next_0_sqmuxa_7_2_cZ.DATAB
+g <= g_Z.REGOUT
+b <= b_Z.REGOUT
+v_enable_sig => r_Z.DATAB
+v_enable_sig => b_Z.DATAB
+r <= r_Z.REGOUT
+toggle_sig <= toggle_sig_Z.REGOUT
+un6_dly_counter_0_x => toggle_counter_sig_24_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_23_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_22_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_21_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_20_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_19_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_18_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_17_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_16_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_15_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_14_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_13_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_12_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_11_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_10_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_9_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_8_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_7_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_6_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_5_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_4_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_3_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_2_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_1_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_0_.ACLR
+un6_dly_counter_0_x => toggle_sig_Z.ACLR
+un6_dly_counter_0_x => r_Z.ACLR
+un6_dly_counter_0_x => b_Z.ACLR
+un6_dly_counter_0_x => g_Z.ACLR
+clk_pin_c => toggle_counter_sig_24_.CLK
+clk_pin_c => toggle_counter_sig_23_.CLK
+clk_pin_c => toggle_counter_sig_22_.CLK
+clk_pin_c => toggle_counter_sig_21_.CLK
+clk_pin_c => toggle_counter_sig_20_.CLK
+clk_pin_c => toggle_counter_sig_19_.CLK
+clk_pin_c => toggle_counter_sig_18_.CLK
+clk_pin_c => toggle_counter_sig_17_.CLK
+clk_pin_c => toggle_counter_sig_16_.CLK
+clk_pin_c => toggle_counter_sig_15_.CLK
+clk_pin_c => toggle_counter_sig_14_.CLK
+clk_pin_c => toggle_counter_sig_13_.CLK
+clk_pin_c => toggle_counter_sig_12_.CLK
+clk_pin_c => toggle_counter_sig_11_.CLK
+clk_pin_c => toggle_counter_sig_10_.CLK
+clk_pin_c => toggle_counter_sig_9_.CLK
+clk_pin_c => toggle_counter_sig_8_.CLK
+clk_pin_c => toggle_counter_sig_7_.CLK
+clk_pin_c => toggle_counter_sig_6_.CLK
+clk_pin_c => toggle_counter_sig_5_.CLK
+clk_pin_c => toggle_counter_sig_4_.CLK
+clk_pin_c => toggle_counter_sig_3_.CLK
+clk_pin_c => toggle_counter_sig_2_.CLK
+clk_pin_c => toggle_counter_sig_1_.CLK
+clk_pin_c => toggle_counter_sig_0_.CLK
+clk_pin_c => toggle_sig_Z.CLK
+clk_pin_c => r_Z.CLK
+clk_pin_c => b_Z.CLK
+clk_pin_c => g_Z.CLK
+
+
+|vga_pll|vpll:inst1
+inclk0 => altpll:altpll_component.inclk[0]
+c0 <= altpll:altpll_component.clk[0]
+
+
+|vga_pll|vpll:inst1|altpll:altpll_component
+inclk[0] => pll.CLK
+inclk[1] => ~NO_FANOUT~
+fbin => ~NO_FANOUT~
+pllena => ~NO_FANOUT~
+clkswitch => ~NO_FANOUT~
+areset => ~NO_FANOUT~
+pfdena => ~NO_FANOUT~
+clkena[0] => ~NO_FANOUT~
+clkena[1] => pll.ENA1
+clkena[2] => pll.ENA2
+clkena[3] => pll.ENA3
+clkena[4] => pll.ENA4
+clkena[5] => pll.ENA5
+extclkena[0] => pll.EXTCLKENA
+extclkena[1] => pll.EXTCLKENA1
+extclkena[2] => pll.EXTCLKENA2
+extclkena[3] => pll.EXTCLKENA3
+scanclk => ~NO_FANOUT~
+scanclkena => ~NO_FANOUT~
+scanaclr => ~NO_FANOUT~
+scanread => ~NO_FANOUT~
+scanwrite => ~NO_FANOUT~
+scandata => ~NO_FANOUT~
+phasecounterselect[0] => ~NO_FANOUT~
+phasecounterselect[1] => ~NO_FANOUT~
+phasecounterselect[2] => ~NO_FANOUT~
+phasecounterselect[3] => ~NO_FANOUT~
+phaseupdown => ~NO_FANOUT~
+phasestep => ~NO_FANOUT~
+configupdate => ~NO_FANOUT~
+fbmimicbidir <= <GND>
+clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
+clk[1] <= <GND>
+clk[2] <= <GND>
+clk[3] <= <GND>
+clk[4] <= <GND>
+clk[5] <= <GND>
+extclk[0] <= <GND>
+extclk[1] <= <GND>
+extclk[2] <= <GND>
+extclk[3] <= <GND>
+clkbad[0] <= <GND>
+clkbad[1] <= <GND>
+enable1 <= <GND>
+enable0 <= <GND>
+activeclock <= <GND>
+clkloss <= <GND>
+locked <= <GND>
+scandataout <= <GND>
+scandone <= <GND>
+sclkout0 <= <GND>
+sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
+phasedone <= <GND>
+vcooverrange <= <GND>
+vcounderrange <= <GND>
+fbout <= <GND>
+
+
--- /dev/null
+Version 9.0 Build 132 02/25/2009 SJ Full Version
+45
+3235
+OFF
+OFF
+OFF
+ON
+ON
+OFF
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+synplcty.lmf
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+vga_pll
+# storage
+db|vga_pll.(0).cnf
+db|vga_pll.(0).cnf
+# case_insensitive
+# source_file
+..|..|src|vga_pll.bdf
+99c3b73be69bba6a49dedfda59395ee
+26
+# internal_option {
+BLOCK_DESIGN_NAMING
+AUTO
+}
+# hierarchies {
+|
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga
+# storage
+db|vga_pll.(1).cnf
+db|vga_pll.(1).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+a69bdf2838bc2ddfa265318d6caf919c
+28
+# hierarchies {
+vga:inst
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga_driver
+# storage
+db|vga_pll.(2).cnf
+db|vga_pll.(2).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+a69bdf2838bc2ddfa265318d6caf919c
+28
+# hierarchies {
+vga:inst|vga_driver:vga_driver_unit
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga_control
+# storage
+db|vga_pll.(3).cnf
+db|vga_pll.(3).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+a69bdf2838bc2ddfa265318d6caf919c
+28
+# hierarchies {
+vga:inst|vga_control:vga_control_unit
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vpll
+# storage
+db|vga_pll.(4).cnf
+db|vga_pll.(4).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+..|..|src|vpll.vhd
+ccc2bcb05887d5721243fd22481948be
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# hierarchies {
+vpll:inst1
+}
+# lmf
+|opt|quartus|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+altpll
+# storage
+db|vga_pll.(5).cnf
+db|vga_pll.(5).cnf
+# case_insensitive
+# source_file
+|opt|quartus|quartus|libraries|megafunctions|altpll.tdf
+d980162588d7aa8b78874932c782e18
+7
+# user_parameter {
+OPERATION_MODE
+NORMAL
+PARAMETER_UNKNOWN
+USR
+PLL_TYPE
+AUTO
+PARAMETER_UNKNOWN
+USR
+QUALIFY_CONF_DONE
+OFF
+PARAMETER_UNKNOWN
+DEF
+COMPENSATE_CLOCK
+CLK0
+PARAMETER_UNKNOWN
+USR
+SCAN_CHAIN
+LONG
+PARAMETER_UNKNOWN
+DEF
+PRIMARY_CLOCK
+INCLK0
+PARAMETER_UNKNOWN
+DEF
+INCLK0_INPUT_FREQUENCY
+30003
+PARAMETER_SIGNED_DEC
+USR
+INCLK1_INPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+GATE_LOCK_SIGNAL
+NO
+PARAMETER_UNKNOWN
+USR
+GATE_LOCK_COUNTER
+0
+PARAMETER_UNKNOWN
+DEF
+LOCK_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+LOCK_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+VALID_LOCK_MULTIPLIER
+1
+PARAMETER_SIGNED_DEC
+USR
+INVALID_LOCK_MULTIPLIER
+5
+PARAMETER_SIGNED_DEC
+USR
+SWITCH_OVER_ON_LOSSCLK
+OFF
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_ON_GATED_LOCK
+OFF
+PARAMETER_UNKNOWN
+DEF
+ENABLE_SWITCH_OVER_COUNTER
+OFF
+PARAMETER_UNKNOWN
+DEF
+SKIP_VCO
+OFF
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_COUNTER
+0
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_TYPE
+AUTO
+PARAMETER_UNKNOWN
+DEF
+FEEDBACK_SOURCE
+EXTCLK0
+PARAMETER_UNKNOWN
+DEF
+BANDWIDTH
+0
+PARAMETER_UNKNOWN
+DEF
+BANDWIDTH_TYPE
+AUTO
+PARAMETER_UNKNOWN
+USR
+SPREAD_FREQUENCY
+0
+PARAMETER_SIGNED_DEC
+USR
+DOWN_SPREAD
+0
+PARAMETER_UNKNOWN
+DEF
+SELF_RESET_ON_GATED_LOSS_LOCK
+OFF
+PARAMETER_UNKNOWN
+DEF
+SELF_RESET_ON_LOSS_LOCK
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK9_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK8_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK7_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK6_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK5_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK4_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK3_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK2_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK1_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK0_MULTIPLY_BY
+5435
+PARAMETER_SIGNED_DEC
+USR
+CLK9_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK8_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK7_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK6_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK5_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK4_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK3_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK2_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK1_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK0_DIVIDE_BY
+6666
+PARAMETER_SIGNED_DEC
+USR
+CLK9_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK8_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK7_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK6_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK5_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK4_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK3_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK2_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK1_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK0_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+USR
+CLK5_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK4_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+USR
+CLK9_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK8_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK7_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK6_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK5_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK4_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK3_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK2_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK1_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK0_DUTY_CYCLE
+50
+PARAMETER_SIGNED_DEC
+USR
+CLK9_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK8_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK7_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK6_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK5_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK4_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK3_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK2_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK1_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK0_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK9_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK8_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK7_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK6_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK5_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK4_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK3_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK2_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK1_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK0_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+LOCK_WINDOW_UI
+ 0.05
+PARAMETER_UNKNOWN
+DEF
+LOCK_WINDOW_UI_BITS
+UNUSED
+PARAMETER_UNKNOWN
+DEF
+VCO_RANGE_DETECTOR_LOW_BITS
+UNUSED
+PARAMETER_UNKNOWN
+DEF
+VCO_RANGE_DETECTOR_HIGH_BITS
+UNUSED
+PARAMETER_UNKNOWN
+DEF
+DPA_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+DPA_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+DPA_DIVIDER
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+VCO_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+SCLKOUT0_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+SCLKOUT1_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_MIN
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_MAX
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_CENTER
+0
+PARAMETER_UNKNOWN
+DEF
+PFD_MIN
+0
+PARAMETER_UNKNOWN
+DEF
+PFD_MAX
+0
+PARAMETER_UNKNOWN
+DEF
+M_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+M
+0
+PARAMETER_UNKNOWN
+DEF
+N
+1
+PARAMETER_UNKNOWN
+DEF
+M2
+1
+PARAMETER_UNKNOWN
+DEF
+N2
+1
+PARAMETER_UNKNOWN
+DEF
+SS
+1
+PARAMETER_UNKNOWN
+DEF
+C0_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C1_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C2_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C3_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C4_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C5_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C6_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C7_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C8_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C9_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C0_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C1_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C2_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C3_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C4_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C5_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C6_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C7_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C8_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C9_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C0_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C1_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C2_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C3_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C4_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C5_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C6_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C7_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C8_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C9_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C2_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C3_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C4_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C5_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C6_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C7_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C8_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C9_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C2_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C3_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C4_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C5_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C6_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C7_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C8_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C9_PH
+0
+PARAMETER_UNKNOWN
+DEF
+L0_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+L1_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G0_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G1_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G2_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G3_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E0_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E1_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E2_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E3_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+L0_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+L1_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G0_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G1_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G2_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G3_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E0_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E1_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E2_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E3_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+L0_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+L1_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G0_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G1_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G2_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G3_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E0_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E1_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E2_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E3_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+L0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+L1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G2_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G3_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E2_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E3_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+L0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+L1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G2_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G3_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E2_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E3_PH
+0
+PARAMETER_UNKNOWN
+DEF
+M_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C1_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C2_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C3_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C4_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C5_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C6_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C7_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C8_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C9_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK0_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK1_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK2_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK3_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK4_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK5_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK6_COUNTER
+E0
+PARAMETER_UNKNOWN
+DEF
+CLK7_COUNTER
+E1
+PARAMETER_UNKNOWN
+DEF
+CLK8_COUNTER
+E2
+PARAMETER_UNKNOWN
+DEF
+CLK9_COUNTER
+E3
+PARAMETER_UNKNOWN
+DEF
+L0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+L1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+M_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+N_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_COUNTER
+E3
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_COUNTER
+E2
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_COUNTER
+E1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_COUNTER
+E0
+PARAMETER_UNKNOWN
+DEF
+ENABLE0_COUNTER
+L0
+PARAMETER_UNKNOWN
+DEF
+ENABLE1_COUNTER
+L0
+PARAMETER_UNKNOWN
+DEF
+CHARGE_PUMP_CURRENT
+2
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_R
+ 1.000000
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_C
+5
+PARAMETER_UNKNOWN
+DEF
+CHARGE_PUMP_CURRENT_BITS
+9999
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_R_BITS
+9999
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_C_BITS
+9999
+PARAMETER_UNKNOWN
+DEF
+VCO_POST_SCALE
+0
+PARAMETER_UNKNOWN
+DEF
+CLK2_OUTPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK1_OUTPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK0_OUTPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+INTENDED_DEVICE_FAMILY
+Stratix
+PARAMETER_UNKNOWN
+USR
+PORT_CLKENA0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA2
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA3
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA4
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA5
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA2
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA3
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLK0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLK1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLK2
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLK3
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKBAD0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKBAD1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK2
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK3
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK4
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK5
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK6
+PORT_UNUSED
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK7
+PORT_UNUSED
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK8
+PORT_UNUSED
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK9
+PORT_UNUSED
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANDATA
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANDATAOUT
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANDONE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCLKOUT1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCLKOUT0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ACTIVECLOCK
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKLOSS
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_INCLK1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_INCLK0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_FBIN
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PLLENA
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKSWITCH
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ARESET
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PFDENA
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANCLK
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANACLR
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANREAD
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANWRITE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ENABLE0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ENABLE1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_LOCKED
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CONFIGUPDATE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_FBOUT
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PHASEDONE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PHASESTEP
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PHASEUPDOWN
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANCLKENA
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PHASECOUNTERSELECT
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_VCOOVERRANGE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_VCOUNDERRANGE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+M_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C0_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C1_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C2_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C3_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C4_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C5_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C6_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C7_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C8_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C9_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+CBXI_PARAMETER
+NOTHING
+PARAMETER_UNKNOWN
+DEF
+VCO_FREQUENCY_CONTROL
+AUTO
+PARAMETER_UNKNOWN
+DEF
+VCO_PHASE_SHIFT_STEP
+0
+PARAMETER_UNKNOWN
+DEF
+WIDTH_CLOCK
+6
+PARAMETER_UNKNOWN
+DEF
+WIDTH_PHASECOUNTERSELECT
+4
+PARAMETER_UNKNOWN
+DEF
+USING_FBMIMICBIDIR_PORT
+OFF
+PARAMETER_UNKNOWN
+DEF
+DEVICE_FAMILY
+Stratix
+PARAMETER_UNKNOWN
+USR
+SCAN_CHAIN_MIF_FILE
+UNUSED
+PARAMETER_UNKNOWN
+DEF
+SIM_GATE_LOCK_DEVICE_BEHAVIOR
+OFF
+PARAMETER_UNKNOWN
+DEF
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+}
+# used_port {
+inclk0
+-1
+3
+clk0
+-1
+3
+inclk1
+-1
+1
+extclkena3
+-1
+1
+extclkena2
+-1
+1
+extclkena1
+-1
+1
+extclkena0
+-1
+1
+clkena5
+-1
+1
+clkena4
+-1
+1
+clkena3
+-1
+1
+clkena2
+-1
+1
+clkena1
+-1
+1
+areset
+-1
+1
+pllena
+-1
+2
+clkena0
+-1
+2
+}
+# include_file {
+|opt|quartus|quartus|libraries|megafunctions|cycloneii_pll.inc
+39a0d9d1237d1db39c848c3f9faffc
+|opt|quartus|quartus|libraries|megafunctions|stratix_pll.inc
+5f8211898149ceae8264a0ea5036254f
+|opt|quartus|quartus|libraries|megafunctions|aglobal90.inc
+99832fdf63412df51d7531202d74e75
+|opt|quartus|quartus|libraries|megafunctions|stratixii_pll.inc
+6d1985e16ab5f59a1fd6b0ae20978a4e
+}
+# hierarchies {
+vpll:inst1|altpll:altpll_component
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# complete
+\r
\ No newline at end of file
--- /dev/null
+<TABLE BORDER="1" cellspacing="1" cellpadding="2">
+<TR valign="middle" bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst1</TD>
+<TD ALIGN="LEFT">1</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">1</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst|vga_control_unit</TD>
+<TD ALIGN="LEFT">23</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">29</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst|vga_driver_unit</TD>
+<TD ALIGN="LEFT">4</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">60</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst</TD>
+<TD ALIGN="LEFT">2</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">115</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+</TABLE>
--- /dev/null
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst1 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; inst|vga_control_unit ; 23 ; 0 ; 0 ; 0 ; 29 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; inst|vga_driver_unit ; 4 ; 0 ; 0 ; 0 ; 60 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; inst ; 2 ; 0 ; 0 ; 0 ; 115 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:54:33 2009 " "Info: Processing started: Wed Oct 28 14:54:33 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IACF_REVISION_DEFAULT_FILE_CREATED" "vga_pll 6.0 /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/vga_pll_assignment_defaults.qdf " "Info: Revision \"vga_pll\" was previously opened in Quartus II software version 6.0. Created Quartus II Default Settings File /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/vga_pll_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 6.0." { } { } 0 0 "Revision \"%1!s!\" was previously opened in Quartus II software version %2!s!. Created Quartus II Default Settings File %3!s!, which contains the default assignment setting information from Quartus II software version %2!s!." 0 0 "" 0 -1}
+{ "Info" "IACF_WHERE_TO_VIEW_DEFAULT_CHANGES" "/opt/quartus/quartus/linux/assignment_defaults.qdf " "Info: Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /opt/quartus/quartus/linux/assignment_defaults.qdf" { } { } 0 0 "Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../src/vga_pll.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../src/vga_pll.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 vga_pll " "Info: Found entity 1: vga_pll" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../syn/rev_1/vga.vqm 3 3 " "Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm" { { "Info" "ISGN_ENTITY_NAME" "1 vga_driver " "Info: Found entity 1: vga_driver" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 25 18 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 vga_control " "Info: Found entity 2: vga_control" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3123 19 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 vga " "Info: Found entity 3: vga" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4396 11 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../src/vpll.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../src/vpll.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vpll-SYN " "Info: Found design unit 1: vpll-SYN" { } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd" 57 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 vpll " "Info: Found entity 1: vpll" { } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd" 45 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "vga_pll " "Info: Elaborating entity \"vga_pll\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga vga:inst " "Info: Elaborating entity \"vga\" for hierarchy \"vga:inst\"" { } { { "../../src/vga_pll.bdf" "inst" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 56 712 928 600 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_driver vga:inst\|vga_driver:vga_driver_unit " "Info: Elaborating entity \"vga_driver\" for hierarchy \"vga:inst\|vga_driver:vga_driver_unit\"" { } { { "../../syn/rev_1/vga.vqm" "vga_driver_unit" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6149 3 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_control vga:inst\|vga_control:vga_control_unit " "Info: Elaborating entity \"vga_control\" for hierarchy \"vga:inst\|vga_control:vga_control_unit\"" { } { { "../../syn/rev_1/vga.vqm" "vga_control_unit" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6204 3 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vpll vpll:inst1 " "Info: Elaborating entity \"vpll\" for hierarchy \"vpll:inst1\"" { } { { "../../src/vga_pll.bdf" "inst1" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 56 416 512 152 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "locked vpll.vhd(73) " "Warning (10036): Verilog HDL or VHDL warning at vpll.vhd(73): object \"locked\" assigned a value but never read" { } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd" 73 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll vpll:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"vpll:inst1\|altpll:altpll_component\"" { } { { "../../src/vpll.vhd" "altpll_component" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd" 121 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "vpll:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"vpll:inst1\|altpll:altpll_component\"" { } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd" 121 0 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "vpll:inst1\|altpll:altpll_component " "Info: Instantiated megafunction \"vpll:inst1\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Info: Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5435 " "Info: Parameter \"clk0_multiply_by\" = \"5435\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "invalid_lock_multiplier 5 " "Info: Parameter \"invalid_lock_multiplier\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 30003 " "Info: Parameter \"inclk0_input_frequency\" = \"30003\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "gate_lock_signal NO " "Info: Parameter \"gate_lock_signal\" = \"NO\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 6666 " "Info: Parameter \"clk0_divide_by\" = \"6666\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Info: Parameter \"pll_type\" = \"AUTO\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "valid_lock_multiplier 1 " "Info: Parameter \"valid_lock_multiplier\" = \"1\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_time_delay 0 " "Info: Parameter \"clk0_time_delay\" = \"0\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "spread_frequency 0 " "Info: Parameter \"spread_frequency\" = \"0\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix " "Info: Parameter \"intended_device_family\" = \"Stratix\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info: Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info: Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Info: Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd" 121 0 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISCL_SCL_WYSIWYG_UNMAPPED_IO_HDR" "" "Info: WYSIWYG I/O primitives converted to equivalent logic" { { "Info" "ISCL_SCL_WYSIWYG_UNMAPPED_IO" "vga:inst\|clk_pin_in " "Info: WYSIWYG I/O primitive \"vga:inst\|clk_pin_in\" converted to equivalent logic" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4585 3 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 56 712 928 600 "inst" "" } } } } } 0 0 "WYSIWYG I/O primitive \"%1!s!\" converted to equivalent logic" 0 0 "" 0 -1} } { } 0 0 "WYSIWYG I/O primitives converted to equivalent logic" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "293 " "Info: Implemented 293 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "115 " "Info: Implemented 115 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "175 " "Info: Implemented 175 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" { } { } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 vpll:inst1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"vpll:inst1\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd" 121 0 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 56 416 512 152 "inst1" "" } } } } } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "204 " "Info: Peak virtual memory: 204 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:54:40 2009 " "Info: Processing ended: Wed Oct 28 14:54:40 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:55:36 2009 " "Info: Processing started: Wed Oct 28 14:55:36 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" { } { } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0 -1}
+{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4 register vga:inst\|vga_control:vga_control_unit\|r 28.83 ns " "Info: Slack time is 28.83 ns for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4\" and destination register \"vga:inst\|vga_control:vga_control_unit\|r\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "125.83 MHz 7.947 ns " "Info: Fmax is 125.83 MHz (period= 7.947 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.570 ns + Largest register register " "Info: + Largest register to register requirement is 36.570 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "36.777 ns + " "Info: + Setup relationship between source and destination is 36.777 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 35.747 ns " "Info: + Latch edge is 35.747 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.021 ns + Largest " "Info: + Largest clock skew is -0.021 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.043 ns + Shortest register " "Info: + Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.483 ns) + CELL(0.560 ns) 2.043 ns vga:inst\|vga_control:vga_control_unit\|r 2 REG LC_X72_Y6_N1 4 " "Info: 2: + IC(1.483 ns) + CELL(0.560 ns) = 2.043 ns; Loc. = LC_X72_Y6_N1; Fanout = 4; REG Node = 'vga:inst\|vga_control:vga_control_unit\|r'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.41 % ) " "Info: Total cell delay = 0.560 ns ( 27.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.483 ns ( 72.59 % ) " "Info: Total interconnect delay = 1.483 ns ( 72.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.064 ns - Longest register " "Info: - Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.064 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.504 ns) + CELL(0.560 ns) 2.064 ns vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4 2 REG LC_X22_Y42_N7 9 " "Info: 2: + IC(1.504 ns) + CELL(0.560 ns) = 2.064 ns; Loc. = LC_X22_Y42_N7; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 96 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.13 % ) " "Info: Total cell delay = 0.560 ns ( 27.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.504 ns ( 72.87 % ) " "Info: Total interconnect delay = 1.504 ns ( 72.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} } { 0.000ns 1.504ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} } { 0.000ns 1.504ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 96 28 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} } { 0.000ns 1.504ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.740 ns - Longest register register " "Info: - Longest register to register delay is 7.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4 1 REG LC_X22_Y42_N7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y42_N7; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|line_counter_sig_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 96 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.332 ns) 1.344 ns vga:inst\|vga_control:vga_control_unit\|un13_v_enablelto4_0 2 COMB LC_X18_Y42_N6 1 " "Info: 2: + IC(1.012 ns) + CELL(0.332 ns) = 1.344 ns; Loc. = LC_X18_Y42_N6; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|un13_v_enablelto4_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.344 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3301 27 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.332 ns) 2.012 ns vga:inst\|vga_control:vga_control_unit\|un13_v_enablelto6 3 COMB LC_X18_Y42_N4 1 " "Info: 3: + IC(0.336 ns) + CELL(0.332 ns) = 2.012 ns; Loc. = LC_X18_Y42_N4; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|un13_v_enablelto6'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.668 ns" { vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3293 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.768 ns) + CELL(0.332 ns) 4.112 ns vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4 4 COMB LC_X28_Y35_N2 2 " "Info: 4: + IC(1.768 ns) + CELL(0.332 ns) = 4.112 ns; Loc. = LC_X28_Y35_N2; Fanout = 2; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|b_next_0_sqmuxa_7_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.100 ns" { vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3286 27 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.139 ns) + CELL(0.489 ns) 7.740 ns vga:inst\|vga_control:vga_control_unit\|r 5 REG LC_X72_Y6_N1 4 " "Info: 5: + IC(3.139 ns) + CELL(0.489 ns) = 7.740 ns; Loc. = LC_X72_Y6_N1; Fanout = 4; REG Node = 'vga:inst\|vga_control:vga_control_unit\|r'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.628 ns" { vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3226 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.485 ns ( 19.19 % ) " "Info: Total cell delay = 1.485 ns ( 19.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.255 ns ( 80.81 % ) " "Info: Total interconnect delay = 6.255 ns ( 80.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.740 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.740 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 {} vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 {} vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.012ns 0.336ns 1.768ns 3.139ns } { 0.000ns 0.332ns 0.332ns 0.332ns 0.489ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.064 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} } { 0.000ns 1.504ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.740 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 vga:inst|vga_control:vga_control_unit|r } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.740 ns" { vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 {} vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 {} vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 {} vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 {} vga:inst|vga_control:vga_control_unit|r {} } { 0.000ns 1.012ns 0.336ns 1.768ns 3.139ns } { 0.000ns 0.332ns 0.332ns 0.332ns 0.489ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITAN_NO_REG2REG_EXIST" "board_clk " "Info: No valid register-to-register data paths exist for clock \"board_clk\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 register vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5 730 ps " "Info: Minimum slack time is 730 ps for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0\" and destination register \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.654 ns + Shortest register register " "Info: + Shortest register to register delay is 0.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 1 REG LC_X42_Y42_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.235 ns) 0.654 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5 2 REG LC_X42_Y42_N2 4 " "Info: 2: + IC(0.419 ns) + CELL(0.235 ns) = 0.654 ns; Loc. = LC_X42_Y42_N2; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.235 ns ( 35.93 % ) " "Info: Total cell delay = 0.235 ns ( 35.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.419 ns ( 64.07 % ) " "Info: Total interconnect delay = 0.419 ns ( 64.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.419ns } { 0.000ns 0.235ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.076 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.076 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.030 ns " "Info: + Latch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.097 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.537 ns) + CELL(0.560 ns) 2.097 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5 2 REG LC_X42_Y42_N2 4 " "Info: 2: + IC(1.537 ns) + CELL(0.560 ns) = 2.097 ns; Loc. = LC_X42_Y42_N2; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.70 % ) " "Info: Total cell delay = 0.560 ns ( 26.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.537 ns ( 73.30 % ) " "Info: Total interconnect delay = 1.537 ns ( 73.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.097 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.537 ns) + CELL(0.560 ns) 2.097 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 2 REG LC_X42_Y42_N9 4 " "Info: 2: + IC(1.537 ns) + CELL(0.560 ns) = 2.097 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.70 % ) " "Info: Total cell delay = 0.560 ns ( 26.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.537 ns ( 73.30 % ) " "Info: Total interconnect delay = 1.537 ns ( 73.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.654 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.419ns } { 0.000ns 0.235ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 reset board_clk 10.866 ns register " "Info: tsu for register \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0\" (data pin = \"reset\", clock pin = \"board_clk\") is 10.866 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.923 ns + Longest pin register " "Info: + Longest pin to register delay is 11.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 96 544 712 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.624 ns) + CELL(0.213 ns) 6.978 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X30_Y38_N3 53 " "Info: 2: + IC(5.624 ns) + CELL(0.213 ns) = 6.978 ns; Loc. = LC_X30_Y38_N3; Fanout = 53; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.837 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.397 ns) + CELL(0.213 ns) 9.588 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0 3 COMB LC_X52_Y41_N9 6 " "Info: 3: + IC(2.397 ns) + CELL(0.213 ns) = 9.588 ns; Loc. = LC_X52_Y41_N9; Fanout = 6; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.610 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 246 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.609 ns) + CELL(0.726 ns) 11.923 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 4 REG LC_X42_Y42_N9 4 " "Info: 4: + IC(1.609 ns) + CELL(0.726 ns) = 11.923 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.335 ns" { vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.293 ns ( 19.23 % ) " "Info: Total cell delay = 2.293 ns ( 19.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.630 ns ( 80.77 % ) " "Info: Total interconnect delay = 9.630 ns ( 80.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "11.923 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "11.923 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 0.000ns 5.624ns 2.397ns 1.609ns } { 0.000ns 1.141ns 0.213ns 0.213ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns - " "Info: - Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 80 248 416 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.097 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.537 ns) + CELL(0.560 ns) 2.097 ns vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0 2 REG LC_X42_Y42_N9 4 " "Info: 2: + IC(1.537 ns) + CELL(0.560 ns) = 2.097 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|hsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 112 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.70 % ) " "Info: Total cell delay = 0.560 ns ( 26.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.537 ns ( 73.30 % ) " "Info: Total interconnect delay = 1.537 ns ( 73.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "11.923 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "11.923 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 0.000ns 5.624ns 2.397ns 1.609ns } { 0.000ns 1.141ns 0.213ns 0.213ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|hsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.097 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|hsync_state_0 {} } { 0.000ns 1.537ns } { 0.000ns 0.560ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "board_clk seven_seg_pin\[7\] vga:inst\|dly_counter\[0\] 11.498 ns register " "Info: tco from clock \"board_clk\" to destination pin \"seven_seg_pin\[7\]\" through register \"vga:inst\|dly_counter\[0\]\" is 11.498 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns + " "Info: + Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 80 248 416 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.043 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.483 ns) + CELL(0.560 ns) 2.043 ns vga:inst\|dly_counter\[0\] 2 REG LC_X30_Y39_N4 10 " "Info: 2: + IC(1.483 ns) + CELL(0.560 ns) = 2.043 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.41 % ) " "Info: Total cell delay = 0.560 ns ( 27.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.483 ns ( 72.59 % ) " "Info: Total interconnect delay = 1.483 ns ( 72.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.309 ns + Longest register pin " "Info: + Longest register to pin delay is 10.309 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|dly_counter\[0\] 1 REG LC_X30_Y39_N4 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.164 ns) + CELL(0.087 ns) 1.251 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X30_Y38_N3 53 " "Info: 2: + IC(1.164 ns) + CELL(0.087 ns) = 1.251 ns; Loc. = LC_X30_Y38_N3; Fanout = 53; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.251 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.867 ns) + CELL(4.191 ns) 10.309 ns seven_seg_pin\[7\] 3 PIN PIN_Y11 0 " "Info: 3: + IC(4.867 ns) + CELL(4.191 ns) = 10.309 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin\[7\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.058 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 240 928 1148 256 "seven_seg_pin\[13..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.278 ns ( 41.50 % ) " "Info: Total cell delay = 4.278 ns ( 41.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.031 ns ( 58.50 % ) " "Info: Total interconnect delay = 6.031 ns ( 58.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "10.309 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "10.309 ns" { vga:inst|dly_counter[0] {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 1.164ns 4.867ns } { 0.000ns 0.087ns 4.191ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "10.309 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "10.309 ns" { vga:inst|dly_counter[0] {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 1.164ns 4.867ns } { 0.000ns 0.087ns 4.191ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "reset seven_seg_pin\[7\] 16.036 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"seven_seg_pin\[7\]\" is 16.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 96 544 712 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.624 ns) + CELL(0.213 ns) 6.978 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X30_Y38_N3 53 " "Info: 2: + IC(5.624 ns) + CELL(0.213 ns) = 6.978 ns; Loc. = LC_X30_Y38_N3; Fanout = 53; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.837 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.867 ns) + CELL(4.191 ns) 16.036 ns seven_seg_pin\[7\] 3 PIN PIN_Y11 0 " "Info: 3: + IC(4.867 ns) + CELL(4.191 ns) = 16.036 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin\[7\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.058 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 240 928 1148 256 "seven_seg_pin\[13..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.545 ns ( 34.58 % ) " "Info: Total cell delay = 5.545 ns ( 34.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.491 ns ( 65.42 % ) " "Info: Total interconnect delay = 10.491 ns ( 65.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "16.036 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "16.036 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 0.000ns 5.624ns 4.867ns } { 0.000ns 1.141ns 0.213ns 4.191ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "vga:inst\|dly_counter\[0\] reset board_clk -5.569 ns register " "Info: th for register \"vga:inst\|dly_counter\[0\]\" (data pin = \"reset\", clock pin = \"board_clk\") is -5.569 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns + " "Info: + Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 80 248 416 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.043 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.483 ns) + CELL(0.560 ns) 2.043 ns vga:inst\|dly_counter\[0\] 2 REG LC_X30_Y39_N4 10 " "Info: 2: + IC(1.483 ns) + CELL(0.560 ns) = 2.043 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.41 % ) " "Info: Total cell delay = 0.560 ns ( 27.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.483 ns ( 72.59 % ) " "Info: Total interconnect delay = 1.483 ns ( 72.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.682 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf" { { 96 544 712 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.177 ns) + CELL(0.364 ns) 6.682 ns vga:inst\|dly_counter\[0\] 2 REG LC_X30_Y39_N4 10 " "Info: 2: + IC(5.177 ns) + CELL(0.364 ns) = 6.682 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.541 ns" { reset vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.505 ns ( 22.52 % ) " "Info: Total cell delay = 1.505 ns ( 22.52 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.177 ns ( 77.48 % ) " "Info: Total interconnect delay = 5.177 ns ( 77.48 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.682 ns" { reset vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.682 ns" { reset {} reset~out0 {} vga:inst|dly_counter[0] {} } { 0.000ns 0.000ns 5.177ns } { 0.000ns 1.141ns 0.364ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.043 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.483ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.682 ns" { reset vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.682 ns" { reset {} reset~out0 {} vga:inst|dly_counter[0] {} } { 0.000ns 0.000ns 5.177ns } { 0.000ns 1.141ns 0.364ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Peak virtual memory: 141 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:55:37 2009 " "Info: Processing ended: Wed Oct 28 14:55:37 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+Version:
+ 9.0 Build 132 02/25/2009 SJ Full Version
+
+Chip Device Options:
+ Device Name: EP1S25F672C6
+ Device JTAG code: ffffffff
+ Programming_mode: Passive Serial
+ NWS_NRS_NCS: UNRESERVED
+ RDYNBUSY: UNRESERVED
+ DATA 7 to 1: UNRESERVED
+ nCEO: UNRESERVED
+ UNUSED PINS: RESERVED_GND
+ Default IO Standard:: 3.3-V LVTTL
+ User Start-up Clock: 0
+ Auto Restart on Error: 1
+ Release Clears Before Tristates: 0
+ Device Clear: 0
+ Test And Scan: 0
+ Device OE: 0
+ Enable Lock Output: 0
+ Enable Init Done: 0
+ Enable JTAG BST: 0
+ Enable Vref A: 0
+ Enable Vref B: 0
+
+
+
+****************************
+******Individual Atoms******
+****************************
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|h_sync_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 230
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|h_sync LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|v_sync_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 231
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|v_sync LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 232
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 233
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 234
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 FANOUTS 5
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|d_set_vsync_counter_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 235
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|r_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 236
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|b_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 237
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|b LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 4000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|h_enable_sig_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 238
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 FANOUTS 2 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|v_enable_sig_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 239
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vpll:inst1|altpll:altpll_component|pll -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 240
+ Atom Type: stratix_pll (WYSIWYG)
+
+User mode PLL
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [INCLK] board_clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: [INCLK] DISCONNECTED
+ 11: [CLKENA] DISCONNECTED
+ 12: [CLKENA] DISCONNECTED
+ 13: [CLKENA] DISCONNECTED
+ 14: [CLKENA] DISCONNECTED
+ 15: [CLKENA] DISCONNECTED
+ 16: [CLKENA] DISCONNECTED
+ 17: [EXTCLKENA] DISCONNECTED
+ 18: [EXTCLKENA] DISCONNECTED
+ 19: [EXTCLKENA] DISCONNECTED
+ 20: [EXTCLKENA] DISCONNECTED
+ OUTPUTS (Int. Connections):
+ 0: [ACTIVECLOCK] vpll:inst1|altpll:altpll_component|pll~ACTIVECLOCK LIT INDEX 0 FANOUTS 0
+ 1: [CLKLOSS] vpll:inst1|altpll:altpll_component|pll~GLOCKED LIT INDEX 0 FANOUTS 0
+ 2: [LOCKED] vpll:inst1|altpll:altpll_component|pll~LOCKED LIT INDEX 0 FANOUTS 0
+ 3: [SCANDATAOUT] vpll:inst1|altpll:altpll_component|pll~SCANDATAOUT LIT INDEX 0 FANOUTS 0
+ 4: [ENABLE0] vpll:inst1|altpll:altpll_component|pll~ENAOUT0 LIT INDEX 0 FANOUTS 0
+ 5: [ENABLE1] vpll:inst1|altpll:altpll_component|pll~ENAOUT1 LIT INDEX 0 FANOUTS 0
+ 6: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 FANOUTS 84
+ 7: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK1 LIT INDEX 1 FANOUTS 0
+ 8: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK2 LIT INDEX 2 FANOUTS 0
+ 9: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK3 LIT INDEX 3 FANOUTS 0
+ 10: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK4 LIT INDEX 4 FANOUTS 0
+ 11: [CLK] vpll:inst1|altpll:altpll_component|pll~CLK5 LIT INDEX 5 FANOUTS 0
+ 12: [EXTCLK] vpll:inst1|altpll:altpll_component|pll~EXTCLK0 LIT INDEX 0 FANOUTS 0
+ 13: [EXTCLK] vpll:inst1|altpll:altpll_component|pll~EXTCLK1 LIT INDEX 1 FANOUTS 0
+ 14: [EXTCLK] vpll:inst1|altpll:altpll_component|pll~EXTCLK2 LIT INDEX 2 FANOUTS 0
+ 15: [EXTCLK] vpll:inst1|altpll:altpll_component|pll~EXTCLK3 LIT INDEX 3 FANOUTS 0
+ 16: [CLKBAD] vpll:inst1|altpll:altpll_component|pll~CLKBAD0 LIT INDEX 0 FANOUTS 0
+ 17: [CLKBAD] vpll:inst1|altpll:altpll_component|pll~CLKBAD1 LIT INDEX 1 FANOUTS 0
+
+ PARAMETER LIST:
+ operation_mode = normal
+ pll_type = auto
+ qualify_conf_done = off
+ valid_lock_multiplier = 1
+ invalid_lock_multiplier = 5
+ scan_chain_mif_file =
+ compensate_clock = clk0
+ feedback_source =
+ inclk0_input_frequency = 30003
+ inclk1_input_frequency = 30003
+ pfd_min = 2380
+ pfd_max = 333333
+ vco_min = 1250
+ vco_max = 3334
+ vco_center = 1666
+ pll_compensation_delay = 3806
+ input_comp_delay_chain_bits = 0
+ feedback_comp_delay_chain_bits = 0
+ common_rx_tx = on
+ skip_vco = off
+ rx_outclock_resource = auto
+ primary_clock = inclk0
+ switch_over_on_lossclk = off
+ switch_over_on_gated_lock = off
+ enable_switch_over_counter = off
+ gate_lock_signal = no
+ scan_chain =
+ gate_lock_counter = 0
+ switch_over_counter = 1
+ ======= Real External and Internal Parameters ======= =
+ bandwidth_type = auto
+ bandwidth = 8043251
+ spread_frequency = 0
+ down_spread = 0 %
+ clk0_multiply_by = 53
+ clk1_multiply_by = 1
+ clk2_multiply_by = 1
+ clk3_multiply_by = 1
+ clk4_multiply_by = 1
+ clk5_multiply_by = 1
+ extclk0_multiply_by = 1
+ extclk1_multiply_by = 1
+ extclk2_multiply_by = 1
+ extclk3_multiply_by = 1
+ clk0_divide_by = 65
+ clk1_divide_by = 1
+ clk2_divide_by = 1
+ clk3_divide_by = 1
+ clk4_divide_by = 1
+ clk5_divide_by = 1
+ extclk0_divide_by = 1
+ extclk1_divide_by = 1
+ extclk2_divide_by = 1
+ extclk3_divide_by = 1
+ clk0_phase_shift = 0
+ clk1_phase_shift = 0
+ clk2_phase_shift = 0
+ clk3_phase_shift = 0
+ clk4_phase_shift = 0
+ clk5_phase_shift = 0
+ extclk0_phase_shift = 0
+ extclk1_phase_shift = 0
+ extclk2_phase_shift = 0
+ extclk3_phase_shift = 0
+ clk0_time_delay = 0
+ clk1_time_delay = 0
+ clk2_time_delay = 0
+ clk3_time_delay = 0
+ clk4_time_delay = 0
+ clk5_time_delay = 0
+ extclk0_time_delay = 0
+ extclk1_time_delay = 0
+ extclk2_time_delay = 0
+ extclk3_time_delay = 0
+ clk0_duty_cycle = 50
+ clk1_duty_cycle = 50
+ clk2_duty_cycle = 50
+ clk3_duty_cycle = 50
+ clk4_duty_cycle = 50
+ clk5_duty_cycle = 50
+ extclk0_duty_cycle = 50
+ extclk1_duty_cycle = 50
+ extclk2_duty_cycle = 50
+ extclk3_duty_cycle = 50
+ clk0_use_even_counter_mode = off
+ clk1_use_even_counter_mode = off
+ clk2_use_even_counter_mode = off
+ clk3_use_even_counter_mode = off
+ clk4_use_even_counter_mode = off
+ clk5_use_even_counter_mode = off
+ extclk0_use_even_counter_mode = off
+ extclk1_use_even_counter_mode = off
+ extclk2_use_even_counter_mode = off
+ extclk3_use_even_counter_mode = off
+ clk0_use_even_counter_value = off
+ clk1_use_even_counter_value = off
+ clk2_use_even_counter_value = off
+ clk3_use_even_counter_value = off
+ clk4_use_even_counter_value = off
+ clk5_use_even_counter_value = off
+ extclk0_use_even_counter_value = off
+ extclk1_use_even_counter_value = off
+ extclk2_use_even_counter_value = off
+ extclk3_use_even_counter_value = off
+ m = 106
+ n = 5
+ m2 = 1
+ n2 = 1
+ ss = 0
+ charge_pump_current = 50
+ loop_filter_c = 10
+ loop_filter_r = 1.021000
+ enable0_counter =
+ enable1_counter =
+ clk0_counter = g0
+ clk1_counter =
+ clk2_counter =
+ clk3_counter =
+ clk4_counter =
+ clk5_counter =
+ extclk0_counter =
+ extclk1_counter =
+ extclk2_counter =
+ extclk3_counter =
+ l0_is_used = no
+ l1_is_used = no
+ g0_is_used = yes
+ g1_is_used = no
+ g2_is_used = no
+ g3_is_used = no
+ e0_is_used = no
+ e1_is_used = no
+ e2_is_used = no
+ e3_is_used = no
+ l0_mode = odd
+ l1_mode = bypass
+ g0_mode = even
+ g1_mode = bypass
+ g2_mode = bypass
+ g3_mode = bypass
+ e0_mode = bypass
+ e1_mode = bypass
+ e2_mode = bypass
+ e3_mode = bypass
+ l0_high = 10
+ l1_high = 0
+ g0_high = 13
+ g1_high = 0
+ g2_high = 0
+ g3_high = 0
+ e0_high = 0
+ e1_high = 0
+ e2_high = 0
+ e3_high = 0
+ l0_low = 9
+ l1_low = 0
+ g0_low = 13
+ g1_low = 0
+ g2_low = 0
+ g3_low = 0
+ e0_low = 0
+ e1_low = 0
+ e2_low = 0
+ e3_low = 0
+ m_initial = 1
+ l0_initial = 1
+ l1_initial = 1
+ g0_initial = 1
+ g1_initial = 1
+ g2_initial = 1
+ g3_initial = 1
+ e0_initial = 1
+ e1_initial = 1
+ e2_initial = 1
+ e3_initial = 1
+ m_ph = 0
+ l0_ph = 0
+ l1_ph = 0
+ g0_ph = 0
+ g1_ph = 0
+ g2_ph = 0
+ g3_ph = 0
+ e0_ph = 0
+ e1_ph = 0
+ e2_ph = 0
+ e3_ph = 0
+ m_time_delay = 0
+ n_time_delay = 0
+ l0_time_delay = 0
+ l1_time_delay = 0
+ g0_time_delay = 0
+ g1_time_delay = 0
+ g2_time_delay = 0
+ g3_time_delay = 0
+ e0_time_delay = 0
+ e1_time_delay = 0
+ e2_time_delay = 0
+ e3_time_delay = 0
+ ======= User External and Internal Parameters ======= =
+ bandwidth_type = auto
+ bandwidth = 0
+ spread_frequency = 0
+ down_spread = 0
+ clk0_multiply_by = 5435
+ clk1_multiply_by = 1
+ clk2_multiply_by = 1
+ clk3_multiply_by = 1
+ clk4_multiply_by = 1
+ clk5_multiply_by = 1
+ extclk0_multiply_by = 1
+ extclk1_multiply_by = 1
+ extclk2_multiply_by = 1
+ extclk3_multiply_by = 1
+ clk0_divide_by = 6666
+ clk1_divide_by = 1
+ clk2_divide_by = 1
+ clk3_divide_by = 1
+ clk4_divide_by = 1
+ clk5_divide_by = 1
+ extclk0_divide_by = 1
+ extclk1_divide_by = 1
+ extclk2_divide_by = 1
+ extclk3_divide_by = 1
+ clk0_phase_shift = 0
+ clk1_phase_shift = 0
+ clk2_phase_shift = 0
+ clk3_phase_shift = 0
+ clk4_phase_shift = 0
+ clk5_phase_shift = 0
+ extclk0_phase_shift = 0
+ extclk1_phase_shift = 0
+ extclk2_phase_shift = 0
+ extclk3_phase_shift = 0
+ clk0_time_delay = 0
+ clk1_time_delay = 0
+ clk2_time_delay = 0
+ clk3_time_delay = 0
+ clk4_time_delay = 0
+ clk5_time_delay = 0
+ extclk0_time_delay = 0
+ extclk1_time_delay = 0
+ extclk2_time_delay = 0
+ extclk3_time_delay = 0
+ clk0_duty_cycle = 50
+ clk1_duty_cycle = 50
+ clk2_duty_cycle = 50
+ clk3_duty_cycle = 50
+ clk4_duty_cycle = 50
+ clk5_duty_cycle = 50
+ extclk0_duty_cycle = 50
+ extclk1_duty_cycle = 50
+ extclk2_duty_cycle = 50
+ extclk3_duty_cycle = 50
+ clk0_use_even_counter_mode = off
+ clk1_use_even_counter_mode = off
+ clk2_use_even_counter_mode = off
+ clk3_use_even_counter_mode = off
+ clk4_use_even_counter_mode = off
+ clk5_use_even_counter_mode = off
+ extclk0_use_even_counter_mode = off
+ extclk1_use_even_counter_mode = off
+ extclk2_use_even_counter_mode = off
+ extclk3_use_even_counter_mode = off
+ clk0_use_even_counter_value = off
+ clk1_use_even_counter_value = off
+ clk2_use_even_counter_value = off
+ clk3_use_even_counter_value = off
+ clk4_use_even_counter_value = off
+ clk5_use_even_counter_value = off
+ extclk0_use_even_counter_value = off
+ extclk1_use_even_counter_value = off
+ extclk2_use_even_counter_value = off
+ extclk3_use_even_counter_value = off
+ m = 234
+ n = 7
+ m2 = 1
+ n2 = 1
+ ss = 0
+ charge_pump_current = 0
+ loop_filter_c = 0
+ loop_filter_r = 0.000000
+ enable0_counter =
+ enable1_counter =
+ clk0_counter = l0
+ clk1_counter =
+ clk2_counter =
+ clk3_counter =
+ clk4_counter =
+ clk5_counter =
+ extclk0_counter =
+ extclk1_counter =
+ extclk2_counter =
+ extclk3_counter =
+ l0_is_used = yes
+ l1_is_used = no
+ g0_is_used = no
+ g1_is_used = no
+ g2_is_used = no
+ g3_is_used = no
+ e0_is_used = no
+ e1_is_used = no
+ e2_is_used = no
+ e3_is_used = no
+ l0_mode = odd
+ l1_mode = bypass
+ g0_mode = bypass
+ g1_mode = bypass
+ g2_mode = bypass
+ g3_mode = bypass
+ e0_mode = bypass
+ e1_mode = bypass
+ e2_mode = bypass
+ e3_mode = bypass
+ l0_high = 21
+ l1_high = 0
+ g0_high = 0
+ g1_high = 0
+ g2_high = 0
+ g3_high = 0
+ e0_high = 0
+ e1_high = 0
+ e2_high = 0
+ e3_high = 0
+ l0_low = 20
+ l1_low = 0
+ g0_low = 0
+ g1_low = 0
+ g2_low = 0
+ g3_low = 0
+ e0_low = 0
+ e1_low = 0
+ e2_low = 0
+ e3_low = 0
+ m_initial = 1
+ l0_initial = 1
+ l1_initial = 1
+ g0_initial = 1
+ g1_initial = 1
+ g2_initial = 1
+ g3_initial = 1
+ e0_initial = 1
+ e1_initial = 1
+ e2_initial = 1
+ e3_initial = 1
+ m_ph = 0
+ l0_ph = 0
+ l1_ph = 0
+ g0_ph = 0
+ g1_ph = 0
+ g2_ph = 0
+ g3_ph = 0
+ e0_ph = 0
+ e1_ph = 0
+ e2_ph = 0
+ e3_ph = 0
+ m_time_delay = 0
+ n_time_delay = 0
+ l0_time_delay = 0
+ l1_time_delay = 0
+ g0_time_delay = 0
+ g1_time_delay = 0
+ g2_time_delay = 0
+ g3_time_delay = 0
+ e0_time_delay = 0
+ e1_time_delay = 0
+ e2_time_delay = 0
+ e3_time_delay = 0
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_sig_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 241
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_sig LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 9999
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 242
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 243
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 244
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 245
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 246
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 247
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 248
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 249
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 250
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 251
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7777
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 252
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 253
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[8] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 254
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 FANOUTS 7 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 255
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 FANOUTS 7 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 256
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 257
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 FANOUTS 7 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 258
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 259
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 260
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 261
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_cout[0] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 55aa
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 262
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8888
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 263
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8888
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 264
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = aaaa
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 265
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 266
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 267
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff00
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 268
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 269
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 270
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 271
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 272
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 273
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 274
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 275
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 276
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 277
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[18] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a5a5
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 278
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[17] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c6c
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 279
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[16] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[18] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 280
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[15] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[17] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 281
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[14] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[16] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 282
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[13] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[15] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 283
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[12] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[14] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 284
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[11] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[13] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 285
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[10] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[12] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 286
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[11] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 287
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[10] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 288
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[9] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 289
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[8] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 290
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 291
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 292
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 293
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 294
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 295
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_control:vga_control_unit|un2_toggle_counter_next_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 296
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 6688
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 297
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 5555
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 298
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 FANOUTS 9 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 299
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[8] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 300
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 301
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 302
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 303
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 304
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 305
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 306
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 307
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [SYNCH_DATA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga:inst|vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 FANOUTS 9 REGED POS
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[0] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 6688
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 308
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0cae
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 309
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 310
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = aaaa
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 311
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 2000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 312
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 313
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 FANOUTS 53
+ 1: [REGOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f7f
+ output_mode = reg_and_comb
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|dly_counter_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 315
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|dly_counter[0] LIT INDEX 0 FANOUTS 9 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = a2a2
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|dly_counter_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 316
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga:inst|dly_counter[1] LIT INDEX 0 FANOUTS 9 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = a8a8
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 317
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ccd8
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 318
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_2_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ccd8
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 319
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0808
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 320
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 FANOUTS 4
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0101
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 321
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0008
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 322
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 FANOUTS 6
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f0f1
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 323
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 FANOUTS 3
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0001
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 324
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 325
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ef23
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_5_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 326
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|un5_v_enablelto5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_5 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f00
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 327
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f1f1
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 328
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f1f1
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 330
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglto18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1 LIT INDEX 0 FANOUTS 22
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7733
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 331
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[9] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c6c6
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 332
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 1f0f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 333
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 334
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[8] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a5a5
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 335
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[7] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 336
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[6] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 337
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[5] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 338
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[4] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 339
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[3] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 340
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[2] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 341
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_combout[1] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 6688
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 342
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|G_2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 343
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|G_2_i LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0f1f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 344
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9 LIT INDEX 0 FANOUTS 11
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f7ff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 345
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 1000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 346
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 347
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0101
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 348
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 349
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 FANOUTS 9
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 350
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[9] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c6c6
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 351
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 LIT INDEX 0 FANOUTS 9
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 352
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[8] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a5a5
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 353
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[7] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 354
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[6] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 355
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[5] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 356
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[4] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 357
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 358
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_a_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[2] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 359
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_combout[1] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 6688
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|un2_toggle_counter_next_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 360
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un2_toggle_counter_next_0_~COMBOUT LIT INDEX 0 FANOUTS 0
+ 1: NONE
+ 2: [COUT] vga:inst|vga_control:vga_control_unit|un2_toggle_counter_next_cout[0] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff88
+ output_mode = none
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 361
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] reset LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|G_16 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 362
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|G_16_i LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0f1f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 363
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9 LIT INDEX 0 FANOUTS 11
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = fff7
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 364
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 365
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 FANOUTS 5
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = aaab
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 366
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 FANOUTS 4
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8888
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_3_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 368
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_3_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_2_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 369
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_2_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 370
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 2aaa
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 371
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 2aaa
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 372
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0ace
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 373
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0001
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 374
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un13_v_enablelto6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f77
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 375
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|un17_v_enablelto3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0f1f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 376
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|un5_v_enablelt2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un5_v_enablelto5 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = feee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_3_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 377
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|un9_v_enablelto6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = e0f0
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 378
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglto15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglto18 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f77
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 379
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 380
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_0_~COMBOUT LIT INDEX 0 FANOUTS 0
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un2_column_counter_next_cout[0] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff88
+ output_mode = none
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 381
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7fff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 382
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 383
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un13_hsync_counter_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 384
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0008
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 385
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_hsync_counter_4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0010
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 386
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglt4_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto5 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0f07
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_a_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 387
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT LIT INDEX 0 FANOUTS 0
+ 1: NONE
+ 2: [COUT] vga:inst|vga_driver:vga_driver_unit|un1_line_counter_sig_a_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff88
+ output_mode = none
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 388
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9_5 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7fff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 389
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9_6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7fff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 390
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 FANOUTS 3
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0001
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 391
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 1010
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 392
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = d0f0
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 393
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 70f0
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 394
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff2a
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 395
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 1111
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 396
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un17_v_enablelto3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = fe00
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 397
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un5_v_enablelt2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = fefe
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_2_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 398
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0004
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 399
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|un9_v_enablelto4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un9_v_enablelto6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f7f7
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 400
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglto12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglto15 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 401
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglt6_4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7fff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 402
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglt4_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f7f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 403
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|un15_vsync_counter_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0020
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 404
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 2a2a
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 405
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un9_v_enablelto4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0101
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 406
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglto12 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0100
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 407
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglt6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglto9 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f77
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 408
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga:inst|vga_control:vga_control_unit|un1_toggle_counter_siglt6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7777
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: board_clk -- NON-UNIQUE
+ Atom Hier Name:
+ Atom Id: 329
+ Atom Type: stratix_io
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] board_clk LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] board_clk LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = input
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 115
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 116
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_set_column_counter_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 117
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_set_column_counter LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_set_line_counter_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 118
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_set_line_counter LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_set_hsync_counter_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 119
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_set_hsync_counter LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_set_vsync_counter_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 120
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_set_vsync_counter LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_r_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 121
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_r LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_g_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 122
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_g LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_b_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 123
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_b LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_h_enable_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 124
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_h_enable LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_v_enable_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 125
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_v_enable LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_state_clk_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 126
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vpll:inst1|altpll:altpll_component|_clk0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_state_clk LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 127
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|r0_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 128
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] r0_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|r1_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 129
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] r1_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|r2_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 130
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] r2_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|g0_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 131
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] g0_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|g1_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 132
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] g1_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|g2_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 133
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] g2_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|b0_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 134
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] b0_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|b1_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 135
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] b1_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|hsync_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 136
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] hsync_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|vsync_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 137
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] vsync_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 138
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 139
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 140
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 141
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 142
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 143
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 144
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 145
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 146
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_column_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 147
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 148
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 149
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 150
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 151
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 152
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 153
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 154
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 155
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 156
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 157
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_state_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 158
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_state_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 159
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_state_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 160
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_state_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 161
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_state_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 162
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_state_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 163
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_hsync_state_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 164
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_line_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 165
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_line_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 166
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_line_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 167
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_line_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 168
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_line_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 169
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_line_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 170
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_line_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 171
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_line_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 172
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_line_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 173
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_24_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 174
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[24] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_23_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 175
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[23] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_22_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 176
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[22] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_21_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 177
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[21] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_20_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 178
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[20] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_19_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 179
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[19] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_18_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 180
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[18] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_17_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 181
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[17] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_16_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 182
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[16] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_15_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 183
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[15] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_14_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 184
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[14] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_13_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 185
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[13] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_12_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 186
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[12] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_11_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 187
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[11] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_10_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 188
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[10] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 189
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 190
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 191
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 192
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 193
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 194
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 195
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 196
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 197
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_toggle_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 198
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 199
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 200
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 201
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 202
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 203
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 204
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 205
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 206
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 207
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 208
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_state_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 209
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_state_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 210
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_state_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 211
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_state_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 212
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_state_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 213
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_state_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 214
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|d_vsync_state_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 215
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_tri_13_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 216
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[13] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_out_12_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 217
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[12] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_out_11_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 218
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[11] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_out_10_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 219
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[10] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 220
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 221
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 222
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_tri_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 223
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_tri_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 224
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_tri_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 225
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_tri_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 226
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 227
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 228
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|seven_seg_pin_tri_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 229
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga:inst|reset_pin_in -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 314
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [PADIO] DISCONNECTED
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] reset LIT INDEX 0 FANOUTS 9
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] reset LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = input
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: ~STRATIX_FITTER_CREATED_GND~I -- NON-UNIQUE
+ Atom Hier Name:
+ Atom Id: 409
+ Atom Type: stratix_lcell
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 FANOUTS 14
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: ~DATA0~ -- NON-UNIQUE
+ Atom Hier Name:
+ Atom Id: 410
+ Atom Type: stratix_io
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] ~DATA0~ LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = input
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
--- /dev/null
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
--- /dev/null
+<kpt_db name="vga_pll.map_bb" kpt_version="1.1">
+ <key_points_set type="reference" hier_sep="/">
+ <key_point id="1" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="2" type="register">
+ <name>inst/vga_driver_unit/hsync_state_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="3" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="4" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="5" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="6" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_21_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="7" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="8" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_17_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="9" type="register">
+ <name>inst/vga_driver_unit/vsync_state_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="10" type="register">
+ <name>inst/vga_driver_unit/h_enable_sig_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="11" type="register">
+ <name>inst/vga_driver_unit/v_enable_sig_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="12" type="register">
+ <name>inst/vga_driver_unit/h_sync_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="13" type="register">
+ <name>inst/vga_driver_unit/vsync_state_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="14" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="15" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_15_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="16" type="register">
+ <name>inst/vga_control_unit/b_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="17" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="18" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="19" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="20" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="21" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_13_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="22" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="23" type="register">
+ <name>inst/vga_driver_unit/line_counter_sig_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="24" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="25" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_23_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="26" type="register">
+ <name>inst/vga_driver_unit/line_counter_sig_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="27" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="28" type="register">
+ <name>inst/vga_driver_unit/line_counter_sig_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="29" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="30" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_12_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="31" type="register">
+ <name>inst/vga_driver_unit/vsync_state_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="32" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="33" type="register">
+ <name>inst/vga_driver_unit/line_counter_sig_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="34" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="35" type="register">
+ <name>inst/vga_control_unit/g_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="36" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_11_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="37" type="register">
+ <name>inst/dly_counter_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="38" type="register">
+ <name>inst/vga_control_unit/r_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="39" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_10_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="40" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="41" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="42" type="register">
+ <name>inst/vga_driver_unit/line_counter_sig_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="43" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_18_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="44" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_16_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="45" type="register">
+ <name>inst/vga_driver_unit/vsync_state_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="46" type="register">
+ <name>inst/vga_driver_unit/line_counter_sig_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="47" type="register">
+ <name>inst/vga_control_unit/toggle_sig_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="48" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="49" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="50" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="51" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_22_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="52" type="register">
+ <name>inst/vga_driver_unit/vsync_state_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="53" type="register">
+ <name>inst/vga_driver_unit/line_counter_sig_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="54" type="register">
+ <name>inst/vga_driver_unit/hsync_state_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="55" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_24_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="56" type="register">
+ <name>inst/vga_driver_unit/hsync_state_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="57" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="58" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_19_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="59" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="60" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="61" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_14_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="62" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_20_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="63" type="register">
+ <name>inst/dly_counter_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="64" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="65" type="register">
+ <name>inst/vga_driver_unit/vsync_state_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="66" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="67" type="register">
+ <name>inst/vga_driver_unit/hsync_state_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="68" type="register">
+ <name>inst/vga_driver_unit/hsync_state_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="69" type="register">
+ <name>inst/vga_driver_unit/hsync_state_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="70" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="71" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="72" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="73" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="74" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="75" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="76" type="register">
+ <name>inst/vga_driver_unit/line_counter_sig_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="77" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="78" type="register">
+ <name>inst/vga_driver_unit/hsync_state_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="79" type="register">
+ <name>inst/vga_control_unit/toggle_counter_sig_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="80" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="81" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="82" type="register">
+ <name>inst/vga_driver_unit/v_sync_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="83" type="register">
+ <name>inst/vga_driver_unit/vsync_counter_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="84" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="85" type="register">
+ <name>inst/vga_driver_unit/vsync_state_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="86" type="register">
+ <name>inst/vga_driver_unit/hsync_counter_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="87" type="register">
+ <name>inst/vga_driver_unit/column_counter_sig_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="88" type="register">
+ <name>inst/vga_driver_unit/line_counter_sig_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ </key_points_set>
+ <key_points_set type="transition" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transformed" hier_sep="|">
+ <key_point id="89" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|v_sync</name>
+ </key_point>
+ <key_point id="90" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_9</name>
+ </key_point>
+ <key_point id="91" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_7</name>
+ </key_point>
+ <key_point id="92" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_8</name>
+ </key_point>
+ <key_point id="93" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_5</name>
+ </key_point>
+ <key_point id="94" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_6</name>
+ </key_point>
+ <key_point id="95" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_sig</name>
+ </key_point>
+ <key_point id="96" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_3</name>
+ </key_point>
+ <key_point id="97" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_4</name>
+ </key_point>
+ <key_point id="98" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_1</name>
+ </key_point>
+ <key_point id="99" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_2</name>
+ </key_point>
+ <key_point id="100" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_counter_0</name>
+ </key_point>
+ <key_point id="101" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1</name>
+ </key_point>
+ <key_point id="102" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5</name>
+ </key_point>
+ <key_point id="103" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0</name>
+ </key_point>
+ <key_point id="104" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4</name>
+ </key_point>
+ <key_point id="105" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3</name>
+ </key_point>
+ <key_point id="106" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7</name>
+ </key_point>
+ <key_point id="107" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2</name>
+ </key_point>
+ <key_point id="108" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6</name>
+ </key_point>
+ <key_point id="109" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_state_2</name>
+ </key_point>
+ <key_point id="110" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_9</name>
+ </key_point>
+ <key_point id="111" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_state_3</name>
+ </key_point>
+ <key_point id="112" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8</name>
+ </key_point>
+ <key_point id="113" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9</name>
+ </key_point>
+ <key_point id="114" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_state_0</name>
+ </key_point>
+ <key_point id="115" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_state_5</name>
+ </key_point>
+ <key_point id="116" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8</name>
+ </key_point>
+ <key_point id="117" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_state_1</name>
+ </key_point>
+ <key_point id="118" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4</name>
+ </key_point>
+ <key_point id="119" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_state_4</name>
+ </key_point>
+ <key_point id="120" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7</name>
+ </key_point>
+ <key_point id="121" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_state_6</name>
+ </key_point>
+ <key_point id="122" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3</name>
+ </key_point>
+ <key_point id="123" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_state_3</name>
+ </key_point>
+ <key_point id="124" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6</name>
+ </key_point>
+ <key_point id="125" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_state_2</name>
+ </key_point>
+ <key_point id="126" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2</name>
+ </key_point>
+ <key_point id="127" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_state_4</name>
+ </key_point>
+ <key_point id="128" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1</name>
+ </key_point>
+ <key_point id="129" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|vsync_state_5</name>
+ </key_point>
+ <key_point id="130" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0</name>
+ </key_point>
+ <key_point id="131" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_state_6</name>
+ </key_point>
+ <key_point id="132" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1</name>
+ </key_point>
+ <key_point id="133" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0</name>
+ </key_point>
+ <key_point id="134" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5</name>
+ </key_point>
+ <key_point id="135" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_state_1</name>
+ </key_point>
+ <key_point id="136" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4</name>
+ </key_point>
+ <key_point id="137" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_state_0</name>
+ </key_point>
+ <key_point id="138" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3</name>
+ </key_point>
+ <key_point id="139" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2</name>
+ </key_point>
+ <key_point id="140" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|b</name>
+ </key_point>
+ <key_point id="141" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20</name>
+ </key_point>
+ <key_point id="142" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9</name>
+ </key_point>
+ <key_point id="143" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8</name>
+ </key_point>
+ <key_point id="144" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7</name>
+ </key_point>
+ <key_point id="145" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6</name>
+ </key_point>
+ <key_point id="146" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5</name>
+ </key_point>
+ <key_point id="147" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|v_enable_sig</name>
+ </key_point>
+ <key_point id="148" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|h_enable_sig</name>
+ </key_point>
+ <key_point id="149" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12</name>
+ </key_point>
+ <key_point id="150" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13</name>
+ </key_point>
+ <key_point id="151" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14</name>
+ </key_point>
+ <key_point id="152" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15</name>
+ </key_point>
+ <key_point id="153" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16</name>
+ </key_point>
+ <key_point id="154" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17</name>
+ </key_point>
+ <key_point id="155" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18</name>
+ </key_point>
+ <key_point id="156" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19</name>
+ </key_point>
+ <key_point id="157" type="register">
+ <name>vga:inst|dly_counter[1]</name>
+ </key_point>
+ <key_point id="158" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10</name>
+ </key_point>
+ <key_point id="159" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11</name>
+ </key_point>
+ <key_point id="160" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_8</name>
+ </key_point>
+ <key_point id="161" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_7</name>
+ </key_point>
+ <key_point id="162" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_6</name>
+ </key_point>
+ <key_point id="163" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_5</name>
+ </key_point>
+ <key_point id="164" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_4</name>
+ </key_point>
+ <key_point id="165" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_3</name>
+ </key_point>
+ <key_point id="166" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_2</name>
+ </key_point>
+ <key_point id="167" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_1</name>
+ </key_point>
+ <key_point id="168" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|hsync_counter_0</name>
+ </key_point>
+ <key_point id="169" type="register">
+ <name>vga:inst|vga_control:vga_control_unit|r</name>
+ </key_point>
+ <key_point id="170" type="register">
+ <name>vga:inst|vga_driver:vga_driver_unit|h_sync</name>
+ </key_point>
+ <key_point id="171" type="register">
+ <name>vga:inst|dly_counter[0]</name>
+ </key_point>
+ </key_points_set>
+ <transformations_set hier_sep="|">
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="14" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="90" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="63" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="171" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="68" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="131" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="30" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="149" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="32" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="100" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="58" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="156" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="26" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="104" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="50" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="136" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="4" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="133" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="45" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="127" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="60" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="92" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="78" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="119" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="34" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="130" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="21" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="150" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="81" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="110" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="23" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="102" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="29" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="132" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="5" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="134" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="83" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="91" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="49" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="128" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="54" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="125" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="16" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="140" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="61" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="151" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="20" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="160" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="37" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="157" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="53" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="108" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="79" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="124" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="69" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="123" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="80" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="94" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="10" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="148" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="52" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="111" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="73" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="126" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="15" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="152" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="2" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="137" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="17" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="161" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="62" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="141" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="88" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="106" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="74" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="118" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="66" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="120" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="19" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="93" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="11" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="147" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="72" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="168" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="70" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="122" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="44" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="153" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="3" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="139" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="84" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="162" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="38" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="169" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="76" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="112" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="27" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="146" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="18" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="116" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="7" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="97" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="42" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="103" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="13" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="129" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="8" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="154" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="64" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="163" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="85" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="121" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="22" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="113" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="1" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="145" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="41" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="138" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="24" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="96" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="56" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="115" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="28" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="101" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="43" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="155" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="40" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="164" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="67" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="135" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="31" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="117" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="82" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="89" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="87" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="144" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="39" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="158" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="48" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="99" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="33" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="107" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="75" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="166" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="59" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="142" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="65" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="109" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="57" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="165" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="86" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="167" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="12" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="170" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="9" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="114" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="36" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="159" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="77" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="98" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="71" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="143" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="46" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="105" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="47" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="95" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ </transformations_set>
+</kpt_db>
--- /dev/null
+set tool_name "ModelSim-Altera (Verilog)"
+set corner_file_list {
+ {{"Slow Model"} {vga_pll.vo vga_pll_v.sdo}}
+}
--- /dev/null
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II"
+// VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version"
+
+// DATE "10/28/2009 14:55:41"
+
+//
+// Device: Altera EP1S25F672C6 Package FBGA672
+//
+
+//
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+//
+
+`timescale 1 ps/ 1 ps
+
+module vga_pll (
+ d_hsync,
+ board_clk,
+ reset,
+ d_vsync,
+ d_set_column_counter,
+ d_set_line_counter,
+ d_set_hsync_counter,
+ d_set_vsync_counter,
+ d_r,
+ d_g,
+ d_b,
+ d_h_enable,
+ d_v_enable,
+ d_state_clk,
+ d_toggle,
+ r0_pin,
+ r1_pin,
+ r2_pin,
+ g0_pin,
+ g1_pin,
+ g2_pin,
+ b0_pin,
+ b1_pin,
+ hsync_pin,
+ vsync_pin,
+ d_column_counter,
+ d_hsync_counter,
+ d_hsync_state,
+ d_line_counter,
+ d_toggle_counter,
+ d_vsync_counter,
+ d_vsync_state,
+ seven_seg_pin);
+output d_hsync;
+input board_clk;
+input reset;
+output d_vsync;
+output d_set_column_counter;
+output d_set_line_counter;
+output d_set_hsync_counter;
+output d_set_vsync_counter;
+output d_r;
+output d_g;
+output d_b;
+output d_h_enable;
+output d_v_enable;
+output d_state_clk;
+output d_toggle;
+output r0_pin;
+output r1_pin;
+output r2_pin;
+output g0_pin;
+output g1_pin;
+output g2_pin;
+output b0_pin;
+output b1_pin;
+output hsync_pin;
+output vsync_pin;
+output [9:0] d_column_counter;
+output [9:0] d_hsync_counter;
+output [0:6] d_hsync_state;
+output [8:0] d_line_counter;
+output [24:0] d_toggle_counter;
+output [9:0] d_vsync_counter;
+output [0:6] d_vsync_state;
+output [13:0] seven_seg_pin;
+
+wire gnd = 1'b0;
+wire vcc = 1'b1;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("vga_pll_v.sdo");
+// synopsys translate_on
+
+wire \inst1|altpll_component|pll~CLK1 ;
+wire \inst1|altpll_component|pll~CLK2 ;
+wire \inst1|altpll_component|pll~CLK3 ;
+wire \inst1|altpll_component|pll~CLK4 ;
+wire \inst1|altpll_component|pll~CLK5 ;
+wire \inst|vga_control_unit|un2_toggle_counter_next_0_~COMBOUT ;
+wire \inst|vga_driver_unit|un2_column_counter_next_0_~COMBOUT ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT ;
+wire \board_clk~combout ;
+wire \inst1|altpll_component|_clk0 ;
+wire \reset~combout ;
+wire \inst|vga_driver_unit|un6_dly_counter_0_x ;
+wire \inst|vga_driver_unit|hsync_state_6 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ;
+wire \inst|vga_driver_unit|hsync_counter_2 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ;
+wire \inst|vga_driver_unit|hsync_counter_3 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ;
+wire \inst|vga_driver_unit|hsync_counter_4 ;
+wire \inst|vga_driver_unit|hsync_counter_5 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ;
+wire \inst|vga_driver_unit|hsync_counter_6 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ;
+wire \inst|vga_driver_unit|hsync_counter_7 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ;
+wire \inst|vga_driver_unit|hsync_counter_8 ;
+wire \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ;
+wire \inst|vga_driver_unit|hsync_counter_9 ;
+wire \inst|vga_driver_unit|un9_hsync_counterlt9_3 ;
+wire \inst|vga_driver_unit|un13_hsync_counter_7 ;
+wire \inst|vga_driver_unit|un9_hsync_counterlt9 ;
+wire \inst|vga_driver_unit|G_2_i ;
+wire \inst|vga_driver_unit|hsync_counter_0 ;
+wire \inst|vga_driver_unit|un12_hsync_counter_4 ;
+wire \inst|vga_driver_unit|un12_hsync_counter_3 ;
+wire \inst|vga_driver_unit|un12_hsync_counter ;
+wire \inst|vga_driver_unit|un10_hsync_counter_1 ;
+wire \inst|vga_driver_unit|un11_hsync_counter_2 ;
+wire \inst|vga_driver_unit|un11_hsync_counter_3 ;
+wire \inst|vga_driver_unit|un10_hsync_counter_3 ;
+wire \inst|vga_driver_unit|hsync_state_5 ;
+wire \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ;
+wire \inst|vga_driver_unit|un13_hsync_counter_2 ;
+wire \inst|vga_driver_unit|un13_hsync_counter ;
+wire \inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ;
+wire \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ;
+wire \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ;
+wire \inst|vga_driver_unit|hsync_state_1 ;
+wire \inst|vga_driver_unit|hsync_state_3 ;
+wire \inst|vga_driver_unit|hsync_state_2 ;
+wire \inst|vga_driver_unit|hsync_state_0 ;
+wire \inst|vga_driver_unit|d_set_hsync_counter ;
+wire \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ;
+wire \inst|vga_driver_unit|hsync_counter_1 ;
+wire \inst|vga_driver_unit|un10_hsync_counter_4 ;
+wire \inst|vga_driver_unit|hsync_state_4 ;
+wire \inst|vga_driver_unit|un1_hsync_state_3_0 ;
+wire \inst|vga_driver_unit|h_sync_1_0_0_0_g1 ;
+wire \inst|vga_driver_unit|h_sync ;
+wire \inst|vga_driver_unit|vsync_state_6 ;
+wire \inst|vga_driver_unit|vsync_counter_0 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ;
+wire \inst|vga_driver_unit|vsync_counter_1 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ;
+wire \inst|vga_driver_unit|vsync_counter_2 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ;
+wire \inst|vga_driver_unit|vsync_counter_4 ;
+wire \inst|vga_driver_unit|vsync_counter_5 ;
+wire \inst|vga_driver_unit|un9_vsync_counterlt9_6 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ;
+wire \inst|vga_driver_unit|vsync_counter_7 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ;
+wire \inst|vga_driver_unit|vsync_counter_8 ;
+wire \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ;
+wire \inst|vga_driver_unit|vsync_counter_9 ;
+wire \inst|vga_driver_unit|un9_vsync_counterlt9_5 ;
+wire \inst|vga_driver_unit|un9_vsync_counterlt9 ;
+wire \inst|vga_driver_unit|G_16_i ;
+wire \inst|vga_driver_unit|vsync_counter_3 ;
+wire \inst|vga_driver_unit|un15_vsync_counter_3 ;
+wire \inst|vga_driver_unit|un15_vsync_counter_4 ;
+wire \inst|vga_driver_unit|un13_vsync_counter_3 ;
+wire \inst|vga_driver_unit|un13_vsync_counter_4 ;
+wire \inst|vga_driver_unit|un12_vsync_counter_7 ;
+wire \inst|vga_driver_unit|vsync_state_1 ;
+wire \inst|vga_driver_unit|vsync_state_5 ;
+wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ;
+wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ;
+wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ;
+wire \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ;
+wire \inst|vga_driver_unit|vsync_state_next_2_sqmuxa ;
+wire \inst|vga_driver_unit|vsync_state_3 ;
+wire \inst|vga_driver_unit|vsync_state_2 ;
+wire \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ;
+wire \inst|vga_driver_unit|vsync_state_0 ;
+wire \inst|vga_driver_unit|d_set_vsync_counter ;
+wire \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ;
+wire \inst|vga_driver_unit|vsync_counter_6 ;
+wire \inst|vga_driver_unit|un12_vsync_counter_6 ;
+wire \inst|vga_driver_unit|un14_vsync_counter_8 ;
+wire \inst|vga_driver_unit|vsync_state_4 ;
+wire \inst|vga_driver_unit|un1_vsync_state_2_0 ;
+wire \inst|vga_driver_unit|v_sync_1_0_0_0_g1 ;
+wire \inst|vga_driver_unit|v_sync ;
+wire \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ;
+wire \inst|vga_driver_unit|column_counter_sig_0 ;
+wire \inst|vga_driver_unit|column_counter_sig_1 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ;
+wire \inst|vga_driver_unit|column_counter_sig_3 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ;
+wire \inst|vga_driver_unit|column_counter_sig_2 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ;
+wire \inst|vga_driver_unit|column_counter_sig_4 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ;
+wire \inst|vga_driver_unit|column_counter_sig_5 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ;
+wire \inst|vga_driver_unit|column_counter_sig_8 ;
+wire \inst|vga_driver_unit|un10_column_counter_siglt6_4 ;
+wire \inst|vga_driver_unit|un10_column_counter_siglt6 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ;
+wire \inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ;
+wire \inst|vga_driver_unit|column_counter_sig_9 ;
+wire \inst|vga_driver_unit|un10_column_counter_siglto9 ;
+wire \inst|vga_driver_unit|column_counter_sig_7 ;
+wire \inst|vga_driver_unit|column_counter_sig_6 ;
+wire \inst|vga_control_unit|un5_v_enablelt2 ;
+wire \inst|vga_control_unit|un5_v_enablelto5 ;
+wire \inst|vga_control_unit|un9_v_enablelto4 ;
+wire \inst|vga_control_unit|un9_v_enablelto6 ;
+wire \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ;
+wire \inst|vga_driver_unit|line_counter_sig_0 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ;
+wire \inst|vga_driver_unit|line_counter_sig_2 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ;
+wire \inst|vga_driver_unit|line_counter_sig_1 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ;
+wire \inst|vga_driver_unit|line_counter_sig_4 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ;
+wire \inst|vga_driver_unit|line_counter_sig_3 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ;
+wire \inst|vga_driver_unit|line_counter_sig_6 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ;
+wire \inst|vga_driver_unit|line_counter_sig_5 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ;
+wire \inst|vga_driver_unit|line_counter_sig_7 ;
+wire \inst|vga_driver_unit|un10_line_counter_siglt4_2 ;
+wire \inst|vga_driver_unit|un10_line_counter_siglto5 ;
+wire \inst|vga_driver_unit|un10_line_counter_siglto8 ;
+wire \inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ;
+wire \inst|vga_driver_unit|line_counter_sig_8 ;
+wire \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ;
+wire \inst|vga_driver_unit|h_enable_sig ;
+wire \inst|vga_control_unit|b_next_0_sqmuxa_7_2 ;
+wire \inst|vga_control_unit|b_next_0_sqmuxa_7_3 ;
+wire \inst|vga_control_unit|b_next_0_sqmuxa_7_5 ;
+wire \inst|vga_control_unit|un13_v_enablelto4_0 ;
+wire \inst|vga_control_unit|un13_v_enablelto6 ;
+wire \inst|vga_control_unit|un17_v_enablelto3 ;
+wire \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a ;
+wire \inst|vga_control_unit|b_next_0_sqmuxa_7_4 ;
+wire \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ;
+wire \inst|vga_driver_unit|v_enable_sig ;
+wire \inst|vga_control_unit|toggle_counter_sig_0 ;
+wire \inst|vga_control_unit|toggle_counter_sig_1 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 ;
+wire \inst|vga_control_unit|toggle_counter_sig_3 ;
+wire \inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 ;
+wire \inst|vga_control_unit|toggle_counter_sig_2 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 ;
+wire \inst|vga_control_unit|toggle_counter_sig_5 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 ;
+wire \inst|vga_control_unit|toggle_counter_sig_4 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 ;
+wire \inst|vga_control_unit|toggle_counter_sig_6 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 ;
+wire \inst|vga_control_unit|toggle_counter_sig_7 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 ;
+wire \inst|vga_control_unit|toggle_counter_sig_8 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 ;
+wire \inst|vga_control_unit|toggle_counter_sig_9 ;
+wire \inst|vga_control_unit|toggle_counter_sig_11 ;
+wire \inst|vga_control_unit|toggle_counter_sig_10 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 ;
+wire \inst|vga_control_unit|toggle_counter_sig_13 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 ;
+wire \inst|vga_control_unit|toggle_counter_sig_12 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 ;
+wire \inst|vga_control_unit|toggle_counter_sig_15 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 ;
+wire \inst|vga_control_unit|toggle_counter_sig_14 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglt6 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto9 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto12 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto15 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 ;
+wire \inst|vga_control_unit|toggle_counter_sig_16 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 ;
+wire \inst|vga_control_unit|toggle_counter_sig_17 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 ;
+wire \inst|vga_control_unit|toggle_counter_sig_19 ;
+wire \inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 ;
+wire \inst|vga_control_unit|toggle_counter_sig_18 ;
+wire \inst|vga_control_unit|un1_toggle_counter_siglto18 ;
+wire \inst|vga_control_unit|toggle_counter_sig_20 ;
+wire \inst|vga_control_unit|toggle_sig_0_0_0_g1 ;
+wire \inst|vga_control_unit|toggle_sig ;
+wire \inst|vga_control_unit|r ;
+wire \~STRATIX_FITTER_CREATED_GND~I_combout ;
+wire \inst|vga_control_unit|b ;
+wire [18:1] \inst|vga_control_unit|toggle_counter_sig_cout ;
+wire [0:0] \inst|vga_control_unit|un2_toggle_counter_next_cout ;
+wire [8:0] \inst|vga_driver_unit|hsync_counter_cout ;
+wire [1:1] \inst|vga_driver_unit|un1_line_counter_sig_a_cout ;
+wire [9:1] \inst|vga_driver_unit|un1_line_counter_sig_combout ;
+wire [7:1] \inst|vga_driver_unit|un1_line_counter_sig_cout ;
+wire [9:1] \inst|vga_driver_unit|un2_column_counter_next_combout ;
+wire [7:0] \inst|vga_driver_unit|un2_column_counter_next_cout ;
+wire [8:0] \inst|vga_driver_unit|vsync_counter_cout ;
+wire [1:0] \inst|dly_counter ;
+
+wire [5:0] \inst1|altpll_component|pll_CLK_bus ;
+
+assign \inst1|altpll_component|_clk0 = \inst1|altpll_component|pll_CLK_bus [0];
+assign \inst1|altpll_component|pll~CLK1 = \inst1|altpll_component|pll_CLK_bus [1];
+assign \inst1|altpll_component|pll~CLK2 = \inst1|altpll_component|pll_CLK_bus [2];
+assign \inst1|altpll_component|pll~CLK3 = \inst1|altpll_component|pll_CLK_bus [3];
+assign \inst1|altpll_component|pll~CLK4 = \inst1|altpll_component|pll_CLK_bus [4];
+assign \inst1|altpll_component|pll~CLK5 = \inst1|altpll_component|pll_CLK_bus [5];
+
+// atom is at PIN_N3
+stratix_io \board_clk~I (
+ .datain(gnd),
+ .ddiodatain(gnd),
+ .oe(gnd),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(\board_clk~combout ),
+ .regout(),
+ .ddioregout(),
+ .padio(board_clk),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \board_clk~I .ddio_mode = "none";
+defparam \board_clk~I .input_async_reset = "none";
+defparam \board_clk~I .input_power_up = "low";
+defparam \board_clk~I .input_register_mode = "none";
+defparam \board_clk~I .input_sync_reset = "none";
+defparam \board_clk~I .oe_async_reset = "none";
+defparam \board_clk~I .oe_power_up = "low";
+defparam \board_clk~I .oe_register_mode = "none";
+defparam \board_clk~I .oe_sync_reset = "none";
+defparam \board_clk~I .operation_mode = "input";
+defparam \board_clk~I .output_async_reset = "none";
+defparam \board_clk~I .output_power_up = "low";
+defparam \board_clk~I .output_register_mode = "none";
+defparam \board_clk~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PLL_1
+stratix_pll \inst1|altpll_component|pll (
+ .fbin(vcc),
+ .ena(vcc),
+ .clkswitch(gnd),
+ .areset(gnd),
+ .pfdena(vcc),
+ .scanclk(gnd),
+ .scanaclr(gnd),
+ .scandata(gnd),
+ .comparator(gnd),
+ .inclk({gnd,\board_clk~combout }),
+ .clkena(6'b111111),
+ .extclkena(4'b1111),
+ .activeclock(),
+ .clkloss(),
+ .locked(),
+ .scandataout(),
+ .enable0(),
+ .enable1(),
+ .clk(\inst1|altpll_component|pll_CLK_bus ),
+ .extclk(),
+ .clkbad());
+// synopsys translate_off
+defparam \inst1|altpll_component|pll .clk0_counter = "g0";
+defparam \inst1|altpll_component|pll .clk0_divide_by = 38;
+defparam \inst1|altpll_component|pll .clk0_duty_cycle = 50;
+defparam \inst1|altpll_component|pll .clk0_multiply_by = 31;
+defparam \inst1|altpll_component|pll .clk0_phase_shift = "-725";
+defparam \inst1|altpll_component|pll .clk1_divide_by = 1;
+defparam \inst1|altpll_component|pll .clk1_duty_cycle = 50;
+defparam \inst1|altpll_component|pll .clk1_multiply_by = 1;
+defparam \inst1|altpll_component|pll .clk1_phase_shift = "0";
+defparam \inst1|altpll_component|pll .clk2_divide_by = 1;
+defparam \inst1|altpll_component|pll .clk2_duty_cycle = 50;
+defparam \inst1|altpll_component|pll .clk2_multiply_by = 1;
+defparam \inst1|altpll_component|pll .clk2_phase_shift = "0";
+defparam \inst1|altpll_component|pll .compensate_clock = "clk0";
+defparam \inst1|altpll_component|pll .enable_switch_over_counter = "off";
+defparam \inst1|altpll_component|pll .g0_high = 10;
+defparam \inst1|altpll_component|pll .g0_initial = 1;
+defparam \inst1|altpll_component|pll .g0_low = 9;
+defparam \inst1|altpll_component|pll .g0_mode = "odd";
+defparam \inst1|altpll_component|pll .g0_ph = 0;
+defparam \inst1|altpll_component|pll .gate_lock_counter = 0;
+defparam \inst1|altpll_component|pll .gate_lock_signal = "no";
+defparam \inst1|altpll_component|pll .inclk0_input_frequency = 30003;
+defparam \inst1|altpll_component|pll .inclk1_input_frequency = 30003;
+defparam \inst1|altpll_component|pll .invalid_lock_multiplier = 5;
+defparam \inst1|altpll_component|pll .l0_high = 13;
+defparam \inst1|altpll_component|pll .l0_initial = 1;
+defparam \inst1|altpll_component|pll .l0_low = 13;
+defparam \inst1|altpll_component|pll .l0_mode = "even";
+defparam \inst1|altpll_component|pll .l0_ph = 0;
+defparam \inst1|altpll_component|pll .l1_mode = "bypass";
+defparam \inst1|altpll_component|pll .l1_ph = 0;
+defparam \inst1|altpll_component|pll .m = 31;
+defparam \inst1|altpll_component|pll .m_initial = 1;
+defparam \inst1|altpll_component|pll .m_ph = 3;
+defparam \inst1|altpll_component|pll .n = 2;
+defparam \inst1|altpll_component|pll .operation_mode = "normal";
+defparam \inst1|altpll_component|pll .pfd_max = 100000;
+defparam \inst1|altpll_component|pll .pfd_min = 2000;
+defparam \inst1|altpll_component|pll .pll_compensation_delay = 1713;
+defparam \inst1|altpll_component|pll .pll_type = "fast";
+defparam \inst1|altpll_component|pll .primary_clock = "inclk0";
+defparam \inst1|altpll_component|pll .qualify_conf_done = "off";
+defparam \inst1|altpll_component|pll .simulation_type = "timing";
+defparam \inst1|altpll_component|pll .skip_vco = "off";
+defparam \inst1|altpll_component|pll .switch_over_counter = 1;
+defparam \inst1|altpll_component|pll .switch_over_on_gated_lock = "off";
+defparam \inst1|altpll_component|pll .switch_over_on_lossclk = "off";
+defparam \inst1|altpll_component|pll .valid_lock_multiplier = 1;
+defparam \inst1|altpll_component|pll .vco_center = 1250;
+defparam \inst1|altpll_component|pll .vco_max = 3334;
+defparam \inst1|altpll_component|pll .vco_min = 1000;
+// synopsys translate_on
+
+// atom is at PIN_A5
+stratix_io \inst|reset_pin_in~I (
+ .datain(gnd),
+ .ddiodatain(gnd),
+ .oe(gnd),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(\reset~combout ),
+ .regout(),
+ .ddioregout(),
+ .padio(reset),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|reset_pin_in~I .ddio_mode = "none";
+defparam \inst|reset_pin_in~I .input_async_reset = "none";
+defparam \inst|reset_pin_in~I .input_power_up = "low";
+defparam \inst|reset_pin_in~I .input_register_mode = "none";
+defparam \inst|reset_pin_in~I .input_sync_reset = "none";
+defparam \inst|reset_pin_in~I .oe_async_reset = "none";
+defparam \inst|reset_pin_in~I .oe_power_up = "low";
+defparam \inst|reset_pin_in~I .oe_register_mode = "none";
+defparam \inst|reset_pin_in~I .oe_sync_reset = "none";
+defparam \inst|reset_pin_in~I .operation_mode = "input";
+defparam \inst|reset_pin_in~I .output_async_reset = "none";
+defparam \inst|reset_pin_in~I .output_power_up = "low";
+defparam \inst|reset_pin_in~I .output_register_mode = "none";
+defparam \inst|reset_pin_in~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N4
+stratix_lcell \inst|dly_counter_0_ (
+// Equation(s):
+// \inst|dly_counter [0] = DFFEAS(\reset~combout & (\inst|dly_counter [1] # !\inst|dly_counter [0]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|dly_counter [1]),
+ .datab(vcc),
+ .datac(\reset~combout ),
+ .datad(\inst|dly_counter [0]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|dly_counter [0]),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|dly_counter_0_ .lut_mask = "a0f0";
+defparam \inst|dly_counter_0_ .operation_mode = "normal";
+defparam \inst|dly_counter_0_ .output_mode = "reg_only";
+defparam \inst|dly_counter_0_ .register_cascade_mode = "off";
+defparam \inst|dly_counter_0_ .sum_lutc_input = "datac";
+defparam \inst|dly_counter_0_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N0
+stratix_lcell \inst|dly_counter_1_ (
+// Equation(s):
+// \inst|dly_counter [1] = DFFEAS(\reset~combout & (\inst|dly_counter [1] # \inst|dly_counter [0]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|dly_counter [1]),
+ .datac(\reset~combout ),
+ .datad(\inst|dly_counter [0]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|dly_counter [1]),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|dly_counter_1_ .lut_mask = "f0c0";
+defparam \inst|dly_counter_1_ .operation_mode = "normal";
+defparam \inst|dly_counter_1_ .output_mode = "reg_only";
+defparam \inst|dly_counter_1_ .register_cascade_mode = "off";
+defparam \inst|dly_counter_1_ .sum_lutc_input = "datac";
+defparam \inst|dly_counter_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N3
+stratix_lcell \inst|vga_driver_unit|vsync_state_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|un6_dly_counter_0_x = !\inst|dly_counter [0] # !\reset~combout # !\inst|dly_counter [1]
+// \inst|vga_driver_unit|vsync_state_6 = DFFEAS(\inst|vga_driver_unit|un6_dly_counter_0_x , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|dly_counter [1]),
+ .datac(\reset~combout ),
+ .datad(\inst|dly_counter [0]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .regout(\inst|vga_driver_unit|vsync_state_6 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_6_ .lut_mask = "3fff";
+defparam \inst|vga_driver_unit|vsync_state_6_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_6_ .output_mode = "reg_and_comb";
+defparam \inst|vga_driver_unit|vsync_state_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_6_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_6_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X27_Y42_N7
+stratix_lcell \inst|vga_driver_unit|hsync_state_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|d_set_hsync_counter = \inst|vga_driver_unit|hsync_state_0 # E1_hsync_state_6
+// \inst|vga_driver_unit|hsync_state_6 = DFFEAS(\inst|vga_driver_unit|d_set_hsync_counter , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|un6_dly_counter_0_x , , , VCC)
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_state_0 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .regout(\inst|vga_driver_unit|hsync_state_6 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_6_ .lut_mask = "fafa";
+defparam \inst|vga_driver_unit|hsync_state_6_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_6_ .output_mode = "reg_and_comb";
+defparam \inst|vga_driver_unit|hsync_state_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_6_ .sum_lutc_input = "qfbk";
+defparam \inst|vga_driver_unit|hsync_state_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N0
+stratix_lcell \inst|vga_driver_unit|hsync_counter_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_0 = DFFEAS(!\inst|vga_driver_unit|hsync_counter_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i ,
+// !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [0] = CARRY(\inst|vga_driver_unit|hsync_counter_0 )
+// \inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 = CARRY(\inst|vga_driver_unit|hsync_counter_0 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_counter_0 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_0 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [0]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_0_ .lut_mask = "33cc";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_counter_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N1
+stratix_lcell \inst|vga_driver_unit|hsync_counter_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_1 = DFFEAS(\inst|vga_driver_unit|hsync_counter_1 $ \inst|vga_driver_unit|hsync_counter_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [1] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [0] # !\inst|vga_driver_unit|hsync_counter_1 )
+// \inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 # !\inst|vga_driver_unit|hsync_counter_1 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_counter_1 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [0]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_1 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [1]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_1_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .lut_mask = "3c3f";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N2
+stratix_lcell \inst|vga_driver_unit|hsync_counter_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_2 = DFFEAS(\inst|vga_driver_unit|hsync_counter_2 $ (!\inst|vga_driver_unit|hsync_counter_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [2] = CARRY(\inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_cout [1]))
+// \inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 = CARRY(\inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [1]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_2 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [2]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_2_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N3
+stratix_lcell \inst|vga_driver_unit|hsync_counter_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_3 = DFFEAS(\inst|vga_driver_unit|hsync_counter_3 $ (\inst|vga_driver_unit|hsync_counter_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [3] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [2] # !\inst|vga_driver_unit|hsync_counter_3 )
+// \inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 # !\inst|vga_driver_unit|hsync_counter_3 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [2]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_3 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [3]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_3_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .lut_mask = "5a5f";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N4
+stratix_lcell \inst|vga_driver_unit|hsync_counter_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_4 = DFFEAS(\inst|vga_driver_unit|hsync_counter_4 $ (!\inst|vga_driver_unit|hsync_counter_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [4] = CARRY(\inst|vga_driver_unit|hsync_counter_4 & (!\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_4 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [3]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_4 ),
+ .cout(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_4_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N5
+stratix_lcell \inst|vga_driver_unit|hsync_counter_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_5 = DFFEAS(\inst|vga_driver_unit|hsync_counter_5 $ \inst|vga_driver_unit|hsync_counter_cout [4], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [5] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [4] # !\inst|vga_driver_unit|hsync_counter_5 )
+// \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [4] # !\inst|vga_driver_unit|hsync_counter_5 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_counter_5 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_5 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [5]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_5_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .lut_mask = "3c3f";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N6
+stratix_lcell \inst|vga_driver_unit|hsync_counter_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_6 = DFFEAS(\inst|vga_driver_unit|hsync_counter_6 $ !(!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [5]) # (\inst|vga_driver_unit|hsync_counter_cout [4] &
+// \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [6] = CARRY(\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_cout [5])
+// \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 = CARRY(\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [5]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_6 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [6]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_6_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .lut_mask = "c30c";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N7
+stratix_lcell \inst|vga_driver_unit|hsync_counter_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_7 = DFFEAS(\inst|vga_driver_unit|hsync_counter_7 $ ((!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [6]) # (\inst|vga_driver_unit|hsync_counter_cout [4] &
+// \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [7] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [6] # !\inst|vga_driver_unit|hsync_counter_7 )
+// \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 # !\inst|vga_driver_unit|hsync_counter_7 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [6]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_7 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [7]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_7_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .lut_mask = "5a5f";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_7_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N8
+stratix_lcell \inst|vga_driver_unit|hsync_counter_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_8 = DFFEAS(\inst|vga_driver_unit|hsync_counter_8 $ (!(!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [7]) # (\inst|vga_driver_unit|hsync_counter_cout [4] &
+// \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+// \inst|vga_driver_unit|hsync_counter_cout [8] = CARRY(\inst|vga_driver_unit|hsync_counter_8 & (!\inst|vga_driver_unit|hsync_counter_cout [7]))
+// \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 = CARRY(\inst|vga_driver_unit|hsync_counter_8 & (!\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_counter_8 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [7]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_8 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|hsync_counter_cout [8]),
+ .cout1(\inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_8_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_8_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X51_Y42_N9
+stratix_lcell \inst|vga_driver_unit|hsync_counter_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_9 = DFFEAS((!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [8]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ) $
+// \inst|vga_driver_unit|hsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .datad(\inst|vga_driver_unit|hsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_2_i ),
+ .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|hsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|hsync_counter_cout [8]),
+ .cin1(\inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_counter_9 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_9_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .cin_used = "true";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .lut_mask = "0ff0";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|hsync_counter_9_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N5
+stratix_lcell \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_hsync_counterlt9_3 = !\inst|vga_driver_unit|hsync_counter_4 # !\inst|vga_driver_unit|hsync_counter_6 # !\inst|vga_driver_unit|hsync_counter_7 # !\inst|vga_driver_unit|hsync_counter_5
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_5 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_6 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_hsync_counterlt9_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .lut_mask = "7fff";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N6
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 (
+// Equation(s):
+// \inst|vga_driver_unit|un13_hsync_counter_7 = \inst|vga_driver_unit|hsync_counter_0 & \inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_2 & \inst|vga_driver_unit|hsync_counter_1
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_0 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_hsync_counter_7 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .lut_mask = "8000";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N2
+stratix_lcell \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_hsync_counterlt9 = \inst|vga_driver_unit|un9_hsync_counterlt9_3 # !\inst|vga_driver_unit|un13_hsync_counter_7 # !\inst|vga_driver_unit|hsync_counter_9 # !\inst|vga_driver_unit|hsync_counter_8
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_8 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_9 ),
+ .datac(\inst|vga_driver_unit|un9_hsync_counterlt9_3 ),
+ .datad(\inst|vga_driver_unit|un13_hsync_counter_7 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .lut_mask = "f7ff";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N3
+stratix_lcell \inst|vga_driver_unit|G_2 (
+// Equation(s):
+// \inst|vga_driver_unit|G_2_i = !\inst|vga_driver_unit|hsync_state_6 & !\inst|vga_driver_unit|un6_dly_counter_0_x & !\inst|vga_driver_unit|hsync_state_0 # !\inst|vga_driver_unit|un9_hsync_counterlt9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_state_6 ),
+ .datab(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .datac(\inst|vga_driver_unit|hsync_state_0 ),
+ .datad(\inst|vga_driver_unit|un9_hsync_counterlt9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|G_2_i ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|G_2 .lut_mask = "01ff";
+defparam \inst|vga_driver_unit|G_2 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|G_2 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|G_2 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|G_2 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|G_2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N5
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 (
+// Equation(s):
+// \inst|vga_driver_unit|un12_hsync_counter_4 = !\inst|vga_driver_unit|hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_9 & !\inst|vga_driver_unit|hsync_counter_6
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_9 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_hsync_counter_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .lut_mask = "0010";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N6
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un12_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_5 & !\inst|vga_driver_unit|hsync_counter_4 & \inst|vga_driver_unit|hsync_counter_2 & \inst|vga_driver_unit|hsync_counter_8
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_5 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_4 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_hsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .lut_mask = "1000";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N1
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter (
+// Equation(s):
+// \inst|vga_driver_unit|un12_hsync_counter = \inst|vga_driver_unit|hsync_counter_0 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|un12_hsync_counter_4 & \inst|vga_driver_unit|un12_hsync_counter_3
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_0 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_1 ),
+ .datac(\inst|vga_driver_unit|un12_hsync_counter_4 ),
+ .datad(\inst|vga_driver_unit|un12_hsync_counter_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_hsync_counter ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .lut_mask = "8000";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N2
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_hsync_counter_1 = !\inst|vga_driver_unit|hsync_counter_5 & (!\inst|vga_driver_unit|hsync_counter_9 & !\inst|vga_driver_unit|hsync_counter_8 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_5 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_counter_9 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .lut_mask = "0005";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N0
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 (
+// Equation(s):
+// \inst|vga_driver_unit|un11_hsync_counter_2 = \inst|vga_driver_unit|hsync_counter_7 & \inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|hsync_counter_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un11_hsync_counter_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .lut_mask = "0088";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N4
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un11_hsync_counter_3 = \inst|vga_driver_unit|hsync_counter_0 & !\inst|vga_driver_unit|hsync_counter_4 & !\inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_1
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_0 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_4 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un11_hsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .lut_mask = "0200";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N1
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_0 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_7 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_2 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|hsync_counter_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_hsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .lut_mask = "0011";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X42_Y42_N2
+stratix_lcell \inst|vga_driver_unit|hsync_state_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_5 = DFFEAS(\inst|vga_driver_unit|hsync_state_6 # \inst|vga_driver_unit|hsync_state_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_state_6 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|hsync_state_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_5 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_5_ .lut_mask = "ffaa";
+defparam \inst|vga_driver_unit|hsync_state_5_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_5_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N8
+stratix_lcell \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 = \inst|vga_driver_unit|hsync_state_5 & (!\inst|vga_driver_unit|un10_hsync_counter_1 # !\inst|vga_driver_unit|un10_hsync_counter_3 # !\inst|vga_driver_unit|un10_hsync_counter_4 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un10_hsync_counter_4 ),
+ .datab(\inst|vga_driver_unit|un10_hsync_counter_3 ),
+ .datac(\inst|vga_driver_unit|hsync_state_5 ),
+ .datad(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .lut_mask = "70f0";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N7
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 (
+// Equation(s):
+// \inst|vga_driver_unit|un13_hsync_counter_2 = \inst|vga_driver_unit|hsync_counter_4 & \inst|vga_driver_unit|hsync_counter_8 & !\inst|vga_driver_unit|hsync_counter_5 & \inst|vga_driver_unit|hsync_counter_9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_4 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_8 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_5 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_hsync_counter_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .lut_mask = "0800";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N4
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter (
+// Equation(s):
+// \inst|vga_driver_unit|un13_hsync_counter = \inst|vga_driver_unit|un13_hsync_counter_2 & \inst|vga_driver_unit|un13_hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_7
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un13_hsync_counter_2 ),
+ .datab(\inst|vga_driver_unit|un13_hsync_counter_7 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_6 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_7 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_hsync_counter ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .lut_mask = "0008";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N0
+stratix_lcell \inst|vga_driver_unit|hsync_state_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 = \inst|vga_driver_unit|hsync_state_2 & (!\inst|vga_driver_unit|un12_hsync_counter & E1_hsync_state_3 # !\inst|vga_driver_unit|un13_hsync_counter ) # !\inst|vga_driver_unit|hsync_state_2 &
+// !\inst|vga_driver_unit|un12_hsync_counter & E1_hsync_state_3
+// \inst|vga_driver_unit|hsync_state_3 = DFFEAS(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , \inst|vga_driver_unit|hsync_state_1 , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , VCC)
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|hsync_state_2 ),
+ .datab(\inst|vga_driver_unit|un12_hsync_counter ),
+ .datac(\inst|vga_driver_unit|hsync_state_1 ),
+ .datad(\inst|vga_driver_unit|un13_hsync_counter ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(vcc),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ),
+ .regout(\inst|vga_driver_unit|hsync_state_3 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_3_ .lut_mask = "30ba";
+defparam \inst|vga_driver_unit|hsync_state_3_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_3_ .output_mode = "reg_and_comb";
+defparam \inst|vga_driver_unit|hsync_state_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_3_ .sum_lutc_input = "qfbk";
+defparam \inst|vga_driver_unit|hsync_state_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N3
+stratix_lcell \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 = \inst|vga_driver_unit|hsync_state_4 & (!\inst|vga_driver_unit|un11_hsync_counter_3 # !\inst|vga_driver_unit|un11_hsync_counter_2 # !\inst|vga_driver_unit|un10_hsync_counter_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .datab(\inst|vga_driver_unit|un11_hsync_counter_2 ),
+ .datac(\inst|vga_driver_unit|un11_hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|hsync_state_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .lut_mask = "7f00";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y41_N9
+stratix_lcell \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 & !\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 &
+// !\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ),
+ .datab(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ),
+ .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .datad(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .lut_mask = "f0f1";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N9
+stratix_lcell \inst|vga_driver_unit|hsync_state_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_1 = DFFEAS(\inst|vga_driver_unit|un10_hsync_counter_1 & \inst|vga_driver_unit|un11_hsync_counter_2 & \inst|vga_driver_unit|un11_hsync_counter_3 & \inst|vga_driver_unit|hsync_state_4 ,
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .datab(\inst|vga_driver_unit|un11_hsync_counter_2 ),
+ .datac(\inst|vga_driver_unit|un11_hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|hsync_state_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_1 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_1_ .lut_mask = "8000";
+defparam \inst|vga_driver_unit|hsync_state_1_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X42_Y42_N5
+stratix_lcell \inst|vga_driver_unit|hsync_state_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_2 = DFFEAS(\inst|vga_driver_unit|un12_hsync_counter & (\inst|vga_driver_unit|hsync_state_3 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un12_hsync_counter ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|hsync_state_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_2 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_2_ .lut_mask = "aa00";
+defparam \inst|vga_driver_unit|hsync_state_2_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_2_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X42_Y42_N9
+stratix_lcell \inst|vga_driver_unit|hsync_state_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_0 = DFFEAS(\inst|vga_driver_unit|hsync_state_2 & \inst|vga_driver_unit|un13_hsync_counter , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_state_2 ),
+ .datad(\inst|vga_driver_unit|un13_hsync_counter ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_0_ .lut_mask = "f000";
+defparam \inst|vga_driver_unit|hsync_state_0_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X42_Y42_N8
+stratix_lcell \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa = !\inst|vga_driver_unit|d_set_hsync_counter & \inst|dly_counter [1] & \reset~combout & \inst|dly_counter [0]
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .datab(\inst|dly_counter [1]),
+ .datac(\reset~combout ),
+ .datad(\inst|dly_counter [0]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .lut_mask = "4000";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N7
+stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_hsync_counter_4 = \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|hsync_counter_4 & \inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_6
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_counter_1 ),
+ .datab(\inst|vga_driver_unit|hsync_counter_4 ),
+ .datac(\inst|vga_driver_unit|hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|hsync_counter_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_hsync_counter_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .lut_mask = "8000";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X52_Y42_N8
+stratix_lcell \inst|vga_driver_unit|hsync_state_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|hsync_state_4 = DFFEAS(\inst|vga_driver_unit|un10_hsync_counter_4 & \inst|vga_driver_unit|hsync_state_5 & \inst|vga_driver_unit|un10_hsync_counter_3 & \inst|vga_driver_unit|un10_hsync_counter_1 ,
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un10_hsync_counter_4 ),
+ .datab(\inst|vga_driver_unit|hsync_state_5 ),
+ .datac(\inst|vga_driver_unit|un10_hsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|un10_hsync_counter_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|hsync_state_4 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|hsync_state_4_ .lut_mask = "8000";
+defparam \inst|vga_driver_unit|hsync_state_4_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|hsync_state_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|hsync_state_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|hsync_state_4_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|hsync_state_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X42_Y42_N3
+stratix_lcell \inst|vga_driver_unit|un1_hsync_state_3_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_hsync_state_3_0 = \inst|vga_driver_unit|hsync_state_1 # \inst|vga_driver_unit|hsync_state_3
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_state_1 ),
+ .datad(\inst|vga_driver_unit|hsync_state_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_hsync_state_3_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .lut_mask = "fff0";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X42_Y42_N4
+stratix_lcell \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|h_sync_1_0_0_0_g1 = \inst|vga_driver_unit|hsync_state_2 & \inst|vga_driver_unit|h_sync # !\inst|vga_driver_unit|hsync_state_2 & (\inst|vga_driver_unit|un1_hsync_state_3_0 & \inst|vga_driver_unit|h_sync #
+// !\inst|vga_driver_unit|un1_hsync_state_3_0 & (\inst|vga_driver_unit|hsync_state_4 ))
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|h_sync ),
+ .datab(\inst|vga_driver_unit|hsync_state_4 ),
+ .datac(\inst|vga_driver_unit|hsync_state_2 ),
+ .datad(\inst|vga_driver_unit|un1_hsync_state_3_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .lut_mask = "aaac";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X42_Y42_N6
+stratix_lcell \inst|vga_driver_unit|h_sync_Z (
+// Equation(s):
+// \inst|vga_driver_unit|h_sync = DFFEAS(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 # !\inst|dly_counter [0] # !\reset~combout # !\inst|dly_counter [1], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 ),
+ .datab(\inst|dly_counter [1]),
+ .datac(\reset~combout ),
+ .datad(\inst|dly_counter [0]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|h_sync ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|h_sync_Z .lut_mask = "bfff";
+defparam \inst|vga_driver_unit|h_sync_Z .operation_mode = "normal";
+defparam \inst|vga_driver_unit|h_sync_Z .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|h_sync_Z .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|h_sync_Z .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|h_sync_Z .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N0
+stratix_lcell \inst|vga_driver_unit|vsync_counter_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_0 = DFFEAS(\inst|vga_driver_unit|d_set_hsync_counter $ \inst|vga_driver_unit|vsync_counter_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [0] = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|vsync_counter_0 )
+// \inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|vsync_counter_0 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .datab(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_0 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [0]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_0_ .lut_mask = "6688";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_counter_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N1
+stratix_lcell \inst|vga_driver_unit|vsync_counter_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_1 = DFFEAS(\inst|vga_driver_unit|vsync_counter_1 $ \inst|vga_driver_unit|vsync_counter_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [1] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [0] # !\inst|vga_driver_unit|vsync_counter_1 )
+// \inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 # !\inst|vga_driver_unit|vsync_counter_1 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|vsync_counter_1 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [0]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_1 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [1]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_1_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .lut_mask = "3c3f";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N2
+stratix_lcell \inst|vga_driver_unit|vsync_counter_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_2 = DFFEAS(\inst|vga_driver_unit|vsync_counter_2 $ (!\inst|vga_driver_unit|vsync_counter_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [2] = CARRY(\inst|vga_driver_unit|vsync_counter_2 & (!\inst|vga_driver_unit|vsync_counter_cout [1]))
+// \inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 = CARRY(\inst|vga_driver_unit|vsync_counter_2 & (!\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_2 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [1]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_2 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [2]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_2_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N3
+stratix_lcell \inst|vga_driver_unit|vsync_counter_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_3 = DFFEAS(\inst|vga_driver_unit|vsync_counter_3 $ (\inst|vga_driver_unit|vsync_counter_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [3] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [2] # !\inst|vga_driver_unit|vsync_counter_3 )
+// \inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 # !\inst|vga_driver_unit|vsync_counter_3 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_3 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [2]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_3 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [3]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_3_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .lut_mask = "5a5f";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N4
+stratix_lcell \inst|vga_driver_unit|vsync_counter_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_4 = DFFEAS(\inst|vga_driver_unit|vsync_counter_4 $ (!\inst|vga_driver_unit|vsync_counter_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [4] = CARRY(\inst|vga_driver_unit|vsync_counter_4 & (!\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_4 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [3]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_4 ),
+ .cout(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_4_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N5
+stratix_lcell \inst|vga_driver_unit|vsync_counter_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_5 = DFFEAS(\inst|vga_driver_unit|vsync_counter_5 $ \inst|vga_driver_unit|vsync_counter_cout [4], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , ,
+// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [5] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [4] # !\inst|vga_driver_unit|vsync_counter_5 )
+// \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [4] # !\inst|vga_driver_unit|vsync_counter_5 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|vsync_counter_5 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_5 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [5]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_5_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .lut_mask = "3c3f";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N5
+stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_vsync_counterlt9_6 = !\inst|vga_driver_unit|vsync_counter_2 # !\inst|vga_driver_unit|vsync_counter_3 # !\inst|vga_driver_unit|vsync_counter_1 # !\inst|vga_driver_unit|vsync_counter_0
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_1 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_3 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_vsync_counterlt9_6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .lut_mask = "7fff";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N6
+stratix_lcell \inst|vga_driver_unit|vsync_counter_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_6 = DFFEAS(\inst|vga_driver_unit|vsync_counter_6 $ !(!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [5]) # (\inst|vga_driver_unit|vsync_counter_cout [4] &
+// \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [6] = CARRY(\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_cout [5])
+// \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 = CARRY(\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|vsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [5]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_6 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [6]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_6_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .lut_mask = "c30c";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N7
+stratix_lcell \inst|vga_driver_unit|vsync_counter_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_7 = DFFEAS(\inst|vga_driver_unit|vsync_counter_7 $ ((!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [6]) # (\inst|vga_driver_unit|vsync_counter_cout [4] &
+// \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [7] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [6] # !\inst|vga_driver_unit|vsync_counter_7 )
+// \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 # !\inst|vga_driver_unit|vsync_counter_7 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_7 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [6]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_7 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [7]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_7_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .lut_mask = "5a5f";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_7_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N8
+stratix_lcell \inst|vga_driver_unit|vsync_counter_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_8 = DFFEAS(\inst|vga_driver_unit|vsync_counter_8 $ (!(!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [7]) # (\inst|vga_driver_unit|vsync_counter_cout [4] &
+// \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+// \inst|vga_driver_unit|vsync_counter_cout [8] = CARRY(\inst|vga_driver_unit|vsync_counter_8 & (!\inst|vga_driver_unit|vsync_counter_cout [7]))
+// \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 = CARRY(\inst|vga_driver_unit|vsync_counter_8 & (!\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ))
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_counter_8 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [7]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_8 ),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|vsync_counter_cout [8]),
+ .cout1(\inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_8_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .lut_mask = "a50a";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_8_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X29_Y38_N9
+stratix_lcell \inst|vga_driver_unit|vsync_counter_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_9 = DFFEAS((!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [8]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ) $
+// \inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|G_16_i ),
+ .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .ena(vcc),
+ .cin(\inst|vga_driver_unit|vsync_counter_cout [4]),
+ .cin0(\inst|vga_driver_unit|vsync_counter_cout [8]),
+ .cin1(\inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_counter_9 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_9_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .cin_used = "true";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .lut_mask = "0ff0";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|vsync_counter_9_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N4
+stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_vsync_counterlt9_5 = !\inst|vga_driver_unit|vsync_counter_8 # !\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|vsync_counter_6 # !\inst|vga_driver_unit|vsync_counter_7
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_7 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_9 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_vsync_counterlt9_5 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .lut_mask = "7fff";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N8
+stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 (
+// Equation(s):
+// \inst|vga_driver_unit|un9_vsync_counterlt9 = \inst|vga_driver_unit|un9_vsync_counterlt9_6 # \inst|vga_driver_unit|un9_vsync_counterlt9_5 # !\inst|vga_driver_unit|vsync_counter_4 # !\inst|vga_driver_unit|vsync_counter_5
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_5 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_4 ),
+ .datac(\inst|vga_driver_unit|un9_vsync_counterlt9_6 ),
+ .datad(\inst|vga_driver_unit|un9_vsync_counterlt9_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .lut_mask = "fff7";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N6
+stratix_lcell \inst|vga_driver_unit|G_16 (
+// Equation(s):
+// \inst|vga_driver_unit|G_16_i = !\inst|vga_driver_unit|vsync_state_6 & !\inst|vga_driver_unit|vsync_state_0 & !\inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|un9_vsync_counterlt9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_6 ),
+ .datab(\inst|vga_driver_unit|vsync_state_0 ),
+ .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .datad(\inst|vga_driver_unit|un9_vsync_counterlt9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|G_16_i ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|G_16 .lut_mask = "01ff";
+defparam \inst|vga_driver_unit|G_16 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|G_16 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|G_16 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|G_16 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|G_16 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y38_N5
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un15_vsync_counter_3 = \inst|vga_driver_unit|vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_2 & !\inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|vsync_counter_9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_3 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_2 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un15_vsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .lut_mask = "0200";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y38_N4
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 (
+// Equation(s):
+// \inst|vga_driver_unit|un15_vsync_counter_4 = \inst|vga_driver_unit|un15_vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_4 & !\inst|vga_driver_unit|vsync_counter_1
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un15_vsync_counter_3 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_4 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un15_vsync_counter_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .lut_mask = "000c";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N9
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 (
+// Equation(s):
+// \inst|vga_driver_unit|un13_vsync_counter_3 = !\inst|vga_driver_unit|vsync_counter_7 & !\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_9 & !\inst|vga_driver_unit|vsync_counter_8
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_7 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_6 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_9 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_vsync_counter_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .lut_mask = "0001";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N7
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 (
+// Equation(s):
+// \inst|vga_driver_unit|un13_vsync_counter_4 = \inst|vga_driver_unit|vsync_counter_5 & \inst|vga_driver_unit|un13_vsync_counter_3 & (\inst|vga_driver_unit|vsync_counter_0 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_5 ),
+ .datab(\inst|vga_driver_unit|un13_vsync_counter_3 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|vsync_counter_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un13_vsync_counter_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .lut_mask = "8800";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N4
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 (
+// Equation(s):
+// \inst|vga_driver_unit|un12_vsync_counter_7 = !\inst|vga_driver_unit|vsync_counter_2 & !\inst|vga_driver_unit|vsync_counter_4 & !\inst|vga_driver_unit|vsync_counter_1 & !\inst|vga_driver_unit|vsync_counter_3
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_2 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_4 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_1 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_vsync_counter_7 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .lut_mask = "0001";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N2
+stratix_lcell \inst|vga_driver_unit|vsync_state_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_1 = DFFEAS(!\inst|vga_driver_unit|un6_dly_counter_0_x & \inst|vga_driver_unit|un13_vsync_counter_4 & \inst|vga_driver_unit|vsync_state_4 & \inst|vga_driver_unit|un12_vsync_counter_7 ,
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .datab(\inst|vga_driver_unit|un13_vsync_counter_4 ),
+ .datac(\inst|vga_driver_unit|vsync_state_4 ),
+ .datad(\inst|vga_driver_unit|un12_vsync_counter_7 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_1 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_1_ .lut_mask = "4000";
+defparam \inst|vga_driver_unit|vsync_state_1_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N3
+stratix_lcell \inst|vga_driver_unit|vsync_state_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_5 = DFFEAS(\inst|vga_driver_unit|vsync_state_0 # \inst|vga_driver_unit|vsync_state_6 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_state_0 ),
+ .datad(\inst|vga_driver_unit|vsync_state_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_5 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_5_ .lut_mask = "fff0";
+defparam \inst|vga_driver_unit|vsync_state_5_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_5_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N8
+stratix_lcell \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 = \inst|vga_driver_unit|vsync_state_5 & (\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|vsync_counter_0 # !\inst|vga_driver_unit|un14_vsync_counter_8 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_9 ),
+ .datac(\inst|vga_driver_unit|vsync_state_5 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .lut_mask = "d0f0";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N9
+stratix_lcell \inst|vga_driver_unit|vsync_state_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 = E1_vsync_state_3 & (!\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|vsync_counter_0 # !\inst|vga_driver_unit|un14_vsync_counter_8 )
+// \inst|vga_driver_unit|vsync_state_3 = DFFEAS(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , \inst|vga_driver_unit|vsync_state_1 , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , VCC)
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datac(\inst|vga_driver_unit|vsync_state_1 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(vcc),
+ .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ),
+ .regout(\inst|vga_driver_unit|vsync_state_3 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_3_ .lut_mask = "70f0";
+defparam \inst|vga_driver_unit|vsync_state_3_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_3_ .output_mode = "reg_and_comb";
+defparam \inst|vga_driver_unit|vsync_state_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_3_ .sum_lutc_input = "qfbk";
+defparam \inst|vga_driver_unit|vsync_state_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N5
+stratix_lcell \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 = \inst|vga_driver_unit|vsync_state_4 & (!\inst|vga_driver_unit|un13_vsync_counter_4 # !\inst|vga_driver_unit|un12_vsync_counter_7 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un12_vsync_counter_7 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un13_vsync_counter_4 ),
+ .datad(\inst|vga_driver_unit|vsync_state_4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .lut_mask = "5f00";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N3
+stratix_lcell \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 = \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 # \inst|vga_driver_unit|vsync_state_2 & (!\inst|vga_driver_unit|un12_vsync_counter_6 # !\inst|vga_driver_unit|un15_vsync_counter_4 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un15_vsync_counter_4 ),
+ .datab(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ),
+ .datac(\inst|vga_driver_unit|un12_vsync_counter_6 ),
+ .datad(\inst|vga_driver_unit|vsync_state_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .lut_mask = "dfcc";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N6
+stratix_lcell \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_next_2_sqmuxa = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 & !\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 &
+// !\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ),
+ .datab(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ),
+ .datac(\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .lut_mask = "ff01";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N0
+stratix_lcell \inst|vga_driver_unit|vsync_state_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_2 = DFFEAS(\inst|vga_driver_unit|un14_vsync_counter_8 & \inst|vga_driver_unit|vsync_state_3 & \inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ),
+// VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .datab(\inst|vga_driver_unit|vsync_state_3 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_2 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_2_ .lut_mask = "8000";
+defparam \inst|vga_driver_unit|vsync_state_2_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_2_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X28_Y38_N2
+stratix_lcell \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 = \inst|vga_driver_unit|un15_vsync_counter_4 & (\inst|vga_driver_unit|vsync_state_2 & \inst|vga_driver_unit|un12_vsync_counter_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un15_vsync_counter_4 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_state_2 ),
+ .datad(\inst|vga_driver_unit|un12_vsync_counter_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .lut_mask = "a000";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N0
+stratix_lcell \inst|vga_driver_unit|vsync_state_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_0 = DFFEAS(\inst|vga_driver_unit|vsync_state_0 & (\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 & !\inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ) #
+// !\inst|vga_driver_unit|vsync_state_0 & \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 & (!\inst|vga_driver_unit|un6_dly_counter_0_x ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_state_0 ),
+ .datab(\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ),
+ .datac(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_0_ .lut_mask = "0ace";
+defparam \inst|vga_driver_unit|vsync_state_0_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_0_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N1
+stratix_lcell \inst|vga_driver_unit|d_set_vsync_counter_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|d_set_vsync_counter = \inst|vga_driver_unit|vsync_state_6 # \inst|vga_driver_unit|vsync_state_0
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_6 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_state_0 ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|d_set_vsync_counter ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .lut_mask = "fafa";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N7
+stratix_lcell \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa = \inst|dly_counter [0] & !\inst|vga_driver_unit|d_set_vsync_counter & \reset~combout & \inst|dly_counter [1]
+
+ .clk(gnd),
+ .dataa(\inst|dly_counter [0]),
+ .datab(\inst|vga_driver_unit|d_set_vsync_counter ),
+ .datac(\reset~combout ),
+ .datad(\inst|dly_counter [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .lut_mask = "2000";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N1
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 (
+// Equation(s):
+// \inst|vga_driver_unit|un12_vsync_counter_6 = !\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_7 & !\inst|vga_driver_unit|vsync_counter_5 & !\inst|vga_driver_unit|vsync_counter_8
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_counter_6 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_7 ),
+ .datac(\inst|vga_driver_unit|vsync_counter_5 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un12_vsync_counter_6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .lut_mask = "0001";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y39_N2
+stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 (
+// Equation(s):
+// \inst|vga_driver_unit|un14_vsync_counter_8 = \inst|vga_driver_unit|un12_vsync_counter_6 & \inst|vga_driver_unit|un12_vsync_counter_7
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un12_vsync_counter_6 ),
+ .datad(\inst|vga_driver_unit|un12_vsync_counter_7 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .lut_mask = "f000";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N7
+stratix_lcell \inst|vga_driver_unit|vsync_state_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|vsync_state_4 = DFFEAS(\inst|vga_driver_unit|un14_vsync_counter_8 & \inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|vsync_state_5 & !\inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ),
+// VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un14_vsync_counter_8 ),
+ .datab(\inst|vga_driver_unit|vsync_counter_0 ),
+ .datac(\inst|vga_driver_unit|vsync_state_5 ),
+ .datad(\inst|vga_driver_unit|vsync_counter_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|vsync_state_4 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|vsync_state_4_ .lut_mask = "0080";
+defparam \inst|vga_driver_unit|vsync_state_4_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|vsync_state_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|vsync_state_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|vsync_state_4_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|vsync_state_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N5
+stratix_lcell \inst|vga_driver_unit|un1_vsync_state_2_0_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_vsync_state_2_0 = \inst|vga_driver_unit|vsync_state_3 # \inst|vga_driver_unit|vsync_state_1
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_state_3 ),
+ .datad(\inst|vga_driver_unit|vsync_state_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_vsync_state_2_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .lut_mask = "fff0";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N6
+stratix_lcell \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|v_sync_1_0_0_0_g1 = \inst|vga_driver_unit|vsync_state_2 & (\inst|vga_driver_unit|v_sync ) # !\inst|vga_driver_unit|vsync_state_2 & (\inst|vga_driver_unit|un1_vsync_state_2_0 & (\inst|vga_driver_unit|v_sync ) #
+// !\inst|vga_driver_unit|un1_vsync_state_2_0 & \inst|vga_driver_unit|vsync_state_4 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_4 ),
+ .datab(\inst|vga_driver_unit|vsync_state_2 ),
+ .datac(\inst|vga_driver_unit|v_sync ),
+ .datad(\inst|vga_driver_unit|un1_vsync_state_2_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .lut_mask = "f0e2";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N1
+stratix_lcell \inst|vga_driver_unit|v_sync_Z (
+// Equation(s):
+// \inst|vga_driver_unit|v_sync = DFFEAS(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 # !\inst|dly_counter [0] # !\reset~combout # !\inst|dly_counter [1], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|dly_counter [1]),
+ .datab(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 ),
+ .datac(\reset~combout ),
+ .datad(\inst|dly_counter [0]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|v_sync ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|v_sync_Z .lut_mask = "dfff";
+defparam \inst|vga_driver_unit|v_sync_Z .operation_mode = "normal";
+defparam \inst|vga_driver_unit|v_sync_Z .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|v_sync_Z .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|v_sync_Z .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|v_sync_Z .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y38_N2
+stratix_lcell \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 = \inst|dly_counter [0] & \inst|dly_counter [1] & \reset~combout & !\inst|vga_driver_unit|hsync_state_1
+
+ .clk(gnd),
+ .dataa(\inst|dly_counter [0]),
+ .datab(\inst|dly_counter [1]),
+ .datac(\reset~combout ),
+ .datad(\inst|vga_driver_unit|hsync_state_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .lut_mask = "0080";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N4
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_0 = DFFEAS(!\inst|vga_driver_unit|un10_column_counter_siglto9 # !\inst|vga_driver_unit|column_counter_sig_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .lut_mask = "55ff";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y35_N5
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [1] = \inst|vga_driver_unit|column_counter_sig_0 $ \inst|vga_driver_unit|column_counter_sig_1
+// \inst|vga_driver_unit|un2_column_counter_next_cout [1] = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [1]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [1]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .lut_mask = "6688";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N8
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_1 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [1] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .lut_mask = "ff55";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y35_N6
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [3] = \inst|vga_driver_unit|column_counter_sig_3 $ (\inst|vga_driver_unit|column_counter_sig_2 & \inst|vga_driver_unit|un2_column_counter_next_cout [1])
+// \inst|vga_driver_unit|un2_column_counter_next_cout [3] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [1] # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [1]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [3]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [3]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .lut_mask = "6c7f";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N1
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_3 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [3] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un2_column_counter_next_combout [3]),
+ .datad(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .lut_mask = "f0ff";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X24_Y35_N0
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_cout [0] = CARRY(\inst|vga_driver_unit|column_counter_sig_1 & \inst|vga_driver_unit|column_counter_sig_0 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 = CARRY(\inst|vga_driver_unit|column_counter_sig_1 & \inst|vga_driver_unit|column_counter_sig_0 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_0_~COMBOUT ),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [0]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .lut_mask = "ff88";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .output_mode = "none";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y35_N1
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [2] = \inst|vga_driver_unit|column_counter_sig_2 $ (\inst|vga_driver_unit|un2_column_counter_next_cout [0])
+// \inst|vga_driver_unit|un2_column_counter_next_cout [2] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [0] # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [0]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [2]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [2]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .lut_mask = "5a7f";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N6
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_2 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [2] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un2_column_counter_next_combout [2]),
+ .datad(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .lut_mask = "f0ff";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X24_Y35_N2
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [4] = \inst|vga_driver_unit|column_counter_sig_4 $ !\inst|vga_driver_unit|un2_column_counter_next_cout [2]
+// \inst|vga_driver_unit|un2_column_counter_next_cout [4] = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [2])
+// \inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [2]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [4]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [4]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .lut_mask = "c308";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N7
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_4 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [4] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [4]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .lut_mask = "ff55";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y35_N7
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [5] = \inst|vga_driver_unit|column_counter_sig_5 $ (\inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [3])
+// \inst|vga_driver_unit|un2_column_counter_next_cout [5] = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [3])
+// \inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [3]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [5]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [5]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .lut_mask = "a608";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N0
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_5 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [5] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [5]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .lut_mask = "ff55";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X24_Y35_N3
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [6] = \inst|vga_driver_unit|column_counter_sig_6 $ (\inst|vga_driver_unit|un2_column_counter_next_cout [4])
+// \inst|vga_driver_unit|un2_column_counter_next_cout [6] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [4] # !\inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|column_counter_sig_6 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 # !\inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|column_counter_sig_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [4]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [6]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [6]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .lut_mask = "5a7f";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X24_Y35_N4
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [8] = \inst|vga_driver_unit|un2_column_counter_next_cout [6] $ !\inst|vga_driver_unit|column_counter_sig_8
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [6]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [8]),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .lut_mask = "f00f";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y35_N3
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_8 = DFFEAS(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 & \inst|vga_driver_unit|un10_column_counter_siglto9 & (\inst|vga_driver_unit|un2_column_counter_next_combout [8]),
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .datab(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [8]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .lut_mask = "8800";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_8_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N5
+stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_column_counter_siglt6_4 = !\inst|vga_driver_unit|column_counter_sig_1 # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 # !\inst|vga_driver_unit|column_counter_sig_0
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_column_counter_siglt6_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 .lut_mask = "7fff";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N3
+stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_column_counter_siglt6 = \inst|vga_driver_unit|un10_column_counter_siglt6_4 # !\inst|vga_driver_unit|column_counter_sig_5 # !\inst|vga_driver_unit|column_counter_sig_4 # !\inst|vga_driver_unit|column_counter_sig_6
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|un10_column_counter_siglt6_4 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_column_counter_siglt6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .lut_mask = "bfff";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y35_N8
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [7] = \inst|vga_driver_unit|column_counter_sig_7 $ (\inst|vga_driver_unit|column_counter_sig_6 & \inst|vga_driver_unit|un2_column_counter_next_cout [5])
+// \inst|vga_driver_unit|un2_column_counter_next_cout [7] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [5] # !\inst|vga_driver_unit|column_counter_sig_6 # !\inst|vga_driver_unit|column_counter_sig_7 )
+// \inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 # !\inst|vga_driver_unit|column_counter_sig_6 # !\inst|vga_driver_unit|column_counter_sig_7 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [5]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [7]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [7]),
+ .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .lut_mask = "6a7f";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y35_N9
+stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|un2_column_counter_next_combout [9] = \inst|vga_driver_unit|column_counter_sig_9 $ (\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_driver_unit|un2_column_counter_next_cout [7])
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [7]),
+ .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [9]),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .lut_mask = "c6c6";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y35_N1
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_9 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [9] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [9]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .lut_mask = "ff0f";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_9_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N2
+stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_column_counter_siglto9 = !\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_driver_unit|column_counter_sig_7 & \inst|vga_driver_unit|un10_column_counter_siglt6 # !\inst|vga_driver_unit|column_counter_sig_9
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglt6 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .lut_mask = "10ff";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X25_Y35_N2
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_7 = DFFEAS(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 & (\inst|vga_driver_unit|un10_column_counter_siglto9 & \inst|vga_driver_unit|un2_column_counter_next_combout [7]),
+// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [7]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .lut_mask = "a000";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_7_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y35_N9
+stratix_lcell \inst|vga_driver_unit|column_counter_sig_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|column_counter_sig_6 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [6] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un2_column_counter_next_combout [6]),
+ .datad(\inst|vga_driver_unit|un10_column_counter_siglto9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .lut_mask = "f0ff";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|column_counter_sig_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X25_Y35_N4
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 (
+// Equation(s):
+// \inst|vga_control_unit|un5_v_enablelt2 = \inst|vga_driver_unit|column_counter_sig_1 # \inst|vga_driver_unit|column_counter_sig_0 # \inst|vga_driver_unit|column_counter_sig_2
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un5_v_enablelt2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 .lut_mask = "fffc";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N7
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 (
+// Equation(s):
+// \inst|vga_control_unit|un5_v_enablelto5 = \inst|vga_driver_unit|column_counter_sig_5 # \inst|vga_driver_unit|column_counter_sig_4 # \inst|vga_driver_unit|column_counter_sig_3 & \inst|vga_control_unit|un5_v_enablelt2
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .datad(\inst|vga_control_unit|un5_v_enablelt2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un5_v_enablelto5 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 .lut_mask = "fefa";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N4
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 (
+// Equation(s):
+// \inst|vga_control_unit|un9_v_enablelto4 = !\inst|vga_driver_unit|column_counter_sig_2 & !\inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|column_counter_sig_3
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .datac(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .datad(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un9_v_enablelto4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 .lut_mask = "0003";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N5
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 (
+// Equation(s):
+// \inst|vga_control_unit|un9_v_enablelto6 = \inst|vga_control_unit|un9_v_enablelto4 # !\inst|vga_driver_unit|column_counter_sig_5 # !\inst|vga_driver_unit|column_counter_sig_6
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .datad(\inst|vga_control_unit|un9_v_enablelto4 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un9_v_enablelto6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .lut_mask = "ff5f";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N0
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [1] = \inst|vga_driver_unit|d_set_hsync_counter $ \inst|vga_driver_unit|line_counter_sig_0
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [1] = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [1]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [1]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .lut_mask = "6688";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N8
+stratix_lcell \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 = \inst|dly_counter [0] & !\inst|vga_driver_unit|vsync_state_1 & \reset~combout & \inst|dly_counter [1]
+
+ .clk(gnd),
+ .dataa(\inst|dly_counter [0]),
+ .datab(\inst|vga_driver_unit|vsync_state_1 ),
+ .datac(\reset~combout ),
+ .datad(\inst|dly_counter [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .lut_mask = "2000";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N5
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_0_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_0 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [1] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [1]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .lut_mask = "ff33";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N1
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [3] = \inst|vga_driver_unit|line_counter_sig_2 $ (\inst|vga_driver_unit|line_counter_sig_1 & \inst|vga_driver_unit|un1_line_counter_sig_cout [1])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [3] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [1] # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [1]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [3]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [3]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .lut_mask = "6c7f";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N9
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_2 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [3] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un1_line_counter_sig_combout [3]),
+ .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .lut_mask = "f0ff";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N5
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_a_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_a_cout [1] = CARRY(\inst|vga_driver_unit|line_counter_sig_0 & \inst|vga_driver_unit|d_set_hsync_counter )
+// \inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 = CARRY(\inst|vga_driver_unit|line_counter_sig_0 & \inst|vga_driver_unit|d_set_hsync_counter )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .datab(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT ),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .lut_mask = "ff88";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .output_mode = "none";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N6
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_2_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [2] = \inst|vga_driver_unit|line_counter_sig_1 $ (\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [2] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1] # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [2]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [2]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .lut_mask = "5a7f";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X18_Y42_N5
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_1_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_1 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [2] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datac(\inst|vga_driver_unit|un1_line_counter_sig_combout [2]),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .lut_mask = "f3f3";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N2
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [5] = \inst|vga_driver_unit|line_counter_sig_4 $ (\inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [3])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [5] = CARRY(\inst|vga_driver_unit|line_counter_sig_3 & \inst|vga_driver_unit|line_counter_sig_4 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [3])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 = CARRY(\inst|vga_driver_unit|line_counter_sig_3 & \inst|vga_driver_unit|line_counter_sig_4 & !\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [3]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [5]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [5]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .lut_mask = "c608";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N7
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_4 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [5] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [5]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .lut_mask = "ff33";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N7
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_4_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [4] = \inst|vga_driver_unit|line_counter_sig_3 $ !\inst|vga_driver_unit|un1_line_counter_sig_cout [2]
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [4] = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [2])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [2]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [4]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [4]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .lut_mask = "c308";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N1
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_3_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_3 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [4] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un1_line_counter_sig_combout [4]),
+ .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .lut_mask = "f0ff";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N3
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [7] = \inst|vga_driver_unit|line_counter_sig_6 $ (\inst|vga_driver_unit|line_counter_sig_5 & \inst|vga_driver_unit|un1_line_counter_sig_cout [5])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [7] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [5] # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_5 )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_5 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [5]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [7]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [7]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .lut_mask = "6c7f";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N6
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_6 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [7] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|un1_line_counter_sig_combout [7]),
+ .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .lut_mask = "f0ff";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N8
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_6_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [6] = \inst|vga_driver_unit|line_counter_sig_5 $ (\inst|vga_driver_unit|un1_line_counter_sig_cout [4])
+// \inst|vga_driver_unit|un1_line_counter_sig_cout [6] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [4] # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_5 )
+// \inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_5 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [4]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [6]),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [6]),
+ .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ));
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .lut_mask = "5a7f";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X18_Y42_N2
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_5_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_5 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [6] & \inst|vga_driver_unit|un10_line_counter_siglto8 & \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , GLOBAL(\inst1|altpll_component|_clk0 ),
+// VCC, , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|un1_line_counter_sig_combout [6]),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datac(\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .lut_mask = "8080";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_5_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N9
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [8] = \inst|vga_driver_unit|un1_line_counter_sig_cout [6] $ !\inst|vga_driver_unit|line_counter_sig_7
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [6]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [8]),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .lut_mask = "f00f";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N2
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_7_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_7 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [8] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un1_line_counter_sig_combout [8]),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .lut_mask = "ccff";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_7_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N0
+stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_line_counter_siglt4_2 = !\inst|vga_driver_unit|line_counter_sig_0 # !\inst|vga_driver_unit|line_counter_sig_3 # !\inst|vga_driver_unit|line_counter_sig_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .datad(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_line_counter_siglt4_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .lut_mask = "5fff";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N3
+stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_line_counter_siglto5 = !\inst|vga_driver_unit|line_counter_sig_5 & (\inst|vga_driver_unit|un10_line_counter_siglt4_2 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglt4_2 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .datad(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_line_counter_siglto5 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .lut_mask = "0d0f";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X21_Y42_N4
+stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 (
+// Equation(s):
+// \inst|vga_driver_unit|un10_line_counter_siglto8 = \inst|vga_driver_unit|un10_line_counter_siglto5 # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_8 # !\inst|vga_driver_unit|line_counter_sig_7
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .datad(\inst|vga_driver_unit|un10_line_counter_siglto5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .lut_mask = "ff7f";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .operation_mode = "normal";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N4
+stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_9_ (
+// Equation(s):
+// \inst|vga_driver_unit|un1_line_counter_sig_combout [9] = \inst|vga_driver_unit|line_counter_sig_8 $ (\inst|vga_driver_unit|line_counter_sig_7 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [7])
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [7]),
+ .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [9]),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .cin0_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .cin1_used = "true";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .lut_mask = "f30c";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X22_Y42_N8
+stratix_lcell \inst|vga_driver_unit|line_counter_sig_8_ (
+// Equation(s):
+// \inst|vga_driver_unit|line_counter_sig_8 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [9] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , ,
+// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|un10_line_counter_siglto8 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [9]),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .lut_mask = "ff33";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|line_counter_sig_8_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X30_Y39_N9
+stratix_lcell \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|vsync_state_4 & !\inst|vga_driver_unit|vsync_state_5
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|vsync_state_4 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|vsync_state_5 ),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .lut_mask = "ff05";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N0
+stratix_lcell \inst|vga_driver_unit|h_enable_sig_Z (
+// Equation(s):
+// \inst|vga_driver_unit|h_enable_sig = DFFEAS(\inst|vga_driver_unit|vsync_state_3 # \inst|vga_driver_unit|vsync_state_1 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_driver_unit|vsync_state_3 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|vsync_state_1 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|h_enable_sig ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|h_enable_sig_Z .lut_mask = "ffaa";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .operation_mode = "normal";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|h_enable_sig_Z .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N8
+stratix_lcell \inst|vga_control_unit|b_next_0_sqmuxa_7_2_cZ (
+// Equation(s):
+// \inst|vga_control_unit|b_next_0_sqmuxa_7_2 = !\inst|vga_driver_unit|column_counter_sig_9 & !\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_driver_unit|line_counter_sig_8 & \inst|vga_driver_unit|h_enable_sig
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .datad(\inst|vga_driver_unit|h_enable_sig ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|b_next_0_sqmuxa_7_2 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_2_cZ .lut_mask = "0100";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_2_cZ .operation_mode = "normal";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_2_cZ .output_mode = "comb_only";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_2_cZ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_2_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_2_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N6
+stratix_lcell \inst|vga_control_unit|b_next_0_sqmuxa_7_3_cZ (
+// Equation(s):
+// \inst|vga_control_unit|b_next_0_sqmuxa_7_3 = \inst|vga_control_unit|b_next_0_sqmuxa_7_2 & (\inst|vga_driver_unit|column_counter_sig_9 # \inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_control_unit|un9_v_enablelto6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datac(\inst|vga_control_unit|un9_v_enablelto6 ),
+ .datad(\inst|vga_control_unit|b_next_0_sqmuxa_7_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|b_next_0_sqmuxa_7_3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_3_cZ .lut_mask = "ef00";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_3_cZ .operation_mode = "normal";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_3_cZ .output_mode = "comb_only";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_3_cZ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_3_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_3_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N9
+stratix_lcell \inst|vga_control_unit|b_next_0_sqmuxa_7_5_cZ (
+// Equation(s):
+// \inst|vga_control_unit|b_next_0_sqmuxa_7_5 = \inst|vga_control_unit|b_next_0_sqmuxa_7_3 & (!\inst|vga_control_unit|un5_v_enablelto5 # !\inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|column_counter_sig_6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .datab(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .datac(\inst|vga_control_unit|un5_v_enablelto5 ),
+ .datad(\inst|vga_control_unit|b_next_0_sqmuxa_7_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|b_next_0_sqmuxa_7_5 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_5_cZ .lut_mask = "7f00";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_5_cZ .operation_mode = "normal";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_5_cZ .output_mode = "comb_only";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_5_cZ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_5_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_5_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X18_Y42_N6
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 (
+// Equation(s):
+// \inst|vga_control_unit|un13_v_enablelto4_0 = !\inst|vga_driver_unit|line_counter_sig_4 & (!\inst|vga_driver_unit|line_counter_sig_2 )
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un13_v_enablelto4_0 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 .lut_mask = "0033";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X18_Y42_N4
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 (
+// Equation(s):
+// \inst|vga_control_unit|un13_v_enablelto6 = \inst|vga_control_unit|un13_v_enablelto4_0 & !\inst|vga_driver_unit|line_counter_sig_3 # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_5
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .datab(\inst|vga_control_unit|un13_v_enablelto4_0 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .datad(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un13_v_enablelto6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 .lut_mask = "5dff";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X18_Y42_N8
+stratix_lcell \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 (
+// Equation(s):
+// \inst|vga_control_unit|un17_v_enablelto3 = \inst|vga_driver_unit|line_counter_sig_3 & (\inst|vga_driver_unit|line_counter_sig_1 # \inst|vga_driver_unit|line_counter_sig_0 # \inst|vga_driver_unit|line_counter_sig_2 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .datad(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un17_v_enablelto3 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 .lut_mask = "ccc8";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 .operation_mode = "normal";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N1
+stratix_lcell \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ (
+// Equation(s):
+// \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a = !\inst|vga_control_unit|un17_v_enablelto3 & !\inst|vga_driver_unit|line_counter_sig_4 & !\inst|vga_driver_unit|line_counter_sig_5 # !\inst|vga_driver_unit|line_counter_sig_6
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|un17_v_enablelto3 ),
+ .datab(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .datad(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|b_next_0_sqmuxa_7_4_a ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ .lut_mask = "3337";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ .operation_mode = "normal";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ .output_mode = "comb_only";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N2
+stratix_lcell \inst|vga_control_unit|b_next_0_sqmuxa_7_4_cZ (
+// Equation(s):
+// \inst|vga_control_unit|b_next_0_sqmuxa_7_4 = \inst|vga_driver_unit|line_counter_sig_7 & (\inst|vga_control_unit|b_next_0_sqmuxa_7_4_a ) # !\inst|vga_driver_unit|line_counter_sig_7 & (\inst|vga_driver_unit|line_counter_sig_8 #
+// !\inst|vga_control_unit|un13_v_enablelto6 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .datab(\inst|vga_control_unit|un13_v_enablelto6 ),
+ .datac(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .datad(\inst|vga_control_unit|b_next_0_sqmuxa_7_4_a ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|b_next_0_sqmuxa_7_4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_cZ .lut_mask = "fb0b";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_cZ .operation_mode = "normal";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_cZ .output_mode = "comb_only";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_cZ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|b_next_0_sqmuxa_7_4_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X42_Y42_N7
+stratix_lcell \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ (
+// Equation(s):
+// \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|hsync_state_5 & !\inst|vga_driver_unit|hsync_state_4
+
+ .clk(gnd),
+ .dataa(\inst|vga_driver_unit|hsync_state_5 ),
+ .datab(vcc),
+ .datac(\inst|vga_driver_unit|hsync_state_4 ),
+ .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .lut_mask = "ff05";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .operation_mode = "normal";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .output_mode = "comb_only";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X50_Y42_N2
+stratix_lcell \inst|vga_driver_unit|v_enable_sig_Z (
+// Equation(s):
+// \inst|vga_driver_unit|v_enable_sig = DFFEAS(\inst|vga_driver_unit|hsync_state_1 # \inst|vga_driver_unit|hsync_state_3 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 , , ,
+// \inst|vga_driver_unit|un6_dly_counter_0_x , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_driver_unit|hsync_state_1 ),
+ .datac(vcc),
+ .datad(\inst|vga_driver_unit|hsync_state_3 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .sload(gnd),
+ .ena(\inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_driver_unit|v_enable_sig ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_driver_unit|v_enable_sig_Z .lut_mask = "ffcc";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .operation_mode = "normal";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .output_mode = "reg_only";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .register_cascade_mode = "off";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .sum_lutc_input = "datac";
+defparam \inst|vga_driver_unit|v_enable_sig_Z .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N0
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_0_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_0 = DFFEAS(!\inst|vga_control_unit|toggle_counter_sig_0 , GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .lut_mask = "00ff";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|toggle_counter_sig_0_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N0
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_1_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_1 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_0 $ \inst|vga_control_unit|toggle_counter_sig_1 , GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [1] = CARRY(\inst|vga_control_unit|toggle_counter_sig_0 & \inst|vga_control_unit|toggle_counter_sig_1 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 = CARRY(\inst|vga_control_unit|toggle_counter_sig_0 & \inst|vga_control_unit|toggle_counter_sig_1 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_1 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_1 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [1]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .lut_mask = "6688";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|toggle_counter_sig_1_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N1
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_3_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_3 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_3 $ (\inst|vga_control_unit|toggle_counter_sig_2 & \inst|vga_control_unit|toggle_counter_sig_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [3] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [1] # !\inst|vga_control_unit|toggle_counter_sig_3 # !\inst|vga_control_unit|toggle_counter_sig_2 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 # !\inst|vga_control_unit|toggle_counter_sig_3 # !\inst|vga_control_unit|toggle_counter_sig_2 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_2 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_3 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [1]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_3 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [3]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .lut_mask = "6c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_3_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N5
+stratix_lcell \inst|vga_control_unit|un2_toggle_counter_next_0_ (
+// Equation(s):
+// \inst|vga_control_unit|un2_toggle_counter_next_cout [0] = CARRY(\inst|vga_control_unit|toggle_counter_sig_1 & \inst|vga_control_unit|toggle_counter_sig_0 )
+// \inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 = CARRY(\inst|vga_control_unit|toggle_counter_sig_1 & \inst|vga_control_unit|toggle_counter_sig_0 )
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_1 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un2_toggle_counter_next_0_~COMBOUT ),
+ .regout(),
+ .cout(),
+ .cout0(\inst|vga_control_unit|un2_toggle_counter_next_cout [0]),
+ .cout1(\inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .lut_mask = "ff88";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .output_mode = "none";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|un2_toggle_counter_next_0_ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N6
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_2_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_2 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_2 $ \inst|vga_control_unit|un2_toggle_counter_next_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , ,
+// , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [2] = CARRY(!\inst|vga_control_unit|un2_toggle_counter_next_cout [0] # !\inst|vga_control_unit|toggle_counter_sig_2 # !\inst|vga_control_unit|toggle_counter_sig_3 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 = CARRY(!\inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 # !\inst|vga_control_unit|toggle_counter_sig_2 # !\inst|vga_control_unit|toggle_counter_sig_3 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_3 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_2 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|un2_toggle_counter_next_cout [0]),
+ .cin1(\inst|vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_2 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [2]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .lut_mask = "3c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_2_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N2
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_5_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_5 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_5 $ (\inst|vga_control_unit|toggle_counter_sig_4 & !\inst|vga_control_unit|toggle_counter_sig_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [5] = CARRY(\inst|vga_control_unit|toggle_counter_sig_5 & \inst|vga_control_unit|toggle_counter_sig_4 & !\inst|vga_control_unit|toggle_counter_sig_cout [3])
+// \inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 = CARRY(\inst|vga_control_unit|toggle_counter_sig_5 & \inst|vga_control_unit|toggle_counter_sig_4 & !\inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_4 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [3]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [5]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .lut_mask = "a608";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_5_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N7
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_4_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_4 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_4 $ (!\inst|vga_control_unit|toggle_counter_sig_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , ,
+// , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [4] = CARRY(\inst|vga_control_unit|toggle_counter_sig_4 & \inst|vga_control_unit|toggle_counter_sig_5 & !\inst|vga_control_unit|toggle_counter_sig_cout [2])
+// \inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 = CARRY(\inst|vga_control_unit|toggle_counter_sig_4 & \inst|vga_control_unit|toggle_counter_sig_5 & !\inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_4 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [2]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_4 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [4]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .lut_mask = "a508";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_4_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N8
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_6_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_6 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_6 $ \inst|vga_control_unit|toggle_counter_sig_cout [4], GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [6] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [4] # !\inst|vga_control_unit|toggle_counter_sig_6 # !\inst|vga_control_unit|toggle_counter_sig_7 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 # !\inst|vga_control_unit|toggle_counter_sig_6 # !\inst|vga_control_unit|toggle_counter_sig_7 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [4]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [6]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .lut_mask = "3c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_6_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N3
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_7_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_7 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_7 $ (\inst|vga_control_unit|toggle_counter_sig_6 & \inst|vga_control_unit|toggle_counter_sig_cout [5]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [7] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [5] # !\inst|vga_control_unit|toggle_counter_sig_6 # !\inst|vga_control_unit|toggle_counter_sig_7 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 # !\inst|vga_control_unit|toggle_counter_sig_6 # !\inst|vga_control_unit|toggle_counter_sig_7 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [5]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [7]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .lut_mask = "6a7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_7_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N9
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_8_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_8 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_8 $ !\inst|vga_control_unit|toggle_counter_sig_cout [6], GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [8] = CARRY(\inst|vga_control_unit|toggle_counter_sig_9 & \inst|vga_control_unit|toggle_counter_sig_8 & !\inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [6]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .cout(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .lut_mask = "c308";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_8_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N4
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_9_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_9 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_9 $ (\inst|vga_control_unit|toggle_counter_sig_8 & !\inst|vga_control_unit|toggle_counter_sig_cout [7]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [9] = CARRY(\inst|vga_control_unit|toggle_counter_sig_9 & \inst|vga_control_unit|toggle_counter_sig_8 & !\inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [7]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .cout(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .lut_mask = "a608";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_9_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N5
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_11_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_11 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_11 $ (\inst|vga_control_unit|toggle_counter_sig_10 & \inst|vga_control_unit|toggle_counter_sig_cout [9]), GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [11] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [9] # !\inst|vga_control_unit|toggle_counter_sig_11 # !\inst|vga_control_unit|toggle_counter_sig_10 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [9] # !\inst|vga_control_unit|toggle_counter_sig_11 # !\inst|vga_control_unit|toggle_counter_sig_10 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [11]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .lut_mask = "6c7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_11_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N0
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_10_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_10 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_10 $ (\inst|vga_control_unit|toggle_counter_sig_cout [8]), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , ,
+// , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [10] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [8] # !\inst|vga_control_unit|toggle_counter_sig_11 # !\inst|vga_control_unit|toggle_counter_sig_10 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [8] # !\inst|vga_control_unit|toggle_counter_sig_11 # !\inst|vga_control_unit|toggle_counter_sig_10 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [10]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .lut_mask = "5a7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_10_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N6
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_13_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_13 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_13 $ (\inst|vga_control_unit|toggle_counter_sig_12 & !(!\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout
+// [11]) # (\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [13] = CARRY(\inst|vga_control_unit|toggle_counter_sig_12 & \inst|vga_control_unit|toggle_counter_sig_13 & !\inst|vga_control_unit|toggle_counter_sig_cout [11])
+// \inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 = CARRY(\inst|vga_control_unit|toggle_counter_sig_12 & \inst|vga_control_unit|toggle_counter_sig_13 & !\inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [11]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [13]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .lut_mask = "c608";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_13_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N1
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_12_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_12 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_12 $ (!(!\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout [10]) #
+// (\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [12] = CARRY(\inst|vga_control_unit|toggle_counter_sig_12 & \inst|vga_control_unit|toggle_counter_sig_13 & !\inst|vga_control_unit|toggle_counter_sig_cout [10])
+// \inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 = CARRY(\inst|vga_control_unit|toggle_counter_sig_12 & \inst|vga_control_unit|toggle_counter_sig_13 & !\inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [10]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [12]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .lut_mask = "a508";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_12_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N7
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_15_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_15 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_15 $ (\inst|vga_control_unit|toggle_counter_sig_14 & (!\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout
+// [13]) # (\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [15] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [13] # !\inst|vga_control_unit|toggle_counter_sig_14 # !\inst|vga_control_unit|toggle_counter_sig_15 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 # !\inst|vga_control_unit|toggle_counter_sig_14 # !\inst|vga_control_unit|toggle_counter_sig_15 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [13]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [15]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .lut_mask = "6a7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_15_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N2
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_14_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_14 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_14 $ ((!\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout [12]) #
+// (\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [14] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout [12] # !\inst|vga_control_unit|toggle_counter_sig_15 # !\inst|vga_control_unit|toggle_counter_sig_14 )
+// \inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 # !\inst|vga_control_unit|toggle_counter_sig_15 # !\inst|vga_control_unit|toggle_counter_sig_14 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [12]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [14]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .lut_mask = "5a7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_14_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N3
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglt6 = !\inst|vga_control_unit|toggle_counter_sig_5 # !\inst|vga_control_unit|toggle_counter_sig_6
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglt6 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 .lut_mask = "55ff";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N4
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto9 = !\inst|vga_control_unit|toggle_counter_sig_7 & \inst|vga_control_unit|un1_toggle_counter_siglt6 # !\inst|vga_control_unit|toggle_counter_sig_9 # !\inst|vga_control_unit|toggle_counter_sig_8
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .datac(\inst|vga_control_unit|un1_toggle_counter_siglt6 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto9 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 .lut_mask = "73ff";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N6
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto12 = \inst|vga_control_unit|un1_toggle_counter_siglto9 & !\inst|vga_control_unit|toggle_counter_sig_10 & !\inst|vga_control_unit|toggle_counter_sig_12 & !\inst|vga_control_unit|toggle_counter_sig_11
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|un1_toggle_counter_siglto9 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .datac(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto12 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 .lut_mask = "0002";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N7
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto15 = \inst|vga_control_unit|un1_toggle_counter_siglto12 # !\inst|vga_control_unit|toggle_counter_sig_13 # !\inst|vga_control_unit|toggle_counter_sig_15 # !\inst|vga_control_unit|toggle_counter_sig_14
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .datab(\inst|vga_control_unit|un1_toggle_counter_siglto12 ),
+ .datac(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto15 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 .lut_mask = "dfff";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N3
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_16_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_16 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_16 $ (!(!\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout [14]) #
+// (\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [16] = CARRY(\inst|vga_control_unit|toggle_counter_sig_16 & \inst|vga_control_unit|toggle_counter_sig_17 & !\inst|vga_control_unit|toggle_counter_sig_cout [14])
+// \inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 = CARRY(\inst|vga_control_unit|toggle_counter_sig_16 & \inst|vga_control_unit|toggle_counter_sig_17 & !\inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [14]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [16]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .lut_mask = "a508";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_16_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N8
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_17_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_17 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_17 $ (\inst|vga_control_unit|toggle_counter_sig_16 & !(!\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout
+// [15]) # (\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [17] = CARRY(\inst|vga_control_unit|toggle_counter_sig_17 & \inst|vga_control_unit|toggle_counter_sig_16 & !\inst|vga_control_unit|toggle_counter_sig_cout [15])
+// \inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 = CARRY(\inst|vga_control_unit|toggle_counter_sig_17 & \inst|vga_control_unit|toggle_counter_sig_16 & !\inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [15]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .cout(),
+ .cout0(\inst|vga_control_unit|toggle_counter_sig_cout [17]),
+ .cout1(\inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 ));
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .lut_mask = "a608";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_17_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X76_Y6_N9
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_19_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_19 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_19 $ (\inst|vga_control_unit|toggle_counter_sig_18 & (!\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout
+// [17]) # (\inst|vga_control_unit|toggle_counter_sig_cout [9] & \inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .datac(vcc),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_19 ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [9]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [17]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_19 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .lut_mask = "3fc0";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_19_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N4
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_18_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_18 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_18 $ ((!\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout [16]) #
+// (\inst|vga_control_unit|toggle_counter_sig_cout [8] & \inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 )), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , ,
+// !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+// \inst|vga_control_unit|toggle_counter_sig_cout [18] = CARRY(!\inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 # !\inst|vga_control_unit|toggle_counter_sig_19 # !\inst|vga_control_unit|toggle_counter_sig_18 )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_19 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [8]),
+ .cin0(\inst|vga_control_unit|toggle_counter_sig_cout [16]),
+ .cin1(\inst|vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45 ),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .cout(\inst|vga_control_unit|toggle_counter_sig_cout [18]),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .cin0_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .cin1_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .lut_mask = "5a7f";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .operation_mode = "arithmetic";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_18_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N8
+stratix_lcell \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 (
+// Equation(s):
+// \inst|vga_control_unit|un1_toggle_counter_siglto18 = \inst|vga_control_unit|un1_toggle_counter_siglto15 & !\inst|vga_control_unit|toggle_counter_sig_16 # !\inst|vga_control_unit|toggle_counter_sig_18 # !\inst|vga_control_unit|toggle_counter_sig_17
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|un1_toggle_counter_siglto15 ),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .datac(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|un1_toggle_counter_siglto18 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 .lut_mask = "3bff";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 .operation_mode = "normal";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 .output_mode = "comb_only";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N5
+stratix_lcell \inst|vga_control_unit|toggle_counter_sig_20_ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_counter_sig_20 = DFFEAS(\inst|vga_control_unit|toggle_counter_sig_20 $ !\inst|vga_control_unit|toggle_counter_sig_cout [18], GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , ,
+// , !\inst|vga_control_unit|toggle_sig_0_0_0_g1 , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(\inst|vga_control_unit|toggle_counter_sig_20 ),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(!\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(\inst|vga_control_unit|toggle_counter_sig_cout [18]),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_counter_sig_20 ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_counter_sig_20_ .cin_used = "true";
+defparam \inst|vga_control_unit|toggle_counter_sig_20_ .lut_mask = "c3c3";
+defparam \inst|vga_control_unit|toggle_counter_sig_20_ .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_counter_sig_20_ .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_counter_sig_20_ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_counter_sig_20_ .sum_lutc_input = "cin";
+defparam \inst|vga_control_unit|toggle_counter_sig_20_ .synch_mode = "on";
+// synopsys translate_on
+
+// atom is at LC_X72_Y5_N9
+stratix_lcell \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ (
+// Equation(s):
+// \inst|vga_control_unit|toggle_sig_0_0_0_g1 = \inst|vga_control_unit|un1_toggle_counter_siglto18 & !\inst|vga_control_unit|toggle_counter_sig_19 # !\inst|vga_control_unit|toggle_counter_sig_20
+
+ .clk(gnd),
+ .dataa(\inst|vga_control_unit|un1_toggle_counter_siglto18 ),
+ .datab(vcc),
+ .datac(\inst|vga_control_unit|toggle_counter_sig_20 ),
+ .datad(\inst|vga_control_unit|toggle_counter_sig_19 ),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .lut_mask = "0faf";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .output_mode = "comb_only";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N2
+stratix_lcell \inst|vga_control_unit|toggle_sig_Z (
+// Equation(s):
+// \inst|vga_control_unit|toggle_sig = DFFEAS(\inst|vga_control_unit|toggle_sig_0_0_0_g1 $ !\inst|vga_control_unit|toggle_sig , GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(\inst|vga_control_unit|toggle_sig_0_0_0_g1 ),
+ .datad(\inst|vga_control_unit|toggle_sig ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|toggle_sig ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|toggle_sig_Z .lut_mask = "f00f";
+defparam \inst|vga_control_unit|toggle_sig_Z .operation_mode = "normal";
+defparam \inst|vga_control_unit|toggle_sig_Z .output_mode = "reg_only";
+defparam \inst|vga_control_unit|toggle_sig_Z .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|toggle_sig_Z .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|toggle_sig_Z .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X72_Y6_N1
+stratix_lcell \inst|vga_control_unit|r_Z (
+// Equation(s):
+// \inst|vga_control_unit|r = DFFEAS(\inst|vga_control_unit|b_next_0_sqmuxa_7_5 & \inst|vga_control_unit|b_next_0_sqmuxa_7_4 & \inst|vga_driver_unit|v_enable_sig & \inst|vga_control_unit|toggle_sig , GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|b_next_0_sqmuxa_7_5 ),
+ .datab(\inst|vga_control_unit|b_next_0_sqmuxa_7_4 ),
+ .datac(\inst|vga_driver_unit|v_enable_sig ),
+ .datad(\inst|vga_control_unit|toggle_sig ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|r ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|r_Z .lut_mask = "8000";
+defparam \inst|vga_control_unit|r_Z .operation_mode = "normal";
+defparam \inst|vga_control_unit|r_Z .output_mode = "reg_only";
+defparam \inst|vga_control_unit|r_Z .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|r_Z .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|r_Z .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X41_Y42_N2
+stratix_lcell \~STRATIX_FITTER_CREATED_GND~I (
+// Equation(s):
+// \~STRATIX_FITTER_CREATED_GND~I_combout = GND
+
+ .clk(gnd),
+ .dataa(vcc),
+ .datab(vcc),
+ .datac(vcc),
+ .datad(vcc),
+ .aclr(gnd),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .regout(),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \~STRATIX_FITTER_CREATED_GND~I .lut_mask = "0000";
+defparam \~STRATIX_FITTER_CREATED_GND~I .operation_mode = "normal";
+defparam \~STRATIX_FITTER_CREATED_GND~I .output_mode = "comb_only";
+defparam \~STRATIX_FITTER_CREATED_GND~I .register_cascade_mode = "off";
+defparam \~STRATIX_FITTER_CREATED_GND~I .sum_lutc_input = "datac";
+defparam \~STRATIX_FITTER_CREATED_GND~I .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at LC_X28_Y35_N3
+stratix_lcell \inst|vga_control_unit|b_Z (
+// Equation(s):
+// \inst|vga_control_unit|b = DFFEAS(\inst|vga_control_unit|b_next_0_sqmuxa_7_4 & \inst|vga_control_unit|b_next_0_sqmuxa_7_5 & !\inst|vga_control_unit|toggle_sig & \inst|vga_driver_unit|v_enable_sig , GLOBAL(\inst1|altpll_component|_clk0 ),
+// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , )
+
+ .clk(\inst1|altpll_component|_clk0 ),
+ .dataa(\inst|vga_control_unit|b_next_0_sqmuxa_7_4 ),
+ .datab(\inst|vga_control_unit|b_next_0_sqmuxa_7_5 ),
+ .datac(\inst|vga_control_unit|toggle_sig ),
+ .datad(\inst|vga_driver_unit|v_enable_sig ),
+ .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .cin(gnd),
+ .cin0(gnd),
+ .cin1(vcc),
+ .inverta(gnd),
+ .regcascin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .combout(),
+ .regout(\inst|vga_control_unit|b ),
+ .cout(),
+ .cout0(),
+ .cout1());
+// synopsys translate_off
+defparam \inst|vga_control_unit|b_Z .lut_mask = "0800";
+defparam \inst|vga_control_unit|b_Z .operation_mode = "normal";
+defparam \inst|vga_control_unit|b_Z .output_mode = "reg_only";
+defparam \inst|vga_control_unit|b_Z .register_cascade_mode = "off";
+defparam \inst|vga_control_unit|b_Z .sum_lutc_input = "datac";
+defparam \inst|vga_control_unit|b_Z .synch_mode = "off";
+// synopsys translate_on
+
+// atom is at PIN_L7
+stratix_io \inst|d_hsync_out~I (
+ .datain(\inst|vga_driver_unit|h_sync ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_out~I .ddio_mode = "none";
+defparam \inst|d_hsync_out~I .input_async_reset = "none";
+defparam \inst|d_hsync_out~I .input_power_up = "low";
+defparam \inst|d_hsync_out~I .input_register_mode = "none";
+defparam \inst|d_hsync_out~I .input_sync_reset = "none";
+defparam \inst|d_hsync_out~I .oe_async_reset = "none";
+defparam \inst|d_hsync_out~I .oe_power_up = "low";
+defparam \inst|d_hsync_out~I .oe_register_mode = "none";
+defparam \inst|d_hsync_out~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_out~I .operation_mode = "output";
+defparam \inst|d_hsync_out~I .output_async_reset = "none";
+defparam \inst|d_hsync_out~I .output_power_up = "low";
+defparam \inst|d_hsync_out~I .output_register_mode = "none";
+defparam \inst|d_hsync_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L5
+stratix_io \inst|d_vsync_out~I (
+ .datain(\inst|vga_driver_unit|v_sync ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_out~I .ddio_mode = "none";
+defparam \inst|d_vsync_out~I .input_async_reset = "none";
+defparam \inst|d_vsync_out~I .input_power_up = "low";
+defparam \inst|d_vsync_out~I .input_register_mode = "none";
+defparam \inst|d_vsync_out~I .input_sync_reset = "none";
+defparam \inst|d_vsync_out~I .oe_async_reset = "none";
+defparam \inst|d_vsync_out~I .oe_power_up = "low";
+defparam \inst|d_vsync_out~I .oe_register_mode = "none";
+defparam \inst|d_vsync_out~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_out~I .operation_mode = "output";
+defparam \inst|d_vsync_out~I .output_async_reset = "none";
+defparam \inst|d_vsync_out~I .output_power_up = "low";
+defparam \inst|d_vsync_out~I .output_register_mode = "none";
+defparam \inst|d_vsync_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_Y23
+stratix_io \inst|d_set_column_counter_out~I (
+ .datain(\inst|vga_driver_unit|hsync_state_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_set_column_counter),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_set_column_counter_out~I .ddio_mode = "none";
+defparam \inst|d_set_column_counter_out~I .input_async_reset = "none";
+defparam \inst|d_set_column_counter_out~I .input_power_up = "low";
+defparam \inst|d_set_column_counter_out~I .input_register_mode = "none";
+defparam \inst|d_set_column_counter_out~I .input_sync_reset = "none";
+defparam \inst|d_set_column_counter_out~I .oe_async_reset = "none";
+defparam \inst|d_set_column_counter_out~I .oe_power_up = "low";
+defparam \inst|d_set_column_counter_out~I .oe_register_mode = "none";
+defparam \inst|d_set_column_counter_out~I .oe_sync_reset = "none";
+defparam \inst|d_set_column_counter_out~I .operation_mode = "output";
+defparam \inst|d_set_column_counter_out~I .output_async_reset = "none";
+defparam \inst|d_set_column_counter_out~I .output_power_up = "low";
+defparam \inst|d_set_column_counter_out~I .output_register_mode = "none";
+defparam \inst|d_set_column_counter_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F21
+stratix_io \inst|d_set_line_counter_out~I (
+ .datain(\inst|vga_driver_unit|vsync_state_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_set_line_counter),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_set_line_counter_out~I .ddio_mode = "none";
+defparam \inst|d_set_line_counter_out~I .input_async_reset = "none";
+defparam \inst|d_set_line_counter_out~I .input_power_up = "low";
+defparam \inst|d_set_line_counter_out~I .input_register_mode = "none";
+defparam \inst|d_set_line_counter_out~I .input_sync_reset = "none";
+defparam \inst|d_set_line_counter_out~I .oe_async_reset = "none";
+defparam \inst|d_set_line_counter_out~I .oe_power_up = "low";
+defparam \inst|d_set_line_counter_out~I .oe_register_mode = "none";
+defparam \inst|d_set_line_counter_out~I .oe_sync_reset = "none";
+defparam \inst|d_set_line_counter_out~I .operation_mode = "output";
+defparam \inst|d_set_line_counter_out~I .output_async_reset = "none";
+defparam \inst|d_set_line_counter_out~I .output_power_up = "low";
+defparam \inst|d_set_line_counter_out~I .output_register_mode = "none";
+defparam \inst|d_set_line_counter_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F26
+stratix_io \inst|d_set_hsync_counter_out~I (
+ .datain(\inst|vga_driver_unit|d_set_hsync_counter ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_set_hsync_counter),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_set_hsync_counter_out~I .ddio_mode = "none";
+defparam \inst|d_set_hsync_counter_out~I .input_async_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .input_power_up = "low";
+defparam \inst|d_set_hsync_counter_out~I .input_register_mode = "none";
+defparam \inst|d_set_hsync_counter_out~I .input_sync_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .oe_async_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .oe_power_up = "low";
+defparam \inst|d_set_hsync_counter_out~I .oe_register_mode = "none";
+defparam \inst|d_set_hsync_counter_out~I .oe_sync_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .operation_mode = "output";
+defparam \inst|d_set_hsync_counter_out~I .output_async_reset = "none";
+defparam \inst|d_set_hsync_counter_out~I .output_power_up = "low";
+defparam \inst|d_set_hsync_counter_out~I .output_register_mode = "none";
+defparam \inst|d_set_hsync_counter_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F24
+stratix_io \inst|d_set_vsync_counter_out~I (
+ .datain(\inst|vga_driver_unit|d_set_vsync_counter ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_set_vsync_counter),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_set_vsync_counter_out~I .ddio_mode = "none";
+defparam \inst|d_set_vsync_counter_out~I .input_async_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .input_power_up = "low";
+defparam \inst|d_set_vsync_counter_out~I .input_register_mode = "none";
+defparam \inst|d_set_vsync_counter_out~I .input_sync_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .oe_async_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .oe_power_up = "low";
+defparam \inst|d_set_vsync_counter_out~I .oe_register_mode = "none";
+defparam \inst|d_set_vsync_counter_out~I .oe_sync_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .operation_mode = "output";
+defparam \inst|d_set_vsync_counter_out~I .output_async_reset = "none";
+defparam \inst|d_set_vsync_counter_out~I .output_power_up = "low";
+defparam \inst|d_set_vsync_counter_out~I .output_register_mode = "none";
+defparam \inst|d_set_vsync_counter_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L3
+stratix_io \inst|d_r_out~I (
+ .datain(\inst|vga_control_unit|r ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_r),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_r_out~I .ddio_mode = "none";
+defparam \inst|d_r_out~I .input_async_reset = "none";
+defparam \inst|d_r_out~I .input_power_up = "low";
+defparam \inst|d_r_out~I .input_register_mode = "none";
+defparam \inst|d_r_out~I .input_sync_reset = "none";
+defparam \inst|d_r_out~I .oe_async_reset = "none";
+defparam \inst|d_r_out~I .oe_power_up = "low";
+defparam \inst|d_r_out~I .oe_register_mode = "none";
+defparam \inst|d_r_out~I .oe_sync_reset = "none";
+defparam \inst|d_r_out~I .operation_mode = "output";
+defparam \inst|d_r_out~I .output_async_reset = "none";
+defparam \inst|d_r_out~I .output_power_up = "low";
+defparam \inst|d_r_out~I .output_register_mode = "none";
+defparam \inst|d_r_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K24
+stratix_io \inst|d_g_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_g),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_g_out~I .ddio_mode = "none";
+defparam \inst|d_g_out~I .input_async_reset = "none";
+defparam \inst|d_g_out~I .input_power_up = "low";
+defparam \inst|d_g_out~I .input_register_mode = "none";
+defparam \inst|d_g_out~I .input_sync_reset = "none";
+defparam \inst|d_g_out~I .oe_async_reset = "none";
+defparam \inst|d_g_out~I .oe_power_up = "low";
+defparam \inst|d_g_out~I .oe_register_mode = "none";
+defparam \inst|d_g_out~I .oe_sync_reset = "none";
+defparam \inst|d_g_out~I .operation_mode = "output";
+defparam \inst|d_g_out~I .output_async_reset = "none";
+defparam \inst|d_g_out~I .output_power_up = "low";
+defparam \inst|d_g_out~I .output_register_mode = "none";
+defparam \inst|d_g_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K20
+stratix_io \inst|d_b_out~I (
+ .datain(\inst|vga_control_unit|b ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_b),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_b_out~I .ddio_mode = "none";
+defparam \inst|d_b_out~I .input_async_reset = "none";
+defparam \inst|d_b_out~I .input_power_up = "low";
+defparam \inst|d_b_out~I .input_register_mode = "none";
+defparam \inst|d_b_out~I .input_sync_reset = "none";
+defparam \inst|d_b_out~I .oe_async_reset = "none";
+defparam \inst|d_b_out~I .oe_power_up = "low";
+defparam \inst|d_b_out~I .oe_register_mode = "none";
+defparam \inst|d_b_out~I .oe_sync_reset = "none";
+defparam \inst|d_b_out~I .operation_mode = "output";
+defparam \inst|d_b_out~I .output_async_reset = "none";
+defparam \inst|d_b_out~I .output_power_up = "low";
+defparam \inst|d_b_out~I .output_register_mode = "none";
+defparam \inst|d_b_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_J21
+stratix_io \inst|d_h_enable_out~I (
+ .datain(\inst|vga_driver_unit|h_enable_sig ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_h_enable),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_h_enable_out~I .ddio_mode = "none";
+defparam \inst|d_h_enable_out~I .input_async_reset = "none";
+defparam \inst|d_h_enable_out~I .input_power_up = "low";
+defparam \inst|d_h_enable_out~I .input_register_mode = "none";
+defparam \inst|d_h_enable_out~I .input_sync_reset = "none";
+defparam \inst|d_h_enable_out~I .oe_async_reset = "none";
+defparam \inst|d_h_enable_out~I .oe_power_up = "low";
+defparam \inst|d_h_enable_out~I .oe_register_mode = "none";
+defparam \inst|d_h_enable_out~I .oe_sync_reset = "none";
+defparam \inst|d_h_enable_out~I .operation_mode = "output";
+defparam \inst|d_h_enable_out~I .output_async_reset = "none";
+defparam \inst|d_h_enable_out~I .output_power_up = "low";
+defparam \inst|d_h_enable_out~I .output_register_mode = "none";
+defparam \inst|d_h_enable_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H18
+stratix_io \inst|d_v_enable_out~I (
+ .datain(\inst|vga_driver_unit|v_enable_sig ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_v_enable),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_v_enable_out~I .ddio_mode = "none";
+defparam \inst|d_v_enable_out~I .input_async_reset = "none";
+defparam \inst|d_v_enable_out~I .input_power_up = "low";
+defparam \inst|d_v_enable_out~I .input_register_mode = "none";
+defparam \inst|d_v_enable_out~I .input_sync_reset = "none";
+defparam \inst|d_v_enable_out~I .oe_async_reset = "none";
+defparam \inst|d_v_enable_out~I .oe_power_up = "low";
+defparam \inst|d_v_enable_out~I .oe_register_mode = "none";
+defparam \inst|d_v_enable_out~I .oe_sync_reset = "none";
+defparam \inst|d_v_enable_out~I .operation_mode = "output";
+defparam \inst|d_v_enable_out~I .output_async_reset = "none";
+defparam \inst|d_v_enable_out~I .output_power_up = "low";
+defparam \inst|d_v_enable_out~I .output_register_mode = "none";
+defparam \inst|d_v_enable_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K3
+stratix_io \inst|d_state_clk_out~I (
+ .datain(\inst1|altpll_component|_clk0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_state_clk),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_state_clk_out~I .ddio_mode = "none";
+defparam \inst|d_state_clk_out~I .input_async_reset = "none";
+defparam \inst|d_state_clk_out~I .input_power_up = "low";
+defparam \inst|d_state_clk_out~I .input_register_mode = "none";
+defparam \inst|d_state_clk_out~I .input_sync_reset = "none";
+defparam \inst|d_state_clk_out~I .oe_async_reset = "none";
+defparam \inst|d_state_clk_out~I .oe_power_up = "low";
+defparam \inst|d_state_clk_out~I .oe_register_mode = "none";
+defparam \inst|d_state_clk_out~I .oe_sync_reset = "none";
+defparam \inst|d_state_clk_out~I .operation_mode = "output";
+defparam \inst|d_state_clk_out~I .output_async_reset = "none";
+defparam \inst|d_state_clk_out~I .output_power_up = "low";
+defparam \inst|d_state_clk_out~I .output_register_mode = "none";
+defparam \inst|d_state_clk_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H3
+stratix_io \inst|d_toggle_out~I (
+ .datain(\inst|vga_control_unit|toggle_sig ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_out~I .ddio_mode = "none";
+defparam \inst|d_toggle_out~I .input_async_reset = "none";
+defparam \inst|d_toggle_out~I .input_power_up = "low";
+defparam \inst|d_toggle_out~I .input_register_mode = "none";
+defparam \inst|d_toggle_out~I .input_sync_reset = "none";
+defparam \inst|d_toggle_out~I .oe_async_reset = "none";
+defparam \inst|d_toggle_out~I .oe_power_up = "low";
+defparam \inst|d_toggle_out~I .oe_register_mode = "none";
+defparam \inst|d_toggle_out~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_out~I .operation_mode = "output";
+defparam \inst|d_toggle_out~I .output_async_reset = "none";
+defparam \inst|d_toggle_out~I .output_power_up = "low";
+defparam \inst|d_toggle_out~I .output_register_mode = "none";
+defparam \inst|d_toggle_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_E22
+stratix_io \inst|r0_pin_out~I (
+ .datain(\inst|vga_control_unit|r ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(r0_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|r0_pin_out~I .ddio_mode = "none";
+defparam \inst|r0_pin_out~I .input_async_reset = "none";
+defparam \inst|r0_pin_out~I .input_power_up = "low";
+defparam \inst|r0_pin_out~I .input_register_mode = "none";
+defparam \inst|r0_pin_out~I .input_sync_reset = "none";
+defparam \inst|r0_pin_out~I .oe_async_reset = "none";
+defparam \inst|r0_pin_out~I .oe_power_up = "low";
+defparam \inst|r0_pin_out~I .oe_register_mode = "none";
+defparam \inst|r0_pin_out~I .oe_sync_reset = "none";
+defparam \inst|r0_pin_out~I .operation_mode = "output";
+defparam \inst|r0_pin_out~I .output_async_reset = "none";
+defparam \inst|r0_pin_out~I .output_power_up = "low";
+defparam \inst|r0_pin_out~I .output_register_mode = "none";
+defparam \inst|r0_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T4
+stratix_io \inst|r1_pin_out~I (
+ .datain(\inst|vga_control_unit|r ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(r1_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|r1_pin_out~I .ddio_mode = "none";
+defparam \inst|r1_pin_out~I .input_async_reset = "none";
+defparam \inst|r1_pin_out~I .input_power_up = "low";
+defparam \inst|r1_pin_out~I .input_register_mode = "none";
+defparam \inst|r1_pin_out~I .input_sync_reset = "none";
+defparam \inst|r1_pin_out~I .oe_async_reset = "none";
+defparam \inst|r1_pin_out~I .oe_power_up = "low";
+defparam \inst|r1_pin_out~I .oe_register_mode = "none";
+defparam \inst|r1_pin_out~I .oe_sync_reset = "none";
+defparam \inst|r1_pin_out~I .operation_mode = "output";
+defparam \inst|r1_pin_out~I .output_async_reset = "none";
+defparam \inst|r1_pin_out~I .output_power_up = "low";
+defparam \inst|r1_pin_out~I .output_register_mode = "none";
+defparam \inst|r1_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T7
+stratix_io \inst|r2_pin_out~I (
+ .datain(\inst|vga_control_unit|r ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(r2_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|r2_pin_out~I .ddio_mode = "none";
+defparam \inst|r2_pin_out~I .input_async_reset = "none";
+defparam \inst|r2_pin_out~I .input_power_up = "low";
+defparam \inst|r2_pin_out~I .input_register_mode = "none";
+defparam \inst|r2_pin_out~I .input_sync_reset = "none";
+defparam \inst|r2_pin_out~I .oe_async_reset = "none";
+defparam \inst|r2_pin_out~I .oe_power_up = "low";
+defparam \inst|r2_pin_out~I .oe_register_mode = "none";
+defparam \inst|r2_pin_out~I .oe_sync_reset = "none";
+defparam \inst|r2_pin_out~I .operation_mode = "output";
+defparam \inst|r2_pin_out~I .output_async_reset = "none";
+defparam \inst|r2_pin_out~I .output_power_up = "low";
+defparam \inst|r2_pin_out~I .output_register_mode = "none";
+defparam \inst|r2_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_E23
+stratix_io \inst|g0_pin_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(g0_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|g0_pin_out~I .ddio_mode = "none";
+defparam \inst|g0_pin_out~I .input_async_reset = "none";
+defparam \inst|g0_pin_out~I .input_power_up = "low";
+defparam \inst|g0_pin_out~I .input_register_mode = "none";
+defparam \inst|g0_pin_out~I .input_sync_reset = "none";
+defparam \inst|g0_pin_out~I .oe_async_reset = "none";
+defparam \inst|g0_pin_out~I .oe_power_up = "low";
+defparam \inst|g0_pin_out~I .oe_register_mode = "none";
+defparam \inst|g0_pin_out~I .oe_sync_reset = "none";
+defparam \inst|g0_pin_out~I .operation_mode = "output";
+defparam \inst|g0_pin_out~I .output_async_reset = "none";
+defparam \inst|g0_pin_out~I .output_power_up = "low";
+defparam \inst|g0_pin_out~I .output_register_mode = "none";
+defparam \inst|g0_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T5
+stratix_io \inst|g1_pin_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(g1_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|g1_pin_out~I .ddio_mode = "none";
+defparam \inst|g1_pin_out~I .input_async_reset = "none";
+defparam \inst|g1_pin_out~I .input_power_up = "low";
+defparam \inst|g1_pin_out~I .input_register_mode = "none";
+defparam \inst|g1_pin_out~I .input_sync_reset = "none";
+defparam \inst|g1_pin_out~I .oe_async_reset = "none";
+defparam \inst|g1_pin_out~I .oe_power_up = "low";
+defparam \inst|g1_pin_out~I .oe_register_mode = "none";
+defparam \inst|g1_pin_out~I .oe_sync_reset = "none";
+defparam \inst|g1_pin_out~I .operation_mode = "output";
+defparam \inst|g1_pin_out~I .output_async_reset = "none";
+defparam \inst|g1_pin_out~I .output_power_up = "low";
+defparam \inst|g1_pin_out~I .output_register_mode = "none";
+defparam \inst|g1_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T24
+stratix_io \inst|g2_pin_out~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(g2_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|g2_pin_out~I .ddio_mode = "none";
+defparam \inst|g2_pin_out~I .input_async_reset = "none";
+defparam \inst|g2_pin_out~I .input_power_up = "low";
+defparam \inst|g2_pin_out~I .input_register_mode = "none";
+defparam \inst|g2_pin_out~I .input_sync_reset = "none";
+defparam \inst|g2_pin_out~I .oe_async_reset = "none";
+defparam \inst|g2_pin_out~I .oe_power_up = "low";
+defparam \inst|g2_pin_out~I .oe_register_mode = "none";
+defparam \inst|g2_pin_out~I .oe_sync_reset = "none";
+defparam \inst|g2_pin_out~I .operation_mode = "output";
+defparam \inst|g2_pin_out~I .output_async_reset = "none";
+defparam \inst|g2_pin_out~I .output_power_up = "low";
+defparam \inst|g2_pin_out~I .output_register_mode = "none";
+defparam \inst|g2_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_E24
+stratix_io \inst|b0_pin_out~I (
+ .datain(\inst|vga_control_unit|b ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(b0_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|b0_pin_out~I .ddio_mode = "none";
+defparam \inst|b0_pin_out~I .input_async_reset = "none";
+defparam \inst|b0_pin_out~I .input_power_up = "low";
+defparam \inst|b0_pin_out~I .input_register_mode = "none";
+defparam \inst|b0_pin_out~I .input_sync_reset = "none";
+defparam \inst|b0_pin_out~I .oe_async_reset = "none";
+defparam \inst|b0_pin_out~I .oe_power_up = "low";
+defparam \inst|b0_pin_out~I .oe_register_mode = "none";
+defparam \inst|b0_pin_out~I .oe_sync_reset = "none";
+defparam \inst|b0_pin_out~I .operation_mode = "output";
+defparam \inst|b0_pin_out~I .output_async_reset = "none";
+defparam \inst|b0_pin_out~I .output_power_up = "low";
+defparam \inst|b0_pin_out~I .output_register_mode = "none";
+defparam \inst|b0_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T6
+stratix_io \inst|b1_pin_out~I (
+ .datain(\inst|vga_control_unit|b ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(b1_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|b1_pin_out~I .ddio_mode = "none";
+defparam \inst|b1_pin_out~I .input_async_reset = "none";
+defparam \inst|b1_pin_out~I .input_power_up = "low";
+defparam \inst|b1_pin_out~I .input_register_mode = "none";
+defparam \inst|b1_pin_out~I .input_sync_reset = "none";
+defparam \inst|b1_pin_out~I .oe_async_reset = "none";
+defparam \inst|b1_pin_out~I .oe_power_up = "low";
+defparam \inst|b1_pin_out~I .oe_register_mode = "none";
+defparam \inst|b1_pin_out~I .oe_sync_reset = "none";
+defparam \inst|b1_pin_out~I .operation_mode = "output";
+defparam \inst|b1_pin_out~I .output_async_reset = "none";
+defparam \inst|b1_pin_out~I .output_power_up = "low";
+defparam \inst|b1_pin_out~I .output_register_mode = "none";
+defparam \inst|b1_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F1
+stratix_io \inst|hsync_pin_out~I (
+ .datain(\inst|vga_driver_unit|h_sync ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(hsync_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|hsync_pin_out~I .ddio_mode = "none";
+defparam \inst|hsync_pin_out~I .input_async_reset = "none";
+defparam \inst|hsync_pin_out~I .input_power_up = "low";
+defparam \inst|hsync_pin_out~I .input_register_mode = "none";
+defparam \inst|hsync_pin_out~I .input_sync_reset = "none";
+defparam \inst|hsync_pin_out~I .oe_async_reset = "none";
+defparam \inst|hsync_pin_out~I .oe_power_up = "low";
+defparam \inst|hsync_pin_out~I .oe_register_mode = "none";
+defparam \inst|hsync_pin_out~I .oe_sync_reset = "none";
+defparam \inst|hsync_pin_out~I .operation_mode = "output";
+defparam \inst|hsync_pin_out~I .output_async_reset = "none";
+defparam \inst|hsync_pin_out~I .output_power_up = "low";
+defparam \inst|hsync_pin_out~I .output_register_mode = "none";
+defparam \inst|hsync_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F2
+stratix_io \inst|vsync_pin_out~I (
+ .datain(\inst|vga_driver_unit|v_sync ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(vsync_pin),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|vsync_pin_out~I .ddio_mode = "none";
+defparam \inst|vsync_pin_out~I .input_async_reset = "none";
+defparam \inst|vsync_pin_out~I .input_power_up = "low";
+defparam \inst|vsync_pin_out~I .input_register_mode = "none";
+defparam \inst|vsync_pin_out~I .input_sync_reset = "none";
+defparam \inst|vsync_pin_out~I .oe_async_reset = "none";
+defparam \inst|vsync_pin_out~I .oe_power_up = "low";
+defparam \inst|vsync_pin_out~I .oe_register_mode = "none";
+defparam \inst|vsync_pin_out~I .oe_sync_reset = "none";
+defparam \inst|vsync_pin_out~I .operation_mode = "output";
+defparam \inst|vsync_pin_out~I .output_async_reset = "none";
+defparam \inst|vsync_pin_out~I .output_power_up = "low";
+defparam \inst|vsync_pin_out~I .output_register_mode = "none";
+defparam \inst|vsync_pin_out~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K5
+stratix_io \inst|d_column_counter_out_9_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_9 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_9_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_9_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_9_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_9_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_9_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_9_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_9_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_9_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_9_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K19
+stratix_io \inst|d_column_counter_out_8_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K23
+stratix_io \inst|d_column_counter_out_7_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L2
+stratix_io \inst|d_column_counter_out_6_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L4
+stratix_io \inst|d_column_counter_out_5_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L6
+stratix_io \inst|d_column_counter_out_4_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L20
+stratix_io \inst|d_column_counter_out_3_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L21
+stratix_io \inst|d_column_counter_out_2_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L22
+stratix_io \inst|d_column_counter_out_1_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L23
+stratix_io \inst|d_column_counter_out_0_~I (
+ .datain(\inst|vga_driver_unit|column_counter_sig_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_column_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_column_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_column_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_column_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_column_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_column_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_column_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_column_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_column_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_column_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_column_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G18
+stratix_io \inst|d_hsync_counter_out_9_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_9 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_9_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_9_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_9_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_9_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_9_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_9_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_9_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_9_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_9_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G22
+stratix_io \inst|d_hsync_counter_out_8_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G25
+stratix_io \inst|d_hsync_counter_out_7_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_C15
+stratix_io \inst|d_hsync_counter_out_6_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H2
+stratix_io \inst|d_hsync_counter_out_5_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H1
+stratix_io \inst|d_hsync_counter_out_4_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H25
+stratix_io \inst|d_hsync_counter_out_3_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_B16
+stratix_io \inst|d_hsync_counter_out_2_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AD15
+stratix_io \inst|d_hsync_counter_out_1_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H4
+stratix_io \inst|d_hsync_counter_out_0_~I (
+ .datain(\inst|vga_driver_unit|hsync_counter_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_hsync_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_hsync_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_hsync_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_hsync_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_hsync_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_hsync_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_hsync_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_hsync_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_Y5
+stratix_io \inst|d_hsync_state_out_0_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_0_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_0_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_0_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_0_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_0_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_0_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F19
+stratix_io \inst|d_hsync_state_out_1_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_1_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_1_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_1_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_1_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_1_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_1_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F17
+stratix_io \inst|d_hsync_state_out_2_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_2_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_2_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_2_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_2_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_2_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_2_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_Y2
+stratix_io \inst|d_hsync_state_out_3_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_3_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_3_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_3_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_3_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_3_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_3_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F10
+stratix_io \inst|d_hsync_state_out_4_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_4_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_4_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_4_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_4_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_4_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_4_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F9
+stratix_io \inst|d_hsync_state_out_5_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_5_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_5_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_5_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_5_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_5_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_5_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F6
+stratix_io \inst|d_hsync_state_out_6_~I (
+ .datain(\inst|vga_driver_unit|hsync_state_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_hsync_state[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_hsync_state_out_6_~I .ddio_mode = "none";
+defparam \inst|d_hsync_state_out_6_~I .input_async_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .input_power_up = "low";
+defparam \inst|d_hsync_state_out_6_~I .input_register_mode = "none";
+defparam \inst|d_hsync_state_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .oe_power_up = "low";
+defparam \inst|d_hsync_state_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_hsync_state_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .operation_mode = "output";
+defparam \inst|d_hsync_state_out_6_~I .output_async_reset = "none";
+defparam \inst|d_hsync_state_out_6_~I .output_power_up = "low";
+defparam \inst|d_hsync_state_out_6_~I .output_register_mode = "none";
+defparam \inst|d_hsync_state_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L25
+stratix_io \inst|d_line_counter_out_8_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_L24
+stratix_io \inst|d_line_counter_out_7_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M5
+stratix_io \inst|d_line_counter_out_6_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M6
+stratix_io \inst|d_line_counter_out_5_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M8
+stratix_io \inst|d_line_counter_out_4_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M9
+stratix_io \inst|d_line_counter_out_3_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_J22
+stratix_io \inst|d_line_counter_out_2_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K4
+stratix_io \inst|d_line_counter_out_1_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_K6
+stratix_io \inst|d_line_counter_out_0_~I (
+ .datain(\inst|vga_driver_unit|line_counter_sig_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_line_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_line_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_line_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_line_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_line_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_line_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_line_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_line_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_line_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_line_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_line_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T19
+stratix_io \inst|d_toggle_counter_out_24_~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[24]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_24_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_24_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_24_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_24_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_24_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_24_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_24_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_24_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_24_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_24_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F23
+stratix_io \inst|d_toggle_counter_out_23_~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[23]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_23_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_23_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_23_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_23_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_23_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_23_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_23_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_23_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_23_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_23_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F25
+stratix_io \inst|d_toggle_counter_out_22_~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[22]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_22_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_22_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_22_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_22_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_22_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_22_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_22_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_22_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_22_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_22_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G1
+stratix_io \inst|d_toggle_counter_out_21_~I (
+ .datain(\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[21]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_21_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_21_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_21_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_21_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_21_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_21_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_21_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_21_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_21_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_21_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G3
+stratix_io \inst|d_toggle_counter_out_20_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_20 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[20]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_20_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_20_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_20_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_20_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_20_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_20_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_20_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_20_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_20_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_20_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G5
+stratix_io \inst|d_toggle_counter_out_19_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_19 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[19]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_19_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_19_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_19_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_19_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_19_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_19_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_19_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_19_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_19_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_19_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G20
+stratix_io \inst|d_toggle_counter_out_18_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_18 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[18]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_18_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_18_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_18_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_18_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_18_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_18_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_18_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_18_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_18_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_18_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G21
+stratix_io \inst|d_toggle_counter_out_17_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_17 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[17]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_17_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_17_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_17_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_17_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_17_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_17_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_17_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_17_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_17_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_17_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G23
+stratix_io \inst|d_toggle_counter_out_16_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_16 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[16]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_16_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_16_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_16_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_16_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_16_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_16_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_16_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_16_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_16_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_16_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G24
+stratix_io \inst|d_toggle_counter_out_15_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_15 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[15]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_15_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_15_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_15_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_15_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_15_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_15_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_15_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_15_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_15_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_15_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AB21
+stratix_io \inst|d_toggle_counter_out_14_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_14 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[14]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_14_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_14_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_14_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_14_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_14_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_14_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_14_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_14_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_14_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_14_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_C20
+stratix_io \inst|d_toggle_counter_out_13_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_13 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[13]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_13_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_13_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_13_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_13_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_13_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_13_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_13_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_13_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_13_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_13_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AA21
+stratix_io \inst|d_toggle_counter_out_12_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_12 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[12]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_12_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_12_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_12_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_12_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_12_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_12_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_12_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_12_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_12_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_12_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AA26
+stratix_io \inst|d_toggle_counter_out_11_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_11 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[11]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_11_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_11_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_11_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_11_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_11_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_11_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_11_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_11_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_11_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_11_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_W24
+stratix_io \inst|d_toggle_counter_out_10_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_10 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[10]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_10_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_10_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_10_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_10_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_10_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_10_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_10_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_10_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_10_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_10_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AF22
+stratix_io \inst|d_toggle_counter_out_9_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_9 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_9_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_9_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_9_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_9_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_9_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_9_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_9_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_9_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_9_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_W22
+stratix_io \inst|d_toggle_counter_out_8_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AE22
+stratix_io \inst|d_toggle_counter_out_7_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_B3
+stratix_io \inst|d_toggle_counter_out_6_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AC21
+stratix_io \inst|d_toggle_counter_out_5_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AF24
+stratix_io \inst|d_toggle_counter_out_4_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_A24
+stratix_io \inst|d_toggle_counter_out_3_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_B23
+stratix_io \inst|d_toggle_counter_out_2_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_W21
+stratix_io \inst|d_toggle_counter_out_1_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_H26
+stratix_io \inst|d_toggle_counter_out_0_~I (
+ .datain(\inst|vga_control_unit|toggle_counter_sig_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_toggle_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_toggle_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_toggle_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_toggle_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_toggle_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_toggle_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_toggle_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_toggle_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_toggle_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_toggle_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_toggle_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G2
+stratix_io \inst|d_vsync_counter_out_9_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_9 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_9_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_9_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_9_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_9_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_9_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_9_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_9_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_9_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_9_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G4
+stratix_io \inst|d_vsync_counter_out_8_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_8 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_8_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_8_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_8_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_8_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_8_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_8_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_8_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_8_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_8_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G6
+stratix_io \inst|d_vsync_counter_out_7_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_7 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_7_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_7_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_7_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_7_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_7_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_7_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_7_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_7_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_7_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_J4
+stratix_io \inst|d_vsync_counter_out_6_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_6_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_6_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_6_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_6_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_6_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_6_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G11
+stratix_io \inst|d_vsync_counter_out_5_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_5_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_5_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_5_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_5_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_5_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_5_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AD11
+stratix_io \inst|d_vsync_counter_out_4_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_4_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_4_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_4_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_4_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_4_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_4_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_J1
+stratix_io \inst|d_vsync_counter_out_3_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_3_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_3_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_3_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_3_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_3_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_3_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_B11
+stratix_io \inst|d_vsync_counter_out_2_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_2_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_2_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_2_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_2_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_2_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_2_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_J23
+stratix_io \inst|d_vsync_counter_out_1_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_1_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_1_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_1_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_1_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_1_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_1_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_G9
+stratix_io \inst|d_vsync_counter_out_0_~I (
+ .datain(\inst|vga_driver_unit|vsync_counter_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_counter[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_counter_out_0_~I .ddio_mode = "none";
+defparam \inst|d_vsync_counter_out_0_~I .input_async_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .input_power_up = "low";
+defparam \inst|d_vsync_counter_out_0_~I .input_register_mode = "none";
+defparam \inst|d_vsync_counter_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .oe_power_up = "low";
+defparam \inst|d_vsync_counter_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_counter_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .operation_mode = "output";
+defparam \inst|d_vsync_counter_out_0_~I .output_async_reset = "none";
+defparam \inst|d_vsync_counter_out_0_~I .output_power_up = "low";
+defparam \inst|d_vsync_counter_out_0_~I .output_register_mode = "none";
+defparam \inst|d_vsync_counter_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F5
+stratix_io \inst|d_vsync_state_out_0_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_0 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_0_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_0_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_0_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_0_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_0_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_0_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_0_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_0_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_0_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F4
+stratix_io \inst|d_vsync_state_out_1_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_1 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_1_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_1_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_1_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_1_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_1_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_1_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_1_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_1_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_1_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_F3
+stratix_io \inst|d_vsync_state_out_2_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_2 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_2_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_2_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_2_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_2_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_2_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_2_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_2_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_2_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_2_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M19
+stratix_io \inst|d_vsync_state_out_3_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_3 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_3_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_3_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_3_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_3_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_3_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_3_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_3_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_3_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_3_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M18
+stratix_io \inst|d_vsync_state_out_4_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_4 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_4_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_4_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_4_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_4_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_4_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_4_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_4_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_4_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_4_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M7
+stratix_io \inst|d_vsync_state_out_5_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_5 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_5_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_5_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_5_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_5_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_5_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_5_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_5_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_5_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_5_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_M4
+stratix_io \inst|d_vsync_state_out_6_~I (
+ .datain(\inst|vga_driver_unit|vsync_state_6 ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(d_vsync_state[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|d_vsync_state_out_6_~I .ddio_mode = "none";
+defparam \inst|d_vsync_state_out_6_~I .input_async_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .input_power_up = "low";
+defparam \inst|d_vsync_state_out_6_~I .input_register_mode = "none";
+defparam \inst|d_vsync_state_out_6_~I .input_sync_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .oe_async_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .oe_power_up = "low";
+defparam \inst|d_vsync_state_out_6_~I .oe_register_mode = "none";
+defparam \inst|d_vsync_state_out_6_~I .oe_sync_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .operation_mode = "output";
+defparam \inst|d_vsync_state_out_6_~I .output_async_reset = "none";
+defparam \inst|d_vsync_state_out_6_~I .output_power_up = "low";
+defparam \inst|d_vsync_state_out_6_~I .output_register_mode = "none";
+defparam \inst|d_vsync_state_out_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_T2
+stratix_io \inst|seven_seg_pin_tri_13_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[13]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_13_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_13_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_13_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_13_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_13_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_13_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_AA11
+stratix_io \inst|seven_seg_pin_out_12_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[12]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_12_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_12_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_12_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_12_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_12_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_12_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_12_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_12_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_12_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_12_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R6
+stratix_io \inst|seven_seg_pin_out_11_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[11]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_11_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_11_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_11_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_11_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_11_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_11_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_11_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_11_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_11_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_11_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R4
+stratix_io \inst|seven_seg_pin_out_10_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[10]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_10_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_10_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_10_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_10_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_10_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_10_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_10_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_10_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_10_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_10_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_N8
+stratix_io \inst|seven_seg_pin_out_9_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[9]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_9_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_9_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_9_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_9_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_9_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_9_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_9_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_9_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_9_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_9_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_N7
+stratix_io \inst|seven_seg_pin_out_8_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[8]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_8_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_8_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_8_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_8_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_8_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_8_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_8_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_8_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_8_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_8_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_Y11
+stratix_io \inst|seven_seg_pin_out_7_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[7]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_7_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_7_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_7_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_7_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_7_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_7_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_7_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_7_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_7_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_7_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R23
+stratix_io \inst|seven_seg_pin_tri_6_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[6]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_6_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_6_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_6_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_6_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_6_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_6_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R22
+stratix_io \inst|seven_seg_pin_tri_5_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[5]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_5_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_5_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_5_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_5_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_5_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_5_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R21
+stratix_io \inst|seven_seg_pin_tri_4_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[4]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_4_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_4_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_4_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_4_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_4_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_4_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R20
+stratix_io \inst|seven_seg_pin_tri_3_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[3]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_3_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_3_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_3_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_3_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_3_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_3_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R19
+stratix_io \inst|seven_seg_pin_out_2_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[2]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_2_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_2_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_2_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_2_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_2_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_2_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_2_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_2_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_2_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_2_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R9
+stratix_io \inst|seven_seg_pin_out_1_~I (
+ .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[1]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_out_1_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_out_1_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_out_1_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_out_1_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_out_1_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_out_1_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_out_1_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_out_1_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_out_1_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_out_1_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+// atom is at PIN_R8
+stratix_io \inst|seven_seg_pin_tri_0_~I (
+ .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ),
+ .ddiodatain(gnd),
+ .oe(vcc),
+ .outclk(gnd),
+ .outclkena(vcc),
+ .inclk(gnd),
+ .inclkena(vcc),
+ .areset(gnd),
+ .sreset(gnd),
+ .delayctrlin(gnd),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .devoe(devoe),
+ .combout(),
+ .regout(),
+ .ddioregout(),
+ .padio(seven_seg_pin[0]),
+ .dqsundelayedout());
+// synopsys translate_off
+defparam \inst|seven_seg_pin_tri_0_~I .ddio_mode = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .input_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .input_power_up = "low";
+defparam \inst|seven_seg_pin_tri_0_~I .input_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .input_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .oe_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .oe_power_up = "low";
+defparam \inst|seven_seg_pin_tri_0_~I .oe_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .oe_sync_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .operation_mode = "output";
+defparam \inst|seven_seg_pin_tri_0_~I .output_async_reset = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .output_power_up = "low";
+defparam \inst|seven_seg_pin_tri_0_~I .output_register_mode = "none";
+defparam \inst|seven_seg_pin_tri_0_~I .output_sync_reset = "none";
+// synopsys translate_on
+
+endmodule
--- /dev/null
+vendor_name = ModelSim
+source_file = 1, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf
+source_file = 1, /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm
+source_file = 1, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.bsf
+source_file = 1, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd
+source_file = 1, /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/db/vga_pll.cbx.xml
+source_file = 1, /opt/quartus/quartus/libraries/megafunctions/altpll.tdf
+source_file = 1, /opt/quartus/quartus/libraries/megafunctions/aglobal90.inc
+source_file = 1, /opt/quartus/quartus/libraries/megafunctions/stratix_pll.inc
+source_file = 1, /opt/quartus/quartus/libraries/megafunctions/stratixii_pll.inc
+source_file = 1, /opt/quartus/quartus/libraries/megafunctions/cycloneii_pll.inc
+source_file = 1, /opt/quartus/quartus/libraries/megafunctions/cbx.lst
+design_name = vga_pll
+instance = comp, \board_clk~I , board_clk, vga_pll, 1
+instance = comp, \inst1|altpll_component|pll , inst1|altpll_component|pll, vga_pll, 1
+instance = comp, \inst|reset_pin_in~I , inst|reset_pin_in, vga_pll, 1
+instance = comp, \inst|dly_counter_0_ , inst|dly_counter_0_, vga_pll, 1
+instance = comp, \inst|dly_counter_1_ , inst|dly_counter_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_6_ , inst|vga_driver_unit|vsync_state_6_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_6_ , inst|vga_driver_unit|hsync_state_6_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_0_ , inst|vga_driver_unit|hsync_counter_0_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_1_ , inst|vga_driver_unit|hsync_counter_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_2_ , inst|vga_driver_unit|hsync_counter_2_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_3_ , inst|vga_driver_unit|hsync_counter_3_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_4_ , inst|vga_driver_unit|hsync_counter_4_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_5_ , inst|vga_driver_unit|hsync_counter_5_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_6_ , inst|vga_driver_unit|hsync_counter_6_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_7_ , inst|vga_driver_unit|hsync_counter_7_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_8_ , inst|vga_driver_unit|hsync_counter_8_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_9_ , inst|vga_driver_unit|hsync_counter_9_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 , inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 , inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 , inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|G_2 , inst|vga_driver_unit|G_2, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 , inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 , inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter , inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 , inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 , inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 , inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 , inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_5_ , inst|vga_driver_unit|hsync_state_5_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ , inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 , inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter , inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_3_ , inst|vga_driver_unit|hsync_state_3_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ , inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ , inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_1_ , inst|vga_driver_unit|hsync_state_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_2_ , inst|vga_driver_unit|hsync_state_2_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_0_ , inst|vga_driver_unit|hsync_state_0_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ , inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 , inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|hsync_state_4_ , inst|vga_driver_unit|hsync_state_4_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_hsync_state_3_0_cZ , inst|vga_driver_unit|un1_hsync_state_3_0_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ , inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|h_sync_Z , inst|vga_driver_unit|h_sync_Z, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_0_ , inst|vga_driver_unit|vsync_counter_0_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_1_ , inst|vga_driver_unit|vsync_counter_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_2_ , inst|vga_driver_unit|vsync_counter_2_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_3_ , inst|vga_driver_unit|vsync_counter_3_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_4_ , inst|vga_driver_unit|vsync_counter_4_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_5_ , inst|vga_driver_unit|vsync_counter_5_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 , inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_6_ , inst|vga_driver_unit|vsync_counter_6_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_7_ , inst|vga_driver_unit|vsync_counter_7_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_8_ , inst|vga_driver_unit|vsync_counter_8_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_9_ , inst|vga_driver_unit|vsync_counter_9_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 , inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 , inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|G_16 , inst|vga_driver_unit|G_16, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 , inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 , inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 , inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 , inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 , inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_1_ , inst|vga_driver_unit|vsync_state_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_5_ , inst|vga_driver_unit|vsync_state_5_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ , inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_3_ , inst|vga_driver_unit|vsync_state_3_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ , inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ , inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ , inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_2_ , inst|vga_driver_unit|vsync_state_2_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ , inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_0_ , inst|vga_driver_unit|vsync_state_0_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|d_set_vsync_counter_cZ , inst|vga_driver_unit|d_set_vsync_counter_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ , inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 , inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 , inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|vsync_state_4_ , inst|vga_driver_unit|vsync_state_4_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_vsync_state_2_0_cZ , inst|vga_driver_unit|un1_vsync_state_2_0_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ , inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|v_sync_Z , inst|vga_driver_unit|v_sync_Z, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ , inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_0_ , inst|vga_driver_unit|column_counter_sig_0_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_1_ , inst|vga_driver_unit|un2_column_counter_next_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_1_ , inst|vga_driver_unit|column_counter_sig_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_3_ , inst|vga_driver_unit|un2_column_counter_next_3_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_3_ , inst|vga_driver_unit|column_counter_sig_3_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_0_ , inst|vga_driver_unit|un2_column_counter_next_0_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_2_ , inst|vga_driver_unit|un2_column_counter_next_2_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_2_ , inst|vga_driver_unit|column_counter_sig_2_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_4_ , inst|vga_driver_unit|un2_column_counter_next_4_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_4_ , inst|vga_driver_unit|column_counter_sig_4_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_5_ , inst|vga_driver_unit|un2_column_counter_next_5_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_5_ , inst|vga_driver_unit|column_counter_sig_5_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_6_ , inst|vga_driver_unit|un2_column_counter_next_6_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_8_ , inst|vga_driver_unit|un2_column_counter_next_8_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_8_ , inst|vga_driver_unit|column_counter_sig_8_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 , inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 , inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_7_ , inst|vga_driver_unit|un2_column_counter_next_7_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un2_column_counter_next_9_ , inst|vga_driver_unit|un2_column_counter_next_9_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_9_ , inst|vga_driver_unit|column_counter_sig_9_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 , inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_7_ , inst|vga_driver_unit|column_counter_sig_7_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|column_counter_sig_6_ , inst|vga_driver_unit|column_counter_sig_6_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 , inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2, vga_pll, 1
+instance = comp, \inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 , inst|vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5, vga_pll, 1
+instance = comp, \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 , inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4, vga_pll, 1
+instance = comp, \inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 , inst|vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_1_ , inst|vga_driver_unit|un1_line_counter_sig_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ , inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_sig_0_ , inst|vga_driver_unit|line_counter_sig_0_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_3_ , inst|vga_driver_unit|un1_line_counter_sig_3_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_sig_2_ , inst|vga_driver_unit|line_counter_sig_2_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_a_1_ , inst|vga_driver_unit|un1_line_counter_sig_a_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_2_ , inst|vga_driver_unit|un1_line_counter_sig_2_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_sig_1_ , inst|vga_driver_unit|line_counter_sig_1_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_5_ , inst|vga_driver_unit|un1_line_counter_sig_5_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_sig_4_ , inst|vga_driver_unit|line_counter_sig_4_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_4_ , inst|vga_driver_unit|un1_line_counter_sig_4_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_sig_3_ , inst|vga_driver_unit|line_counter_sig_3_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_7_ , inst|vga_driver_unit|un1_line_counter_sig_7_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_sig_6_ , inst|vga_driver_unit|line_counter_sig_6_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_6_ , inst|vga_driver_unit|un1_line_counter_sig_6_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_sig_5_ , inst|vga_driver_unit|line_counter_sig_5_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_8_ , inst|vga_driver_unit|un1_line_counter_sig_8_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_sig_7_ , inst|vga_driver_unit|line_counter_sig_7_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 , inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 , inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 , inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|un1_line_counter_sig_9_ , inst|vga_driver_unit|un1_line_counter_sig_9_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|line_counter_sig_8_ , inst|vga_driver_unit|line_counter_sig_8_, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ , inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|h_enable_sig_Z , inst|vga_driver_unit|h_enable_sig_Z, vga_pll, 1
+instance = comp, \inst|vga_control_unit|b_next_0_sqmuxa_7_2_cZ , inst|vga_control_unit|b_next_0_sqmuxa_7_2_cZ, vga_pll, 1
+instance = comp, \inst|vga_control_unit|b_next_0_sqmuxa_7_3_cZ , inst|vga_control_unit|b_next_0_sqmuxa_7_3_cZ, vga_pll, 1
+instance = comp, \inst|vga_control_unit|b_next_0_sqmuxa_7_5_cZ , inst|vga_control_unit|b_next_0_sqmuxa_7_5_cZ, vga_pll, 1
+instance = comp, \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 , inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0, vga_pll, 1
+instance = comp, \inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 , inst|vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6, vga_pll, 1
+instance = comp, \inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 , inst|vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3, vga_pll, 1
+instance = comp, \inst|vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ , inst|vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ, vga_pll, 1
+instance = comp, \inst|vga_control_unit|b_next_0_sqmuxa_7_4_cZ , inst|vga_control_unit|b_next_0_sqmuxa_7_4_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ , inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ, vga_pll, 1
+instance = comp, \inst|vga_driver_unit|v_enable_sig_Z , inst|vga_driver_unit|v_enable_sig_Z, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_0_ , inst|vga_control_unit|toggle_counter_sig_0_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_1_ , inst|vga_control_unit|toggle_counter_sig_1_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_3_ , inst|vga_control_unit|toggle_counter_sig_3_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|un2_toggle_counter_next_0_ , inst|vga_control_unit|un2_toggle_counter_next_0_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_2_ , inst|vga_control_unit|toggle_counter_sig_2_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_5_ , inst|vga_control_unit|toggle_counter_sig_5_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_4_ , inst|vga_control_unit|toggle_counter_sig_4_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_6_ , inst|vga_control_unit|toggle_counter_sig_6_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_7_ , inst|vga_control_unit|toggle_counter_sig_7_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_8_ , inst|vga_control_unit|toggle_counter_sig_8_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_9_ , inst|vga_control_unit|toggle_counter_sig_9_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_11_ , inst|vga_control_unit|toggle_counter_sig_11_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_10_ , inst|vga_control_unit|toggle_counter_sig_10_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_13_ , inst|vga_control_unit|toggle_counter_sig_13_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_12_ , inst|vga_control_unit|toggle_counter_sig_12_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_15_ , inst|vga_control_unit|toggle_counter_sig_15_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_14_ , inst|vga_control_unit|toggle_counter_sig_14_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 , inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6, vga_pll, 1
+instance = comp, \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 , inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9, vga_pll, 1
+instance = comp, \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 , inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12, vga_pll, 1
+instance = comp, \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 , inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_16_ , inst|vga_control_unit|toggle_counter_sig_16_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_17_ , inst|vga_control_unit|toggle_counter_sig_17_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_19_ , inst|vga_control_unit|toggle_counter_sig_19_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_18_ , inst|vga_control_unit|toggle_counter_sig_18_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 , inst|vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_counter_sig_20_ , inst|vga_control_unit|toggle_counter_sig_20_, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ , inst|vga_control_unit|toggle_sig_0_0_0_g1_cZ, vga_pll, 1
+instance = comp, \inst|vga_control_unit|toggle_sig_Z , inst|vga_control_unit|toggle_sig_Z, vga_pll, 1
+instance = comp, \inst|vga_control_unit|r_Z , inst|vga_control_unit|r_Z, vga_pll, 1
+instance = comp, \~STRATIX_FITTER_CREATED_GND~I , ~STRATIX_FITTER_CREATED_GND~I, vga_pll, 1
+instance = comp, \inst|vga_control_unit|b_Z , inst|vga_control_unit|b_Z, vga_pll, 1
+instance = comp, \inst|d_hsync_out~I , inst|d_hsync_out, vga_pll, 1
+instance = comp, \inst|d_vsync_out~I , inst|d_vsync_out, vga_pll, 1
+instance = comp, \inst|d_set_column_counter_out~I , inst|d_set_column_counter_out, vga_pll, 1
+instance = comp, \inst|d_set_line_counter_out~I , inst|d_set_line_counter_out, vga_pll, 1
+instance = comp, \inst|d_set_hsync_counter_out~I , inst|d_set_hsync_counter_out, vga_pll, 1
+instance = comp, \inst|d_set_vsync_counter_out~I , inst|d_set_vsync_counter_out, vga_pll, 1
+instance = comp, \inst|d_r_out~I , inst|d_r_out, vga_pll, 1
+instance = comp, \inst|d_g_out~I , inst|d_g_out, vga_pll, 1
+instance = comp, \inst|d_b_out~I , inst|d_b_out, vga_pll, 1
+instance = comp, \inst|d_h_enable_out~I , inst|d_h_enable_out, vga_pll, 1
+instance = comp, \inst|d_v_enable_out~I , inst|d_v_enable_out, vga_pll, 1
+instance = comp, \inst|d_state_clk_out~I , inst|d_state_clk_out, vga_pll, 1
+instance = comp, \inst|d_toggle_out~I , inst|d_toggle_out, vga_pll, 1
+instance = comp, \inst|r0_pin_out~I , inst|r0_pin_out, vga_pll, 1
+instance = comp, \inst|r1_pin_out~I , inst|r1_pin_out, vga_pll, 1
+instance = comp, \inst|r2_pin_out~I , inst|r2_pin_out, vga_pll, 1
+instance = comp, \inst|g0_pin_out~I , inst|g0_pin_out, vga_pll, 1
+instance = comp, \inst|g1_pin_out~I , inst|g1_pin_out, vga_pll, 1
+instance = comp, \inst|g2_pin_out~I , inst|g2_pin_out, vga_pll, 1
+instance = comp, \inst|b0_pin_out~I , inst|b0_pin_out, vga_pll, 1
+instance = comp, \inst|b1_pin_out~I , inst|b1_pin_out, vga_pll, 1
+instance = comp, \inst|hsync_pin_out~I , inst|hsync_pin_out, vga_pll, 1
+instance = comp, \inst|vsync_pin_out~I , inst|vsync_pin_out, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_9_~I , inst|d_column_counter_out_9_, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_8_~I , inst|d_column_counter_out_8_, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_7_~I , inst|d_column_counter_out_7_, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_6_~I , inst|d_column_counter_out_6_, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_5_~I , inst|d_column_counter_out_5_, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_4_~I , inst|d_column_counter_out_4_, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_3_~I , inst|d_column_counter_out_3_, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_2_~I , inst|d_column_counter_out_2_, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_1_~I , inst|d_column_counter_out_1_, vga_pll, 1
+instance = comp, \inst|d_column_counter_out_0_~I , inst|d_column_counter_out_0_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_9_~I , inst|d_hsync_counter_out_9_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_8_~I , inst|d_hsync_counter_out_8_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_7_~I , inst|d_hsync_counter_out_7_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_6_~I , inst|d_hsync_counter_out_6_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_5_~I , inst|d_hsync_counter_out_5_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_4_~I , inst|d_hsync_counter_out_4_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_3_~I , inst|d_hsync_counter_out_3_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_2_~I , inst|d_hsync_counter_out_2_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_1_~I , inst|d_hsync_counter_out_1_, vga_pll, 1
+instance = comp, \inst|d_hsync_counter_out_0_~I , inst|d_hsync_counter_out_0_, vga_pll, 1
+instance = comp, \inst|d_hsync_state_out_0_~I , inst|d_hsync_state_out_0_, vga_pll, 1
+instance = comp, \inst|d_hsync_state_out_1_~I , inst|d_hsync_state_out_1_, vga_pll, 1
+instance = comp, \inst|d_hsync_state_out_2_~I , inst|d_hsync_state_out_2_, vga_pll, 1
+instance = comp, \inst|d_hsync_state_out_3_~I , inst|d_hsync_state_out_3_, vga_pll, 1
+instance = comp, \inst|d_hsync_state_out_4_~I , inst|d_hsync_state_out_4_, vga_pll, 1
+instance = comp, \inst|d_hsync_state_out_5_~I , inst|d_hsync_state_out_5_, vga_pll, 1
+instance = comp, \inst|d_hsync_state_out_6_~I , inst|d_hsync_state_out_6_, vga_pll, 1
+instance = comp, \inst|d_line_counter_out_8_~I , inst|d_line_counter_out_8_, vga_pll, 1
+instance = comp, \inst|d_line_counter_out_7_~I , inst|d_line_counter_out_7_, vga_pll, 1
+instance = comp, \inst|d_line_counter_out_6_~I , inst|d_line_counter_out_6_, vga_pll, 1
+instance = comp, \inst|d_line_counter_out_5_~I , inst|d_line_counter_out_5_, vga_pll, 1
+instance = comp, \inst|d_line_counter_out_4_~I , inst|d_line_counter_out_4_, vga_pll, 1
+instance = comp, \inst|d_line_counter_out_3_~I , inst|d_line_counter_out_3_, vga_pll, 1
+instance = comp, \inst|d_line_counter_out_2_~I , inst|d_line_counter_out_2_, vga_pll, 1
+instance = comp, \inst|d_line_counter_out_1_~I , inst|d_line_counter_out_1_, vga_pll, 1
+instance = comp, \inst|d_line_counter_out_0_~I , inst|d_line_counter_out_0_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_24_~I , inst|d_toggle_counter_out_24_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_23_~I , inst|d_toggle_counter_out_23_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_22_~I , inst|d_toggle_counter_out_22_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_21_~I , inst|d_toggle_counter_out_21_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_20_~I , inst|d_toggle_counter_out_20_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_19_~I , inst|d_toggle_counter_out_19_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_18_~I , inst|d_toggle_counter_out_18_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_17_~I , inst|d_toggle_counter_out_17_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_16_~I , inst|d_toggle_counter_out_16_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_15_~I , inst|d_toggle_counter_out_15_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_14_~I , inst|d_toggle_counter_out_14_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_13_~I , inst|d_toggle_counter_out_13_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_12_~I , inst|d_toggle_counter_out_12_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_11_~I , inst|d_toggle_counter_out_11_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_10_~I , inst|d_toggle_counter_out_10_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_9_~I , inst|d_toggle_counter_out_9_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_8_~I , inst|d_toggle_counter_out_8_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_7_~I , inst|d_toggle_counter_out_7_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_6_~I , inst|d_toggle_counter_out_6_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_5_~I , inst|d_toggle_counter_out_5_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_4_~I , inst|d_toggle_counter_out_4_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_3_~I , inst|d_toggle_counter_out_3_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_2_~I , inst|d_toggle_counter_out_2_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_1_~I , inst|d_toggle_counter_out_1_, vga_pll, 1
+instance = comp, \inst|d_toggle_counter_out_0_~I , inst|d_toggle_counter_out_0_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_9_~I , inst|d_vsync_counter_out_9_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_8_~I , inst|d_vsync_counter_out_8_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_7_~I , inst|d_vsync_counter_out_7_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_6_~I , inst|d_vsync_counter_out_6_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_5_~I , inst|d_vsync_counter_out_5_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_4_~I , inst|d_vsync_counter_out_4_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_3_~I , inst|d_vsync_counter_out_3_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_2_~I , inst|d_vsync_counter_out_2_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_1_~I , inst|d_vsync_counter_out_1_, vga_pll, 1
+instance = comp, \inst|d_vsync_counter_out_0_~I , inst|d_vsync_counter_out_0_, vga_pll, 1
+instance = comp, \inst|d_vsync_state_out_0_~I , inst|d_vsync_state_out_0_, vga_pll, 1
+instance = comp, \inst|d_vsync_state_out_1_~I , inst|d_vsync_state_out_1_, vga_pll, 1
+instance = comp, \inst|d_vsync_state_out_2_~I , inst|d_vsync_state_out_2_, vga_pll, 1
+instance = comp, \inst|d_vsync_state_out_3_~I , inst|d_vsync_state_out_3_, vga_pll, 1
+instance = comp, \inst|d_vsync_state_out_4_~I , inst|d_vsync_state_out_4_, vga_pll, 1
+instance = comp, \inst|d_vsync_state_out_5_~I , inst|d_vsync_state_out_5_, vga_pll, 1
+instance = comp, \inst|d_vsync_state_out_6_~I , inst|d_vsync_state_out_6_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_tri_13_~I , inst|seven_seg_pin_tri_13_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_out_12_~I , inst|seven_seg_pin_out_12_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_out_11_~I , inst|seven_seg_pin_out_11_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_out_10_~I , inst|seven_seg_pin_out_10_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_out_9_~I , inst|seven_seg_pin_out_9_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_out_8_~I , inst|seven_seg_pin_out_8_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_out_7_~I , inst|seven_seg_pin_out_7_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_tri_6_~I , inst|seven_seg_pin_tri_6_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_tri_5_~I , inst|seven_seg_pin_tri_5_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_tri_4_~I , inst|seven_seg_pin_tri_4_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_tri_3_~I , inst|seven_seg_pin_tri_3_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_out_2_~I , inst|seven_seg_pin_out_2_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_out_1_~I , inst|seven_seg_pin_out_1_, vga_pll, 1
+instance = comp, \inst|seven_seg_pin_tri_0_~I , inst|seven_seg_pin_tri_0_, vga_pll, 1
--- /dev/null
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+
+
+//
+// Device: Altera EP1S25F672C6 Package FBGA672
+//
+
+//
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+//
+
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "vga_pll")
+ (DATE "10/28/2009 14:55:41")
+ (VENDOR "Altera")
+ (PROGRAM "Quartus II")
+ (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version")
+ (DIVIDER .)
+ (TIMESCALE 1 ps)
+
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE board_clk\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (760:760:760) (760:760:760))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_pll")
+ (INSTANCE inst1\|altpll_component\|pll)
+ (DELAY
+ (ABSOLUTE
+ (PORT inclk[0] (649:649:649) (649:649:649))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|reset_pin_in\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (1141:1141:1141) (1141:1141:1141))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|dly_counter_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1191:1191:1191) (1191:1191:1191))
+ (PORT datac (5177:5177:5177) (5177:5177:5177))
+ (PORT datad (448:448:448) (448:448:448))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|dly_counter_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|dly_counter_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (441:441:441) (441:441:441))
+ (PORT datac (5628:5628:5628) (5628:5628:5628))
+ (PORT datad (1162:1162:1162) (1162:1162:1162))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|dly_counter_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (446:446:446) (446:446:446))
+ (PORT datac (5624:5624:5624) (5624:5624:5624))
+ (PORT datad (1164:1164:1164) (1164:1164:1164))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1379:1379:1379) (1379:1379:1379))
+ (PORT datac (1388:1388:1388) (1388:1388:1388))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1478:1478:1478) (1478:1478:1478))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2064:2064:2064) (2064:2064:2064))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (423:423:423) (423:423:423))
+ (PORT datac (1322:1322:1322) (1322:1322:1322))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1412:1412:1412) (1412:1412:1412))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (1321:1321:1321) (1321:1321:1321))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1411:1411:1411) (1411:1411:1411))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (1320:1320:1320) (1320:1320:1320))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1410:1410:1410) (1410:1410:1410))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (1318:1318:1318) (1318:1318:1318))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1408:1408:1408) (1408:1408:1408))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1317:1317:1317) (1317:1317:1317))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1407:1407:1407) (1407:1407:1407))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (1304:1304:1304) (1304:1304:1304))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1394:1394:1394) (1394:1394:1394))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (422:422:422) (422:422:422))
+ (PORT datac (1307:1307:1307) (1307:1307:1307))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1397:1397:1397) (1397:1397:1397))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (1310:1310:1310) (1310:1310:1310))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1400:1400:1400) (1400:1400:1400))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1313:1313:1313) (1313:1313:1313))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1403:1403:1403) (1403:1403:1403))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1316:1316:1316) (1316:1316:1316))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1938:1938:1938) (1938:1938:1938))
+ (PORT datac (1406:1406:1406) (1406:1406:1406))
+ (PORT sclr (1841:1841:1841) (1841:1841:1841))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1127:1127:1127) (1127:1127:1127))
+ (PORT datab (1242:1242:1242) (1242:1242:1242))
+ (PORT datac (1186:1186:1186) (1186:1186:1186))
+ (PORT datad (1405:1405:1405) (1405:1405:1405))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1183:1183:1183) (1183:1183:1183))
+ (PORT datab (1157:1157:1157) (1157:1157:1157))
+ (PORT datac (1190:1190:1190) (1190:1190:1190))
+ (PORT datad (1419:1419:1419) (1419:1419:1419))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1430:1430:1430) (1430:1430:1430))
+ (PORT datab (1145:1145:1145) (1145:1145:1145))
+ (PORT datac (373:373:373) (373:373:373))
+ (PORT datad (359:359:359) (359:359:359))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|G_2.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1983:1983:1983) (1983:1983:1983))
+ (PORT datab (2383:2383:2383) (2383:2383:2383))
+ (PORT datac (2111:2111:2111) (2111:2111:2111))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (774:774:774) (774:774:774))
+ (PORT datab (685:685:685) (685:685:685))
+ (PORT datac (650:650:650) (650:650:650))
+ (PORT datad (632:632:632) (632:632:632))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (666:666:666) (666:666:666))
+ (PORT datab (685:685:685) (685:685:685))
+ (PORT datac (1003:1003:1003) (1003:1003:1003))
+ (PORT datad (682:682:682) (682:682:682))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1179:1179:1179) (1179:1179:1179))
+ (PORT datab (1403:1403:1403) (1403:1403:1403))
+ (PORT datac (1075:1075:1075) (1075:1075:1075))
+ (PORT datad (1060:1060:1060) (1060:1060:1060))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (671:671:671) (671:671:671))
+ (PORT datac (655:655:655) (655:655:655))
+ (PORT datad (687:687:687) (687:687:687))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (776:776:776) (776:776:776))
+ (PORT datab (694:694:694) (694:694:694))
+ (PORT datad (635:635:635) (635:635:635))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (687:687:687) (687:687:687))
+ (PORT datab (681:681:681) (681:681:681))
+ (PORT datac (697:697:697) (697:697:697))
+ (PORT datad (642:642:642) (642:642:642))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (775:775:775) (775:775:775))
+ (PORT datab (694:694:694) (694:694:694))
+ (PORT datad (672:672:672) (672:672:672))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1745:1745:1745) (1745:1745:1745))
+ (PORT datad (419:419:419) (419:419:419))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3036:3036:3036) (3036:3036:3036))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (PORT ena (2335:2335:2335) (2335:2335:2335))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1066:1066:1066) (1066:1066:1066))
+ (PORT datab (1067:1067:1067) (1067:1067:1067))
+ (PORT datac (1736:1736:1736) (1736:1736:1736))
+ (PORT datad (1360:1360:1360) (1360:1360:1360))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1416:1416:1416) (1416:1416:1416))
+ (PORT datab (1406:1406:1406) (1406:1406:1406))
+ (PORT datac (1133:1133:1133) (1133:1133:1133))
+ (PORT datad (1151:1151:1151) (1151:1151:1151))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (351:351:351) (351:351:351))
+ (PORT datab (353:353:353) (353:353:353))
+ (PORT datac (1188:1188:1188) (1188:1188:1188))
+ (PORT datad (1246:1246:1246) (1246:1246:1246))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1731:1731:1731) (1731:1731:1731))
+ (PORT datab (340:340:340) (340:340:340))
+ (PORT datac (1162:1162:1162) (1162:1162:1162))
+ (PORT datad (348:348:348) (348:348:348))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1252:1252:1252) (1252:1252:1252))
+ (PORT sclr (3171:3171:3171) (3171:3171:3171))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2092:2092:2092) (2092:2092:2092))
+ (PORT ena (1645:1645:1645) (1645:1645:1645))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (384:384:384) (384:384:384))
+ (PORT datab (346:346:346) (346:346:346))
+ (PORT datac (557:557:557) (557:557:557))
+ (PORT datad (449:449:449) (449:449:449))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (358:358:358) (358:358:358))
+ (PORT datab (347:347:347) (347:347:347))
+ (PORT datac (2397:2397:2397) (2397:2397:2397))
+ (PORT datad (1052:1052:1052) (1052:1052:1052))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (388:388:388) (388:388:388))
+ (PORT datab (347:347:347) (347:347:347))
+ (PORT datac (557:557:557) (557:557:557))
+ (PORT datad (448:448:448) (448:448:448))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3335:3335:3335) (3335:3335:3335))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (PORT ena (1806:1806:1806) (1806:1806:1806))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1613:1613:1613) (1613:1613:1613))
+ (PORT datad (1734:1734:1734) (1734:1734:1734))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3036:3036:3036) (3036:3036:3036))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (PORT ena (2335:2335:2335) (2335:2335:2335))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (454:454:454) (454:454:454))
+ (PORT datad (1621:1621:1621) (1621:1621:1621))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3036:3036:3036) (3036:3036:3036))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (PORT ena (2335:2335:2335) (2335:2335:2335))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2023:2023:2023) (2023:2023:2023))
+ (PORT datab (2145:2145:2145) (2145:2145:2145))
+ (PORT datac (5551:5551:5551) (5551:5551:5551))
+ (PORT datad (2002:2002:2002) (2002:2002:2002))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (656:656:656) (656:656:656))
+ (PORT datab (684:684:684) (684:684:684))
+ (PORT datac (701:701:701) (701:701:701))
+ (PORT datad (631:631:631) (631:631:631))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (352:352:352) (352:352:352))
+ (PORT datab (1323:1323:1323) (1323:1323:1323))
+ (PORT datac (365:365:365) (365:365:365))
+ (PORT datad (376:376:376) (376:376:376))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3335:3335:3335) (3335:3335:3335))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (PORT ena (1806:1806:1806) (1806:1806:1806))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_hsync_state_3_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1588:1588:1588) (1588:1588:1588))
+ (PORT datad (1728:1728:1728) (1728:1728:1728))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|h_sync_1_0_0_0_g1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (604:604:604) (604:604:604))
+ (PORT datab (1266:1266:1266) (1266:1266:1266))
+ (PORT datac (455:455:455) (455:455:455))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (361:361:361) (361:361:361))
+ (PORT datab (2145:2145:2145) (2145:2145:2145))
+ (PORT datac (5552:5552:5552) (5552:5552:5552))
+ (PORT datad (2003:2003:2003) (2003:2003:2003))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1348:1348:1348) (1348:1348:1348))
+ (PORT datab (423:423:423) (423:423:423))
+ (PORT datac (689:689:689) (689:689:689))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (779:779:779) (779:779:779))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (689:689:689) (689:689:689))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (779:779:779) (779:779:779))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (689:689:689) (689:689:689))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (779:779:779) (779:779:779))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (687:687:687) (687:687:687))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (777:777:777) (777:777:777))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (686:686:686) (686:686:686))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (776:776:776) (776:776:776))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (672:672:672) (672:672:672))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (762:762:762) (762:762:762))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (683:683:683) (683:683:683))
+ (PORT datab (935:935:935) (935:935:935))
+ (PORT datac (623:623:623) (623:623:623))
+ (PORT datad (719:719:719) (719:719:719))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (422:422:422) (422:422:422))
+ (PORT datac (675:675:675) (675:675:675))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (765:765:765) (765:765:765))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (678:678:678) (678:678:678))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (768:768:768) (768:768:768))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (681:681:681) (681:681:681))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (771:771:771) (771:771:771))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (684:684:684) (684:684:684))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1440:1440:1440) (1440:1440:1440))
+ (PORT datac (774:774:774) (774:774:774))
+ (PORT sclr (1317:1317:1317) (1317:1317:1317))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2034:2034:2034) (2034:2034:2034))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (688:688:688) (688:688:688))
+ (PORT datab (626:626:626) (626:626:626))
+ (PORT datac (688:688:688) (688:688:688))
+ (PORT datad (732:732:732) (732:732:732))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (938:938:938) (938:938:938))
+ (PORT datab (597:597:597) (597:597:597))
+ (PORT datac (371:371:371) (371:371:371))
+ (PORT datad (346:346:346) (346:346:346))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|G_16.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (698:698:698) (698:698:698))
+ (PORT datab (1398:1398:1398) (1398:1398:1398))
+ (PORT datac (360:360:360) (360:360:360))
+ (PORT datad (345:345:345) (345:345:345))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (681:681:681) (681:681:681))
+ (PORT datab (576:576:576) (576:576:576))
+ (PORT datac (651:651:651) (651:651:651))
+ (PORT datad (597:597:597) (597:597:597))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (337:337:337) (337:337:337))
+ (PORT datac (640:640:640) (640:640:640))
+ (PORT datad (647:647:647) (647:647:647))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (687:687:687) (687:687:687))
+ (PORT datab (626:626:626) (626:626:626))
+ (PORT datac (687:687:687) (687:687:687))
+ (PORT datad (731:731:731) (731:731:731))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1182:1182:1182) (1182:1182:1182))
+ (PORT datab (1299:1299:1299) (1299:1299:1299))
+ (PORT datad (1467:1467:1467) (1467:1467:1467))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1222:1222:1222) (1222:1222:1222))
+ (PORT datab (1117:1117:1117) (1117:1117:1117))
+ (PORT datac (1389:1389:1389) (1389:1389:1389))
+ (PORT datad (1160:1160:1160) (1160:1160:1160))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1416:1416:1416) (1416:1416:1416))
+ (PORT datab (846:846:846) (846:846:846))
+ (PORT datac (473:473:473) (473:473:473))
+ (PORT datad (833:833:833) (833:833:833))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (969:969:969) (969:969:969))
+ (PORT datad (1159:1159:1159) (1159:1159:1159))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2179:2179:2179) (2179:2179:2179))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (PORT ena (1573:1573:1573) (1573:1573:1573))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (383:383:383) (383:383:383))
+ (PORT datab (1168:1168:1168) (1168:1168:1168))
+ (PORT datac (924:924:924) (924:924:924))
+ (PORT datad (1466:1466:1466) (1466:1466:1466))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (382:382:382) (382:382:382))
+ (PORT datab (1457:1457:1457) (1457:1457:1457))
+ (PORT datac (990:990:990) (990:990:990))
+ (PORT datad (1178:1178:1178) (1178:1178:1178))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1080:1080:1080) (1080:1080:1080))
+ (PORT sclr (2188:2188:2188) (2188:2188:2188))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (PORT ena (1294:1294:1294) (1294:1294:1294))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (384:384:384) (384:384:384))
+ (PORT datac (366:366:366) (366:366:366))
+ (PORT datad (940:940:940) (940:940:940))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1060:1060:1060) (1060:1060:1060))
+ (PORT datab (349:349:349) (349:349:349))
+ (PORT datac (381:381:381) (381:381:381))
+ (PORT datad (937:937:937) (937:937:937))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (376:376:376) (376:376:376))
+ (PORT datab (335:335:335) (335:335:335))
+ (PORT datac (368:368:368) (368:368:368))
+ (PORT datad (1412:1412:1412) (1412:1412:1412))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (910:910:910) (910:910:910))
+ (PORT datab (947:947:947) (947:947:947))
+ (PORT datac (1155:1155:1155) (1155:1155:1155))
+ (PORT datad (1187:1187:1187) (1187:1187:1187))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2179:2179:2179) (2179:2179:2179))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (PORT ena (1573:1573:1573) (1573:1573:1573))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (354:354:354) (354:354:354))
+ (PORT datac (1614:1614:1614) (1614:1614:1614))
+ (PORT datad (1042:1042:1042) (1042:1042:1042))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (619:619:619) (619:619:619))
+ (PORT datab (1075:1075:1075) (1075:1075:1075))
+ (PORT datac (579:579:579) (579:579:579))
+ (PORT datad (1413:1413:1413) (1413:1413:1413))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|d_set_vsync_counter_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (696:696:696) (696:696:696))
+ (PORT datac (1410:1410:1410) (1410:1410:1410))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1180:1180:1180) (1180:1180:1180))
+ (PORT datab (343:343:343) (343:343:343))
+ (PORT datac (5619:5619:5619) (5619:5619:5619))
+ (PORT datad (453:453:453) (453:453:453))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1113:1113:1113) (1113:1113:1113))
+ (PORT datab (1378:1378:1378) (1378:1378:1378))
+ (PORT datac (1182:1182:1182) (1182:1182:1182))
+ (PORT datad (1202:1202:1202) (1202:1202:1202))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (379:379:379) (379:379:379))
+ (PORT datad (369:369:369) (369:369:369))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (916:916:916) (916:916:916))
+ (PORT datab (1143:1143:1143) (1143:1143:1143))
+ (PORT datac (469:469:469) (469:469:469))
+ (PORT datad (1181:1181:1181) (1181:1181:1181))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2179:2179:2179) (2179:2179:2179))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (PORT ena (1573:1573:1573) (1573:1573:1573))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_2_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (960:960:960) (960:960:960))
+ (PORT datad (437:437:437) (437:437:437))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|v_sync_1_0_0_0_g1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (461:461:461) (461:461:461))
+ (PORT datab (423:423:423) (423:423:423))
+ (PORT datac (445:445:445) (445:445:445))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1184:1184:1184) (1184:1184:1184))
+ (PORT datab (344:344:344) (344:344:344))
+ (PORT datac (5178:5178:5178) (5178:5178:5178))
+ (PORT datad (448:448:448) (448:448:448))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1176:1176:1176) (1176:1176:1176))
+ (PORT datab (444:444:444) (444:444:444))
+ (PORT datac (5625:5625:5625) (5625:5625:5625))
+ (PORT datad (1973:1973:1973) (1973:1973:1973))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (485:485:485) (485:485:485))
+ (PORT datad (442:442:442) (442:442:442))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2533:2533:2533) (2533:2533:2533))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (972:972:972) (972:972:972))
+ (PORT datab (944:944:944) (944:944:944))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (456:456:456) (456:456:456))
+ (PORT datad (843:843:843) (843:843:843))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2533:2533:2533) (2533:2533:2533))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (952:952:952) (952:952:952))
+ (PORT datab (973:973:973) (973:973:973))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (875:875:875) (875:875:875))
+ (PORT datad (437:437:437) (437:437:437))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2533:2533:2533) (2533:2533:2533))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (955:955:955) (955:955:955))
+ (PORT datab (919:919:919) (919:919:919))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (954:954:954) (954:954:954))
+ (PORT datab (945:945:945) (945:945:945))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (868:868:868) (868:868:868))
+ (PORT datad (445:445:445) (445:445:445))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2533:2533:2533) (2533:2533:2533))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1004:1004:1004) (1004:1004:1004))
+ (PORT datab (1004:1004:1004) (1004:1004:1004))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (457:457:457) (457:457:457))
+ (PORT datad (845:845:845) (845:845:845))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2533:2533:2533) (2533:2533:2533))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1034:1034:1034) (1034:1034:1034))
+ (PORT datab (1020:1020:1020) (1020:1020:1020))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (450:450:450) (450:450:450))
+ (PORT datad (851:851:851) (851:851:851))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2533:2533:2533) (2533:2533:2533))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1015:1015:1015) (1015:1015:1015))
+ (PORT datab (644:644:644) (644:644:644))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (636:636:636) (636:636:636))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1510:1510:1510) (1510:1510:1510))
+ (PORT datab (865:865:865) (865:865:865))
+ (PORT datad (536:536:536) (536:536:536))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (489:489:489) (489:489:489))
+ (PORT datab (418:418:418) (418:418:418))
+ (PORT datac (446:446:446) (446:446:446))
+ (PORT datad (470:470:470) (470:470:470))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (564:564:564) (564:564:564))
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (666:666:666) (666:666:666))
+ (PORT datad (958:958:958) (958:958:958))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (439:439:439) (439:439:439))
+ (PORT datab (962:962:962) (962:962:962))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (430:430:430) (430:430:430))
+ (PORT datab (416:416:416) (416:416:416))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (884:884:884) (884:884:884))
+ (PORT datad (341:341:341) (341:341:341))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2278:2278:2278) (2278:2278:2278))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (942:942:942) (942:942:942))
+ (PORT datab (945:945:945) (945:945:945))
+ (PORT datac (359:359:359) (359:359:359))
+ (PORT datad (940:940:940) (940:940:940))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1509:1509:1509) (1509:1509:1509))
+ (PORT datac (884:884:884) (884:884:884))
+ (PORT datad (348:348:348) (348:348:348))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (882:882:882) (882:882:882))
+ (PORT datad (442:442:442) (442:442:442))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2533:2533:2533) (2533:2533:2533))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelt2.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (947:947:947) (947:947:947))
+ (PORT datac (963:963:963) (963:963:963))
+ (PORT datad (958:958:958) (958:958:958))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto5.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1057:1057:1057) (1057:1057:1057))
+ (PORT datab (1007:1007:1007) (1007:1007:1007))
+ (PORT datac (1086:1086:1086) (1086:1086:1086))
+ (PORT datad (881:881:881) (881:881:881))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1471:1471:1471) (1471:1471:1471))
+ (PORT datac (1089:1089:1089) (1089:1089:1089))
+ (PORT datad (1013:1013:1013) (1013:1013:1013))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto6.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1061:1061:1061) (1061:1061:1061))
+ (PORT datac (1054:1054:1054) (1054:1054:1054))
+ (PORT datad (253:253:253) (253:253:253))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1183:1183:1183) (1183:1183:1183))
+ (PORT datab (424:424:424) (424:424:424))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (460:460:460) (460:460:460))
+ (PORT datab (987:987:987) (987:987:987))
+ (PORT datac (5175:5175:5175) (5175:5175:5175))
+ (PORT datad (1181:1181:1181) (1181:1181:1181))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (635:635:635) (635:635:635))
+ (PORT datad (357:357:357) (357:357:357))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2226:2226:2226) (2226:2226:2226))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2064:2064:2064) (2064:2064:2064))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1028:1028:1028) (1028:1028:1028))
+ (PORT datab (425:425:425) (425:425:425))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (371:371:371) (371:371:371))
+ (PORT datad (641:641:641) (641:641:641))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2226:2226:2226) (2226:2226:2226))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2064:2064:2064) (2064:2064:2064))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_a_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1012:1012:1012) (1012:1012:1012))
+ (PORT datab (1225:1225:1225) (1225:1225:1225))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1041:1041:1041) (1041:1041:1041))
+ (PORT datab (620:620:620) (620:620:620))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (937:937:937) (937:937:937))
+ (PORT datac (905:905:905) (905:905:905))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2572:2572:2572) (2572:2572:2572))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2110:2110:2110) (2110:2110:2110))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (615:615:615) (615:615:615))
+ (PORT datab (616:616:616) (616:616:616))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (634:634:634) (634:634:634))
+ (PORT datad (351:351:351) (351:351:351))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2226:2226:2226) (2226:2226:2226))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2064:2064:2064) (2064:2064:2064))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (666:666:666) (666:666:666))
+ (PORT datab (427:427:427) (427:427:427))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (361:361:361) (361:361:361))
+ (PORT datad (362:362:362) (362:362:362))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2225:2225:2225) (2225:2225:2225))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2064:2064:2064) (2064:2064:2064))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1068:1068:1068) (1068:1068:1068))
+ (PORT datab (426:426:426) (426:426:426))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (360:360:360) (360:360:360))
+ (PORT datad (644:644:644) (644:644:644))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2226:2226:2226) (2226:2226:2226))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2064:2064:2064) (2064:2064:2064))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1062:1062:1062) (1062:1062:1062))
+ (PORT datab (656:656:656) (656:656:656))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (900:900:900) (900:900:900))
+ (PORT datab (932:932:932) (932:932:932))
+ (PORT datac (1799:1799:1799) (1799:1799:1799))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2110:2110:2110) (2110:2110:2110))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (440:440:440) (440:440:440))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (342:342:342) (342:342:342))
+ (PORT datad (362:362:362) (362:362:362))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2225:2225:2225) (2225:2225:2225))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2064:2064:2064) (2064:2064:2064))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (671:671:671) (671:671:671))
+ (PORT datac (451:451:451) (451:451:451))
+ (PORT datad (1002:1002:1002) (1002:1002:1002))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1039:1039:1039) (1039:1039:1039))
+ (PORT datab (342:342:342) (342:342:342))
+ (PORT datac (1056:1056:1056) (1056:1056:1056))
+ (PORT datad (631:631:631) (631:631:631))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (453:453:453) (453:453:453))
+ (PORT datab (651:651:651) (651:651:651))
+ (PORT datac (672:672:672) (672:672:672))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (967:967:967) (967:967:967))
+ (PORT datad (428:428:428) (428:428:428))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (633:633:633) (633:633:633))
+ (PORT datad (350:350:350) (350:350:350))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2226:2226:2226) (2226:2226:2226))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2064:2064:2064) (2064:2064:2064))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (463:463:463) (463:463:463))
+ (PORT datac (466:466:466) (466:466:466))
+ (PORT datad (1406:1406:1406) (1406:1406:1406))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1200:1200:1200) (1200:1200:1200))
+ (PORT datad (1471:1471:1471) (1471:1471:1471))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2226:2226:2226) (2226:2226:2226))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (PORT ena (2067:2067:2067) (2067:2067:2067))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_2_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1006:1006:1006) (1006:1006:1006))
+ (PORT datab (977:977:977) (977:977:977))
+ (PORT datac (1591:1591:1591) (1591:1591:1591))
+ (PORT datad (433:433:433) (433:433:433))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_3_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1006:1006:1006) (1006:1006:1006))
+ (PORT datab (1002:1002:1002) (1002:1002:1002))
+ (PORT datac (363:363:363) (363:363:363))
+ (PORT datad (346:346:346) (346:346:346))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_5_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1064:1064:1064) (1064:1064:1064))
+ (PORT datab (1002:1002:1002) (1002:1002:1002))
+ (PORT datac (359:359:359) (359:359:359))
+ (PORT datad (352:352:352) (352:352:352))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto4_0.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1012:1012:1012) (1012:1012:1012))
+ (PORT datad (992:992:992) (992:992:992))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto6.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (433:433:433) (433:433:433))
+ (PORT datab (336:336:336) (336:336:336))
+ (PORT datac (1002:1002:1002) (1002:1002:1002))
+ (PORT datad (940:940:940) (940:940:940))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelto3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (616:616:616) (616:616:616))
+ (PORT datab (984:984:984) (984:984:984))
+ (PORT datac (1041:1041:1041) (1041:1041:1041))
+ (PORT datad (991:991:991) (991:991:991))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_4_a_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2058:2058:2058) (2058:2058:2058))
+ (PORT datab (1540:1540:1540) (1540:1540:1540))
+ (PORT datac (1550:1550:1550) (1550:1550:1550))
+ (PORT datad (1887:1887:1887) (1887:1887:1887))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_4_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1596:1596:1596) (1596:1596:1596))
+ (PORT datab (1768:1768:1768) (1768:1768:1768))
+ (PORT datac (2067:2067:2067) (2067:2067:2067))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (441:441:441) (441:441:441))
+ (PORT datac (1283:1283:1283) (1283:1283:1283))
+ (PORT datad (2257:2257:2257) (2257:2257:2257))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (953:953:953) (953:953:953))
+ (PORT datad (1367:1367:1367) (1367:1367:1367))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3066:3066:3066) (3066:3066:3066))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2097:2097:2097) (2097:2097:2097))
+ (PORT ena (1631:1631:1631) (1631:1631:1631))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (443:443:443) (443:443:443))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (958:958:958) (958:958:958))
+ (PORT datab (423:423:423) (423:423:423))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (976:976:976) (976:976:976))
+ (PORT datab (419:419:419) (419:419:419))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|un2_toggle_counter_next_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (966:966:966) (966:966:966))
+ (PORT datab (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (971:971:971) (971:971:971))
+ (PORT datab (434:434:434) (434:434:434))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datab (942:942:942) (942:942:942))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datab (955:955:955) (955:955:955))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1000:1000:1000) (1000:1000:1000))
+ (PORT datab (609:609:609) (609:609:609))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datab (897:897:897) (897:897:897))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_7_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (942:942:942) (942:942:942))
+ (PORT datab (440:440:440) (440:440:440))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (644:644:644) (644:644:644))
+ (IOPATH datab cout (533:533:533) (533:533:533))
+ (IOPATH cin0 cout (219:219:219) (219:219:219))
+ (IOPATH cin1 cout (205:205:205) (205:205:205))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_8_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datab (945:945:945) (945:945:945))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH datab cout (460:460:460) (460:460:460))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_9_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_11_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1409:1409:1409) (1409:1409:1409))
+ (PORT datab (420:420:420) (420:420:420))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_11_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_10_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (596:596:596) (596:596:596))
+ (PORT datab (1407:1407:1407) (1407:1407:1407))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_10_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1150:1150:1150) (1150:1150:1150))
+ (PORT aclr (5475:5475:5475) (5475:5475:5475))
+ (PORT clk (2051:2051:2051) (2051:2051:2051))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_13_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1465:1465:1465) (1465:1465:1465))
+ (PORT datab (422:422:422) (422:422:422))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_13_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_12_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (996:996:996) (996:996:996))
+ (PORT datab (1423:1423:1423) (1423:1423:1423))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_12_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1150:1150:1150) (1150:1150:1150))
+ (PORT aclr (5475:5475:5475) (5475:5475:5475))
+ (PORT clk (2051:2051:2051) (2051:2051:2051))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_15_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datab (1362:1362:1362) (1362:1362:1362))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_15_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_14_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (458:458:458) (458:458:458))
+ (PORT datab (1387:1387:1387) (1387:1387:1387))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_14_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1150:1150:1150) (1150:1150:1150))
+ (PORT aclr (5475:5475:5475) (5475:5475:5475))
+ (PORT clk (2051:2051:2051) (2051:2051:2051))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglt6.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (443:443:443) (443:443:443))
+ (PORT datad (961:961:961) (961:961:961))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto9.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1002:1002:1002) (1002:1002:1002))
+ (PORT datab (440:440:440) (440:440:440))
+ (PORT datac (367:367:367) (367:367:367))
+ (PORT datad (932:932:932) (932:932:932))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto12.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1061:1061:1061) (1061:1061:1061))
+ (PORT datab (428:428:428) (428:428:428))
+ (PORT datac (457:457:457) (457:457:457))
+ (PORT datad (1408:1408:1408) (1408:1408:1408))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto15.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (461:461:461) (461:461:461))
+ (PORT datab (345:345:345) (345:345:345))
+ (PORT datac (1403:1403:1403) (1403:1403:1403))
+ (PORT datad (1429:1429:1429) (1429:1429:1429))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_16_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (447:447:447) (447:447:447))
+ (PORT datab (1377:1377:1377) (1377:1377:1377))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_16_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1150:1150:1150) (1150:1150:1150))
+ (PORT aclr (5475:5475:5475) (5475:5475:5475))
+ (PORT clk (2051:2051:2051) (2051:2051:2051))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_17_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datab (1366:1366:1366) (1366:1366:1366))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_17_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_19_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1379:1379:1379) (1379:1379:1379))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_19_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2111:2111:2111) (2111:2111:2111))
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_18_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (461:461:461) (461:461:461))
+ (PORT datab (1385:1385:1385) (1385:1385:1385))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH datab cout (460:460:460) (460:460:460))
+ (IOPATH cin cout (110:110:110) (110:110:110))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_18_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1150:1150:1150) (1150:1150:1150))
+ (PORT aclr (5475:5475:5475) (5475:5475:5475))
+ (PORT clk (2051:2051:2051) (2051:2051:2051))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto18.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (364:364:364) (364:364:364))
+ (PORT datab (1377:1377:1377) (1377:1377:1377))
+ (PORT datac (458:458:458) (458:458:458))
+ (PORT datad (449:449:449) (449:449:449))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_20_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (427:427:427) (427:427:427))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_20_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1150:1150:1150) (1150:1150:1150))
+ (PORT aclr (5475:5475:5475) (5475:5475:5475))
+ (PORT clk (2051:2051:2051) (2051:2051:2051))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_sig_0_0_0_g1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (376:376:376) (376:376:376))
+ (PORT datac (460:460:460) (460:460:460))
+ (PORT datad (1393:1393:1393) (1393:1393:1393))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|toggle_sig_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1085:1085:1085) (1085:1085:1085))
+ (PORT datad (436:436:436) (436:436:436))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|toggle_sig_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|r_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (3166:3166:3166) (3166:3166:3166))
+ (PORT datab (3139:3139:3139) (3139:3139:3139))
+ (PORT datac (2967:2967:2967) (2967:2967:2967))
+ (PORT datad (435:435:435) (435:435:435))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|r_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5468:5468:5468) (5468:5468:5468))
+ (PORT clk (2043:2043:2043) (2043:2043:2043))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|b_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (359:359:359) (359:359:359))
+ (PORT datab (344:344:344) (344:344:344))
+ (PORT datac (3215:3215:3215) (3215:3215:3215))
+ (PORT datad (2167:2167:2167) (2167:2167:2167))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|b_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5413:5413:5413) (5413:5413:5413))
+ (PORT clk (2025:2025:2025) (2025:2025:2025))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3422:3422:3422) (3422:3422:3422))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2656:2656:2656) (2656:2656:2656))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_set_column_counter_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3695:3695:3695) (3695:3695:3695))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_set_line_counter_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3004:3004:3004) (3004:3004:3004))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_set_hsync_counter_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3189:3189:3189) (3189:3189:3189))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_set_vsync_counter_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2937:2937:2937) (2937:2937:2937))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_r_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4042:4042:4042) (4042:4042:4042))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_g_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3227:3227:3227) (3227:3227:3227))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_b_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3536:3536:3536) (3536:3536:3536))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_h_enable_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3035:3035:3035) (3035:3035:3035))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_v_enable_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1665:1665:1665) (1665:1665:1665))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_state_clk_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2239:2239:2239) (2239:2239:2239))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_toggle_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4509:4509:4509) (4509:4509:4509))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|r0_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3637:3637:3637) (3637:3637:3637))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|r1_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3447:3447:3447) (3447:3447:3447))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|r2_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3473:3473:3473) (3473:3473:3473))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|g0_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3335:3335:3335) (3335:3335:3335))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|g1_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3519:3519:3519) (3519:3519:3519))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|g2_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3768:3768:3768) (3768:3768:3768))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|b0_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3020:3020:3020) (3020:3020:3020))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|b1_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2936:2936:2936) (2936:2936:2936))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|hsync_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2478:2478:2478) (2478:2478:2478))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|vsync_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2475:2475:2475) (2475:2475:2475))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_9_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2563:2563:2563) (2563:2563:2563))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_8_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3085:3085:3085) (3085:3085:3085))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_7_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2835:2835:2835) (2835:2835:2835))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_6_\~I.inst1)
+ (DELAY
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+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
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+ )
+ (CELL
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+ (INSTANCE inst\|d_column_counter_out_5_\~I.inst1)
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+ (CELL
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+ (INSTANCE inst\|d_column_counter_out_4_\~I.inst1)
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+ )
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+ (CELL
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+ (INSTANCE inst\|d_column_counter_out_3_\~I.inst1)
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+ (CELL
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+ (INSTANCE inst\|d_column_counter_out_2_\~I.inst1)
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+ )
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+ (CELL
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+ (INSTANCE inst\|d_column_counter_out_1_\~I.inst1)
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+ (CELL
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+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2307:2307:2307) (2307:2307:2307))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2340:2340:2340) (2340:2340:2340))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1914:1914:1914) (1914:1914:1914))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1790:1790:1790) (1790:1790:1790))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2543:2543:2543) (2543:2543:2543))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2087:2087:2087) (2087:2087:2087))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2661:2661:2661) (2661:2661:2661))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2763:2763:2763) (2763:2763:2763))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2969:2969:2969) (2969:2969:2969))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3068:3068:3068) (3068:3068:3068))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3360:3360:3360) (3360:3360:3360))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3036:3036:3036) (3036:3036:3036))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_6_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2653:2653:2653) (2653:2653:2653))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_13_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3481:3481:3481) (3481:3481:3481))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_12_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4857:4857:4857) (4857:4857:4857))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_11_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2937:2937:2937) (2937:2937:2937))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_10_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2929:2929:2929) (2929:2929:2929))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_9_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2778:2778:2778) (2778:2778:2778))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_8_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2763:2763:2763) (2763:2763:2763))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_7_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4867:4867:4867) (4867:4867:4867))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_6_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3621:3621:3621) (3621:3621:3621))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3621:3621:3621) (3621:3621:3621))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3615:3615:3615) (3615:3615:3615))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3615:3615:3615) (3615:3615:3615))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4048:4048:4048) (4048:4048:4048))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2937:2937:2937) (2937:2937:2937))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3465:3465:3465) (3465:3465:3465))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+)
--- /dev/null
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 16 16 296 560)
+ (text "vga" (rect 5 0 26 12)(font "Arial" ))
+ (text "inst" (rect 8 528 36 540)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "clk_pin" (rect 0 0 49 12)(font "Arial" ))
+ (text "clk_pin" (rect 21 27 70 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "reset_pin" (rect 0 0 63 12)(font "Arial" ))
+ (text "reset_pin" (rect 21 43 84 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 280 32)
+ (output)
+ (text "r0_pin" (rect 0 0 42 12)(font "Arial" ))
+ (text "r0_pin" (rect 217 27 259 39)(font "Arial" ))
+ (line (pt 280 32)(pt 264 32)(line_width 1))
+ )
+ (port
+ (pt 280 48)
+ (output)
+ (text "r1_pin" (rect 0 0 42 12)(font "Arial" ))
+ (text "r1_pin" (rect 217 43 259 55)(font "Arial" ))
+ (line (pt 280 48)(pt 264 48)(line_width 1))
+ )
+ (port
+ (pt 280 64)
+ (output)
+ (text "r2_pin" (rect 0 0 42 12)(font "Arial" ))
+ (text "r2_pin" (rect 217 59 259 71)(font "Arial" ))
+ (line (pt 280 64)(pt 264 64)(line_width 1))
+ )
+ (port
+ (pt 280 80)
+ (output)
+ (text "g0_pin" (rect 0 0 42 12)(font "Arial" ))
+ (text "g0_pin" (rect 217 75 259 87)(font "Arial" ))
+ (line (pt 280 80)(pt 264 80)(line_width 1))
+ )
+ (port
+ (pt 280 96)
+ (output)
+ (text "g1_pin" (rect 0 0 42 12)(font "Arial" ))
+ (text "g1_pin" (rect 217 91 259 103)(font "Arial" ))
+ (line (pt 280 96)(pt 264 96)(line_width 1))
+ )
+ (port
+ (pt 280 112)
+ (output)
+ (text "g2_pin" (rect 0 0 42 12)(font "Arial" ))
+ (text "g2_pin" (rect 217 107 259 119)(font "Arial" ))
+ (line (pt 280 112)(pt 264 112)(line_width 1))
+ )
+ (port
+ (pt 280 128)
+ (output)
+ (text "b0_pin" (rect 0 0 42 12)(font "Arial" ))
+ (text "b0_pin" (rect 217 123 259 135)(font "Arial" ))
+ (line (pt 280 128)(pt 264 128)(line_width 1))
+ )
+ (port
+ (pt 280 144)
+ (output)
+ (text "b1_pin" (rect 0 0 42 12)(font "Arial" ))
+ (text "b1_pin" (rect 217 139 259 151)(font "Arial" ))
+ (line (pt 280 144)(pt 264 144)(line_width 1))
+ )
+ (port
+ (pt 280 160)
+ (output)
+ (text "hsync_pin" (rect 0 0 63 12)(font "Arial" ))
+ (text "hsync_pin" (rect 196 155 259 167)(font "Arial" ))
+ (line (pt 280 160)(pt 264 160)(line_width 1))
+ )
+ (port
+ (pt 280 176)
+ (output)
+ (text "vsync_pin" (rect 0 0 63 12)(font "Arial" ))
+ (text "vsync_pin" (rect 196 171 259 183)(font "Arial" ))
+ (line (pt 280 176)(pt 264 176)(line_width 1))
+ )
+ (port
+ (pt 280 192)
+ (output)
+ (text "seven_seg_pin[13..0]" (rect 0 0 141 12)(font "Arial" ))
+ (text "seven_seg_pin[13..0]" (rect 118 187 259 199)(font "Arial" ))
+ (line (pt 280 192)(pt 264 192)(line_width 3))
+ )
+ (port
+ (pt 280 208)
+ (output)
+ (text "d_hsync" (rect 0 0 49 12)(font "Arial" ))
+ (text "d_hsync" (rect 210 203 259 215)(font "Arial" ))
+ (line (pt 280 208)(pt 264 208)(line_width 1))
+ )
+ (port
+ (pt 280 224)
+ (output)
+ (text "d_vsync" (rect 0 0 49 12)(font "Arial" ))
+ (text "d_vsync" (rect 210 219 259 231)(font "Arial" ))
+ (line (pt 280 224)(pt 264 224)(line_width 1))
+ )
+ (port
+ (pt 280 240)
+ (output)
+ (text "d_column_counter[9..0]" (rect 0 0 155 12)(font "Arial" ))
+ (text "d_column_counter[9..0]" (rect 104 235 259 247)(font "Arial" ))
+ (line (pt 280 240)(pt 264 240)(line_width 3))
+ )
+ (port
+ (pt 280 256)
+ (output)
+ (text "d_line_counter[8..0]" (rect 0 0 141 12)(font "Arial" ))
+ (text "d_line_counter[8..0]" (rect 118 251 259 263)(font "Arial" ))
+ (line (pt 280 256)(pt 264 256)(line_width 3))
+ )
+ (port
+ (pt 280 272)
+ (output)
+ (text "d_set_column_counter" (rect 0 0 141 12)(font "Arial" ))
+ (text "d_set_column_counter" (rect 118 267 259 279)(font "Arial" ))
+ (line (pt 280 272)(pt 264 272)(line_width 1))
+ )
+ (port
+ (pt 280 288)
+ (output)
+ (text "d_set_line_counter" (rect 0 0 127 12)(font "Arial" ))
+ (text "d_set_line_counter" (rect 132 283 259 295)(font "Arial" ))
+ (line (pt 280 288)(pt 264 288)(line_width 1))
+ )
+ (port
+ (pt 280 304)
+ (output)
+ (text "d_hsync_counter[9..0]" (rect 0 0 148 12)(font "Arial" ))
+ (text "d_hsync_counter[9..0]" (rect 111 299 259 311)(font "Arial" ))
+ (line (pt 280 304)(pt 264 304)(line_width 3))
+ )
+ (port
+ (pt 280 320)
+ (output)
+ (text "d_vsync_counter[9..0]" (rect 0 0 148 12)(font "Arial" ))
+ (text "d_vsync_counter[9..0]" (rect 111 315 259 327)(font "Arial" ))
+ (line (pt 280 320)(pt 264 320)(line_width 3))
+ )
+ (port
+ (pt 280 336)
+ (output)
+ (text "d_set_hsync_counter" (rect 0 0 134 12)(font "Arial" ))
+ (text "d_set_hsync_counter" (rect 125 331 259 343)(font "Arial" ))
+ (line (pt 280 336)(pt 264 336)(line_width 1))
+ )
+ (port
+ (pt 280 352)
+ (output)
+ (text "d_set_vsync_counter" (rect 0 0 134 12)(font "Arial" ))
+ (text "d_set_vsync_counter" (rect 125 347 259 359)(font "Arial" ))
+ (line (pt 280 352)(pt 264 352)(line_width 1))
+ )
+ (port
+ (pt 280 368)
+ (output)
+ (text "d_h_enable" (rect 0 0 70 12)(font "Arial" ))
+ (text "d_h_enable" (rect 189 363 259 375)(font "Arial" ))
+ (line (pt 280 368)(pt 264 368)(line_width 1))
+ )
+ (port
+ (pt 280 384)
+ (output)
+ (text "d_v_enable" (rect 0 0 70 12)(font "Arial" ))
+ (text "d_v_enable" (rect 189 379 259 391)(font "Arial" ))
+ (line (pt 280 384)(pt 264 384)(line_width 1))
+ )
+ (port
+ (pt 280 400)
+ (output)
+ (text "d_r" (rect 0 0 21 12)(font "Arial" ))
+ (text "d_r" (rect 238 395 259 407)(font "Arial" ))
+ (line (pt 280 400)(pt 264 400)(line_width 1))
+ )
+ (port
+ (pt 280 416)
+ (output)
+ (text "d_g" (rect 0 0 21 12)(font "Arial" ))
+ (text "d_g" (rect 238 411 259 423)(font "Arial" ))
+ (line (pt 280 416)(pt 264 416)(line_width 1))
+ )
+ (port
+ (pt 280 432)
+ (output)
+ (text "d_b" (rect 0 0 21 12)(font "Arial" ))
+ (text "d_b" (rect 238 427 259 439)(font "Arial" ))
+ (line (pt 280 432)(pt 264 432)(line_width 1))
+ )
+ (port
+ (pt 280 448)
+ (output)
+ (text "d_hsync_state[0..6]" (rect 0 0 134 12)(font "Arial" ))
+ (text "d_hsync_state[0..6]" (rect 125 443 259 455)(font "Arial" ))
+ (line (pt 280 448)(pt 264 448)(line_width 3))
+ )
+ (port
+ (pt 280 464)
+ (output)
+ (text "d_vsync_state[0..6]" (rect 0 0 134 12)(font "Arial" ))
+ (text "d_vsync_state[0..6]" (rect 125 459 259 471)(font "Arial" ))
+ (line (pt 280 464)(pt 264 464)(line_width 3))
+ )
+ (port
+ (pt 280 480)
+ (output)
+ (text "d_state_clk" (rect 0 0 77 12)(font "Arial" ))
+ (text "d_state_clk" (rect 182 475 259 487)(font "Arial" ))
+ (line (pt 280 480)(pt 264 480)(line_width 1))
+ )
+ (port
+ (pt 280 496)
+ (output)
+ (text "d_toggle" (rect 0 0 56 12)(font "Arial" ))
+ (text "d_toggle" (rect 203 491 259 503)(font "Arial" ))
+ (line (pt 280 496)(pt 264 496)(line_width 1))
+ )
+ (port
+ (pt 280 512)
+ (output)
+ (text "d_toggle_counter[24..0]" (rect 0 0 162 12)(font "Arial" ))
+ (text "d_toggle_counter[24..0]" (rect 97 507 259 519)(font "Arial" ))
+ (line (pt 280 512)(pt 264 512)(line_width 3))
+ )
+ (drawing
+ (rectangle (rect 16 16 264 528)(line_width 1))
+ )
+)
--- /dev/null
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 16 16 360 528)
+ (text "vga_control" (rect 5 0 82 12)(font "Arial" ))
+ (text "inst" (rect 8 496 36 508)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "line_counter_sig_0" (rect 0 0 127 12)(font "Arial" ))
+ (text "line_counter_sig_0" (rect 21 27 148 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "line_counter_sig_2" (rect 0 0 127 12)(font "Arial" ))
+ (text "line_counter_sig_2" (rect 21 43 148 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "line_counter_sig_1" (rect 0 0 127 12)(font "Arial" ))
+ (text "line_counter_sig_1" (rect 21 59 148 71)(font "Arial" ))
+ (line (pt 0 64)(pt 16 64)(line_width 1))
+ )
+ (port
+ (pt 0 80)
+ (input)
+ (text "line_counter_sig_3" (rect 0 0 127 12)(font "Arial" ))
+ (text "line_counter_sig_3" (rect 21 75 148 87)(font "Arial" ))
+ (line (pt 0 80)(pt 16 80)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "line_counter_sig_6" (rect 0 0 127 12)(font "Arial" ))
+ (text "line_counter_sig_6" (rect 21 91 148 103)(font "Arial" ))
+ (line (pt 0 96)(pt 16 96)(line_width 1))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "line_counter_sig_5" (rect 0 0 127 12)(font "Arial" ))
+ (text "line_counter_sig_5" (rect 21 107 148 119)(font "Arial" ))
+ (line (pt 0 112)(pt 16 112)(line_width 1))
+ )
+ (port
+ (pt 0 128)
+ (input)
+ (text "line_counter_sig_4" (rect 0 0 127 12)(font "Arial" ))
+ (text "line_counter_sig_4" (rect 21 123 148 135)(font "Arial" ))
+ (line (pt 0 128)(pt 16 128)(line_width 1))
+ )
+ (port
+ (pt 0 144)
+ (input)
+ (text "line_counter_sig_7" (rect 0 0 127 12)(font "Arial" ))
+ (text "line_counter_sig_7" (rect 21 139 148 151)(font "Arial" ))
+ (line (pt 0 144)(pt 16 144)(line_width 1))
+ )
+ (port
+ (pt 0 160)
+ (input)
+ (text "line_counter_sig_8" (rect 0 0 127 12)(font "Arial" ))
+ (text "line_counter_sig_8" (rect 21 155 148 167)(font "Arial" ))
+ (line (pt 0 160)(pt 16 160)(line_width 1))
+ )
+ (port
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--- /dev/null
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
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+ (line (pt 288 864)(pt 272 864)(line_width 1))
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+ (line (pt 288 880)(pt 272 880)(line_width 1))
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+ (line (pt 288 944)(pt 272 944)(line_width 1))
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+ (output)
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+ )
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+ (pt 288 976)
+ (output)
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+ (text "d_set_hsync_counter" (rect 133 971 267 983)(font "Arial" ))
+ (line (pt 288 976)(pt 272 976)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 272 1008)(line_width 1))
+ )
+)
--- /dev/null
+Assembler report for vga_pll
+Wed Oct 28 14:55:34 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: vga_pll.sof
+ 6. Assembler Device Options: vga_pll.pof
+ 7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Wed Oct 28 14:55:34 2009 ;
+; Revision Name ; vga_pll ;
+; Top-level Entity Name ; vga_pll ;
+; Family ; Stratix ;
+; Device ; EP1S25F672C6 ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option ; Setting ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation ; Off ; Off ;
+; Compression mode ; Off ; Off ;
+; Clock source for configuration device ; Internal ; Internal ;
+; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
+; Divide clock frequency by ; 1 ; 1 ;
+; Auto user code ; Off ; Off ;
+; Use configuration device ; On ; On ;
+; Configuration device ; Auto ; Auto ;
+; Configuration device auto user code ; Off ; Off ;
+; Auto-increment JTAG user code for multiple configuration devices ; On ; On ;
+; Disable CONF_DONE and nSTATUS pull-ups on configuration device ; Off ; Off ;
+; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
+; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
+; Hexadecimal Output File start address ; 0 ; 0 ;
+; Hexadecimal Output File count direction ; Up ; Up ;
+; Release clears before tri-states ; Off ; Off ;
+; Auto-restart configuration after error ; On ; On ;
+; Use Checkered Pattern as Uninitialized RAM Content ; Off ; Off ;
+; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------+
+; Assembler Generated Files ;
++---------------------------+
+; File Name ;
++---------------------------+
+; vga_pll.sof ;
+; vga_pll.pof ;
++---------------------------+
+
+
++---------------------------------------+
+; Assembler Device Options: vga_pll.sof ;
++----------------+----------------------+
+; Option ; Setting ;
++----------------+----------------------+
+; Device ; EP1S25F672C6 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x002E62F1 ;
++----------------+----------------------+
+
+
++---------------------------------------+
+; Assembler Device Options: vga_pll.pof ;
++--------------------+------------------+
+; Option ; Setting ;
++--------------------+------------------+
+; Device ; EPC8 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x0BFBA6EA ;
+; Compression Ratio ; 1 ;
++--------------------+------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:55:16 2009
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
+Info: Assembler is generating device programming files
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 269 megabytes
+ Info: Processing ended: Wed Oct 28 14:55:34 2009
+ Info: Elapsed time: 00:00:18
+ Info: Total CPU time (on all processors): 00:00:18
+
+
--- /dev/null
+Wed Oct 28 14:55:42 2009
--- /dev/null
+EDA Netlist Writer report for vga_pll
+Wed Oct 28 14:55:41 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. EDA Netlist Writer Summary
+ 3. Simulation Settings
+ 4. Simulation Generated Files
+ 5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Wed Oct 28 14:55:41 2009 ;
+; Revision Name ; vga_pll ;
+; Top-level Entity Name ; vga_pll ;
+; Family ; Stratix ;
+; Simulation Files Creation ; Successful ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option ; Setting ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name ; ModelSim-Altera (Verilog) ;
+; Generate netlist for functional simulation only ; Off ;
+; Time scale ; 1 ps ;
+; Truncate long hierarchy paths ; Off ;
+; Map illegal HDL characters ; Off ;
+; Flatten buses into individual nodes ; Off ;
+; Maintain hierarchy ; Off ;
+; Bring out device-wide set/reset signals as ports ; Off ;
+; Enable glitch filtering ; Off ;
+; Do not write top level VHDL entity ; Off ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
+; Architecture name in VHDL output netlist ; structure ;
+; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
+; Generate third-party EDA tool command script for gate-level simulation ; Off ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Simulation Generated Files ;
++---------------------------------------------------------------------------------------------+
+; Generated Files ;
++---------------------------------------------------------------------------------------------+
+; /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll.vo ;
+; /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo ;
++---------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II EDA Netlist Writer
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:55:40 2009
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
+Info: Generated files "vga_pll.vo" and "vga_pll_v.sdo" in directory "/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 162 megabytes
+ Info: Processing ended: Wed Oct 28 14:55:41 2009
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+
+
--- /dev/null
+Fitter report for vga_pll
+Wed Oct 28 14:55:12 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Pin-Out File
+ 6. Fitter Resource Usage Summary
+ 7. Input Pins
+ 8. Output Pins
+ 9. I/O Bank Usage
+ 10. All Package Pins
+ 11. PLL Summary
+ 12. PLL Usage
+ 13. Output Pin Default Load For Reported TCO
+ 14. Fitter Resource Utilization by Entity
+ 15. Delay Chain Summary
+ 16. Pad To Core Delay Chain Fanout
+ 17. Control Signals
+ 18. Global & Other Fast Signals
+ 19. Non-Global High Fan-Out Signals
+ 20. Interconnect Usage Summary
+ 21. LAB Logic Elements
+ 22. LAB-wide Signals
+ 23. LAB Signals Sourced
+ 24. LAB Signals Sourced Out
+ 25. LAB Distinct Inputs
+ 26. Fitter Device Options
+ 27. Estimated Delay Added for Hold Timing
+ 28. Fitter Messages
+ 29. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------+
+; Fitter Summary ;
++--------------------------+------------------------------------------+
+; Fitter Status ; Successful - Wed Oct 28 14:55:12 2009 ;
+; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
+; Revision Name ; vga_pll ;
+; Top-level Entity Name ; vga_pll ;
+; Family ; Stratix ;
+; Device ; EP1S25F672C6 ;
+; Timing Models ; Final ;
+; Total logic elements ; 173 / 25,660 ( < 1 % ) ;
+; Total pins ; 117 / 474 ( 25 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 1,944,576 ( 0 % ) ;
+; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ;
+; Total PLLs ; 1 / 6 ( 17 % ) ;
+; Total DLLs ; 0 / 2 ( 0 % ) ;
++--------------------------+------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; EP1S25F672C6 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Use smart compilation ; Off ; Off ;
+; Use TimeQuest Timing Analyzer ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate full fit report during ECO compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; On ; On ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Slow Slew Rate ; Off ; Off ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Save Intermediate Fitting Results ; Off ; Off ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 2 ;
+; Maximum allowed ; 2 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 2 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; 1 processor ; 100.0% ;
+; 2 processors ; < 0.1% ;
++----------------------------+-------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/vga_pll.pin.
+
+
++---------------------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+-----------------------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+-----------------------------------------------------------+
+; Total logic elements ; 173 / 25,660 ( < 1 % ) ;
+; -- Combinational with no register ; 90 ;
+; -- Register only ; 0 ;
+; -- Combinational with a register ; 83 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 60 ;
+; -- 3 input functions ; 52 ;
+; -- 2 input functions ; 58 ;
+; -- 1 input functions ; 2 ;
+; -- 0 input functions ; 1 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 120 ;
+; -- arithmetic mode ; 53 ;
+; -- qfbk mode ; 3 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 70 ;
+; -- asynchronous clear/load mode ; 24 ;
+; ; ;
+; Total registers ; 83 / 28,424 ( < 1 % ) ;
+; Total LABs ; 22 / 2,566 ( < 1 % ) ;
+; Logic elements in carry chains ; 61 ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 117 / 474 ( 25 % ) ;
+; -- Clock pins ; 1 / 16 ( 6 % ) ;
+; Global signals ; 2 ;
+; M512s ; 0 / 224 ( 0 % ) ;
+; M4Ks ; 0 / 138 ( 0 % ) ;
+; M-RAMs ; 0 / 2 ( 0 % ) ;
+; Total memory bits ; 0 / 1,944,576 ( 0 % ) ;
+; Total RAM block bits ; 0 / 1,944,576 ( 0 % ) ;
+; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ;
+; PLLs ; 1 / 6 ( 17 % ) ;
+; Global clocks ; 2 / 16 ( 13 % ) ;
+; Regional clocks ; 0 / 16 ( 0 % ) ;
+; Fast regional clocks ; 0 / 8 ( 0 % ) ;
+; SERDES transmitters ; 0 / 78 ( 0 % ) ;
+; SERDES receivers ; 0 / 78 ( 0 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Remote update blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Peak interconnect usage (total/H/V) ; 1% / 1% / 1% ;
+; Maximum fan-out node ; vpll:inst1|altpll:altpll_component|_clk0 ;
+; Maximum fan-out ; 84 ;
+; Highest non-global fan-out signal ; vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1 ;
+; Highest non-global fan-out ; 22 ;
+; Total fan-out ; 872 ;
+; Average fan-out ; 2.99 ;
++---------------------------------------------+-----------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; board_clk ; N3 ; 2 ; 0 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; reset ; A5 ; 3 ; 7 ; 47 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
+; b0_pin ; E24 ; 5 ; 79 ; 45 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; b1_pin ; T6 ; 1 ; 0 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_b ; K20 ; 5 ; 79 ; 33 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[0] ; L23 ; 5 ; 79 ; 31 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[1] ; L22 ; 5 ; 79 ; 31 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[2] ; L21 ; 5 ; 79 ; 32 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[3] ; L20 ; 5 ; 79 ; 32 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[4] ; L6 ; 2 ; 0 ; 32 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[5] ; L4 ; 2 ; 0 ; 33 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[6] ; L2 ; 2 ; 0 ; 33 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[7] ; K23 ; 5 ; 79 ; 34 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[8] ; K19 ; 5 ; 79 ; 33 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_column_counter[9] ; K5 ; 2 ; 0 ; 34 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_g ; K24 ; 5 ; 79 ; 34 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_h_enable ; J21 ; 5 ; 79 ; 37 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync ; L7 ; 2 ; 0 ; 32 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_counter[0] ; H4 ; 2 ; 0 ; 42 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_counter[1] ; AD15 ; 7 ; 52 ; 0 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[2] ; B16 ; 4 ; 52 ; 47 ; 4 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[3] ; H25 ; 5 ; 79 ; 42 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[4] ; H1 ; 2 ; 0 ; 42 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[5] ; H2 ; 2 ; 0 ; 42 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[6] ; C15 ; 4 ; 50 ; 47 ; 5 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[7] ; G25 ; 5 ; 79 ; 43 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_counter[8] ; G22 ; 5 ; 79 ; 42 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_counter[9] ; G18 ; 4 ; 58 ; 47 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_state[0] ; Y5 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_state[1] ; F19 ; 4 ; 62 ; 47 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_state[2] ; F17 ; 4 ; 56 ; 47 ; 5 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_state[3] ; Y2 ; 1 ; 0 ; 4 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_state[4] ; F10 ; 3 ; 23 ; 47 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_state[5] ; F9 ; 3 ; 21 ; 47 ; 4 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_hsync_state[6] ; F6 ; 3 ; 9 ; 47 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_line_counter[0] ; K6 ; 2 ; 0 ; 34 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_line_counter[1] ; K4 ; 2 ; 0 ; 37 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_line_counter[2] ; J22 ; 5 ; 79 ; 37 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_line_counter[3] ; M9 ; 2 ; 0 ; 29 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_line_counter[4] ; M8 ; 2 ; 0 ; 29 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_line_counter[5] ; M6 ; 2 ; 0 ; 31 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_line_counter[6] ; M5 ; 2 ; 0 ; 30 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_line_counter[7] ; L24 ; 5 ; 79 ; 33 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_line_counter[8] ; L25 ; 5 ; 79 ; 33 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_r ; L3 ; 2 ; 0 ; 33 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_set_column_counter ; Y23 ; 6 ; 79 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_set_hsync_counter ; F26 ; 5 ; 79 ; 44 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_set_line_counter ; F21 ; 4 ; 70 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_set_vsync_counter ; F24 ; 5 ; 79 ; 44 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_state_clk ; K3 ; 2 ; 0 ; 37 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle ; H3 ; 2 ; 0 ; 42 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[0] ; H26 ; 5 ; 79 ; 42 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[10] ; W24 ; 6 ; 79 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[11] ; AA26 ; 6 ; 79 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[12] ; AA21 ; 7 ; 72 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[13] ; C20 ; 4 ; 74 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[14] ; AB21 ; 7 ; 72 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[15] ; G24 ; 5 ; 79 ; 43 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[16] ; G23 ; 5 ; 79 ; 43 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[17] ; G21 ; 5 ; 79 ; 42 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[18] ; G20 ; 4 ; 62 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[19] ; G5 ; 2 ; 0 ; 44 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[1] ; W21 ; 6 ; 79 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[20] ; G3 ; 2 ; 0 ; 43 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[21] ; G1 ; 2 ; 0 ; 43 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[22] ; F25 ; 5 ; 79 ; 44 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[23] ; F23 ; 5 ; 79 ; 44 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[24] ; T19 ; 6 ; 79 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_toggle_counter[2] ; B23 ; 4 ; 76 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[3] ; A24 ; 4 ; 76 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[4] ; AF24 ; 7 ; 76 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[5] ; AC21 ; 7 ; 74 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[6] ; B3 ; 3 ; 1 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[7] ; AE22 ; 7 ; 76 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[8] ; W22 ; 6 ; 79 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[9] ; AF22 ; 7 ; 74 ; 0 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_v_enable ; H18 ; 4 ; 56 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync ; L5 ; 2 ; 0 ; 33 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_counter[0] ; G9 ; 3 ; 23 ; 47 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_counter[1] ; J23 ; 5 ; 79 ; 39 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[2] ; B11 ; 3 ; 29 ; 47 ; 5 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[3] ; J1 ; 2 ; 0 ; 38 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[4] ; AD11 ; 8 ; 29 ; 0 ; 5 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[5] ; G11 ; 3 ; 29 ; 47 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[6] ; J4 ; 2 ; 0 ; 39 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[7] ; G6 ; 2 ; 0 ; 44 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_counter[8] ; G4 ; 2 ; 0 ; 43 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_counter[9] ; G2 ; 2 ; 0 ; 43 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_state[0] ; F5 ; 3 ; 9 ; 47 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_state[1] ; F4 ; 2 ; 0 ; 45 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_state[2] ; F3 ; 2 ; 0 ; 45 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_state[3] ; M19 ; 5 ; 79 ; 29 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_state[4] ; M18 ; 5 ; 79 ; 29 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_state[5] ; M7 ; 2 ; 0 ; 31 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; d_vsync_state[6] ; M4 ; 2 ; 0 ; 30 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; g0_pin ; E23 ; 5 ; 79 ; 45 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; g1_pin ; T5 ; 1 ; 0 ; 15 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; g2_pin ; T24 ; 6 ; 79 ; 15 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; hsync_pin ; F1 ; 2 ; 0 ; 44 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; r0_pin ; E22 ; 4 ; 76 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; r1_pin ; T4 ; 1 ; 0 ; 15 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; r2_pin ; T7 ; 1 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[0] ; R8 ; 1 ; 0 ; 19 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[10] ; R4 ; 1 ; 0 ; 18 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[11] ; R6 ; 1 ; 0 ; 19 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[12] ; AA11 ; 8 ; 31 ; 0 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[13] ; T2 ; 1 ; 0 ; 17 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[1] ; R9 ; 1 ; 0 ; 19 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[2] ; R19 ; 6 ; 79 ; 16 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[3] ; R20 ; 6 ; 79 ; 19 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[4] ; R21 ; 6 ; 79 ; 19 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[5] ; R22 ; 6 ; 79 ; 18 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[6] ; R23 ; 6 ; 79 ; 18 ; 2 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[7] ; Y11 ; 8 ; 29 ; 0 ; 0 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[8] ; N7 ; 2 ; 0 ; 29 ; 3 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; seven_seg_pin[9] ; N8 ; 2 ; 0 ; 28 ; 1 ; no ; no ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
+; vsync_pin ; F2 ; 2 ; 0 ; 44 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ;
++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1 ; 11 / 61 ( 18 % ) ; 3.3V ; -- ;
+; 2 ; 35 / 59 ( 59 % ) ; 3.3V ; -- ;
+; 3 ; 9 / 54 ( 17 % ) ; 3.3V ; -- ;
+; 4 ; 13 / 56 ( 23 % ) ; 3.3V ; -- ;
+; 5 ; 28 / 59 ( 47 % ) ; 3.3V ; -- ;
+; 6 ; 12 / 61 ( 20 % ) ; 3.3V ; -- ;
+; 7 ; 7 / 57 ( 12 % ) ; 3.3V ; -- ;
+; 8 ; 3 / 54 ( 6 % ) ; 3.3V ; -- ;
+; 9 ; 0 / 6 ( 0 % ) ; 3.3V ; -- ;
+; 11 ; 0 / 6 ( 0 % ) ; 3.3V ; -- ;
++----------+------------------+---------------+--------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; Termination ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+
+; A2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; A3 ; 733 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A4 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; A5 ; 725 ; 3 ; reset ; input ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; A6 ; 717 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A7 ; 703 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A8 ; 702 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A9 ; 695 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A10 ; 684 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; A12 ; 656 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; A14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; A15 ; 640 ; 4 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; A16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; A17 ; 602 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A18 ; 589 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A19 ; 579 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A20 ; 571 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A21 ; 564 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A22 ; 554 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; A24 ; 552 ; 4 ; d_toggle_counter[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; A25 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AA1 ; 158 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA2 ; 157 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA3 ; 160 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA4 ; 159 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA5 ; 155 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA6 ; 154 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA7 ; 195 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA8 ; 214 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA9 ; 223 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA10 ; 227 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA11 ; 251 ; 8 ; seven_seg_pin[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; AA12 ; 269 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA13 ; 273 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA14 ; 271 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA15 ; 283 ; 7 ; ^nIO_PULLUP ; ; ; ; -- ; -- ; ; -- ; -- ;
+; AA16 ; 304 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA17 ; 316 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA18 ; 324 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA19 ; 334 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA20 ; 344 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA21 ; 350 ; 7 ; d_toggle_counter[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AA22 ; 386 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA23 ; 382 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA24 ; 381 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA25 ; 384 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA26 ; 383 ; 6 ; d_toggle_counter[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; AB1 ; 162 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB2 ; 161 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB3 ; 164 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB4 ; 163 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB5 ; 181 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB6 ; 184 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB7 ; 191 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB8 ; 203 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB9 ; 217 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB10 ; 229 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB11 ; 231 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB12 ; 268 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB13 ; 272 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB14 ; 270 ; 11 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB15 ; 292 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AB16 ; 309 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB17 ; 322 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB18 ; 323 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AB19 ; 336 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB20 ; 346 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB21 ; 351 ; 7 ; d_toggle_counter[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AB22 ; 365 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB23 ; 378 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB24 ; 377 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB25 ; 380 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB26 ; 379 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AC2 ; 165 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC3 ; 168 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC4 ; 167 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC5 ; 171 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC6 ; 185 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC7 ; 186 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC8 ; 201 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC9 ; 215 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC10 ; 224 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC11 ; 239 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC12 ; 257 ; 8 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; AC13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AC14 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AC15 ; 293 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC16 ; 307 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC17 ; 328 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC18 ; 338 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC19 ; 339 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC20 ; 349 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC21 ; 355 ; 7 ; d_toggle_counter[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AC22 ; 369 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC23 ; 368 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC24 ; 374 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC25 ; 376 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AD1 ; 166 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AD2 ; 172 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD3 ; 174 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD4 ; 178 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD5 ; 170 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD6 ; 188 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD7 ; 192 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD8 ; 204 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD9 ; 216 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD10 ; 220 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD11 ; 247 ; 8 ; d_vsync_counter[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AD12 ; 256 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD13 ; ; ; VCCG_PLL6 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; AD14 ; ; ; VCCA_PLL6 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; AD15 ; 302 ; 7 ; d_hsync_counter[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AD16 ; 310 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD17 ; 329 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD18 ; 335 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD19 ; 337 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD20 ; 353 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD21 ; 354 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AD22 ; 370 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD23 ; 364 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD24 ; 367 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD25 ; 373 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AD26 ; 375 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AE1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AE2 ; 173 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE3 ; 179 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE4 ; 176 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE5 ; 187 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AE6 ; 194 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE7 ; 189 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE8 ; 206 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE9 ; 218 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AE10 ; 222 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE11 ; 232 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE12 ; 259 ; 8 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; AE13 ; ; 11 ; VCC_PLL6_OUTA ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AE14 ; ; ; GNDG_PLL6 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AE15 ; 274 ; 7 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; AE16 ; 313 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE17 ; 319 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE18 ; 330 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE19 ; 340 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE20 ; 343 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE21 ; 352 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE22 ; 363 ; 7 ; d_toggle_counter[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AE23 ; 366 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE24 ; 371 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE25 ; 358 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AF2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AF3 ; 183 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF4 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AF5 ; 190 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF6 ; 198 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF7 ; 197 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF8 ; 207 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF9 ; 219 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF10 ; 230 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AF12 ; 258 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AF14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AF15 ; 276 ; 7 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; AF16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AF17 ; 315 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF18 ; 327 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF19 ; 331 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF20 ; 342 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF21 ; 347 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF22 ; 360 ; 7 ; d_toggle_counter[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AF23 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AF24 ; 362 ; 7 ; d_toggle_counter[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AF25 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B3 ; 740 ; 3 ; d_toggle_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B4 ; 736 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B5 ; 730 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B6 ; 716 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B7 ; 709 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B8 ; 704 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B9 ; 698 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B10 ; 694 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B11 ; 667 ; 3 ; d_vsync_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B12 ; 655 ; 3 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; B13 ; ; ; GNDG_PLL5 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B14 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B15 ; 638 ; 4 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; B16 ; 610 ; 4 ; d_hsync_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B17 ; 596 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B18 ; 582 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B19 ; 577 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B20 ; 567 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B21 ; 563 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B22 ; 551 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B23 ; 548 ; 4 ; d_toggle_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B24 ; 543 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B25 ; 544 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; C1 ; 0 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; C2 ; 738 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C3 ; 731 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C4 ; 742 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C5 ; 743 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C6 ; 729 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C7 ; 728 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C8 ; 710 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C9 ; 699 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C10 ; 692 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C11 ; 682 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C12 ; 658 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; C14 ; ; ; VCCG_PLL5 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; C15 ; 617 ; 4 ; d_hsync_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; C16 ; 605 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C17 ; 592 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C18 ; 581 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C19 ; 573 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C20 ; 559 ; 4 ; d_toggle_counter[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; C21 ; 566 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C22 ; 556 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C23 ; 550 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C24 ; 547 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C25 ; 539 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; C26 ; 541 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; D1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; D2 ; 1 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; D3 ; 744 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D4 ; 741 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D5 ; 735 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D6 ; 722 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D7 ; 727 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; D8 ; 712 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D9 ; 696 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; D10 ; 691 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D11 ; 683 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D12 ; 657 ; 3 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; D13 ; ; 9 ; VCC_PLL5_OUTA ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; D14 ; ; ; VCCA_PLL5 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; D15 ; 630 ; 4 ; #TRST ; input ; ; ; -- ; -- ; ; -- ; -- ;
+; D16 ; 604 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D17 ; 600 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D18 ; 583 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D19 ; 575 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D20 ; 562 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D21 ; 561 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D22 ; 546 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D23 ; 545 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D24 ; 538 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; D25 ; 540 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; D26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; E1 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E2 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E5 ; 726 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E6 ; 723 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E7 ; 713 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E8 ; 706 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E9 ; 697 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E10 ; 685 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E11 ; 662 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E12 ; 646 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E13 ; 642 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E14 ; 644 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E15 ; 629 ; 4 ; #TMS ; input ; ; ; -- ; -- ; ; -- ; -- ;
+; E16 ; 607 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E17 ; 597 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E18 ; 586 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E19 ; 578 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E20 ; 576 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E21 ; 569 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E22 ; 549 ; 4 ; r0_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; E23 ; 534 ; 5 ; g0_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; E24 ; 535 ; 5 ; b0_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; E25 ; 536 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E26 ; 537 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; F1 ; 8 ; 2 ; hsync_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; F2 ; 9 ; 2 ; vsync_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; F3 ; 6 ; 2 ; d_vsync_state[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; F4 ; 7 ; 2 ; d_vsync_state[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; F5 ; 720 ; 3 ; d_vsync_state[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; F6 ; 719 ; 3 ; d_hsync_state[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; F7 ; 707 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F8 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; F9 ; 690 ; 3 ; d_hsync_state[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; F10 ; 687 ; 3 ; d_hsync_state[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; F11 ; 659 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; F12 ; 645 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F13 ; 641 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F14 ; 643 ; 9 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F15 ; 632 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F16 ; 612 ; 4 ; ~DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F17 ; 599 ; 4 ; d_hsync_state[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; F18 ; 591 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; F19 ; 590 ; 4 ; d_hsync_state[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; F20 ; 584 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F21 ; 572 ; 4 ; d_set_line_counter ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; F22 ; 560 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; F23 ; 530 ; 5 ; d_toggle_counter[23] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; F24 ; 531 ; 5 ; d_set_vsync_counter ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; F25 ; 532 ; 5 ; d_toggle_counter[22] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; F26 ; 533 ; 5 ; d_set_hsync_counter ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G1 ; 12 ; 2 ; d_toggle_counter[21] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G2 ; 13 ; 2 ; d_vsync_counter[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G3 ; 14 ; 2 ; d_toggle_counter[20] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G4 ; 15 ; 2 ; d_vsync_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G5 ; 10 ; 2 ; d_toggle_counter[19] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G6 ; 11 ; 2 ; d_vsync_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G7 ; 700 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; G8 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; G9 ; 688 ; 3 ; d_vsync_counter[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; G10 ; 686 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; G11 ; 670 ; 3 ; d_vsync_counter[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; G12 ; 653 ; 3 ; ^DCLK ; ; ; ; -- ; -- ; ; -- ; -- ;
+; G13 ; ; ; TEMPDIODEn ; ; ; ; -- ; -- ; ; -- ; -- ;
+; G14 ; 636 ; 4 ; #TDO ; output ; ; ; -- ; -- ; ; -- ; -- ;
+; G15 ; 631 ; 4 ; #TCK ; input ; ; ; -- ; -- ; ; -- ; -- ;
+; G16 ; 622 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; G17 ; 601 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; G18 ; 594 ; 4 ; d_hsync_counter[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; G19 ; 585 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; G20 ; 587 ; 4 ; d_toggle_counter[18] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; G21 ; 522 ; 5 ; d_toggle_counter[17] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G22 ; 523 ; 5 ; d_hsync_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G23 ; 526 ; 5 ; d_toggle_counter[16] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G24 ; 527 ; 5 ; d_toggle_counter[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G25 ; 528 ; 5 ; d_hsync_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; G26 ; 529 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H1 ; 16 ; 2 ; d_hsync_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; H2 ; 17 ; 2 ; d_hsync_counter[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; H3 ; 18 ; 2 ; d_toggle ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; H4 ; 19 ; 2 ; d_hsync_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; H5 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H6 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H7 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H8 ; 20 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; H9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; H10 ; 675 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; H11 ; 654 ; 3 ; ^CONF_DONE ; ; ; ; -- ; -- ; ; -- ; -- ;
+; H12 ; 652 ; 3 ; ^nCONFIG ; ; ; ; -- ; -- ; ; -- ; -- ;
+; H13 ; 651 ; 3 ; ^nSTATUS ; ; ; ; -- ; -- ; ; -- ; -- ;
+; H14 ; ; ; TEMPDIODEp ; ; ; ; -- ; -- ; ; -- ; -- ;
+; H15 ; 635 ; 4 ; #TDI ; input ; ; ; -- ; -- ; ; -- ; -- ;
+; H16 ; 621 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; H17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; H18 ; 603 ; 4 ; d_v_enable ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; H19 ; 506 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H20 ; 505 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H21 ; 514 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H22 ; 513 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H23 ; 518 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H24 ; 517 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H25 ; 524 ; 5 ; d_hsync_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; H26 ; 525 ; 5 ; d_toggle_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; J1 ; 34 ; 2 ; d_vsync_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; J2 ; 33 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J3 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J4 ; 29 ; 2 ; d_vsync_counter[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; J5 ; 36 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J6 ; 35 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J7 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J8 ; 48 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; J12 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; J13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J15 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; J16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; J17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J18 ; 521 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; J19 ; 494 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J20 ; 493 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J21 ; 504 ; 5 ; d_h_enable ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; J22 ; 503 ; 5 ; d_line_counter[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; J23 ; 512 ; 5 ; d_vsync_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; J24 ; 511 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J25 ; 508 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J26 ; 507 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K1 ; 46 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K2 ; 45 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K3 ; 38 ; 2 ; d_state_clk ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; K4 ; 37 ; 2 ; d_line_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; K5 ; 50 ; 2 ; d_column_counter[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; K6 ; 49 ; 2 ; d_line_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; K7 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K8 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K9 ; 47 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; K12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; K14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; K16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; K18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K19 ; 486 ; 5 ; d_column_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; K20 ; 485 ; 5 ; d_b ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; K21 ; 490 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K22 ; 489 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K23 ; 492 ; 5 ; d_column_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; K24 ; 491 ; 5 ; d_g ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; K25 ; 496 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K26 ; 495 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; L1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; L2 ; 54 ; 2 ; d_column_counter[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L3 ; 53 ; 2 ; d_r ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L4 ; 56 ; 2 ; d_column_counter[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L5 ; 55 ; 2 ; d_vsync ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L6 ; 60 ; 2 ; d_column_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L7 ; 59 ; 2 ; d_hsync ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L8 ; 61 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; L9 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; L10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; L12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; L14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; L16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; L18 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; L19 ; 480 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; L20 ; 482 ; 5 ; d_column_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L21 ; 481 ; 5 ; d_column_counter[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L22 ; 478 ; 5 ; d_column_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L23 ; 479 ; 5 ; d_column_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L24 ; 488 ; 5 ; d_line_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L25 ; 487 ; 5 ; d_line_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; L26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; M1 ; 81 ; 2 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; M2 ; ; ; VCCG_PLL1 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M3 ; ; ; VCCA_PLL1 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M4 ; 66 ; 2 ; d_vsync_state[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; M5 ; 67 ; 2 ; d_line_counter[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; M6 ; 62 ; 2 ; d_line_counter[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; M7 ; 63 ; 2 ; d_vsync_state[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; M8 ; 72 ; 2 ; d_line_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; M9 ; 73 ; 2 ; d_line_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; M11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; M13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; M15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; M17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M18 ; 468 ; 5 ; d_vsync_state[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; M19 ; 469 ; 5 ; d_vsync_state[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; M20 ; 470 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; M21 ; 471 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; M22 ; 474 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; M23 ; 475 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; M24 ; 462 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; M25 ; 463 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; M26 ; 460 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; N1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N2 ; 78 ; 2 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; N3 ; 79 ; 2 ; board_clk ; input ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; N4 ; ; ; GNDG_PLL1 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N5 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N6 ; 70 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; N7 ; 71 ; 2 ; seven_seg_pin[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; N8 ; 77 ; 2 ; seven_seg_pin[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N19 ; 453 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; N20 ; 464 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; N21 ; 465 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; N22 ; ; ; GNDG_PLL4 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N23 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N24 ; ; ; VCCG_PLL4 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N25 ; ; ; VCCA_PLL4 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P2 ; ; ; GNDG_PLL2 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P3 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P4 ; ; ; VCCG_PLL2 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P5 ; ; ; VCCA_PLL2 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P6 ; 88 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; P7 ; 89 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; P8 ; 76 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P19 ; 452 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; P20 ; 448 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; P21 ; 449 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; P22 ; ; ; VCCA_PLL3 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P23 ; ; ; VCCG_PLL3 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P24 ; 457 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; P25 ; 458 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; P26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R1 ; 82 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; R2 ; 83 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; R3 ; 84 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; R4 ; 94 ; 1 ; seven_seg_pin[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; R5 ; 95 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R6 ; 90 ; 1 ; seven_seg_pin[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; R7 ; 91 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R8 ; 92 ; 1 ; seven_seg_pin[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; R9 ; 93 ; 1 ; seven_seg_pin[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; R10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R18 ; 443 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; R19 ; 436 ; 6 ; seven_seg_pin[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; R20 ; 450 ; 6 ; seven_seg_pin[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; R21 ; 451 ; 6 ; seven_seg_pin[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; R22 ; 446 ; 6 ; seven_seg_pin[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; R23 ; 447 ; 6 ; seven_seg_pin[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; R24 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R25 ; ; ; GNDG_PLL3 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R26 ; 459 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; T1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; T2 ; 100 ; 1 ; seven_seg_pin[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; T3 ; 99 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T4 ; 108 ; 1 ; r1_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; T5 ; 107 ; 1 ; g1_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; T6 ; 106 ; 1 ; b1_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; T7 ; 105 ; 1 ; r2_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; T8 ; 98 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; T9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; T11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; T13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; T15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; T17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; T18 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; T19 ; 435 ; 6 ; d_toggle_counter[24] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; T20 ; 432 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T21 ; 431 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T22 ; 442 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T23 ; 441 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T24 ; 434 ; 6 ; g2_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; T25 ; 433 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; U1 ; 112 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U2 ; 111 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U3 ; 116 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U4 ; 115 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U5 ; 110 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U6 ; 109 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U7 ; 114 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U8 ; 113 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U9 ; 117 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; U12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; U14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; U16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; U18 ; 428 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U19 ; 427 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U20 ; 424 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U21 ; 430 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U22 ; 429 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U23 ; 418 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U24 ; 417 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U25 ; 426 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U26 ; 425 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V1 ; 132 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V2 ; 133 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V3 ; 136 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V4 ; 137 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V5 ; 124 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V6 ; 123 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V7 ; 127 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; V8 ; 118 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; V12 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; V13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V15 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; V16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; V17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V19 ; 423 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V20 ; 414 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; V21 ; 406 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V22 ; 407 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V23 ; 404 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V24 ; 405 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V25 ; 408 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V26 ; 409 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W1 ; 140 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W2 ; 141 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W3 ; 148 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W4 ; 149 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W5 ; 134 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W6 ; 135 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W7 ; 138 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W8 ; 139 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W9 ; 212 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; W10 ; 228 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; W11 ; 255 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; W12 ; 260 ; 8 ; PLL_ENA ; ; ; ; -- ; -- ; ; -- ; -- ;
+; W13 ; 263 ; 8 ; ^MSEL2 ; ; ; ; -- ; -- ; ; -- ; -- ;
+; W14 ; 279 ; 7 ; ^nCEO ; ; ; ; -- ; -- ; ; -- ; -- ;
+; W15 ; 282 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; W16 ; 285 ; 7 ; ^PORSEL ; ; ; ; -- ; -- ; ; -- ; -- ;
+; W17 ; 311 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; W18 ; 321 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; W19 ; 402 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W20 ; 403 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W21 ; 394 ; 6 ; d_toggle_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; W22 ; 395 ; 6 ; d_toggle_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; W23 ; 392 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W24 ; 393 ; 6 ; d_toggle_counter[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; W25 ; 400 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W26 ; 401 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y1 ; 153 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y2 ; 152 ; 1 ; d_hsync_state[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; Y3 ; 146 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y4 ; 147 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y5 ; 151 ; 1 ; d_hsync_state[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; Y6 ; 150 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y7 ; 156 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; Y8 ; 210 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y9 ; 209 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y10 ; 226 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y11 ; 244 ; 8 ; seven_seg_pin[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; Y ; no ; Off ;
+; Y12 ; 261 ; 8 ; ^MSEL0 ; ; ; ; -- ; -- ; ; -- ; -- ;
+; Y13 ; 262 ; 8 ; ^MSEL1 ; ; ; ; -- ; -- ; ; -- ; -- ;
+; Y14 ; 278 ; 7 ; ^nCE ; ; ; ; -- ; -- ; ; -- ; -- ;
+; Y15 ; 284 ; 7 ; ^VCCSEL ; ; ; ; -- ; -- ; ; -- ; -- ;
+; Y16 ; 297 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y17 ; 314 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y18 ; 317 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y19 ; 325 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y20 ; 333 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y21 ; 385 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; Y22 ; 387 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y23 ; 391 ; 6 ; d_set_column_counter ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; Y ; no ; Off ;
+; Y24 ; 390 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y25 ; 389 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y26 ; 388 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------------+
+; PLL Summary ;
++-------------------------------+----------------------------------------+
+; Name ; vpll:inst1|altpll:altpll_component|pll ;
++-------------------------------+----------------------------------------+
+; SDC pin name ; inst1|altpll_component|pll ;
+; PLL type ; Fast ;
+; Scan chain ; None ;
+; PLL mode ; Normal ;
+; Feedback source ; -- ;
+; Compensate clock ; clock0 ;
+; Compensated input/output pins ; -- ;
+; Switchover on loss of clock ; -- ;
+; Switchover counter ; -- ;
+; Primary clock ; -- ;
+; Input frequency 0 ; 33.33 MHz ;
+; Input frequency 1 ; -- ;
+; Nominal PFD frequency ; 16.7 MHz ;
+; Nominal VCO frequency ; 516.5 MHz ;
+; Freq min lock ; 20.0 MHz ;
+; Freq max lock ; 64.52 MHz ;
+; Clock Offset ; -707 ps ;
+; M VCO Tap ; 3 ;
+; M Initial ; 1 ;
+; M value ; 31 ;
+; N value ; 2 ;
+; M counter delay ; -- ;
+; N counter delay ; -- ;
+; M2 value ; -- ;
+; N2 value ; -- ;
+; SS counter ; -- ;
+; Downspread ; -- ;
+; Spread frequency ; -- ;
+; Charge pump current ; 20 uA ;
+; Loop filter resistance ; 1.021000 KOhm ;
+; Loop filter capacitance ; 10 pF ;
+; Freq zero ; 0.240 MHz ;
+; Bandwidth ; 200 KHz ;
+; Freq pole ; 15.844 MHz ;
+; enable0 counter ; -- ;
+; enable1 counter ; -- ;
+; Real time reconfigurable ; -- ;
+; Scan chain MIF file ; -- ;
+; Preserve PLL counter order ; Off ;
+; PLL location ; PLL_1 ;
+; Inclk0 signal ; board_clk ;
+; Inclk1 signal ; -- ;
+; Inclk0 signal type ; Dedicated Pin ;
+; Inclk1 signal type ; -- ;
++-------------------------------+----------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage ;
++------------------------------------------+--------------+------+-----+------------------+--------------+-------+------------+---------+---------------+---------------+------------+---------+---------+-----------------------------------+
+; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Delay ; Duty Cycle ; Counter ; Counter Delay ; Counter Value ; High / Low ; Initial ; VCO Tap ; SDC Pin Name ;
++------------------------------------------+--------------+------+-----+------------------+--------------+-------+------------+---------+---------------+---------------+------------+---------+---------+-----------------------------------+
+; vpll:inst1|altpll:altpll_component|_clk0 ; clock0 ; 31 ; 38 ; 27.19 MHz ; -7 (-725 ps) ; 0 ps ; 50/50 ; G0 ; -- ; 19 ; 10/9 Odd ; 1 ; 0 ; inst1|altpll_component|pll|clk[0] ;
++------------------------------------------+--------------+------+-----+------------------+--------------+-------+------------+---------+---------------+---------------+------------+---------+---------+-----------------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++----------------------------------+-------+------------------------------------+
+; 3.3-V LVTTL ; 10 pF ; Not Available ;
+; 3.3-V LVCMOS ; 10 pF ; Not Available ;
+; 2.5 V ; 10 pF ; Not Available ;
+; 1.8 V ; 10 pF ; Not Available ;
+; 1.5 V ; 10 pF ; Not Available ;
+; GTL ; 30 pF ; 25 Ohm (Parallel) ;
+; GTL+ ; 30 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI-X ; 8 pF ; 25 Ohm (Parallel) ;
+; Compact PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; AGP 1X ; 10 pF ; Not Available ;
+; AGP 2X ; 10 pF ; Not Available ;
+; CTT ; 30 pF ; 50 Ohm (Parallel) ;
+; SSTL-3 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-3 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; 1.5-V HSTL Class I ; 20 pF ; 50 Ohm (Parallel) ;
+; 1.5-V HSTL Class II ; 20 pF ; 25 Ohm (Parallel) ;
+; 1.8-V HSTL Class I ; 20 pF ; 50 Ohm (Parallel) ;
+; 1.8-V HSTL Class II ; 20 pF ; 25 Ohm (Parallel) ;
+; LVDS ; 4 pF ; 100 Ohm (Differential) ;
+; Differential LVPECL ; 4 pF ; 100 Ohm (Differential) ;
+; 3.3-V PCML ; 4 pF ; 50 Ohm (Parallel) ;
+; HyperTransport ; 4 pF ; 100 Ohm (Differential) ;
+; Differential 1.5-V HSTL Class I ; 20 pF ; (See 1.5-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class I ; 20 pF ; (See 1.8-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class II ; 20 pF ; (See 1.8-V HSTL Class II) ;
+; Differential SSTL-2 ; 30 pF ; (See SSTL-2) ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++--------------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++--------------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
+; |vga_pll ; 173 (1) ; 83 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 117 ; 0 ; 90 (1) ; 0 (0) ; 83 (0) ; 61 (0) ; 3 (0) ; |vga_pll ; work ;
+; |vga:inst| ; 172 (2) ; 83 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 116 ; 0 ; 89 (0) ; 0 (0) ; 83 (2) ; 61 (0) ; 3 (0) ; |vga_pll|vga:inst ; work ;
+; |vga_control:vga_control_unit| ; 43 (43) ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 0 (0) ; 24 (24) ; 21 (21) ; 0 (0) ; |vga_pll|vga:inst|vga_control:vga_control_unit ; work ;
+; |vga_driver:vga_driver_unit| ; 127 (127) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 70 (70) ; 0 (0) ; 57 (57) ; 40 (40) ; 3 (3) ; |vga_pll|vga:inst|vga_driver:vga_driver_unit ; work ;
+; |vpll:inst1| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1 ; work ;
+; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1|altpll:altpll_component ; work ;
++--------------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; Core to Output Register ; Clock Enable to Output Enable Register ; Clock Enable to Output Register ; Clock Enable to Input Register ; TCO ; TCOE ; Falling Edge Output Enable ;
++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+
+; board_clk ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; d_hsync ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_set_column_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_set_line_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_set_hsync_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_set_vsync_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_r ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_g ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_b ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_h_enable ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_v_enable ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_state_clk ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; r0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; r1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; r2_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; g0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; g1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; g2_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; b0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; b1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; hsync_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; vsync_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[24] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[23] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[22] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[21] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[20] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[19] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[18] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[17] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[16] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[15] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[14] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[13] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[12] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[11] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[10] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[13] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[12] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[11] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[10] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; reset ; Input ; ON ; ON ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++--------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++--------------------------------------------------------------------------------+-------------------+---------+
+; board_clk ; ; ;
+; vga:inst|reset_pin_in ; ; ;
+; - vga:inst|vga_driver:vga_driver_unit|vsync_state_6_ ; 0 ; ON ;
+; - vga:inst|vga_driver:vga_driver_unit|h_sync_Z ; 0 ; ON ;
+; - vga:inst|vga_driver:vga_driver_unit|v_sync_Z ; 0 ; ON ;
+; - vga:inst|dly_counter_0_ ; 0 ; ON ;
+; - vga:inst|dly_counter_1_ ; 0 ; ON ;
+; - vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ ; 0 ; ON ;
+; - vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ ; 0 ; ON ;
+; - vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ ; 0 ; ON ;
+; - vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ ; 0 ; ON ;
++--------------------------------------------------------------------------------+-------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++----------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++----------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+; board_clk ; PIN_N3 ; 1 ; Clock ; no ; -- ; -- ;
+; vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1 ; LC_X72_Y5_N9 ; 22 ; Sync. clear ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|G_16_i ; LC_X30_Y38_N6 ; 10 ; Sync. clear ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|G_2_i ; LC_X52_Y41_N3 ; 10 ; Sync. clear ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; LC_X30_Y38_N2 ; 10 ; Sync. clear ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ; LC_X30_Y39_N9 ; 1 ; Clock enable ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; LC_X52_Y41_N9 ; 6 ; Clock enable ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; LC_X30_Y39_N8 ; 9 ; Sync. clear ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x ; LC_X30_Y38_N3 ; 53 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK12 ;
+; vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; LC_X52_Y41_N2 ; 11 ; Sync. load ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9 ; LC_X30_Y38_N8 ; 11 ; Sync. load ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ; LC_X42_Y42_N7 ; 1 ; Clock enable ; no ; -- ; -- ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa ; LC_X28_Y39_N6 ; 5 ; Clock enable ; no ; -- ; -- ;
+; vpll:inst1|altpll:altpll_component|_clk0 ; PLL_1 ; 84 ; Clock ; yes ; Global Clock ; GCLK1 ;
++----------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++---------------------------------------------------------+---------------+---------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
++---------------------------------------------------------+---------------+---------+----------------------+------------------+
+; vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x ; LC_X30_Y38_N3 ; 53 ; Global Clock ; GCLK12 ;
+; vpll:inst1|altpll:altpll_component|_clk0 ; PLL_1 ; 84 ; Global Clock ; GCLK1 ;
++---------------------------------------------------------+---------------+---------+----------------------+------------------+
+
+
++--------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++----------------------------------------------------------------------+---------+
+; Name ; Fan-Out ;
++----------------------------------------------------------------------+---------+
+; vga:inst|vga_control:vga_control_unit|toggle_sig_0_0_0_g1 ; 22 ;
+; ~STRATIX_FITTER_CREATED_GND~I ; 14 ;
+; vga:inst|vga_driver:vga_driver_unit|un9_vsync_counterlt9 ; 11 ;
+; vga:inst|vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; 11 ;
+; vga:inst|vga_driver:vga_driver_unit|G_16_i ; 10 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa ; 10 ;
+; vga:inst|vga_driver:vga_driver_unit|G_2_i ; 10 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa ; 10 ;
+; vga:inst|vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; 10 ;
+; vga:inst|vga_driver:vga_driver_unit|un10_column_counter_siglto9 ; 10 ;
+; reset ; 9 ;
+; vga:inst|vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; 9 ;
+; vga:inst|vga_driver:vga_driver_unit|un10_line_counter_siglto8 ; 9 ;
+; vga:inst|dly_counter[1] ; 9 ;
+; vga:inst|dly_counter[0] ; 9 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; 9 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; 9 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; 7 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; 7 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; 7 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; 6 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa ; 5 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; 5 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; 5 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; 5 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; 5 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; 5 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_counter_cout[4] ; 5 ;
+; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; 5 ;
++----------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------+
+; Interconnect Usage Summary ;
++-----------------------------+-------------------------+
+; Interconnect Resource Type ; Usage ;
++-----------------------------+-------------------------+
+; C16 interconnects ; 78 / 4,620 ( 2 % ) ;
+; C4 interconnects ; 125 / 69,840 ( < 1 % ) ;
+; C8 interconnects ; 45 / 15,568 ( < 1 % ) ;
+; DIFFIOCLKs ; 0 / 16 ( 0 % ) ;
+; DQS bus muxes ; 0 / 102 ( 0 % ) ;
+; DQS-16 I/O buses ; 0 / 8 ( 0 % ) ;
+; DQS-32 I/O buses ; 0 / 4 ( 0 % ) ;
+; DQS-8 I/O buses ; 0 / 20 ( 0 % ) ;
+; Direct links ; 47 / 104,060 ( < 1 % ) ;
+; Fast regional clocks ; 0 / 8 ( 0 % ) ;
+; Global clocks ; 2 / 16 ( 13 % ) ;
+; I/O buses ; 25 / 320 ( 8 % ) ;
+; LUT chains ; 6 / 23,094 ( < 1 % ) ;
+; Local routing interconnects ; 122 / 25,660 ( < 1 % ) ;
+; R24 interconnects ; 106 / 4,692 ( 2 % ) ;
+; R4 interconnects ; 189 / 141,520 ( < 1 % ) ;
+; R8 interconnects ; 78 / 22,956 ( < 1 % ) ;
+; Regional clocks ; 0 / 16 ( 0 % ) ;
++-----------------------------+-------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements ;
++--------------------------------------------+------------------------------+
+; Number of Logic Elements (Average = 7.86) ; Number of LABs (Total = 22) ;
++--------------------------------------------+------------------------------+
+; 1 ; 3 ;
+; 2 ; 0 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 2 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
+; 9 ; 1 ;
+; 10 ; 14 ;
++--------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+------------------------------+
+; LAB-wide Signals (Average = 1.82) ; Number of LABs (Total = 22) ;
++------------------------------------+------------------------------+
+; 1 Async. clear ; 4 ;
+; 1 Clock ; 19 ;
+; 1 Clock enable ; 5 ;
+; 1 Sync. clear ; 10 ;
+; 1 Sync. load ; 2 ;
++------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++---------------------------------------------+------------------------------+
+; Number of Signals Sourced (Average = 7.91) ; Number of LABs (Total = 22) ;
++---------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 2 ;
+; 2 ; 1 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
+; 5 ; 1 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
+; 9 ; 3 ;
+; 10 ; 9 ;
+; 11 ; 3 ;
++---------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out (Average = 6.00) ; Number of LABs (Total = 22) ;
++-------------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 2 ;
+; 2 ; 2 ;
+; 3 ; 0 ;
+; 4 ; 3 ;
+; 5 ; 2 ;
+; 6 ; 2 ;
+; 7 ; 3 ;
+; 8 ; 4 ;
+; 9 ; 1 ;
+; 10 ; 3 ;
++-------------------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+------------------------------+
+; Number of Distinct Inputs (Average = 10.77) ; Number of LABs (Total = 22) ;
++----------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
+; 5 ; 2 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 2 ;
+; 9 ; 2 ;
+; 10 ; 2 ;
+; 11 ; 3 ;
+; 12 ; 0 ;
+; 13 ; 3 ;
+; 14 ; 1 ;
+; 15 ; 1 ;
+; 16 ; 0 ;
+; 17 ; 0 ;
+; 18 ; 0 ;
+; 19 ; 1 ;
+; 20 ; 0 ;
+; 21 ; 0 ;
+; 22 ; 0 ;
+; 23 ; 2 ;
++----------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+--------------------------+
+; Option ; Setting ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Error detection CRC ; Off ;
+; nWS, nRS, nCS, CS ; Unreserved ;
+; RDYnBUSY ; Unreserved ;
+; Data[7..1] ; Unreserved ;
+; Data[0] ; As input tri-stated ;
+; Reserve all unused pins ; As output driving ground ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:54:43 2009
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
+Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
+Info: Selected device EP1S25F672C6 for design "vga_pll"
+Warning: Output port clk0 of PLL "vpll:inst1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP1S10F672C6 is compatible
+ Info: Device EP1S20F672C6 is compatible
+ Info: Device EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE is compatible
+Info: Fitter converted 1 user pins into dedicated programming pins
+ Info: Pin ~DATA0~ is reserved at location F16
+Warning: No exact pin location assignment(s) for 26 pins of 117 total pins
+ Info: Pin d_hsync_counter[6] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[5] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[4] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[3] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[2] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[1] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[14] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[13] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[12] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[11] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[10] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[9] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[8] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[7] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[6] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[5] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[4] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[3] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[2] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[1] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[6] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[5] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[4] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[3] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[2] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[1] not assigned to an exact location on the device
+Info: Fitter is using the Classic Timing Analyzer
+Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
+Info: Completed User Assigned Global Signals Promotion Operation
+Info: Implementing parameter values for PLL "vpll:inst1|altpll:altpll_component|pll"
+ Info: Implementing clock multiplication of 31, clock division of 38, and phase shift of 0 degrees (-18 ps) for vpll:inst1|altpll:altpll_component|_clk0 port
+Info: Promoted PLL clock signals
+ Info: Promoted signal "vpll:inst1|altpll:altpll_component|_clk0" to use global clock
+Info: Completed PLL Placement Operation
+Info: Automatically promoted some destinations of signal "vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x" to use Global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|hsync_state_6_" may be non-global or may not use global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_0_" may be non-global or may not use global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_1_" may be non-global or may not use global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|v_enable_sig_Z" may be non-global or may not use global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|h_enable_sig_Z" may be non-global or may not use global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_5_" may be non-global or may not use global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_4_" may be non-global or may not use global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_3_" may be non-global or may not use global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|vsync_state_2_" may be non-global or may not use global clock
+ Info: Destination "vga:inst|vga_driver:vga_driver_unit|hsync_state_5_" may be non-global or may not use global clock
+ Info: Limited to 10 non-global destinations
+Info: Completed Auto Global Promotion Operation
+Info: Starting register packing
+Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
+Info: Finished register packing
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 0 input, 26 output, 0 bidirectional)
+ Info: I/O standards used: 3.3-V LVTTL.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 11 total pin(s) used -- 50 pins available
+ Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 31 total pin(s) used -- 28 pins available
+ Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 6 total pin(s) used -- 48 pins available
+ Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used -- 48 pins available
+ Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used -- 33 pins available
+ Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used -- 53 pins available
+ Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 57 pins available
+ Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used -- 52 pins available
+ Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
+ Info: I/O bank number 11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
+Info: Fitter preparation operations ending: elapsed time is 00:00:02
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:03
+Info: Slack time is 29.678 ns between source register "vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3" and destination register "vga:inst|vga_control:vga_control_unit|r"
+ Info: + Largest register to register requirement is 36.591 ns
+ Info: Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.138 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst|vga_control:vga_control_unit|r'
+ Info: Total cell delay = 0.560 ns ( 26.19 % )
+ Info: Total interconnect delay = 1.578 ns ( 73.81 % )
+ Info: Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.138 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst|vga_control:vga_control_unit|r'
+ Info: Total cell delay = 0.560 ns ( 26.19 % )
+ Info: Total interconnect delay = 1.578 ns ( 73.81 % )
+ Info: Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.138 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 10; REG Node = 'vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3'
+ Info: Total cell delay = 0.560 ns ( 26.19 % )
+ Info: Total interconnect delay = 1.578 ns ( 73.81 % )
+ Info: Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.138 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 10; REG Node = 'vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3'
+ Info: Total cell delay = 0.560 ns ( 26.19 % )
+ Info: Total interconnect delay = 1.578 ns ( 73.81 % )
+ Info: Micro clock to output delay of source is 0.176 ns
+ Info: Micro setup delay of destination is 0.010 ns
+ Info: - Longest register to register delay is 6.913 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 10; REG Node = 'vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3'
+ Info: 2: + IC(1.006 ns) + CELL(0.087 ns) = 1.093 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga:inst|vga_control:vga_control_unit|un17_v_enablelto3'
+ Info: 3: + IC(1.825 ns) + CELL(0.087 ns) = 3.005 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a'
+ Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 3.519 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4'
+ Info: 5: + IC(3.030 ns) + CELL(0.364 ns) = 6.913 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst|vga_control:vga_control_unit|r'
+ Info: Total cell delay = 0.625 ns ( 9.04 % )
+ Info: Total interconnect delay = 6.288 ns ( 90.96 % )
+Info: Estimated most critical path is register to register delay of 6.913 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y42; Fanout = 10; REG Node = 'vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3'
+ Info: 2: + IC(1.006 ns) + CELL(0.087 ns) = 1.093 ns; Loc. = LAB_X18_Y42; Fanout = 1; COMB Node = 'vga:inst|vga_control:vga_control_unit|un17_v_enablelto3'
+ Info: 3: + IC(1.825 ns) + CELL(0.087 ns) = 3.005 ns; Loc. = LAB_X28_Y35; Fanout = 1; COMB Node = 'vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a'
+ Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 3.519 ns; Loc. = LAB_X28_Y35; Fanout = 2; COMB Node = 'vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4'
+ Info: 5: + IC(3.030 ns) + CELL(0.364 ns) = 6.913 ns; Loc. = LAB_X72_Y6; Fanout = 4; REG Node = 'vga:inst|vga_control:vga_control_unit|r'
+ Info: Total cell delay = 0.625 ns ( 9.04 % )
+ Info: Total interconnect delay = 6.288 ns ( 90.96 % )
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources
+ Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X22_Y36 to location X33_Y47
+Info: Fitter routing operations ending: elapsed time is 00:00:01
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Completed Fixed Delay Chain Operation
+Info: Started post-fitting delay annotation
+Info: Delay annotation completed successfully
+Info: Completed Auto Delay Chain Operation
+Warning: Following 14 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
+ Info: Pin d_g has GND driving its datain port
+ Info: Pin g0_pin has GND driving its datain port
+ Info: Pin g1_pin has GND driving its datain port
+ Info: Pin g2_pin has GND driving its datain port
+ Info: Pin d_toggle_counter[24] has GND driving its datain port
+ Info: Pin d_toggle_counter[23] has GND driving its datain port
+ Info: Pin d_toggle_counter[22] has GND driving its datain port
+ Info: Pin d_toggle_counter[21] has GND driving its datain port
+ Info: Pin seven_seg_pin[13] has GND driving its datain port
+ Info: Pin seven_seg_pin[6] has GND driving its datain port
+ Info: Pin seven_seg_pin[5] has GND driving its datain port
+ Info: Pin seven_seg_pin[4] has GND driving its datain port
+ Info: Pin seven_seg_pin[3] has GND driving its datain port
+ Info: Pin seven_seg_pin[0] has GND driving its datain port
+Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
+Info: Generated suppressed messages file /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/vga_pll.fit.smsg
+Info: Quartus II Fitter was successful. 0 errors, 4 warnings
+ Info: Peak virtual memory: 320 megabytes
+ Info: Processing ended: Wed Oct 28 14:55:12 2009
+ Info: Elapsed time: 00:00:29
+ Info: Total CPU time (on all processors): 00:00:29
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/vga_pll.fit.smsg.
+
+
--- /dev/null
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Start inferring scan chains for DSP blocks
+Extra Info: Inferring scan chains for DSP blocks is complete
+Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density
+Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks
--- /dev/null
+Fitter Status : Successful - Wed Oct 28 14:55:12 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga_pll
+Top-level Entity Name : vga_pll
+Family : Stratix
+Device : EP1S25F672C6
+Timing Models : Final
+Total logic elements : 173 / 25,660 ( < 1 % )
+Total pins : 117 / 474 ( 25 % )
+Total virtual pins : 0
+Total memory bits : 0 / 1,944,576 ( 0 % )
+DSP block 9-bit elements : 0 / 80 ( 0 % )
+Total PLLs : 1 / 6 ( 17 % )
+Total DLLs : 0 / 2 ( 0 % )
--- /dev/null
+Flow report for vga_pll
+Wed Oct 28 14:55:41 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------+
+; Flow Summary ;
++--------------------------+------------------------------------------+
+; Flow Status ; Successful - Wed Oct 28 14:55:41 2009 ;
+; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
+; Revision Name ; vga_pll ;
+; Top-level Entity Name ; vga_pll ;
+; Family ; Stratix ;
+; Device ; EP1S25F672C6 ;
+; Timing Models ; Final ;
+; Met timing requirements ; Yes ;
+; Total logic elements ; 173 / 25,660 ( < 1 % ) ;
+; Total pins ; 117 / 474 ( 25 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 1,944,576 ( 0 % ) ;
+; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ;
+; Total PLLs ; 1 / 6 ( 17 % ) ;
+; Total DLLs ; 0 / 2 ( 0 % ) ;
++--------------------------+------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 10/28/2009 14:54:36 ;
+; Main task ; Compilation ;
+; Revision Name ; vga_pll ;
++-------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+-----------------------------+---------------+-------------+----------------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+-----------------------------+---------------+-------------+----------------------+
+; COMPILER_SIGNATURE_ID ; 91815332912.125673807629382 ; -- ; -- ; -- ;
+; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Synplify Pro ; <None> ; -- ; -- ;
+; EDA_INPUT_DATA_FORMAT ; Vqm ; -- ; -- ; eda_design_synthesis ;
+; EDA_LMF_FILE ; synplcty.lmf ; -- ; -- ; eda_design_synthesis ;
+; EDA_OUTPUT_DATA_FORMAT ; Verilog ; -- ; -- ; eda_simulation ;
+; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
+; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+-----------------------------+---------------+-------------+----------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:07 ; 1.0 ; -- ; 00:00:03 ;
+; Fitter ; 00:00:29 ; 1.0 ; -- ; 00:00:29 ;
+; Assembler ; 00:00:18 ; 1.0 ; -- ; 00:00:18 ;
+; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; -- ; 00:00:00 ;
+; EDA Netlist Writer ; 00:00:01 ; 1.0 ; -- ; 00:00:01 ;
+; Total ; 00:00:55 ; -- ; -- ; 00:00:51 ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++-------------------------+------------------+---------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++-------------------------+------------------+---------+------------+----------------+
+; Analysis & Synthesis ; ti15 ; Red Hat ; 5 ; x86_64 ;
+; Fitter ; ti15 ; Red Hat ; 5 ; x86_64 ;
+; Assembler ; ti15 ; Red Hat ; 5 ; x86_64 ;
+; Classic Timing Analyzer ; ti15 ; Red Hat ; 5 ; x86_64 ;
+; EDA Netlist Writer ; ti15 ; Red Hat ; 5 ; x86_64 ;
++-------------------------+------------------+---------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll
+quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
+quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
+quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only
+quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
+
+
+
--- /dev/null
+Analysis & Synthesis report for vga_pll
+Wed Oct 28 14:54:40 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. Registers Removed During Synthesis
+ 8. General Register Statistics
+ 9. Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component
+ 10. altpll Parameter Settings by Entity Instance
+ 11. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++-----------------------------+------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Wed Oct 28 14:54:40 2009 ;
+; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
+; Revision Name ; vga_pll ;
+; Top-level Entity Name ; vga_pll ;
+; Family ; Stratix ;
+; Total logic elements ; 175 ;
+; Total pins ; 117 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 ;
+; DSP block 9-bit elements ; 0 ;
+; Total PLLs ; 1 ;
+; Total DLLs ; 0 ;
++-----------------------------+------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++----------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP1S25F672C6 ; ;
+; Top-level entity name ; vga_pll ; vga_pll ;
+; Family name ; Stratix ; Stratix ;
+; Type of Retiming Performed During Resynthesis ; Full ; ;
+; Resynthesis Optimization Effort ; Normal ; ;
+; Physical Synthesis Level for Resynthesis ; Normal ; ;
+; Use Generated Physical Constraints File ; On ; ;
+; Use smart compilation ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL93 ; VHDL93 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Parallel Synthesis ; Off ; Off ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM Block Balancing ; On ; On ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Block Design Naming ; Auto ; Auto ;
+; Synthesis Effort ; Auto ; Auto ;
+; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
++----------------------------------------------------------------+--------------------+--------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
+; ../../src/vga_pll.bdf ; yes ; User Block Diagram/Schematic File ; /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pll.bdf ;
+; ../../syn/rev_1/vga.vqm ; yes ; User Verilog Quartus Mapping File ; /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm ;
+; ../../src/vpll.vhd ; yes ; User Wizard-Generated File ; /homes/burban/didelu/dide_16/bsp2/Designflow/src/vpll.vhd ;
+; altpll.tdf ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/altpll.tdf ;
+; aglobal90.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/aglobal90.inc ;
+; stratix_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratix_pll.inc ;
+; stratixii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratixii_pll.inc ;
+; cycloneii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/cycloneii_pll.inc ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+------------------------------------------+
+; Total logic elements ; 175 ;
+; -- Combinational with no register ; 92 ;
+; -- Register only ; 3 ;
+; -- Combinational with a register ; 80 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 60 ;
+; -- 3 input functions ; 52 ;
+; -- 2 input functions ; 58 ;
+; -- 1 input functions ; 2 ;
+; -- 0 input functions ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 122 ;
+; -- arithmetic mode ; 53 ;
+; -- qfbk mode ; 0 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 69 ;
+; -- asynchronous clear/load mode ; 24 ;
+; ; ;
+; Total registers ; 83 ;
+; Total logic cells in carry chains ; 61 ;
+; I/O pins ; 117 ;
+; Total PLLs ; 1 ;
+; Maximum fan-out node ; vpll:inst1|altpll:altpll_component|_clk0 ;
+; Maximum fan-out ; 84 ;
+; Total fan-out ; 845 ;
+; Average fan-out ; 2.88 ;
++---------------------------------------------+------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
+; |vga_pll ; 175 (0) ; 83 ; 0 ; 0 ; 0 ; 0 ; 0 ; 117 ; 0 ; 92 (0) ; 3 (0) ; 80 (0) ; 61 (0) ; 0 (0) ; |vga_pll ; work ;
+; |vga:inst| ; 175 (2) ; 83 ; 0 ; 0 ; 0 ; 0 ; 0 ; 116 ; 0 ; 92 (0) ; 3 (0) ; 80 (2) ; 61 (0) ; 0 (0) ; |vga_pll|vga:inst ; work ;
+; |vga_control:vga_control_unit| ; 43 (43) ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 0 (0) ; 24 (24) ; 21 (21) ; 0 (0) ; |vga_pll|vga:inst|vga_control:vga_control_unit ; work ;
+; |vga_driver:vga_driver_unit| ; 130 (130) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 73 (73) ; 3 (3) ; 54 (54) ; 40 (40) ; 0 (0) ; |vga_pll|vga:inst|vga_driver:vga_driver_unit ; work ;
+; |vpll:inst1| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1 ; work ;
+; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1|altpll:altpll_component ; work ;
++--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++-------------------------------------------------------------+----------------------------------------+
+; Register name ; Reason for Removal ;
++-------------------------------------------------------------+----------------------------------------+
+; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_24 ; Stuck at GND due to stuck port reg_out ;
+; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_23 ; Stuck at GND due to stuck port reg_out ;
+; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_22 ; Stuck at GND due to stuck port reg_out ;
+; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_21 ; Stuck at GND due to stuck port reg_out ;
+; vga:inst|vga_control:vga_control_unit|g ; Stuck at GND due to stuck port reg_out ;
+; Total Number of Removed Registers = 5 ; ;
++-------------------------------------------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 83 ;
+; Number of registers using Synchronous Clear ; 69 ;
+; Number of registers using Synchronous Load ; 20 ;
+; Number of registers using Asynchronous Clear ; 24 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 12 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component ;
++-------------------------------+-------------------+-----------------------------+
+; Parameter Name ; Value ; Type ;
++-------------------------------+-------------------+-----------------------------+
+; OPERATION_MODE ; NORMAL ; Untyped ;
+; PLL_TYPE ; AUTO ; Untyped ;
+; QUALIFY_CONF_DONE ; OFF ; Untyped ;
+; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
+; SCAN_CHAIN ; LONG ; Untyped ;
+; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
+; INCLK0_INPUT_FREQUENCY ; 30003 ; Signed Integer ;
+; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
+; GATE_LOCK_SIGNAL ; NO ; Untyped ;
+; GATE_LOCK_COUNTER ; 0 ; Untyped ;
+; LOCK_HIGH ; 1 ; Untyped ;
+; LOCK_LOW ; 1 ; Untyped ;
+; VALID_LOCK_MULTIPLIER ; 1 ; Signed Integer ;
+; INVALID_LOCK_MULTIPLIER ; 5 ; Signed Integer ;
+; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
+; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
+; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
+; SKIP_VCO ; OFF ; Untyped ;
+; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
+; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
+; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
+; BANDWIDTH ; 0 ; Untyped ;
+; BANDWIDTH_TYPE ; AUTO ; Untyped ;
+; SPREAD_FREQUENCY ; 0 ; Signed Integer ;
+; DOWN_SPREAD ; 0 ; Untyped ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
+; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
+; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK1_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK0_MULTIPLY_BY ; 5435 ; Signed Integer ;
+; CLK9_DIVIDE_BY ; 0 ; Untyped ;
+; CLK8_DIVIDE_BY ; 0 ; Untyped ;
+; CLK7_DIVIDE_BY ; 0 ; Untyped ;
+; CLK6_DIVIDE_BY ; 0 ; Untyped ;
+; CLK5_DIVIDE_BY ; 1 ; Untyped ;
+; CLK4_DIVIDE_BY ; 1 ; Untyped ;
+; CLK3_DIVIDE_BY ; 1 ; Untyped ;
+; CLK2_DIVIDE_BY ; 1 ; Untyped ;
+; CLK1_DIVIDE_BY ; 1 ; Untyped ;
+; CLK0_DIVIDE_BY ; 6666 ; Signed Integer ;
+; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK5_TIME_DELAY ; 0 ; Untyped ;
+; CLK4_TIME_DELAY ; 0 ; Untyped ;
+; CLK3_TIME_DELAY ; 0 ; Untyped ;
+; CLK2_TIME_DELAY ; 0 ; Untyped ;
+; CLK1_TIME_DELAY ; 0 ; Untyped ;
+; CLK0_TIME_DELAY ; 0 ; Untyped ;
+; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
+; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
+; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
+; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
+; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
+; DPA_MULTIPLY_BY ; 0 ; Untyped ;
+; DPA_DIVIDE_BY ; 1 ; Untyped ;
+; DPA_DIVIDER ; 0 ; Untyped ;
+; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
+; VCO_MULTIPLY_BY ; 0 ; Untyped ;
+; VCO_DIVIDE_BY ; 0 ; Untyped ;
+; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
+; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
+; VCO_MIN ; 0 ; Untyped ;
+; VCO_MAX ; 0 ; Untyped ;
+; VCO_CENTER ; 0 ; Untyped ;
+; PFD_MIN ; 0 ; Untyped ;
+; PFD_MAX ; 0 ; Untyped ;
+; M_INITIAL ; 0 ; Untyped ;
+; M ; 0 ; Untyped ;
+; N ; 1 ; Untyped ;
+; M2 ; 1 ; Untyped ;
+; N2 ; 1 ; Untyped ;
+; SS ; 1 ; Untyped ;
+; C0_HIGH ; 0 ; Untyped ;
+; C1_HIGH ; 0 ; Untyped ;
+; C2_HIGH ; 0 ; Untyped ;
+; C3_HIGH ; 0 ; Untyped ;
+; C4_HIGH ; 0 ; Untyped ;
+; C5_HIGH ; 0 ; Untyped ;
+; C6_HIGH ; 0 ; Untyped ;
+; C7_HIGH ; 0 ; Untyped ;
+; C8_HIGH ; 0 ; Untyped ;
+; C9_HIGH ; 0 ; Untyped ;
+; C0_LOW ; 0 ; Untyped ;
+; C1_LOW ; 0 ; Untyped ;
+; C2_LOW ; 0 ; Untyped ;
+; C3_LOW ; 0 ; Untyped ;
+; C4_LOW ; 0 ; Untyped ;
+; C5_LOW ; 0 ; Untyped ;
+; C6_LOW ; 0 ; Untyped ;
+; C7_LOW ; 0 ; Untyped ;
+; C8_LOW ; 0 ; Untyped ;
+; C9_LOW ; 0 ; Untyped ;
+; C0_INITIAL ; 0 ; Untyped ;
+; C1_INITIAL ; 0 ; Untyped ;
+; C2_INITIAL ; 0 ; Untyped ;
+; C3_INITIAL ; 0 ; Untyped ;
+; C4_INITIAL ; 0 ; Untyped ;
+; C5_INITIAL ; 0 ; Untyped ;
+; C6_INITIAL ; 0 ; Untyped ;
+; C7_INITIAL ; 0 ; Untyped ;
+; C8_INITIAL ; 0 ; Untyped ;
+; C9_INITIAL ; 0 ; Untyped ;
+; C0_MODE ; BYPASS ; Untyped ;
+; C1_MODE ; BYPASS ; Untyped ;
+; C2_MODE ; BYPASS ; Untyped ;
+; C3_MODE ; BYPASS ; Untyped ;
+; C4_MODE ; BYPASS ; Untyped ;
+; C5_MODE ; BYPASS ; Untyped ;
+; C6_MODE ; BYPASS ; Untyped ;
+; C7_MODE ; BYPASS ; Untyped ;
+; C8_MODE ; BYPASS ; Untyped ;
+; C9_MODE ; BYPASS ; Untyped ;
+; C0_PH ; 0 ; Untyped ;
+; C1_PH ; 0 ; Untyped ;
+; C2_PH ; 0 ; Untyped ;
+; C3_PH ; 0 ; Untyped ;
+; C4_PH ; 0 ; Untyped ;
+; C5_PH ; 0 ; Untyped ;
+; C6_PH ; 0 ; Untyped ;
+; C7_PH ; 0 ; Untyped ;
+; C8_PH ; 0 ; Untyped ;
+; C9_PH ; 0 ; Untyped ;
+; L0_HIGH ; 1 ; Untyped ;
+; L1_HIGH ; 1 ; Untyped ;
+; G0_HIGH ; 1 ; Untyped ;
+; G1_HIGH ; 1 ; Untyped ;
+; G2_HIGH ; 1 ; Untyped ;
+; G3_HIGH ; 1 ; Untyped ;
+; E0_HIGH ; 1 ; Untyped ;
+; E1_HIGH ; 1 ; Untyped ;
+; E2_HIGH ; 1 ; Untyped ;
+; E3_HIGH ; 1 ; Untyped ;
+; L0_LOW ; 1 ; Untyped ;
+; L1_LOW ; 1 ; Untyped ;
+; G0_LOW ; 1 ; Untyped ;
+; G1_LOW ; 1 ; Untyped ;
+; G2_LOW ; 1 ; Untyped ;
+; G3_LOW ; 1 ; Untyped ;
+; E0_LOW ; 1 ; Untyped ;
+; E1_LOW ; 1 ; Untyped ;
+; E2_LOW ; 1 ; Untyped ;
+; E3_LOW ; 1 ; Untyped ;
+; L0_INITIAL ; 1 ; Untyped ;
+; L1_INITIAL ; 1 ; Untyped ;
+; G0_INITIAL ; 1 ; Untyped ;
+; G1_INITIAL ; 1 ; Untyped ;
+; G2_INITIAL ; 1 ; Untyped ;
+; G3_INITIAL ; 1 ; Untyped ;
+; E0_INITIAL ; 1 ; Untyped ;
+; E1_INITIAL ; 1 ; Untyped ;
+; E2_INITIAL ; 1 ; Untyped ;
+; E3_INITIAL ; 1 ; Untyped ;
+; L0_MODE ; BYPASS ; Untyped ;
+; L1_MODE ; BYPASS ; Untyped ;
+; G0_MODE ; BYPASS ; Untyped ;
+; G1_MODE ; BYPASS ; Untyped ;
+; G2_MODE ; BYPASS ; Untyped ;
+; G3_MODE ; BYPASS ; Untyped ;
+; E0_MODE ; BYPASS ; Untyped ;
+; E1_MODE ; BYPASS ; Untyped ;
+; E2_MODE ; BYPASS ; Untyped ;
+; E3_MODE ; BYPASS ; Untyped ;
+; L0_PH ; 0 ; Untyped ;
+; L1_PH ; 0 ; Untyped ;
+; G0_PH ; 0 ; Untyped ;
+; G1_PH ; 0 ; Untyped ;
+; G2_PH ; 0 ; Untyped ;
+; G3_PH ; 0 ; Untyped ;
+; E0_PH ; 0 ; Untyped ;
+; E1_PH ; 0 ; Untyped ;
+; E2_PH ; 0 ; Untyped ;
+; E3_PH ; 0 ; Untyped ;
+; M_PH ; 0 ; Untyped ;
+; C1_USE_CASC_IN ; OFF ; Untyped ;
+; C2_USE_CASC_IN ; OFF ; Untyped ;
+; C3_USE_CASC_IN ; OFF ; Untyped ;
+; C4_USE_CASC_IN ; OFF ; Untyped ;
+; C5_USE_CASC_IN ; OFF ; Untyped ;
+; C6_USE_CASC_IN ; OFF ; Untyped ;
+; C7_USE_CASC_IN ; OFF ; Untyped ;
+; C8_USE_CASC_IN ; OFF ; Untyped ;
+; C9_USE_CASC_IN ; OFF ; Untyped ;
+; CLK0_COUNTER ; G0 ; Untyped ;
+; CLK1_COUNTER ; G0 ; Untyped ;
+; CLK2_COUNTER ; G0 ; Untyped ;
+; CLK3_COUNTER ; G0 ; Untyped ;
+; CLK4_COUNTER ; G0 ; Untyped ;
+; CLK5_COUNTER ; G0 ; Untyped ;
+; CLK6_COUNTER ; E0 ; Untyped ;
+; CLK7_COUNTER ; E1 ; Untyped ;
+; CLK8_COUNTER ; E2 ; Untyped ;
+; CLK9_COUNTER ; E3 ; Untyped ;
+; L0_TIME_DELAY ; 0 ; Untyped ;
+; L1_TIME_DELAY ; 0 ; Untyped ;
+; G0_TIME_DELAY ; 0 ; Untyped ;
+; G1_TIME_DELAY ; 0 ; Untyped ;
+; G2_TIME_DELAY ; 0 ; Untyped ;
+; G3_TIME_DELAY ; 0 ; Untyped ;
+; E0_TIME_DELAY ; 0 ; Untyped ;
+; E1_TIME_DELAY ; 0 ; Untyped ;
+; E2_TIME_DELAY ; 0 ; Untyped ;
+; E3_TIME_DELAY ; 0 ; Untyped ;
+; M_TIME_DELAY ; 0 ; Untyped ;
+; N_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK3_COUNTER ; E3 ; Untyped ;
+; EXTCLK2_COUNTER ; E2 ; Untyped ;
+; EXTCLK1_COUNTER ; E1 ; Untyped ;
+; EXTCLK0_COUNTER ; E0 ; Untyped ;
+; ENABLE0_COUNTER ; L0 ; Untyped ;
+; ENABLE1_COUNTER ; L0 ; Untyped ;
+; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
+; LOOP_FILTER_R ; 1.000000 ; Untyped ;
+; LOOP_FILTER_C ; 5 ; Untyped ;
+; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
+; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
+; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
+; VCO_POST_SCALE ; 0 ; Untyped ;
+; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; INTENDED_DEVICE_FAMILY ; Stratix ; Untyped ;
+; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
+; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_LOCKED ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
+; M_TEST_SOURCE ; 5 ; Untyped ;
+; C0_TEST_SOURCE ; 5 ; Untyped ;
+; C1_TEST_SOURCE ; 5 ; Untyped ;
+; C2_TEST_SOURCE ; 5 ; Untyped ;
+; C3_TEST_SOURCE ; 5 ; Untyped ;
+; C4_TEST_SOURCE ; 5 ; Untyped ;
+; C5_TEST_SOURCE ; 5 ; Untyped ;
+; C6_TEST_SOURCE ; 5 ; Untyped ;
+; C7_TEST_SOURCE ; 5 ; Untyped ;
+; C8_TEST_SOURCE ; 5 ; Untyped ;
+; C9_TEST_SOURCE ; 5 ; Untyped ;
+; CBXI_PARAMETER ; NOTHING ; Untyped ;
+; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
+; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
+; WIDTH_CLOCK ; 6 ; Untyped ;
+; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
+; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
+; DEVICE_FAMILY ; Stratix ; Untyped ;
+; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++-------------------------------+-------------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance ;
++-------------------------------+------------------------------------+
+; Name ; Value ;
++-------------------------------+------------------------------------+
+; Number of entity instances ; 1 ;
+; Entity Instance ; vpll:inst1|altpll:altpll_component ;
+; -- OPERATION_MODE ; NORMAL ;
+; -- PLL_TYPE ; AUTO ;
+; -- PRIMARY_CLOCK ; INCLK0 ;
+; -- INCLK0_INPUT_FREQUENCY ; 30003 ;
+; -- INCLK1_INPUT_FREQUENCY ; 0 ;
+; -- VCO_MULTIPLY_BY ; 0 ;
+; -- VCO_DIVIDE_BY ; 0 ;
++-------------------------------+------------------------------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:54:33 2009
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll
+Info: Revision "vga_pll" was previously opened in Quartus II software version 6.0. Created Quartus II Default Settings File /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/download/vga_pll_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 6.0.
+Info: Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /opt/quartus/quartus/linux/assignment_defaults.qdf
+Info: Found 1 design units, including 1 entities, in source file ../../src/vga_pll.bdf
+ Info: Found entity 1: vga_pll
+Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm
+ Info: Found entity 1: vga_driver
+ Info: Found entity 2: vga_control
+ Info: Found entity 3: vga
+Info: Found 2 design units, including 1 entities, in source file ../../src/vpll.vhd
+ Info: Found design unit 1: vpll-SYN
+ Info: Found entity 1: vpll
+Info: Elaborating entity "vga_pll" for the top level hierarchy
+Info: Elaborating entity "vga" for hierarchy "vga:inst"
+Info: Elaborating entity "vga_driver" for hierarchy "vga:inst|vga_driver:vga_driver_unit"
+Info: Elaborating entity "vga_control" for hierarchy "vga:inst|vga_control:vga_control_unit"
+Info: Elaborating entity "vpll" for hierarchy "vpll:inst1"
+Warning (10036): Verilog HDL or VHDL warning at vpll.vhd(73): object "locked" assigned a value but never read
+Info: Elaborating entity "altpll" for hierarchy "vpll:inst1|altpll:altpll_component"
+Info: Elaborated megafunction instantiation "vpll:inst1|altpll:altpll_component"
+Info: Instantiated megafunction "vpll:inst1|altpll:altpll_component" with the following parameter:
+ Info: Parameter "bandwidth_type" = "AUTO"
+ Info: Parameter "clk0_duty_cycle" = "50"
+ Info: Parameter "lpm_type" = "altpll"
+ Info: Parameter "clk0_multiply_by" = "5435"
+ Info: Parameter "invalid_lock_multiplier" = "5"
+ Info: Parameter "inclk0_input_frequency" = "30003"
+ Info: Parameter "gate_lock_signal" = "NO"
+ Info: Parameter "clk0_divide_by" = "6666"
+ Info: Parameter "pll_type" = "AUTO"
+ Info: Parameter "valid_lock_multiplier" = "1"
+ Info: Parameter "clk0_time_delay" = "0"
+ Info: Parameter "spread_frequency" = "0"
+ Info: Parameter "intended_device_family" = "Stratix"
+ Info: Parameter "operation_mode" = "NORMAL"
+ Info: Parameter "compensate_clock" = "CLK0"
+ Info: Parameter "clk0_phase_shift" = "0"
+Info: WYSIWYG I/O primitives converted to equivalent logic
+ Info: WYSIWYG I/O primitive "vga:inst|clk_pin_in" converted to equivalent logic
+Info: Implemented 293 device resources after synthesis - the final resource count might be different
+ Info: Implemented 2 input pins
+ Info: Implemented 115 output pins
+ Info: Implemented 175 logic cells
+ Info: Implemented 1 ClockLock PLLs
+Warning: Output port clk0 of PLL "vpll:inst1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
+ Info: Peak virtual memory: 204 megabytes
+ Info: Processing ended: Wed Oct 28 14:54:40 2009
+ Info: Elapsed time: 00:00:07
+ Info: Total CPU time (on all processors): 00:00:04
+
+
--- /dev/null
+Analysis & Synthesis Status : Successful - Wed Oct 28 14:54:40 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga_pll
+Top-level Entity Name : vga_pll
+Family : Stratix
+Total logic elements : 175
+Total pins : 117
+Total virtual pins : 0
+Total memory bits : 0
+DSP block 9-bit elements : 0
+Total PLLs : 1
+Total DLLs : 0
--- /dev/null
+ -- Copyright (C) 1991-2009 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- Bank 5: 3.3V
+ -- Bank 6: 3.3V
+ -- Bank 7: 3.3V
+ -- Bank 8: 3.3V
+ -- Bank 9: 3.3V
+ -- Bank 11: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
+ -- connect each pin marked GND* either individually through a 10k Ohm resistor
+ -- to GND or tie all pins together and connect through a single 10k Ohm resistor
+ -- to GND.
+ -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+CHIP "vga_pll" ASSIGNED TO AN: EP1S25F672C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+GND* : A3 : : : : 3 :
+VCCIO3 : A4 : power : : 3.3V : 3 :
+reset : A5 : input : 3.3-V LVTTL : : 3 : Y
+GND* : A6 : : : : 3 :
+GND* : A7 : : : : 3 :
+GND* : A8 : : : : 3 :
+GND* : A9 : : : : 3 :
+GND* : A10 : : : : 3 :
+VCCIO3 : A11 : power : : 3.3V : 3 :
+GND* : A12 : : : : 3 :
+GND : A13 : gnd : : : :
+GND : A14 : gnd : : : :
+GND+ : A15 : : : : 4 :
+VCCIO4 : A16 : power : : 3.3V : 4 :
+GND* : A17 : : : : 4 :
+GND* : A18 : : : : 4 :
+GND* : A19 : : : : 4 :
+GND* : A20 : : : : 4 :
+GND* : A21 : : : : 4 :
+GND* : A22 : : : : 4 :
+VCCIO4 : A23 : power : : 3.3V : 4 :
+d_toggle_counter[3] : A24 : output : 3.3-V LVTTL : : 4 : N
+GND : A25 : gnd : : : :
+GND* : AA1 : : : : 1 :
+GND* : AA2 : : : : 1 :
+GND* : AA3 : : : : 1 :
+GND* : AA4 : : : : 1 :
+GND* : AA5 : : : : 1 :
+GND* : AA6 : : : : 1 :
+GND* : AA7 : : : : 8 :
+GND* : AA8 : : : : 8 :
+GND* : AA9 : : : : 8 :
+GND* : AA10 : : : : 8 :
+seven_seg_pin[12] : AA11 : output : 3.3-V LVTTL : : 8 : Y
+GND* : AA12 : : : : 11 :
+GND* : AA13 : : : : 11 :
+GND* : AA14 : : : : 11 :
+nIO_PULLUP : AA15 : : : : 7 :
+GND* : AA16 : : : : 7 :
+GND* : AA17 : : : : 7 :
+GND* : AA18 : : : : 7 :
+GND* : AA19 : : : : 7 :
+GND* : AA20 : : : : 7 :
+d_toggle_counter[12] : AA21 : output : 3.3-V LVTTL : : 7 : N
+GND* : AA22 : : : : 6 :
+GND* : AA23 : : : : 6 :
+GND* : AA24 : : : : 6 :
+GND* : AA25 : : : : 6 :
+d_toggle_counter[11] : AA26 : output : 3.3-V LVTTL : : 6 : N
+GND* : AB1 : : : : 1 :
+GND* : AB2 : : : : 1 :
+GND* : AB3 : : : : 1 :
+GND* : AB4 : : : : 1 :
+GND* : AB5 : : : : 8 :
+GND* : AB6 : : : : 8 :
+GND* : AB7 : : : : 8 :
+GND* : AB8 : : : : 8 :
+GND* : AB9 : : : : 8 :
+GND* : AB10 : : : : 8 :
+GND* : AB11 : : : : 8 :
+GND* : AB12 : : : : 11 :
+GND* : AB13 : : : : 11 :
+GND* : AB14 : : : : 11 :
+GND : AB15 : gnd : : : :
+GND* : AB16 : : : : 7 :
+GND* : AB17 : : : : 7 :
+GND : AB18 : gnd : : : :
+GND* : AB19 : : : : 7 :
+GND* : AB20 : : : : 7 :
+d_toggle_counter[14] : AB21 : output : 3.3-V LVTTL : : 7 : N
+GND* : AB22 : : : : 7 :
+GND* : AB23 : : : : 6 :
+GND* : AB24 : : : : 6 :
+GND* : AB25 : : : : 6 :
+GND* : AB26 : : : : 6 :
+VCCIO1 : AC1 : power : : 3.3V : 1 :
+GND* : AC2 : : : : 1 :
+GND* : AC3 : : : : 1 :
+GND* : AC4 : : : : 1 :
+GND* : AC5 : : : : 8 :
+GND* : AC6 : : : : 8 :
+GND* : AC7 : : : : 8 :
+GND* : AC8 : : : : 8 :
+GND* : AC9 : : : : 8 :
+GND* : AC10 : : : : 8 :
+GND* : AC11 : : : : 8 :
+GND+ : AC12 : : : : 8 :
+GND : AC13 : gnd : : : :
+GNDA_PLL6 : AC14 : gnd : : : :
+GND* : AC15 : : : : 7 :
+GND* : AC16 : : : : 7 :
+GND* : AC17 : : : : 7 :
+GND* : AC18 : : : : 7 :
+GND* : AC19 : : : : 7 :
+GND* : AC20 : : : : 7 :
+d_toggle_counter[5] : AC21 : output : 3.3-V LVTTL : : 7 : N
+GND* : AC22 : : : : 7 :
+GND* : AC23 : : : : 7 :
+GND* : AC24 : : : : 6 :
+GND* : AC25 : : : : 6 :
+VCCIO6 : AC26 : power : : 3.3V : 6 :
+GND* : AD1 : : : : 1 :
+GND* : AD2 : : : : 8 :
+GND* : AD3 : : : : 8 :
+GND* : AD4 : : : : 8 :
+GND* : AD5 : : : : 8 :
+GND* : AD6 : : : : 8 :
+GND* : AD7 : : : : 8 :
+GND* : AD8 : : : : 8 :
+GND* : AD9 : : : : 8 :
+GND* : AD10 : : : : 8 :
+d_vsync_counter[4] : AD11 : output : 3.3-V LVTTL : : 8 : N
+GND* : AD12 : : : : 8 :
+VCCG_PLL6 : AD13 : power : : 1.5V : :
+VCCA_PLL6 : AD14 : power : : 1.5V : :
+d_hsync_counter[1] : AD15 : output : 3.3-V LVTTL : : 7 : N
+GND* : AD16 : : : : 7 :
+GND* : AD17 : : : : 7 :
+GND* : AD18 : : : : 7 :
+GND* : AD19 : : : : 7 :
+GND* : AD20 : : : : 7 :
+GND : AD21 : gnd : : : :
+GND* : AD22 : : : : 7 :
+GND* : AD23 : : : : 7 :
+GND* : AD24 : : : : 7 :
+GND* : AD25 : : : : 6 :
+GND* : AD26 : : : : 6 :
+GND : AE1 : gnd : : : :
+GND* : AE2 : : : : 8 :
+GND* : AE3 : : : : 8 :
+GND* : AE4 : : : : 8 :
+GND : AE5 : gnd : : : :
+GND* : AE6 : : : : 8 :
+GND* : AE7 : : : : 8 :
+GND* : AE8 : : : : 8 :
+GND : AE9 : gnd : : : :
+GND* : AE10 : : : : 8 :
+GND* : AE11 : : : : 8 :
+GND+ : AE12 : : : : 8 :
+VCC_PLL6_OUTA : AE13 : power : : 3.3V : 11 :
+GNDG_PLL6 : AE14 : gnd : : : :
+GND+ : AE15 : : : : 7 :
+GND* : AE16 : : : : 7 :
+GND* : AE17 : : : : 7 :
+GND* : AE18 : : : : 7 :
+GND* : AE19 : : : : 7 :
+GND* : AE20 : : : : 7 :
+GND* : AE21 : : : : 7 :
+d_toggle_counter[7] : AE22 : output : 3.3-V LVTTL : : 7 : N
+GND* : AE23 : : : : 7 :
+GND* : AE24 : : : : 7 :
+GND* : AE25 : : : : 7 :
+GND : AE26 : gnd : : : :
+GND : AF2 : gnd : : : :
+GND* : AF3 : : : : 8 :
+VCCIO8 : AF4 : power : : 3.3V : 8 :
+GND* : AF5 : : : : 8 :
+GND* : AF6 : : : : 8 :
+GND* : AF7 : : : : 8 :
+GND* : AF8 : : : : 8 :
+GND* : AF9 : : : : 8 :
+GND* : AF10 : : : : 8 :
+VCCIO8 : AF11 : power : : 3.3V : 8 :
+GND* : AF12 : : : : 8 :
+GND : AF13 : gnd : : : :
+GND : AF14 : gnd : : : :
+GND+ : AF15 : : : : 7 :
+VCCIO7 : AF16 : power : : 3.3V : 7 :
+GND* : AF17 : : : : 7 :
+GND* : AF18 : : : : 7 :
+GND* : AF19 : : : : 7 :
+GND* : AF20 : : : : 7 :
+GND* : AF21 : : : : 7 :
+d_toggle_counter[9] : AF22 : output : 3.3-V LVTTL : : 7 : N
+VCCIO7 : AF23 : power : : 3.3V : 7 :
+d_toggle_counter[4] : AF24 : output : 3.3-V LVTTL : : 7 : N
+GND : AF25 : gnd : : : :
+GND : B1 : gnd : : : :
+GND : B2 : gnd : : : :
+d_toggle_counter[6] : B3 : output : 3.3-V LVTTL : : 3 : N
+GND* : B4 : : : : 3 :
+GND* : B5 : : : : 3 :
+GND* : B6 : : : : 3 :
+GND* : B7 : : : : 3 :
+GND* : B8 : : : : 3 :
+GND* : B9 : : : : 3 :
+GND* : B10 : : : : 3 :
+d_vsync_counter[2] : B11 : output : 3.3-V LVTTL : : 3 : N
+GND+ : B12 : : : : 3 :
+GNDG_PLL5 : B13 : gnd : : : :
+GNDA_PLL5 : B14 : gnd : : : :
+GND+ : B15 : : : : 4 :
+d_hsync_counter[2] : B16 : output : 3.3-V LVTTL : : 4 : N
+GND* : B17 : : : : 4 :
+GND* : B18 : : : : 4 :
+GND* : B19 : : : : 4 :
+GND* : B20 : : : : 4 :
+GND* : B21 : : : : 4 :
+GND* : B22 : : : : 4 :
+d_toggle_counter[2] : B23 : output : 3.3-V LVTTL : : 4 : N
+GND* : B24 : : : : 4 :
+GND* : B25 : : : : 4 :
+GND : B26 : gnd : : : :
+GND* : C1 : : : : 2 :
+GND* : C2 : : : : 3 :
+GND* : C3 : : : : 3 :
+GND* : C4 : : : : 3 :
+GND* : C5 : : : : 3 :
+GND* : C6 : : : : 3 :
+GND* : C7 : : : : 3 :
+GND* : C8 : : : : 3 :
+GND* : C9 : : : : 3 :
+GND* : C10 : : : : 3 :
+GND* : C11 : : : : 3 :
+GND* : C12 : : : : 3 :
+GND : C13 : gnd : : : :
+VCCG_PLL5 : C14 : power : : 1.5V : :
+d_hsync_counter[6] : C15 : output : 3.3-V LVTTL : : 4 : N
+GND* : C16 : : : : 4 :
+GND* : C17 : : : : 4 :
+GND* : C18 : : : : 4 :
+GND* : C19 : : : : 4 :
+d_toggle_counter[13] : C20 : output : 3.3-V LVTTL : : 4 : N
+GND* : C21 : : : : 4 :
+GND* : C22 : : : : 4 :
+GND* : C23 : : : : 4 :
+GND* : C24 : : : : 4 :
+GND* : C25 : : : : 5 :
+GND* : C26 : : : : 5 :
+VCCIO2 : D1 : power : : 3.3V : 2 :
+GND* : D2 : : : : 2 :
+GND* : D3 : : : : 3 :
+GND* : D4 : : : : 3 :
+GND* : D5 : : : : 3 :
+GND* : D6 : : : : 3 :
+GND : D7 : gnd : : : :
+GND* : D8 : : : : 3 :
+GND : D9 : gnd : : : :
+GND* : D10 : : : : 3 :
+GND* : D11 : : : : 3 :
+GND+ : D12 : : : : 3 :
+VCC_PLL5_OUTA : D13 : power : : 3.3V : 9 :
+VCCA_PLL5 : D14 : power : : 1.5V : :
+TRST : D15 : input : : : 4 :
+GND* : D16 : : : : 4 :
+GND* : D17 : : : : 4 :
+GND* : D18 : : : : 4 :
+GND* : D19 : : : : 4 :
+GND* : D20 : : : : 4 :
+GND* : D21 : : : : 4 :
+GND* : D22 : : : : 4 :
+GND* : D23 : : : : 4 :
+GND* : D24 : : : : 5 :
+GND* : D25 : : : : 5 :
+VCCIO5 : D26 : power : : 3.3V : 5 :
+GND* : E1 : : : : 2 :
+GND* : E2 : : : : 2 :
+GND* : E3 : : : : 2 :
+GND* : E4 : : : : 2 :
+GND* : E5 : : : : 3 :
+GND* : E6 : : : : 3 :
+GND* : E7 : : : : 3 :
+GND* : E8 : : : : 3 :
+GND* : E9 : : : : 3 :
+GND* : E10 : : : : 3 :
+GND* : E11 : : : : 3 :
+GND* : E12 : : : : 9 :
+GND* : E13 : : : : 9 :
+GND* : E14 : : : : 9 :
+TMS : E15 : input : : : 4 :
+GND* : E16 : : : : 4 :
+GND* : E17 : : : : 4 :
+GND* : E18 : : : : 4 :
+GND* : E19 : : : : 4 :
+GND* : E20 : : : : 4 :
+GND* : E21 : : : : 4 :
+r0_pin : E22 : output : 3.3-V LVTTL : : 4 : Y
+g0_pin : E23 : output : 3.3-V LVTTL : : 5 : Y
+b0_pin : E24 : output : 3.3-V LVTTL : : 5 : Y
+GND* : E25 : : : : 5 :
+GND* : E26 : : : : 5 :
+hsync_pin : F1 : output : 3.3-V LVTTL : : 2 : Y
+vsync_pin : F2 : output : 3.3-V LVTTL : : 2 : Y
+d_vsync_state[2] : F3 : output : 3.3-V LVTTL : : 2 : Y
+d_vsync_state[1] : F4 : output : 3.3-V LVTTL : : 2 : Y
+d_vsync_state[0] : F5 : output : 3.3-V LVTTL : : 3 : Y
+d_hsync_state[6] : F6 : output : 3.3-V LVTTL : : 3 : Y
+GND* : F7 : : : : 3 :
+GND : F8 : gnd : : : :
+d_hsync_state[5] : F9 : output : 3.3-V LVTTL : : 3 : Y
+d_hsync_state[4] : F10 : output : 3.3-V LVTTL : : 3 : Y
+GND : F11 : gnd : : : :
+GND* : F12 : : : : 9 :
+GND* : F13 : : : : 9 :
+GND* : F14 : : : : 9 :
+GND* : F15 : : : : 4 :
+~DATA0~ / RESERVED_INPUT : F16 : input : 3.3-V LVTTL : : 4 : N
+d_hsync_state[2] : F17 : output : 3.3-V LVTTL : : 4 : Y
+GND : F18 : gnd : : : :
+d_hsync_state[1] : F19 : output : 3.3-V LVTTL : : 4 : Y
+GND* : F20 : : : : 4 :
+d_set_line_counter : F21 : output : 3.3-V LVTTL : : 4 : Y
+GND : F22 : gnd : : : :
+d_toggle_counter[23] : F23 : output : 3.3-V LVTTL : : 5 : Y
+d_set_vsync_counter : F24 : output : 3.3-V LVTTL : : 5 : Y
+d_toggle_counter[22] : F25 : output : 3.3-V LVTTL : : 5 : Y
+d_set_hsync_counter : F26 : output : 3.3-V LVTTL : : 5 : Y
+d_toggle_counter[21] : G1 : output : 3.3-V LVTTL : : 2 : Y
+d_vsync_counter[9] : G2 : output : 3.3-V LVTTL : : 2 : Y
+d_toggle_counter[20] : G3 : output : 3.3-V LVTTL : : 2 : Y
+d_vsync_counter[8] : G4 : output : 3.3-V LVTTL : : 2 : Y
+d_toggle_counter[19] : G5 : output : 3.3-V LVTTL : : 2 : Y
+d_vsync_counter[7] : G6 : output : 3.3-V LVTTL : : 2 : Y
+GND* : G7 : : : : 3 :
+GND : G8 : gnd : : : :
+d_vsync_counter[0] : G9 : output : 3.3-V LVTTL : : 3 : Y
+GND* : G10 : : : : 3 :
+d_vsync_counter[5] : G11 : output : 3.3-V LVTTL : : 3 : N
+DCLK : G12 : : : : 3 :
+TEMPDIODEn : G13 : : : : :
+TDO : G14 : output : : : 4 :
+TCK : G15 : input : : : 4 :
+GND : G16 : gnd : : : :
+GND* : G17 : : : : 4 :
+d_hsync_counter[9] : G18 : output : 3.3-V LVTTL : : 4 : Y
+GND* : G19 : : : : 4 :
+d_toggle_counter[18] : G20 : output : 3.3-V LVTTL : : 4 : Y
+d_toggle_counter[17] : G21 : output : 3.3-V LVTTL : : 5 : Y
+d_hsync_counter[8] : G22 : output : 3.3-V LVTTL : : 5 : Y
+d_toggle_counter[16] : G23 : output : 3.3-V LVTTL : : 5 : Y
+d_toggle_counter[15] : G24 : output : 3.3-V LVTTL : : 5 : Y
+d_hsync_counter[7] : G25 : output : 3.3-V LVTTL : : 5 : Y
+GND* : G26 : : : : 5 :
+d_hsync_counter[4] : H1 : output : 3.3-V LVTTL : : 2 : N
+d_hsync_counter[5] : H2 : output : 3.3-V LVTTL : : 2 : N
+d_toggle : H3 : output : 3.3-V LVTTL : : 2 : Y
+d_hsync_counter[0] : H4 : output : 3.3-V LVTTL : : 2 : Y
+GND* : H5 : : : : 2 :
+GND* : H6 : : : : 2 :
+GND* : H7 : : : : 2 :
+GND : H8 : gnd : : : :
+GND : H9 : gnd : : : :
+GND* : H10 : : : : 3 :
+CONF_DONE : H11 : : : : 3 :
+nCONFIG : H12 : : : : 3 :
+nSTATUS : H13 : : : : 3 :
+TEMPDIODEp : H14 : : : : :
+TDI : H15 : input : : : 4 :
+GND* : H16 : : : : 4 :
+GND : H17 : gnd : : : :
+d_v_enable : H18 : output : 3.3-V LVTTL : : 4 : Y
+GND* : H19 : : : : 5 :
+GND* : H20 : : : : 5 :
+GND* : H21 : : : : 5 :
+GND* : H22 : : : : 5 :
+GND* : H23 : : : : 5 :
+GND* : H24 : : : : 5 :
+d_hsync_counter[3] : H25 : output : 3.3-V LVTTL : : 5 : N
+d_toggle_counter[0] : H26 : output : 3.3-V LVTTL : : 5 : Y
+d_vsync_counter[3] : J1 : output : 3.3-V LVTTL : : 2 : N
+GND* : J2 : : : : 2 :
+GND* : J3 : : : : 2 :
+d_vsync_counter[6] : J4 : output : 3.3-V LVTTL : : 2 : N
+GND* : J5 : : : : 2 :
+GND* : J6 : : : : 2 :
+GND* : J7 : : : : 2 :
+GND* : J8 : : : : 2 :
+GND : J9 : gnd : : : :
+GND : J10 : gnd : : : :
+VCCIO3 : J11 : power : : 3.3V : 3 :
+VCCIO3 : J12 : power : : 3.3V : 3 :
+GND : J13 : gnd : : : :
+GND : J14 : gnd : : : :
+VCCIO4 : J15 : power : : 3.3V : 4 :
+VCCIO4 : J16 : power : : 3.3V : 4 :
+GND : J17 : gnd : : : :
+GND : J18 : gnd : : : :
+GND* : J19 : : : : 5 :
+GND* : J20 : : : : 5 :
+d_h_enable : J21 : output : 3.3-V LVTTL : : 5 : Y
+d_line_counter[2] : J22 : output : 3.3-V LVTTL : : 5 : Y
+d_vsync_counter[1] : J23 : output : 3.3-V LVTTL : : 5 : N
+GND* : J24 : : : : 5 :
+GND* : J25 : : : : 5 :
+GND* : J26 : : : : 5 :
+GND* : K1 : : : : 2 :
+GND* : K2 : : : : 2 :
+d_state_clk : K3 : output : 3.3-V LVTTL : : 2 : Y
+d_line_counter[1] : K4 : output : 3.3-V LVTTL : : 2 : Y
+d_column_counter[9] : K5 : output : 3.3-V LVTTL : : 2 : Y
+d_line_counter[0] : K6 : output : 3.3-V LVTTL : : 2 : Y
+GND* : K7 : : : : 2 :
+GND* : K8 : : : : 2 :
+GND* : K9 : : : : 2 :
+GND : K10 : gnd : : : :
+VCCINT : K11 : power : : 1.5V : :
+GND : K12 : gnd : : : :
+VCCINT : K13 : power : : 1.5V : :
+GND : K14 : gnd : : : :
+VCCINT : K15 : power : : 1.5V : :
+GND : K16 : gnd : : : :
+VCCINT : K17 : power : : 1.5V : :
+GND : K18 : gnd : : : :
+d_column_counter[8] : K19 : output : 3.3-V LVTTL : : 5 : Y
+d_b : K20 : output : 3.3-V LVTTL : : 5 : Y
+GND* : K21 : : : : 5 :
+GND* : K22 : : : : 5 :
+d_column_counter[7] : K23 : output : 3.3-V LVTTL : : 5 : Y
+d_g : K24 : output : 3.3-V LVTTL : : 5 : Y
+GND* : K25 : : : : 5 :
+GND* : K26 : : : : 5 :
+VCCIO2 : L1 : power : : 3.3V : 2 :
+d_column_counter[6] : L2 : output : 3.3-V LVTTL : : 2 : Y
+d_r : L3 : output : 3.3-V LVTTL : : 2 : Y
+d_column_counter[5] : L4 : output : 3.3-V LVTTL : : 2 : Y
+d_vsync : L5 : output : 3.3-V LVTTL : : 2 : Y
+d_column_counter[4] : L6 : output : 3.3-V LVTTL : : 2 : Y
+d_hsync : L7 : output : 3.3-V LVTTL : : 2 : Y
+GND : L8 : gnd : : : :
+VCCIO2 : L9 : power : : 3.3V : 2 :
+VCCINT : L10 : power : : 1.5V : :
+GND : L11 : gnd : : : :
+VCCINT : L12 : power : : 1.5V : :
+GND : L13 : gnd : : : :
+VCCINT : L14 : power : : 1.5V : :
+GND : L15 : gnd : : : :
+VCCINT : L16 : power : : 1.5V : :
+GND : L17 : gnd : : : :
+VCCIO5 : L18 : power : : 3.3V : 5 :
+GND : L19 : gnd : : : :
+d_column_counter[3] : L20 : output : 3.3-V LVTTL : : 5 : Y
+d_column_counter[2] : L21 : output : 3.3-V LVTTL : : 5 : Y
+d_column_counter[1] : L22 : output : 3.3-V LVTTL : : 5 : Y
+d_column_counter[0] : L23 : output : 3.3-V LVTTL : : 5 : Y
+d_line_counter[7] : L24 : output : 3.3-V LVTTL : : 5 : Y
+d_line_counter[8] : L25 : output : 3.3-V LVTTL : : 5 : Y
+VCCIO5 : L26 : power : : 3.3V : 5 :
+GND+ : M1 : : : : 2 :
+VCCG_PLL1 : M2 : power : : 1.5V : :
+VCCA_PLL1 : M3 : power : : 1.5V : :
+d_vsync_state[6] : M4 : output : 3.3-V LVTTL : : 2 : Y
+d_line_counter[6] : M5 : output : 3.3-V LVTTL : : 2 : Y
+d_line_counter[5] : M6 : output : 3.3-V LVTTL : : 2 : Y
+d_vsync_state[5] : M7 : output : 3.3-V LVTTL : : 2 : Y
+d_line_counter[4] : M8 : output : 3.3-V LVTTL : : 2 : Y
+d_line_counter[3] : M9 : output : 3.3-V LVTTL : : 2 : Y
+GND : M10 : gnd : : : :
+VCCINT : M11 : power : : 1.5V : :
+GND : M12 : gnd : : : :
+VCCINT : M13 : power : : 1.5V : :
+GND : M14 : gnd : : : :
+VCCINT : M15 : power : : 1.5V : :
+GND : M16 : gnd : : : :
+VCCINT : M17 : power : : 1.5V : :
+d_vsync_state[4] : M18 : output : 3.3-V LVTTL : : 5 : Y
+d_vsync_state[3] : M19 : output : 3.3-V LVTTL : : 5 : Y
+GND* : M20 : : : : 5 :
+GND* : M21 : : : : 5 :
+GND* : M22 : : : : 5 :
+GND* : M23 : : : : 5 :
+GND+ : M24 : : : : 5 :
+GND+ : M25 : : : : 5 :
+GND+ : M26 : : : : 5 :
+GND : N1 : gnd : : : :
+GND+ : N2 : : : : 2 :
+board_clk : N3 : input : 3.3-V LVTTL : : 2 : Y
+GNDG_PLL1 : N4 : gnd : : : :
+GNDA_PLL1 : N5 : gnd : : : :
+GND* : N6 : : : : 2 :
+seven_seg_pin[8] : N7 : output : 3.3-V LVTTL : : 2 : Y
+seven_seg_pin[9] : N8 : output : 3.3-V LVTTL : : 2 : Y
+GND : N9 : gnd : : : :
+VCCINT : N10 : power : : 1.5V : :
+GND : N11 : gnd : : : :
+VCCINT : N12 : power : : 1.5V : :
+GND : N13 : gnd : : : :
+VCCINT : N14 : power : : 1.5V : :
+GND : N15 : gnd : : : :
+VCCINT : N16 : power : : 1.5V : :
+GND : N17 : gnd : : : :
+GND : N18 : gnd : : : :
+GND* : N19 : : : : 6 :
+GND* : N20 : : : : 5 :
+GND* : N21 : : : : 5 :
+GNDG_PLL4 : N22 : gnd : : : :
+GNDA_PLL4 : N23 : gnd : : : :
+VCCG_PLL4 : N24 : power : : 1.5V : :
+VCCA_PLL4 : N25 : power : : 1.5V : :
+GND : N26 : gnd : : : :
+GND : P1 : gnd : : : :
+GNDG_PLL2 : P2 : gnd : : : :
+GNDA_PLL2 : P3 : gnd : : : :
+VCCG_PLL2 : P4 : power : : 1.5V : :
+VCCA_PLL2 : P5 : power : : 1.5V : :
+GND* : P6 : : : : 1 :
+GND* : P7 : : : : 1 :
+GND* : P8 : : : : 2 :
+GND : P9 : gnd : : : :
+GND : P10 : gnd : : : :
+VCCINT : P11 : power : : 1.5V : :
+GND : P12 : gnd : : : :
+VCCINT : P13 : power : : 1.5V : :
+GND : P14 : gnd : : : :
+VCCINT : P15 : power : : 1.5V : :
+GND : P16 : gnd : : : :
+VCCINT : P17 : power : : 1.5V : :
+GND : P18 : gnd : : : :
+GND* : P19 : : : : 6 :
+GND* : P20 : : : : 6 :
+GND* : P21 : : : : 6 :
+VCCA_PLL3 : P22 : power : : 1.5V : :
+VCCG_PLL3 : P23 : power : : 1.5V : :
+GND+ : P24 : : : : 6 :
+GND+ : P25 : : : : 6 :
+GND : P26 : gnd : : : :
+GND+ : R1 : : : : 1 :
+GND+ : R2 : : : : 1 :
+GND+ : R3 : : : : 1 :
+seven_seg_pin[10] : R4 : output : 3.3-V LVTTL : : 1 : Y
+GND* : R5 : : : : 1 :
+seven_seg_pin[11] : R6 : output : 3.3-V LVTTL : : 1 : Y
+GND* : R7 : : : : 1 :
+seven_seg_pin[0] : R8 : output : 3.3-V LVTTL : : 1 : Y
+seven_seg_pin[1] : R9 : output : 3.3-V LVTTL : : 1 : Y
+VCCINT : R10 : power : : 1.5V : :
+GND : R11 : gnd : : : :
+VCCINT : R12 : power : : 1.5V : :
+GND : R13 : gnd : : : :
+VCCINT : R14 : power : : 1.5V : :
+GND : R15 : gnd : : : :
+VCCINT : R16 : power : : 1.5V : :
+GND : R17 : gnd : : : :
+GND : R18 : gnd : : : :
+seven_seg_pin[2] : R19 : output : 3.3-V LVTTL : : 6 : Y
+seven_seg_pin[3] : R20 : output : 3.3-V LVTTL : : 6 : Y
+seven_seg_pin[4] : R21 : output : 3.3-V LVTTL : : 6 : Y
+seven_seg_pin[5] : R22 : output : 3.3-V LVTTL : : 6 : Y
+seven_seg_pin[6] : R23 : output : 3.3-V LVTTL : : 6 : Y
+GNDA_PLL3 : R24 : gnd : : : :
+GNDG_PLL3 : R25 : gnd : : : :
+GND+ : R26 : : : : 6 :
+VCCIO1 : T1 : power : : 3.3V : 1 :
+seven_seg_pin[13] : T2 : output : 3.3-V LVTTL : : 1 : Y
+GND* : T3 : : : : 1 :
+r1_pin : T4 : output : 3.3-V LVTTL : : 1 : Y
+g1_pin : T5 : output : 3.3-V LVTTL : : 1 : Y
+b1_pin : T6 : output : 3.3-V LVTTL : : 1 : Y
+r2_pin : T7 : output : 3.3-V LVTTL : : 1 : Y
+GND : T8 : gnd : : : :
+VCCIO1 : T9 : power : : 3.3V : 1 :
+GND : T10 : gnd : : : :
+VCCINT : T11 : power : : 1.5V : :
+GND : T12 : gnd : : : :
+VCCINT : T13 : power : : 1.5V : :
+GND : T14 : gnd : : : :
+VCCINT : T15 : power : : 1.5V : :
+GND : T16 : gnd : : : :
+VCCINT : T17 : power : : 1.5V : :
+VCCIO6 : T18 : power : : 3.3V : 6 :
+d_toggle_counter[24] : T19 : output : 3.3-V LVTTL : : 6 : Y
+GND* : T20 : : : : 6 :
+GND* : T21 : : : : 6 :
+GND* : T22 : : : : 6 :
+GND* : T23 : : : : 6 :
+g2_pin : T24 : output : 3.3-V LVTTL : : 6 : Y
+GND* : T25 : : : : 6 :
+VCCIO6 : T26 : power : : 3.3V : 6 :
+GND* : U1 : : : : 1 :
+GND* : U2 : : : : 1 :
+GND* : U3 : : : : 1 :
+GND* : U4 : : : : 1 :
+GND* : U5 : : : : 1 :
+GND* : U6 : : : : 1 :
+GND* : U7 : : : : 1 :
+GND* : U8 : : : : 1 :
+GND* : U9 : : : : 1 :
+VCCINT : U10 : power : : 1.5V : :
+GND : U11 : gnd : : : :
+VCCINT : U12 : power : : 1.5V : :
+GND : U13 : gnd : : : :
+VCCINT : U14 : power : : 1.5V : :
+GND : U15 : gnd : : : :
+VCCINT : U16 : power : : 1.5V : :
+GND : U17 : gnd : : : :
+GND* : U18 : : : : 6 :
+GND* : U19 : : : : 6 :
+GND* : U20 : : : : 6 :
+GND* : U21 : : : : 6 :
+GND* : U22 : : : : 6 :
+GND* : U23 : : : : 6 :
+GND* : U24 : : : : 6 :
+GND* : U25 : : : : 6 :
+GND* : U26 : : : : 6 :
+GND* : V1 : : : : 1 :
+GND* : V2 : : : : 1 :
+GND* : V3 : : : : 1 :
+GND* : V4 : : : : 1 :
+GND* : V5 : : : : 1 :
+GND* : V6 : : : : 1 :
+GND : V7 : gnd : : : :
+GND* : V8 : : : : 1 :
+GND : V9 : gnd : : : :
+GND : V10 : gnd : : : :
+VCCIO8 : V11 : power : : 3.3V : 8 :
+VCCIO8 : V12 : power : : 3.3V : 8 :
+GND : V13 : gnd : : : :
+GND : V14 : gnd : : : :
+VCCIO7 : V15 : power : : 3.3V : 7 :
+VCCIO7 : V16 : power : : 3.3V : 7 :
+GND : V17 : gnd : : : :
+GND : V18 : gnd : : : :
+GND* : V19 : : : : 6 :
+GND : V20 : gnd : : : :
+GND* : V21 : : : : 6 :
+GND* : V22 : : : : 6 :
+GND* : V23 : : : : 6 :
+GND* : V24 : : : : 6 :
+GND* : V25 : : : : 6 :
+GND* : V26 : : : : 6 :
+GND* : W1 : : : : 1 :
+GND* : W2 : : : : 1 :
+GND* : W3 : : : : 1 :
+GND* : W4 : : : : 1 :
+GND* : W5 : : : : 1 :
+GND* : W6 : : : : 1 :
+GND* : W7 : : : : 1 :
+GND* : W8 : : : : 1 :
+GND* : W9 : : : : 8 :
+GND* : W10 : : : : 8 :
+GND : W11 : gnd : : : :
+PLL_ENA : W12 : : : : 8 :
+MSEL2 : W13 : : : : 8 :
+nCEO : W14 : : : : 7 :
+GND* : W15 : : : : 7 :
+PORSEL : W16 : : : : 7 :
+GND* : W17 : : : : 7 :
+GND* : W18 : : : : 7 :
+GND* : W19 : : : : 6 :
+GND* : W20 : : : : 6 :
+d_toggle_counter[1] : W21 : output : 3.3-V LVTTL : : 6 : N
+d_toggle_counter[8] : W22 : output : 3.3-V LVTTL : : 6 : N
+GND* : W23 : : : : 6 :
+d_toggle_counter[10] : W24 : output : 3.3-V LVTTL : : 6 : N
+GND* : W25 : : : : 6 :
+GND* : W26 : : : : 6 :
+GND* : Y1 : : : : 1 :
+d_hsync_state[3] : Y2 : output : 3.3-V LVTTL : : 1 : Y
+GND* : Y3 : : : : 1 :
+GND* : Y4 : : : : 1 :
+d_hsync_state[0] : Y5 : output : 3.3-V LVTTL : : 1 : Y
+GND* : Y6 : : : : 1 :
+GND : Y7 : gnd : : : :
+GND* : Y8 : : : : 8 :
+GND* : Y9 : : : : 8 :
+GND* : Y10 : : : : 8 :
+seven_seg_pin[7] : Y11 : output : 3.3-V LVTTL : : 8 : Y
+MSEL0 : Y12 : : : : 8 :
+MSEL1 : Y13 : : : : 8 :
+nCE : Y14 : : : : 7 :
+VCCSEL : Y15 : : : : 7 :
+GND* : Y16 : : : : 7 :
+GND* : Y17 : : : : 7 :
+GND* : Y18 : : : : 7 :
+GND* : Y19 : : : : 7 :
+GND* : Y20 : : : : 7 :
+GND : Y21 : gnd : : : :
+GND* : Y22 : : : : 6 :
+d_set_column_counter : Y23 : output : 3.3-V LVTTL : : 6 : Y
+GND* : Y24 : : : : 6 :
+GND* : Y25 : : : : 6 :
+GND* : Y26 : : : : 6 :
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Full Version
+# Date created = 14:44:43 October 28, 2009
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "14:44:43 October 28, 2009"
+
+# Revisions
+
+PROJECT_REVISION = "vga_pll"
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Full Version
+# Date created = 14:44:43 October 28, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# vga_pll_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY Stratix
+set_global_assignment -name DEVICE EP1S25F672C6
+set_global_assignment -name TOP_LEVEL_ENTITY vga_pll
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006"
+set_global_assignment -name LAST_QUARTUS_VERSION 6.0
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro"
+set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf
+set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+set_global_assignment -name BSF_FILE ../../src/vpll.bsf
+set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
+set_location_assignment PIN_E24 -to b0_pin
+set_location_assignment PIN_T6 -to b1_pin
+set_location_assignment PIN_N3 -to board_clk
+set_location_assignment PIN_E23 -to g0_pin
+set_location_assignment PIN_T5 -to g1_pin
+set_location_assignment PIN_T24 -to g2_pin
+set_location_assignment PIN_F1 -to hsync_pin
+set_location_assignment PIN_E22 -to r0_pin
+set_location_assignment PIN_T4 -to r1_pin
+set_location_assignment PIN_T7 -to r2_pin
+set_location_assignment PIN_A5 -to reset
+set_location_assignment PIN_F2 -to vsync_pin
+set_location_assignment PIN_Y5 -to d_hsync_state[0]
+set_location_assignment PIN_F19 -to d_hsync_state[1]
+set_location_assignment PIN_F17 -to d_hsync_state[2]
+set_location_assignment PIN_Y2 -to d_hsync_state[3]
+set_location_assignment PIN_F10 -to d_hsync_state[4]
+set_location_assignment PIN_F9 -to d_hsync_state[5]
+set_location_assignment PIN_F6 -to d_hsync_state[6]
+set_location_assignment PIN_H4 -to d_hsync_counter[0]
+set_location_assignment PIN_G25 -to d_hsync_counter[7]
+set_location_assignment PIN_G22 -to d_hsync_counter[8]
+set_location_assignment PIN_G18 -to d_hsync_counter[9]
+set_location_assignment PIN_F5 -to d_vsync_state[0]
+set_location_assignment PIN_F4 -to d_vsync_state[1]
+set_location_assignment PIN_F3 -to d_vsync_state[2]
+set_location_assignment PIN_M19 -to d_vsync_state[3]
+set_location_assignment PIN_M18 -to d_vsync_state[4]
+set_location_assignment PIN_M7 -to d_vsync_state[5]
+set_location_assignment PIN_M4 -to d_vsync_state[6]
+set_location_assignment PIN_G9 -to d_vsync_counter[0]
+set_location_assignment PIN_G6 -to d_vsync_counter[7]
+set_location_assignment PIN_G4 -to d_vsync_counter[8]
+set_location_assignment PIN_G2 -to d_vsync_counter[9]
+set_location_assignment PIN_K6 -to d_line_counter[0]
+set_location_assignment PIN_K4 -to d_line_counter[1]
+set_location_assignment PIN_J22 -to d_line_counter[2]
+set_location_assignment PIN_M9 -to d_line_counter[3]
+set_location_assignment PIN_M8 -to d_line_counter[4]
+set_location_assignment PIN_M6 -to d_line_counter[5]
+set_location_assignment PIN_M5 -to d_line_counter[6]
+set_location_assignment PIN_L24 -to d_line_counter[7]
+set_location_assignment PIN_L25 -to d_line_counter[8]
+set_location_assignment PIN_L23 -to d_column_counter[0]
+set_location_assignment PIN_L22 -to d_column_counter[1]
+set_location_assignment PIN_L21 -to d_column_counter[2]
+set_location_assignment PIN_L20 -to d_column_counter[3]
+set_location_assignment PIN_L6 -to d_column_counter[4]
+set_location_assignment PIN_L4 -to d_column_counter[5]
+set_location_assignment PIN_L2 -to d_column_counter[6]
+set_location_assignment PIN_K23 -to d_column_counter[7]
+set_location_assignment PIN_K19 -to d_column_counter[8]
+set_location_assignment PIN_K5 -to d_column_counter[9]
+set_location_assignment PIN_L7 -to d_hsync
+set_location_assignment PIN_L5 -to d_vsync
+set_location_assignment PIN_F26 -to d_set_hsync_counter
+set_location_assignment PIN_F24 -to d_set_vsync_counter
+set_location_assignment PIN_F21 -to d_set_line_counter
+set_location_assignment PIN_Y23 -to d_set_column_counter
+set_location_assignment PIN_L3 -to d_r
+set_location_assignment PIN_K24 -to d_g
+set_location_assignment PIN_K20 -to d_b
+set_location_assignment PIN_H18 -to d_v_enable
+set_location_assignment PIN_J21 -to d_h_enable
+set_location_assignment PIN_R8 -to seven_seg_pin[0]
+set_location_assignment PIN_R9 -to seven_seg_pin[1]
+set_location_assignment PIN_R19 -to seven_seg_pin[2]
+set_location_assignment PIN_R20 -to seven_seg_pin[3]
+set_location_assignment PIN_R21 -to seven_seg_pin[4]
+set_location_assignment PIN_R22 -to seven_seg_pin[5]
+set_location_assignment PIN_R23 -to seven_seg_pin[6]
+set_location_assignment PIN_Y11 -to seven_seg_pin[7]
+set_location_assignment PIN_N7 -to seven_seg_pin[8]
+set_location_assignment PIN_N8 -to seven_seg_pin[9]
+set_location_assignment PIN_R4 -to seven_seg_pin[10]
+set_location_assignment PIN_R6 -to seven_seg_pin[11]
+set_location_assignment PIN_AA11 -to seven_seg_pin[12]
+set_location_assignment PIN_T2 -to seven_seg_pin[13]
+set_location_assignment PIN_K3 -to d_state_clk
+set_location_assignment PIN_H3 -to d_toggle
+set_location_assignment PIN_H26 -to d_toggle_counter[0]
+set_location_assignment PIN_G24 -to d_toggle_counter[15]
+set_location_assignment PIN_G23 -to d_toggle_counter[16]
+set_location_assignment PIN_G21 -to d_toggle_counter[17]
+set_location_assignment PIN_G20 -to d_toggle_counter[18]
+set_location_assignment PIN_G5 -to d_toggle_counter[19]
+set_location_assignment PIN_G3 -to d_toggle_counter[20]
+set_location_assignment PIN_G1 -to d_toggle_counter[21]
+set_location_assignment PIN_F25 -to d_toggle_counter[22]
+set_location_assignment PIN_F23 -to d_toggle_counter[23]
+set_location_assignment PIN_T19 -to d_toggle_counter[24]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state
+set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin
\ No newline at end of file
--- /dev/null
+Classic Timing Analyzer report for vga_pll
+Wed Oct 28 14:55:36 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Timing Analyzer Summary
+ 3. Timing Analyzer Settings
+ 4. Clock Settings Summary
+ 5. Parallel Compilation
+ 6. Clock Setup: 'vpll:inst1|altpll:altpll_component|_clk0'
+ 7. Clock Hold: 'vpll:inst1|altpll:altpll_component|_clk0'
+ 8. tsu
+ 9. tco
+ 10. tpd
+ 11. th
+ 12. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++---------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------+---------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++---------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------+---------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
+; Worst-case tsu ; N/A ; None ; 10.866 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; -- ; board_clk ; 0 ;
+; Worst-case tco ; N/A ; None ; 11.498 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[7] ; board_clk ; -- ; 0 ;
+; Worst-case tpd ; N/A ; None ; 16.036 ns ; reset ; seven_seg_pin[7] ; -- ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -5.569 ns ; reset ; vga:inst|dly_counter[0] ; -- ; board_clk ; 0 ;
+; Clock Setup: 'vpll:inst1|altpll:altpll_component|_clk0' ; 28.830 ns ; 27.19 MHz ( period = 36.777 ns ) ; 125.83 MHz ( period = 7.947 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0 ;
+; Clock Hold: 'vpll:inst1|altpll:altpll_component|_clk0' ; 0.730 ns ; 27.19 MHz ( period = 36.777 ns ) ; N/A ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++---------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------+---------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Option ; Setting ; From ; To ; Entity Name ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Device Name ; EP1S25F672C6 ; ; ; ;
+; Timing Models ; Final ; ; ; ;
+; Default hold multicycle ; Same as Multicycle ; ; ; ;
+; Cut paths between unrelated clock domains ; On ; ; ; ;
+; Cut off read during write signal paths ; On ; ; ; ;
+; Cut off feedback from I/O pins ; On ; ; ; ;
+; Report Combined Fast/Slow Timing ; Off ; ; ; ;
+; Ignore Clock Settings ; Off ; ; ; ;
+; Analyze latches as synchronous elements ; On ; ; ; ;
+; Enable Recovery/Removal analysis ; Off ; ; ; ;
+; Enable Clock Latency ; Off ; ; ; ;
+; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+; Minimum Core Junction Temperature ; 0 ; ; ; ;
+; Maximum Core Junction Temperature ; 85 ; ; ; ;
+; Number of source nodes to report per destination node ; 10 ; ; ; ;
+; Number of destination nodes to report ; 10 ; ; ; ;
+; Number of paths to report ; 200 ; ; ; ;
+; Report Minimum Timing Checks ; Off ; ; ; ;
+; Use Fast Timing Models ; Off ; ; ; ;
+; Report IO Paths Separately ; Off ; ; ; ;
+; Perform Multicorner Analysis ; Off ; ; ; ;
+; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+; Output I/O Timing Endpoint ; Near End ; ; ; ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Settings Summary ;
++------------------------------------------+--------------------+------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+
+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
++------------------------------------------+--------------------+------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+
+; vpll:inst1|altpll:altpll_component|_clk0 ; ; PLL output ; 27.19 MHz ; 0.000 ns ; 0.000 ns ; board_clk ; 31 ; 38 ; -1.030 ns ; ;
+; board_clk ; ; User Pin ; 33.33 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
++------------------------------------------+--------------------+------------+------------------+---------------+--------------+-----------+-----------------------+---------------------+-----------+--------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 2 ;
+; Maximum allowed ; 2 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 1 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; 1 processor ; 100.0% ;
+; 2 processors ; 0.0% ;
++----------------------------+-------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'vpll:inst1|altpll:altpll_component|_clk0' ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; 28.830 ns ; 125.83 MHz ( period = 7.947 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.570 ns ; 7.740 ns ;
+; 28.883 ns ; 126.68 MHz ( period = 7.894 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.570 ns ; 7.687 ns ;
+; 28.945 ns ; 127.68 MHz ( period = 7.832 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.570 ns ; 7.625 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 28.997 ns ; 128.53 MHz ( period = 7.780 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.594 ns ;
+; 29.078 ns ; 129.89 MHz ( period = 7.699 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.524 ns ; 7.446 ns ;
+; 29.095 ns ; 130.17 MHz ( period = 7.682 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.570 ns ; 7.475 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.143 ns ; 130.99 MHz ( period = 7.634 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.448 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.164 ns ; 131.35 MHz ( period = 7.613 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.427 ns ;
+; 29.247 ns ; 132.80 MHz ( period = 7.530 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.344 ns ;
+; 29.247 ns ; 132.80 MHz ( period = 7.530 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.344 ns ;
+; 29.247 ns ; 132.80 MHz ( period = 7.530 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.344 ns ;
+; 29.247 ns ; 132.80 MHz ( period = 7.530 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.344 ns ;
+; 29.247 ns ; 132.80 MHz ( period = 7.530 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.344 ns ;
+; 29.393 ns ; 135.43 MHz ( period = 7.384 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.198 ns ;
+; 29.393 ns ; 135.43 MHz ( period = 7.384 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.198 ns ;
+; 29.393 ns ; 135.43 MHz ( period = 7.384 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.198 ns ;
+; 29.393 ns ; 135.43 MHz ( period = 7.384 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.198 ns ;
+; 29.393 ns ; 135.43 MHz ( period = 7.384 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.198 ns ;
+; 29.414 ns ; 135.81 MHz ( period = 7.363 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.177 ns ;
+; 29.414 ns ; 135.81 MHz ( period = 7.363 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.177 ns ;
+; 29.414 ns ; 135.81 MHz ( period = 7.363 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.177 ns ;
+; 29.414 ns ; 135.81 MHz ( period = 7.363 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.177 ns ;
+; 29.414 ns ; 135.81 MHz ( period = 7.363 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 7.177 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.606 ns ; 139.45 MHz ( period = 7.171 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.985 ns ;
+; 29.659 ns ; 140.49 MHz ( period = 7.118 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.932 ns ;
+; 29.702 ns ; 141.34 MHz ( period = 7.075 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.609 ns ; 6.907 ns ;
+; 29.805 ns ; 143.43 MHz ( period = 6.972 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.786 ns ;
+; 29.815 ns ; 143.64 MHz ( period = 6.962 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.570 ns ; 6.755 ns ;
+; 29.826 ns ; 143.86 MHz ( period = 6.951 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.765 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.853 ns ; 144.43 MHz ( period = 6.924 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.738 ns ;
+; 29.856 ns ; 144.49 MHz ( period = 6.921 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.735 ns ;
+; 29.856 ns ; 144.49 MHz ( period = 6.921 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.735 ns ;
+; 29.856 ns ; 144.49 MHz ( period = 6.921 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.735 ns ;
+; 29.856 ns ; 144.49 MHz ( period = 6.921 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.735 ns ;
+; 29.856 ns ; 144.49 MHz ( period = 6.921 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.735 ns ;
+; 29.904 ns ; 145.50 MHz ( period = 6.873 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.524 ns ; 6.620 ns ;
+; 29.966 ns ; 146.82 MHz ( period = 6.811 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.633 ns ;
+; 29.966 ns ; 146.82 MHz ( period = 6.811 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.633 ns ;
+; 29.966 ns ; 146.82 MHz ( period = 6.811 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.633 ns ;
+; 29.966 ns ; 146.82 MHz ( period = 6.811 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.633 ns ;
+; 29.966 ns ; 146.82 MHz ( period = 6.811 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.633 ns ;
+; 29.966 ns ; 146.82 MHz ( period = 6.811 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.633 ns ;
+; 30.041 ns ; 148.46 MHz ( period = 6.736 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.609 ns ; 6.568 ns ;
+; 30.103 ns ; 149.84 MHz ( period = 6.674 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.488 ns ;
+; 30.103 ns ; 149.84 MHz ( period = 6.674 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.488 ns ;
+; 30.103 ns ; 149.84 MHz ( period = 6.674 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.488 ns ;
+; 30.103 ns ; 149.84 MHz ( period = 6.674 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.488 ns ;
+; 30.103 ns ; 149.84 MHz ( period = 6.674 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.488 ns ;
+; 30.112 ns ; 150.04 MHz ( period = 6.665 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.487 ns ;
+; 30.112 ns ; 150.04 MHz ( period = 6.665 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.487 ns ;
+; 30.112 ns ; 150.04 MHz ( period = 6.665 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.487 ns ;
+; 30.112 ns ; 150.04 MHz ( period = 6.665 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.487 ns ;
+; 30.112 ns ; 150.04 MHz ( period = 6.665 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.487 ns ;
+; 30.112 ns ; 150.04 MHz ( period = 6.665 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.487 ns ;
+; 30.133 ns ; 150.51 MHz ( period = 6.644 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.466 ns ;
+; 30.133 ns ; 150.51 MHz ( period = 6.644 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.466 ns ;
+; 30.133 ns ; 150.51 MHz ( period = 6.644 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.466 ns ;
+; 30.133 ns ; 150.51 MHz ( period = 6.644 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.466 ns ;
+; 30.133 ns ; 150.51 MHz ( period = 6.644 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.466 ns ;
+; 30.133 ns ; 150.51 MHz ( period = 6.644 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.466 ns ;
+; 30.144 ns ; 150.76 MHz ( period = 6.633 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.609 ns ; 6.465 ns ;
+; 30.145 ns ; 150.78 MHz ( period = 6.632 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.570 ns ; 6.425 ns ;
+; 30.203 ns ; 152.11 MHz ( period = 6.574 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.609 ns ; 6.406 ns ;
+; 30.268 ns ; 153.63 MHz ( period = 6.509 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.323 ns ;
+; 30.325 ns ; 154.99 MHz ( period = 6.452 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.609 ns ; 6.284 ns ;
+; 30.384 ns ; 156.42 MHz ( period = 6.393 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.207 ns ;
+; 30.384 ns ; 156.42 MHz ( period = 6.393 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.207 ns ;
+; 30.384 ns ; 156.42 MHz ( period = 6.393 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.207 ns ;
+; 30.405 ns ; 156.94 MHz ( period = 6.372 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.609 ns ; 6.204 ns ;
+; 30.409 ns ; 157.04 MHz ( period = 6.368 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 6.191 ns ;
+; 30.409 ns ; 157.04 MHz ( period = 6.368 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 6.191 ns ;
+; 30.409 ns ; 157.04 MHz ( period = 6.368 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 6.191 ns ;
+; 30.449 ns ; 158.03 MHz ( period = 6.328 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 6.196 ns ;
+; 30.449 ns ; 158.03 MHz ( period = 6.328 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 6.196 ns ;
+; 30.449 ns ; 158.03 MHz ( period = 6.328 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 6.196 ns ;
+; 30.457 ns ; 158.23 MHz ( period = 6.320 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.134 ns ;
+; 30.457 ns ; 158.23 MHz ( period = 6.320 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.134 ns ;
+; 30.457 ns ; 158.23 MHz ( period = 6.320 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.134 ns ;
+; 30.515 ns ; 159.69 MHz ( period = 6.262 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.076 ns ;
+; 30.523 ns ; 159.90 MHz ( period = 6.254 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.609 ns ; 6.086 ns ;
+; 30.542 ns ; 160.38 MHz ( period = 6.235 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.049 ns ;
+; 30.542 ns ; 160.38 MHz ( period = 6.235 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.049 ns ;
+; 30.542 ns ; 160.38 MHz ( period = 6.235 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 6.049 ns ;
+; 30.575 ns ; 161.24 MHz ( period = 6.202 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.024 ns ;
+; 30.575 ns ; 161.24 MHz ( period = 6.202 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.024 ns ;
+; 30.575 ns ; 161.24 MHz ( period = 6.202 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.024 ns ;
+; 30.575 ns ; 161.24 MHz ( period = 6.202 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.024 ns ;
+; 30.575 ns ; 161.24 MHz ( period = 6.202 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.024 ns ;
+; 30.575 ns ; 161.24 MHz ( period = 6.202 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 6.024 ns ;
+; 30.578 ns ; 161.32 MHz ( period = 6.199 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.609 ns ; 6.031 ns ;
+; 30.594 ns ; 161.73 MHz ( period = 6.183 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.997 ns ;
+; 30.594 ns ; 161.73 MHz ( period = 6.183 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.997 ns ;
+; 30.594 ns ; 161.73 MHz ( period = 6.183 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.997 ns ;
+; 30.597 ns ; 161.81 MHz ( period = 6.180 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 6.003 ns ;
+; 30.597 ns ; 161.81 MHz ( period = 6.180 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 6.003 ns ;
+; 30.597 ns ; 161.81 MHz ( period = 6.180 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 6.003 ns ;
+; 30.600 ns ; 161.89 MHz ( period = 6.177 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.991 ns ;
+; 30.600 ns ; 161.89 MHz ( period = 6.177 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.991 ns ;
+; 30.600 ns ; 161.89 MHz ( period = 6.177 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.991 ns ;
+; 30.633 ns ; 162.76 MHz ( period = 6.144 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.958 ns ;
+; 30.633 ns ; 162.76 MHz ( period = 6.144 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.958 ns ;
+; 30.633 ns ; 162.76 MHz ( period = 6.144 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.958 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.650 ns ; 163.21 MHz ( period = 6.127 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.941 ns ;
+; 30.655 ns ; 163.35 MHz ( period = 6.122 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 5.945 ns ;
+; 30.655 ns ; 163.35 MHz ( period = 6.122 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 5.945 ns ;
+; 30.655 ns ; 163.35 MHz ( period = 6.122 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 5.945 ns ;
+; 30.662 ns ; 163.53 MHz ( period = 6.115 ns ) ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.570 ns ; 5.908 ns ;
+; 30.679 ns ; 163.99 MHz ( period = 6.098 ns ) ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.609 ns ; 5.930 ns ;
+; 30.688 ns ; 164.23 MHz ( period = 6.089 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 5.912 ns ;
+; 30.737 ns ; 165.56 MHz ( period = 6.040 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 5.863 ns ;
+; 30.737 ns ; 165.56 MHz ( period = 6.040 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 5.863 ns ;
+; 30.737 ns ; 165.56 MHz ( period = 6.040 ns ) ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.600 ns ; 5.863 ns ;
+; 30.754 ns ; 166.03 MHz ( period = 6.023 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.837 ns ;
+; 30.754 ns ; 166.03 MHz ( period = 6.023 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.837 ns ;
+; 30.754 ns ; 166.03 MHz ( period = 6.023 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.837 ns ;
+; 30.799 ns ; 167.28 MHz ( period = 5.978 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.792 ns ;
+; 30.799 ns ; 167.28 MHz ( period = 5.978 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.792 ns ;
+; 30.799 ns ; 167.28 MHz ( period = 5.978 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.792 ns ;
+; 30.815 ns ; 167.73 MHz ( period = 5.962 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.776 ns ;
+; 30.815 ns ; 167.73 MHz ( period = 5.962 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.776 ns ;
+; 30.815 ns ; 167.73 MHz ( period = 5.962 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.776 ns ;
+; 30.822 ns ; 167.93 MHz ( period = 5.955 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 5.777 ns ;
+; 30.822 ns ; 167.93 MHz ( period = 5.955 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 5.777 ns ;
+; 30.822 ns ; 167.93 MHz ( period = 5.955 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 5.777 ns ;
+; 30.822 ns ; 167.93 MHz ( period = 5.955 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 5.777 ns ;
+; 30.822 ns ; 167.93 MHz ( period = 5.955 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 5.777 ns ;
+; 30.822 ns ; 167.93 MHz ( period = 5.955 ns ) ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.599 ns ; 5.777 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.838 ns ; 168.38 MHz ( period = 5.939 ns ) ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.645 ns ; 5.807 ns ;
+; 30.859 ns ; 168.98 MHz ( period = 5.918 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.732 ns ;
+; 30.860 ns ; 169.00 MHz ( period = 5.917 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.731 ns ;
+; 30.861 ns ; 169.03 MHz ( period = 5.916 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.730 ns ;
+; 30.863 ns ; 169.09 MHz ( period = 5.914 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.728 ns ;
+; 30.864 ns ; 169.12 MHz ( period = 5.913 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.727 ns ;
+; 30.865 ns ; 169.15 MHz ( period = 5.912 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.726 ns ;
+; 30.868 ns ; 169.23 MHz ( period = 5.909 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.723 ns ;
+; 30.871 ns ; 169.32 MHz ( period = 5.906 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.720 ns ;
+; 30.874 ns ; 169.41 MHz ( period = 5.903 ns ) ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 36.777 ns ; 36.591 ns ; 5.717 ns ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'vpll:inst1|altpll:altpll_component|_clk0' ;
++-----------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------------------------------------+------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++-----------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------------------------------------+------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 0.730 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.654 ns ;
+; 0.743 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.667 ns ;
+; 0.743 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.667 ns ;
+; 0.743 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.667 ns ;
+; 0.746 ns ; vga:inst|vga_control:vga_control_unit|toggle_sig ; vga:inst|vga_control:vga_control_unit|r ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.670 ns ;
+; 0.747 ns ; vga:inst|vga_control:vga_control_unit|toggle_sig ; vga:inst|vga_control:vga_control_unit|toggle_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.671 ns ;
+; 0.754 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.678 ns ;
+; 0.759 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.683 ns ;
+; 0.759 ns ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.683 ns ;
+; 0.759 ns ; vga:inst|dly_counter[0] ; vga:inst|dly_counter[0] ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.683 ns ;
+; 0.894 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.818 ns ;
+; 0.909 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.833 ns ;
+; 0.913 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.837 ns ;
+; 0.984 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.908 ns ;
+; 0.984 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.908 ns ;
+; 0.984 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.908 ns ;
+; 0.985 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.909 ns ;
+; 0.985 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.909 ns ;
+; 0.985 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.909 ns ;
+; 0.987 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.911 ns ;
+; 0.987 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.911 ns ;
+; 0.987 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.911 ns ;
+; 0.988 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.912 ns ;
+; 0.988 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.912 ns ;
+; 0.988 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.912 ns ;
+; 0.992 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.916 ns ;
+; 0.999 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.923 ns ;
+; 1.005 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.929 ns ;
+; 1.006 ns ; vga:inst|dly_counter[1] ; vga:inst|dly_counter[1] ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.930 ns ;
+; 1.011 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 0.935 ns ;
+; 1.095 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.019 ns ;
+; 1.095 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.019 ns ;
+; 1.095 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.019 ns ;
+; 1.095 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.019 ns ;
+; 1.096 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.020 ns ;
+; 1.096 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.020 ns ;
+; 1.096 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.020 ns ;
+; 1.103 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.027 ns ;
+; 1.103 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.027 ns ;
+; 1.103 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.027 ns ;
+; 1.104 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ;
+; 1.104 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ;
+; 1.104 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ;
+; 1.104 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ;
+; 1.104 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ;
+; 1.104 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.028 ns ;
+; 1.106 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.030 ns ;
+; 1.117 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.041 ns ;
+; 1.120 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.044 ns ;
+; 1.144 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.068 ns ;
+; 1.156 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.080 ns ;
+; 1.174 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.098 ns ;
+; 1.176 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.100 ns ;
+; 1.255 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.179 ns ;
+; 1.278 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.202 ns ;
+; 1.333 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.081 ns ; 1.252 ns ;
+; 1.378 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.302 ns ;
+; 1.381 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.305 ns ;
+; 1.384 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.308 ns ;
+; 1.387 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.311 ns ;
+; 1.390 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.314 ns ;
+; 1.392 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.316 ns ;
+; 1.393 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.317 ns ;
+; 1.395 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.319 ns ;
+; 1.395 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.319 ns ;
+; 1.395 ns ; vga:inst|dly_counter[1] ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.319 ns ;
+; 1.400 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.324 ns ;
+; 1.409 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.333 ns ;
+; 1.410 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.334 ns ;
+; 1.410 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.334 ns ;
+; 1.410 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.334 ns ;
+; 1.411 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.335 ns ;
+; 1.411 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.335 ns ;
+; 1.411 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.335 ns ;
+; 1.413 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.337 ns ;
+; 1.413 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.337 ns ;
+; 1.413 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.337 ns ;
+; 1.414 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.338 ns ;
+; 1.414 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.338 ns ;
+; 1.414 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.338 ns ;
+; 1.424 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.348 ns ;
+; 1.425 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.349 ns ;
+; 1.434 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.358 ns ;
+; 1.440 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.364 ns ;
+; 1.461 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.067 ns ; 1.394 ns ;
+; 1.461 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.385 ns ;
+; 1.462 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.386 ns ;
+; 1.470 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.394 ns ;
+; 1.470 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.394 ns ;
+; 1.470 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.394 ns ;
+; 1.471 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.395 ns ;
+; 1.471 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.395 ns ;
+; 1.471 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.395 ns ;
+; 1.473 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.397 ns ;
+; 1.473 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.397 ns ;
+; 1.473 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.397 ns ;
+; 1.474 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.398 ns ;
+; 1.474 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.398 ns ;
+; 1.474 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.398 ns ;
+; 1.482 ns ; vga:inst|dly_counter[0] ; vga:inst|dly_counter[1] ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.085 ns ; 1.397 ns ;
+; 1.483 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.067 ns ; 1.416 ns ;
+; 1.484 ns ; vga:inst|dly_counter[0] ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.085 ns ; 1.399 ns ;
+; 1.485 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.409 ns ;
+; 1.489 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.067 ns ; 1.422 ns ;
+; 1.500 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.424 ns ;
+; 1.507 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.431 ns ;
+; 1.510 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.434 ns ;
+; 1.512 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.436 ns ;
+; 1.518 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.442 ns ;
+; 1.526 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.450 ns ;
+; 1.526 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.450 ns ;
+; 1.526 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.450 ns ;
+; 1.526 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.450 ns ;
+; 1.527 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.451 ns ;
+; 1.527 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.451 ns ;
+; 1.527 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.451 ns ;
+; 1.530 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.454 ns ;
+; 1.530 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.454 ns ;
+; 1.530 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.454 ns ;
+; 1.531 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.455 ns ;
+; 1.531 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.455 ns ;
+; 1.531 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.455 ns ;
+; 1.533 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.457 ns ;
+; 1.533 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.457 ns ;
+; 1.533 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.457 ns ;
+; 1.534 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.458 ns ;
+; 1.534 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.458 ns ;
+; 1.534 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.458 ns ;
+; 1.534 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.458 ns ;
+; 1.534 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.458 ns ;
+; 1.534 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.458 ns ;
+; 1.535 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.459 ns ;
+; 1.535 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.459 ns ;
+; 1.535 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.459 ns ;
+; 1.537 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.461 ns ;
+; 1.541 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.465 ns ;
+; 1.545 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.469 ns ;
+; 1.548 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.472 ns ;
+; 1.555 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.479 ns ;
+; 1.557 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.481 ns ;
+; 1.558 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.482 ns ;
+; 1.558 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.482 ns ;
+; 1.558 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.482 ns ;
+; 1.560 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.484 ns ;
+; 1.560 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.484 ns ;
+; 1.564 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.488 ns ;
+; 1.567 ns ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.491 ns ;
+; 1.568 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.492 ns ;
+; 1.570 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.494 ns ;
+; 1.585 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.509 ns ;
+; 1.586 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.067 ns ; 1.519 ns ;
+; 1.586 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.510 ns ;
+; 1.586 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.510 ns ;
+; 1.586 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.510 ns ;
+; 1.586 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.510 ns ;
+; 1.591 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.515 ns ;
+; 1.591 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.515 ns ;
+; 1.591 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.515 ns ;
+; 1.594 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.518 ns ;
+; 1.594 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.518 ns ;
+; 1.594 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.518 ns ;
+; 1.594 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.518 ns ;
+; 1.594 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.518 ns ;
+; 1.594 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.518 ns ;
+; 1.600 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.524 ns ;
+; 1.608 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.532 ns ;
+; 1.610 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.534 ns ;
+; 1.617 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.541 ns ;
+; 1.617 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.541 ns ;
+; 1.617 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.541 ns ;
+; 1.620 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.544 ns ;
+; 1.634 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.558 ns ;
+; 1.635 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.559 ns ;
+; 1.655 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.579 ns ;
+; 1.656 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.580 ns ;
+; 1.656 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.580 ns ;
+; 1.659 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.583 ns ;
+; 1.664 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.588 ns ;
+; 1.669 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.068 ns ; 1.601 ns ;
+; 1.669 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.068 ns ; 1.601 ns ;
+; 1.669 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.068 ns ; 1.601 ns ;
+; 1.669 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.068 ns ; 1.601 ns ;
+; 1.669 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.068 ns ; 1.601 ns ;
+; 1.673 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.071 ns ; 1.602 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.679 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.603 ns ;
+; 1.686 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; vpll:inst1|altpll:altpll_component|_clk0 ; vpll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.076 ns ; 1.610 ns ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ;
++-----------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------------------------------------+------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; tsu ;
++-------+--------------+------------+-------+----------------------------------------------------------+-----------+
+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
++-------+--------------+------------+-------+----------------------------------------------------------+-----------+
+; N/A ; None ; 10.866 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; board_clk ;
+; N/A ; None ; 10.866 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; board_clk ;
+; N/A ; None ; 10.866 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; board_clk ;
+; N/A ; None ; 10.477 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; board_clk ;
+; N/A ; None ; 10.337 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; board_clk ;
+; N/A ; None ; 10.337 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; board_clk ;
+; N/A ; None ; 10.181 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; board_clk ;
+; N/A ; None ; 9.896 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; board_clk ;
+; N/A ; None ; 9.553 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; board_clk ;
+; N/A ; None ; 9.047 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; board_clk ;
+; N/A ; None ; 9.047 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; board_clk ;
+; N/A ; None ; 9.047 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; board_clk ;
+; N/A ; None ; 8.768 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; board_clk ;
+; N/A ; None ; 8.527 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; board_clk ;
+; N/A ; None ; 8.527 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; board_clk ;
+; N/A ; None ; 8.527 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; board_clk ;
+; N/A ; None ; 8.527 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; board_clk ;
+; N/A ; None ; 8.527 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; board_clk ;
+; N/A ; None ; 8.527 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; board_clk ;
+; N/A ; None ; 8.527 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; board_clk ;
+; N/A ; None ; 8.417 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; board_clk ;
+; N/A ; None ; 8.272 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; board_clk ;
+; N/A ; None ; 8.087 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; board_clk ;
+; N/A ; None ; 8.086 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; board_clk ;
+; N/A ; None ; 8.031 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; board_clk ;
+; N/A ; None ; 7.974 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; board_clk ;
+; N/A ; None ; 7.874 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; board_clk ;
+; N/A ; None ; 7.731 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; board_clk ;
+; N/A ; None ; 7.731 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; board_clk ;
+; N/A ; None ; 7.731 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; board_clk ;
+; N/A ; None ; 7.731 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; board_clk ;
+; N/A ; None ; 7.731 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; board_clk ;
+; N/A ; None ; 7.730 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; board_clk ;
+; N/A ; None ; 7.730 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; board_clk ;
+; N/A ; None ; 7.622 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; board_clk ;
+; N/A ; None ; 7.432 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; board_clk ;
+; N/A ; None ; 6.139 ns ; reset ; vga:inst|dly_counter[1] ; board_clk ;
+; N/A ; None ; 6.135 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; board_clk ;
+; N/A ; None ; 6.000 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|h_sync ; board_clk ;
+; N/A ; None ; 5.680 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|v_sync ; board_clk ;
+; N/A ; None ; 5.679 ns ; reset ; vga:inst|dly_counter[0] ; board_clk ;
++-------+--------------+------------+-------+----------------------------------------------------------+-----------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; tco ;
++-------+--------------+------------+-------------------------------------------------------------+----------------------+------------+
+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
++-------+--------------+------------+-------------------------------------------------------------+----------------------+------------+
+; N/A ; None ; 11.498 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[7] ; board_clk ;
+; N/A ; None ; 11.488 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[12] ; board_clk ;
+; N/A ; None ; 11.016 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[7] ; board_clk ;
+; N/A ; None ; 11.006 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[12] ; board_clk ;
+; N/A ; None ; 10.588 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[2] ; board_clk ;
+; N/A ; None ; 10.106 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[2] ; board_clk ;
+; N/A ; None ; 9.477 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[1] ; board_clk ;
+; N/A ; None ; 9.477 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[11] ; board_clk ;
+; N/A ; None ; 9.469 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[10] ; board_clk ;
+; N/A ; None ; 9.408 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; d_hsync_state[0] ; board_clk ;
+; N/A ; None ; 9.318 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[9] ; board_clk ;
+; N/A ; None ; 9.303 ns ; vga:inst|dly_counter[0] ; seven_seg_pin[8] ; board_clk ;
+; N/A ; None ; 9.292 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; d_hsync_state[3] ; board_clk ;
+; N/A ; None ; 8.995 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[1] ; board_clk ;
+; N/A ; None ; 8.995 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[11] ; board_clk ;
+; N/A ; None ; 8.987 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[10] ; board_clk ;
+; N/A ; None ; 8.892 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; d_line_counter[8] ; board_clk ;
+; N/A ; None ; 8.836 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[9] ; board_clk ;
+; N/A ; None ; 8.821 ns ; vga:inst|dly_counter[1] ; seven_seg_pin[8] ; board_clk ;
+; N/A ; None ; 8.765 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; d_set_hsync_counter ; board_clk ;
+; N/A ; None ; 8.649 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; d_vsync_state[4] ; board_clk ;
+; N/A ; None ; 8.622 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; d_column_counter[1] ; board_clk ;
+; N/A ; None ; 8.569 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; d_line_counter[7] ; board_clk ;
+; N/A ; None ; 8.509 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; d_hsync_counter[1] ; board_clk ;
+; N/A ; None ; 8.495 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; d_column_counter[0] ; board_clk ;
+; N/A ; None ; 8.493 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; d_line_counter[2] ; board_clk ;
+; N/A ; None ; 8.490 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_6 ; d_toggle_counter[6] ; board_clk ;
+; N/A ; None ; 8.377 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; d_column_counter[2] ; board_clk ;
+; N/A ; None ; 8.357 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; d_vsync_state[3] ; board_clk ;
+; N/A ; None ; 8.356 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; d_column_counter[8] ; board_clk ;
+; N/A ; None ; 8.325 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; d_vsync_state[5] ; board_clk ;
+; N/A ; None ; 8.258 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; d_vsync_state[2] ; board_clk ;
+; N/A ; None ; 8.244 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; d_set_vsync_counter ; board_clk ;
+; N/A ; None ; 8.224 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; d_hsync_state[6] ; board_clk ;
+; N/A ; None ; 8.193 ns ; vga:inst|vga_control:vga_control_unit|toggle_sig ; d_toggle ; board_clk ;
+; N/A ; None ; 8.158 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; d_column_counter[3] ; board_clk ;
+; N/A ; None ; 8.130 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_19 ; d_toggle_counter[19] ; board_clk ;
+; N/A ; None ; 8.108 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; d_line_counter[4] ; board_clk ;
+; N/A ; None ; 8.106 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; d_column_counter[7] ; board_clk ;
+; N/A ; None ; 8.075 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_20 ; d_toggle_counter[20] ; board_clk ;
+; N/A ; None ; 8.054 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; d_hsync_state[4] ; board_clk ;
+; N/A ; None ; 8.052 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; d_vsync_state[1] ; board_clk ;
+; N/A ; None ; 8.041 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; d_vsync_state[0] ; board_clk ;
+; N/A ; None ; 7.958 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; d_vsync_counter[7] ; board_clk ;
+; N/A ; None ; 7.933 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; d_vsync_state[6] ; board_clk ;
+; N/A ; None ; 7.911 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; d_vsync_counter[8] ; board_clk ;
+; N/A ; None ; 7.885 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; d_line_counter[5] ; board_clk ;
+; N/A ; None ; 7.885 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; d_line_counter[6] ; board_clk ;
+; N/A ; None ; 7.864 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; d_line_counter[1] ; board_clk ;
+; N/A ; None ; 7.834 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; d_column_counter[9] ; board_clk ;
+; N/A ; None ; 7.827 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; d_hsync_state[2] ; board_clk ;
+; N/A ; None ; 7.823 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; d_vsync_counter[1] ; board_clk ;
+; N/A ; None ; 7.767 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; d_set_vsync_counter ; board_clk ;
+; N/A ; None ; 7.753 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; d_hsync_state[5] ; board_clk ;
+; N/A ; None ; 7.748 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_16 ; d_toggle_counter[16] ; board_clk ;
+; N/A ; None ; 7.744 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; d_hsync_counter[7] ; board_clk ;
+; N/A ; None ; 7.726 ns ; vga:inst|vga_control:vga_control_unit|r ; d_r ; board_clk ;
+; N/A ; None ; 7.719 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; d_line_counter[3] ; board_clk ;
+; N/A ; None ; 7.711 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; d_vsync_counter[4] ; board_clk ;
+; N/A ; None ; 7.682 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; d_hsync_counter[4] ; board_clk ;
+; N/A ; None ; 7.678 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; d_vsync_counter[5] ; board_clk ;
+; N/A ; None ; 7.673 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; d_hsync_counter[5] ; board_clk ;
+; N/A ; None ; 7.651 ns ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; d_line_counter[0] ; board_clk ;
+; N/A ; None ; 7.617 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_13 ; d_toggle_counter[13] ; board_clk ;
+; N/A ; None ; 7.599 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; d_column_counter[6] ; board_clk ;
+; N/A ; None ; 7.591 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; d_column_counter[5] ; board_clk ;
+; N/A ; None ; 7.589 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; d_vsync_counter[6] ; board_clk ;
+; N/A ; None ; 7.572 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; d_vsync_counter[9] ; board_clk ;
+; N/A ; None ; 7.486 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; d_hsync_counter[0] ; board_clk ;
+; N/A ; None ; 7.476 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_2 ; d_toggle_counter[2] ; board_clk ;
+; N/A ; None ; 7.458 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; d_vsync_counter[0] ; board_clk ;
+; N/A ; None ; 7.433 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; d_set_column_counter ; board_clk ;
+; N/A ; None ; 7.416 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; d_hsync_state[1] ; board_clk ;
+; N/A ; None ; 7.373 ns ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; d_column_counter[4] ; board_clk ;
+; N/A ; None ; 7.330 ns ; vga:inst|vga_control:vga_control_unit|r ; r0_pin ; board_clk ;
+; N/A ; None ; 7.297 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_0 ; d_toggle_counter[0] ; board_clk ;
+; N/A ; None ; 7.257 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; d_hsync_counter[6] ; board_clk ;
+; N/A ; None ; 7.247 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; d_hsync_counter[3] ; board_clk ;
+; N/A ; None ; 7.230 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; d_hsync_counter[8] ; board_clk ;
+; N/A ; None ; 7.202 ns ; vga:inst|vga_control:vga_control_unit|b ; d_b ; board_clk ;
+; N/A ; None ; 7.194 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; d_vsync_counter[3] ; board_clk ;
+; N/A ; None ; 7.185 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; d_set_hsync_counter ; board_clk ;
+; N/A ; None ; 7.171 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_18 ; d_toggle_counter[18] ; board_clk ;
+; N/A ; None ; 7.161 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; d_vsync_counter[2] ; board_clk ;
+; N/A ; None ; 7.160 ns ; vga:inst|vga_driver:vga_driver_unit|h_sync ; d_hsync ; board_clk ;
+; N/A ; None ; 7.157 ns ; vga:inst|vga_control:vga_control_unit|r ; r2_pin ; board_clk ;
+; N/A ; None ; 7.131 ns ; vga:inst|vga_control:vga_control_unit|r ; r1_pin ; board_clk ;
+; N/A ; None ; 7.090 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; d_hsync_counter[9] ; board_clk ;
+; N/A ; None ; 7.012 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_3 ; d_toggle_counter[3] ; board_clk ;
+; N/A ; None ; 6.796 ns ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; d_hsync_counter[2] ; board_clk ;
+; N/A ; None ; 6.735 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_17 ; d_toggle_counter[17] ; board_clk ;
+; N/A ; None ; 6.701 ns ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; d_h_enable ; board_clk ;
+; N/A ; None ; 6.697 ns ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; d_set_line_counter ; board_clk ;
+; N/A ; None ; 6.686 ns ; vga:inst|vga_control:vga_control_unit|b ; b0_pin ; board_clk ;
+; N/A ; None ; 6.613 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_15 ; d_toggle_counter[15] ; board_clk ;
+; N/A ; None ; 6.602 ns ; vga:inst|vga_control:vga_control_unit|b ; b1_pin ; board_clk ;
+; N/A ; None ; 6.340 ns ; vga:inst|vga_driver:vga_driver_unit|v_sync ; d_vsync ; board_clk ;
+; N/A ; None ; 6.216 ns ; vga:inst|vga_driver:vga_driver_unit|h_sync ; hsync_pin ; board_clk ;
+; N/A ; None ; 6.159 ns ; vga:inst|vga_driver:vga_driver_unit|v_sync ; vsync_pin ; board_clk ;
+; N/A ; None ; 5.785 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_5 ; d_toggle_counter[5] ; board_clk ;
+; N/A ; None ; 5.535 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_7 ; d_toggle_counter[7] ; board_clk ;
+; N/A ; None ; 5.412 ns ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; d_v_enable ; board_clk ;
+; N/A ; None ; 5.351 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_4 ; d_toggle_counter[4] ; board_clk ;
+; N/A ; None ; 5.347 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_9 ; d_toggle_counter[9] ; board_clk ;
+; N/A ; None ; 5.314 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_11 ; d_toggle_counter[11] ; board_clk ;
+; N/A ; None ; 5.060 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_12 ; d_toggle_counter[12] ; board_clk ;
+; N/A ; None ; 5.055 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_14 ; d_toggle_counter[14] ; board_clk ;
+; N/A ; None ; 4.894 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_8 ; d_toggle_counter[8] ; board_clk ;
+; N/A ; None ; 4.891 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_10 ; d_toggle_counter[10] ; board_clk ;
+; N/A ; None ; 4.812 ns ; vga:inst|vga_control:vga_control_unit|toggle_counter_sig_1 ; d_toggle_counter[1] ; board_clk ;
+; N/A ; None ; 3.704 ns ; vpll:inst1|altpll:altpll_component|_clk0 ; d_state_clk ; board_clk ;
++-------+--------------+------------+-------------------------------------------------------------+----------------------+------------+
+
+
++-------------------------------------------------------------------------+
+; tpd ;
++-------+-------------------+-----------------+-------+-------------------+
+; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
++-------+-------------------+-----------------+-------+-------------------+
+; N/A ; None ; 16.036 ns ; reset ; seven_seg_pin[7] ;
+; N/A ; None ; 16.026 ns ; reset ; seven_seg_pin[12] ;
+; N/A ; None ; 15.126 ns ; reset ; seven_seg_pin[2] ;
+; N/A ; None ; 14.015 ns ; reset ; seven_seg_pin[1] ;
+; N/A ; None ; 14.015 ns ; reset ; seven_seg_pin[11] ;
+; N/A ; None ; 14.007 ns ; reset ; seven_seg_pin[10] ;
+; N/A ; None ; 13.856 ns ; reset ; seven_seg_pin[9] ;
+; N/A ; None ; 13.841 ns ; reset ; seven_seg_pin[8] ;
++-------+-------------------+-----------------+-------+-------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; th ;
++---------------+-------------+-----------+-------+----------------------------------------------------------+-----------+
+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
++---------------+-------------+-----------+-------+----------------------------------------------------------+-----------+
+; N/A ; None ; -5.569 ns ; reset ; vga:inst|dly_counter[0] ; board_clk ;
+; N/A ; None ; -5.570 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|v_sync ; board_clk ;
+; N/A ; None ; -5.890 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|h_sync ; board_clk ;
+; N/A ; None ; -6.025 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_6 ; board_clk ;
+; N/A ; None ; -6.029 ns ; reset ; vga:inst|dly_counter[1] ; board_clk ;
+; N/A ; None ; -6.631 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_5 ; board_clk ;
+; N/A ; None ; -6.634 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_6 ; board_clk ;
+; N/A ; None ; -6.637 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_7 ; board_clk ;
+; N/A ; None ; -6.640 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_8 ; board_clk ;
+; N/A ; None ; -6.643 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 ; board_clk ;
+; N/A ; None ; -6.645 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_4 ; board_clk ;
+; N/A ; None ; -6.646 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_3 ; board_clk ;
+; N/A ; None ; -6.648 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_2 ; board_clk ;
+; N/A ; None ; -6.648 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_1 ; board_clk ;
+; N/A ; None ; -6.648 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_counter_0 ; board_clk ;
+; N/A ; None ; -7.132 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_5 ; board_clk ;
+; N/A ; None ; -7.135 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_6 ; board_clk ;
+; N/A ; None ; -7.138 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_7 ; board_clk ;
+; N/A ; None ; -7.141 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_8 ; board_clk ;
+; N/A ; None ; -7.144 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_9 ; board_clk ;
+; N/A ; None ; -7.145 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_4 ; board_clk ;
+; N/A ; None ; -7.146 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_3 ; board_clk ;
+; N/A ; None ; -7.148 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_2 ; board_clk ;
+; N/A ; None ; -7.149 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_1 ; board_clk ;
+; N/A ; None ; -7.150 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_counter_0 ; board_clk ;
+; N/A ; None ; -7.322 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_6 ; board_clk ;
+; N/A ; None ; -7.512 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_5 ; board_clk ;
+; N/A ; None ; -7.513 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_0 ; board_clk ;
+; N/A ; None ; -7.620 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_7 ; board_clk ;
+; N/A ; None ; -7.620 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_3 ; board_clk ;
+; N/A ; None ; -7.621 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_8 ; board_clk ;
+; N/A ; None ; -7.621 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_6 ; board_clk ;
+; N/A ; None ; -7.621 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4 ; board_clk ;
+; N/A ; None ; -7.621 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_2 ; board_clk ;
+; N/A ; None ; -7.621 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_0 ; board_clk ;
+; N/A ; None ; -7.864 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_1 ; board_clk ;
+; N/A ; None ; -7.921 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|line_counter_sig_1 ; board_clk ;
+; N/A ; None ; -7.976 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_7 ; board_clk ;
+; N/A ; None ; -7.977 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_8 ; board_clk ;
+; N/A ; None ; -8.044 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_4 ; board_clk ;
+; N/A ; None ; -8.044 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_2 ; board_clk ;
+; N/A ; None ; -8.044 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_5 ; board_clk ;
+; N/A ; None ; -8.053 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|vsync_state_3 ; board_clk ;
+; N/A ; None ; -8.109 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|h_enable_sig ; board_clk ;
+; N/A ; None ; -8.162 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 ; board_clk ;
+; N/A ; None ; -8.417 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_6 ; board_clk ;
+; N/A ; None ; -8.417 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_5 ; board_clk ;
+; N/A ; None ; -8.417 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_4 ; board_clk ;
+; N/A ; None ; -8.417 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_3 ; board_clk ;
+; N/A ; None ; -8.417 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_2 ; board_clk ;
+; N/A ; None ; -8.417 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_1 ; board_clk ;
+; N/A ; None ; -8.417 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|column_counter_sig_0 ; board_clk ;
+; N/A ; None ; -8.847 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_0 ; board_clk ;
+; N/A ; None ; -8.847 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_2 ; board_clk ;
+; N/A ; None ; -8.847 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_5 ; board_clk ;
+; N/A ; None ; -8.877 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|v_enable_sig ; board_clk ;
+; N/A ; None ; -8.987 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_3 ; board_clk ;
+; N/A ; None ; -9.146 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_1 ; board_clk ;
+; N/A ; None ; -9.146 ns ; reset ; vga:inst|vga_driver:vga_driver_unit|hsync_state_4 ; board_clk ;
++---------------+-------------+-----------+-------+----------------------------------------------------------+-----------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:55:36 2009
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only
+Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
+Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
+Info: Found timing assignments -- calculating delays
+Info: Slack time is 28.83 ns for clock "vpll:inst1|altpll:altpll_component|_clk0" between source register "vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4" and destination register "vga:inst|vga_control:vga_control_unit|r"
+ Info: Fmax is 125.83 MHz (period= 7.947 ns)
+ Info: + Largest register to register requirement is 36.570 ns
+ Info: + Setup relationship between source and destination is 36.777 ns
+ Info: + Latch edge is 35.747 ns
+ Info: Clock period of Destination clock "vpll:inst1|altpll:altpll_component|_clk0" is 36.777 ns with offset of -1.030 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Destination register is 1
+ Info: - Launch edge is -1.030 ns
+ Info: Clock period of Source clock "vpll:inst1|altpll:altpll_component|_clk0" is 36.777 ns with offset of -1.030 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Source register is 1
+ Info: + Largest clock skew is -0.021 ns
+ Info: + Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.043 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.483 ns) + CELL(0.560 ns) = 2.043 ns; Loc. = LC_X72_Y6_N1; Fanout = 4; REG Node = 'vga:inst|vga_control:vga_control_unit|r'
+ Info: Total cell delay = 0.560 ns ( 27.41 % )
+ Info: Total interconnect delay = 1.483 ns ( 72.59 % )
+ Info: - Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.064 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.504 ns) + CELL(0.560 ns) = 2.064 ns; Loc. = LC_X22_Y42_N7; Fanout = 9; REG Node = 'vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4'
+ Info: Total cell delay = 0.560 ns ( 27.13 % )
+ Info: Total interconnect delay = 1.504 ns ( 72.87 % )
+ Info: - Micro clock to output delay of source is 0.176 ns
+ Info: - Micro setup delay of destination is 0.010 ns
+ Info: - Longest register to register delay is 7.740 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y42_N7; Fanout = 9; REG Node = 'vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4'
+ Info: 2: + IC(1.012 ns) + CELL(0.332 ns) = 1.344 ns; Loc. = LC_X18_Y42_N6; Fanout = 1; COMB Node = 'vga:inst|vga_control:vga_control_unit|un13_v_enablelto4_0'
+ Info: 3: + IC(0.336 ns) + CELL(0.332 ns) = 2.012 ns; Loc. = LC_X18_Y42_N4; Fanout = 1; COMB Node = 'vga:inst|vga_control:vga_control_unit|un13_v_enablelto6'
+ Info: 4: + IC(1.768 ns) + CELL(0.332 ns) = 4.112 ns; Loc. = LC_X28_Y35_N2; Fanout = 2; COMB Node = 'vga:inst|vga_control:vga_control_unit|b_next_0_sqmuxa_7_4'
+ Info: 5: + IC(3.139 ns) + CELL(0.489 ns) = 7.740 ns; Loc. = LC_X72_Y6_N1; Fanout = 4; REG Node = 'vga:inst|vga_control:vga_control_unit|r'
+ Info: Total cell delay = 1.485 ns ( 19.19 % )
+ Info: Total interconnect delay = 6.255 ns ( 80.81 % )
+Info: No valid register-to-register data paths exist for clock "board_clk"
+Info: Minimum slack time is 730 ps for clock "vpll:inst1|altpll:altpll_component|_clk0" between source register "vga:inst|vga_driver:vga_driver_unit|hsync_state_0" and destination register "vga:inst|vga_driver:vga_driver_unit|hsync_state_5"
+ Info: + Shortest register to register delay is 0.654 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|hsync_state_0'
+ Info: 2: + IC(0.419 ns) + CELL(0.235 ns) = 0.654 ns; Loc. = LC_X42_Y42_N2; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|hsync_state_5'
+ Info: Total cell delay = 0.235 ns ( 35.93 % )
+ Info: Total interconnect delay = 0.419 ns ( 64.07 % )
+ Info: - Smallest register to register requirement is -0.076 ns
+ Info: + Hold relationship between source and destination is 0.000 ns
+ Info: + Latch edge is -1.030 ns
+ Info: Clock period of Destination clock "vpll:inst1|altpll:altpll_component|_clk0" is 36.777 ns with offset of -1.030 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Destination register is 1
+ Info: Multicycle Hold factor for Destination register is 1
+ Info: - Launch edge is -1.030 ns
+ Info: Clock period of Source clock "vpll:inst1|altpll:altpll_component|_clk0" is 36.777 ns with offset of -1.030 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Source register is 1
+ Info: Multicycle Hold factor for Source register is 1
+ Info: + Smallest clock skew is 0.000 ns
+ Info: + Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.097 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.537 ns) + CELL(0.560 ns) = 2.097 ns; Loc. = LC_X42_Y42_N2; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|hsync_state_5'
+ Info: Total cell delay = 0.560 ns ( 26.70 % )
+ Info: Total interconnect delay = 1.537 ns ( 73.30 % )
+ Info: - Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.097 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.537 ns) + CELL(0.560 ns) = 2.097 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|hsync_state_0'
+ Info: Total cell delay = 0.560 ns ( 26.70 % )
+ Info: Total interconnect delay = 1.537 ns ( 73.30 % )
+ Info: - Micro clock to output delay of source is 0.176 ns
+ Info: + Micro hold delay of destination is 0.100 ns
+Info: tsu for register "vga:inst|vga_driver:vga_driver_unit|hsync_state_0" (data pin = "reset", clock pin = "board_clk") is 10.866 ns
+ Info: + Longest pin to register delay is 11.923 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'
+ Info: 2: + IC(5.624 ns) + CELL(0.213 ns) = 6.978 ns; Loc. = LC_X30_Y38_N3; Fanout = 53; COMB Node = 'vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x'
+ Info: 3: + IC(2.397 ns) + CELL(0.213 ns) = 9.588 ns; Loc. = LC_X52_Y41_N9; Fanout = 6; COMB Node = 'vga:inst|vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0'
+ Info: 4: + IC(1.609 ns) + CELL(0.726 ns) = 11.923 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|hsync_state_0'
+ Info: Total cell delay = 2.293 ns ( 19.23 % )
+ Info: Total interconnect delay = 9.630 ns ( 80.77 % )
+ Info: + Micro setup delay of destination is 0.010 ns
+ Info: - Offset between input clock "board_clk" and output clock "vpll:inst1|altpll:altpll_component|_clk0" is -1.030 ns
+ Info: - Shortest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.097 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.537 ns) + CELL(0.560 ns) = 2.097 ns; Loc. = LC_X42_Y42_N9; Fanout = 4; REG Node = 'vga:inst|vga_driver:vga_driver_unit|hsync_state_0'
+ Info: Total cell delay = 0.560 ns ( 26.70 % )
+ Info: Total interconnect delay = 1.537 ns ( 73.30 % )
+Info: tco from clock "board_clk" to destination pin "seven_seg_pin[7]" through register "vga:inst|dly_counter[0]" is 11.498 ns
+ Info: + Offset between input clock "board_clk" and output clock "vpll:inst1|altpll:altpll_component|_clk0" is -1.030 ns
+ Info: + Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to source register is 2.043 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.483 ns) + CELL(0.560 ns) = 2.043 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst|dly_counter[0]'
+ Info: Total cell delay = 0.560 ns ( 27.41 % )
+ Info: Total interconnect delay = 1.483 ns ( 72.59 % )
+ Info: + Micro clock to output delay of source is 0.176 ns
+ Info: + Longest register to pin delay is 10.309 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst|dly_counter[0]'
+ Info: 2: + IC(1.164 ns) + CELL(0.087 ns) = 1.251 ns; Loc. = LC_X30_Y38_N3; Fanout = 53; COMB Node = 'vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x'
+ Info: 3: + IC(4.867 ns) + CELL(4.191 ns) = 10.309 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin[7]'
+ Info: Total cell delay = 4.278 ns ( 41.50 % )
+ Info: Total interconnect delay = 6.031 ns ( 58.50 % )
+Info: Longest tpd from source pin "reset" to destination pin "seven_seg_pin[7]" is 16.036 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'
+ Info: 2: + IC(5.624 ns) + CELL(0.213 ns) = 6.978 ns; Loc. = LC_X30_Y38_N3; Fanout = 53; COMB Node = 'vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x'
+ Info: 3: + IC(4.867 ns) + CELL(4.191 ns) = 16.036 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin[7]'
+ Info: Total cell delay = 5.545 ns ( 34.58 % )
+ Info: Total interconnect delay = 10.491 ns ( 65.42 % )
+Info: th for register "vga:inst|dly_counter[0]" (data pin = "reset", clock pin = "board_clk") is -5.569 ns
+ Info: + Offset between input clock "board_clk" and output clock "vpll:inst1|altpll:altpll_component|_clk0" is -1.030 ns
+ Info: + Longest clock path from clock "vpll:inst1|altpll:altpll_component|_clk0" to destination register is 2.043 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 84; CLK Node = 'vpll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.483 ns) + CELL(0.560 ns) = 2.043 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst|dly_counter[0]'
+ Info: Total cell delay = 0.560 ns ( 27.41 % )
+ Info: Total interconnect delay = 1.483 ns ( 72.59 % )
+ Info: + Micro hold delay of destination is 0.100 ns
+ Info: - Shortest pin to register delay is 6.682 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'
+ Info: 2: + IC(5.177 ns) + CELL(0.364 ns) = 6.682 ns; Loc. = LC_X30_Y39_N4; Fanout = 10; REG Node = 'vga:inst|dly_counter[0]'
+ Info: Total cell delay = 1.505 ns ( 22.52 % )
+ Info: Total interconnect delay = 5.177 ns ( 77.48 % )
+Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 141 megabytes
+ Info: Processing ended: Wed Oct 28 14:55:37 2009
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+
+
--- /dev/null
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type : Worst-case tsu
+Slack : N/A
+Required Time : None
+Actual Time : 10.866 ns
+From : reset
+To : vga:inst|vga_driver:vga_driver_unit|hsync_state_5
+From Clock : --
+To Clock : board_clk
+Failed Paths : 0
+
+Type : Worst-case tco
+Slack : N/A
+Required Time : None
+Actual Time : 11.498 ns
+From : vga:inst|dly_counter[0]
+To : seven_seg_pin[7]
+From Clock : board_clk
+To Clock : --
+Failed Paths : 0
+
+Type : Worst-case tpd
+Slack : N/A
+Required Time : None
+Actual Time : 16.036 ns
+From : reset
+To : seven_seg_pin[7]
+From Clock : --
+To Clock : --
+Failed Paths : 0
+
+Type : Worst-case th
+Slack : N/A
+Required Time : None
+Actual Time : -5.569 ns
+From : reset
+To : vga:inst|dly_counter[0]
+From Clock : --
+To Clock : board_clk
+Failed Paths : 0
+
+Type : Clock Setup: 'vpll:inst1|altpll:altpll_component|_clk0'
+Slack : 28.830 ns
+Required Time : 27.19 MHz ( period = 36.777 ns )
+Actual Time : 125.83 MHz ( period = 7.947 ns )
+From : vga:inst|vga_driver:vga_driver_unit|line_counter_sig_4
+To : vga:inst|vga_control:vga_control_unit|r
+From Clock : vpll:inst1|altpll:altpll_component|_clk0
+To Clock : vpll:inst1|altpll:altpll_component|_clk0
+Failed Paths : 0
+
+Type : Clock Hold: 'vpll:inst1|altpll:altpll_component|_clk0'
+Slack : 0.730 ns
+Required Time : 27.19 MHz ( period = 36.777 ns )
+Actual Time : N/A
+From : vga:inst|vga_driver:vga_driver_unit|hsync_state_0
+To : vga:inst|vga_driver:vga_driver_unit|hsync_state_5
+From Clock : vpll:inst1|altpll:altpll_component|_clk0
+To Clock : vpll:inst1|altpll:altpll_component|_clk0
+Failed Paths : 0
+
+Type : Total number of failed paths
+Slack :
+Required Time :
+Actual Time :
+From :
+To :
+From Clock :
+To Clock :
+Failed Paths : 0
+
+--------------------------------------------------------------------------------------
+
--- /dev/null
+# Copyright (C) 1991-2006 Altera Corporation\r
+# Your use of Altera Corporation's design tools, logic functions \r
+# and other software and tools, and its AMPP partner logic \r
+# functions, and any output files any of the foregoing \r
+# (including device programming or simulation files), and any \r
+# associated documentation or information are expressly subject \r
+# to the terms and conditions of the Altera Program License \r
+# Subscription Agreement, Altera MegaCore Function License \r
+# Agreement, or other applicable license agreement, including, \r
+# without limitation, that your use is for the sole purpose of \r
+# programming logic devices manufactured by Altera and sold by \r
+# Altera or its authorized distributors. Please refer to the \r
+# applicable agreement for further details.\r
+\r
+# Quartus II: Generate Tcl File for Project\r
+# File: vga_pll.tcl\r
+# Generated on: Fri Sep 29 09:31:24 2006\r
+\r
+# Load Quartus II Tcl Project package\r
+package require ::quartus::project\r
+package require ::quartus::flow\r
+\r
+set need_to_close_project 0\r
+set make_assignments 1\r
+\r
+# Check that the right project is open\r
+if {[is_project_open]} {\r
+ if {[string compare $quartus(project) "vga_pll"]} {\r
+ puts "Project vga_pll is not open"\r
+ set make_assignments 0\r
+ }\r
+} else {\r
+ # Only open if not already open\r
+ if {[project_exists vga_pll]} {\r
+ project_open -cmp vga_pll vga_pll\r
+ } else {\r
+ project_new -cmp vga_pll vga_pll\r
+ }\r
+ set need_to_close_project 1\r
+}\r
+\r
+# Make assignments\r
+if {$make_assignments} {\r
+ catch { set_global_assignment -name FAMILY Stratix } result\r
+ catch { set_global_assignment -name DEVICE EP1S25F672C6 } result\r
+ catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result\r
+ catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result\r
+ catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result\r
+ catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result\r
+ catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result\r
+ catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result\r
+ catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result\r
+ catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result\r
+ catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result\r
+ catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result\r
+ catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result\r
+ catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result\r
+ catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result\r
+ catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result\r
+ catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result\r
+ catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result\r
+\r
+ set_location_assignment PIN_E24 -to b0_pin\r
+ set_location_assignment PIN_T6 -to b1_pin\r
+ set_location_assignment PIN_N3 -to board_clk\r
+ set_location_assignment PIN_E23 -to g0_pin\r
+ set_location_assignment PIN_T5 -to g1_pin\r
+ set_location_assignment PIN_T24 -to g2_pin\r
+ set_location_assignment PIN_F1 -to hsync_pin\r
+ set_location_assignment PIN_E22 -to r0_pin\r
+ set_location_assignment PIN_T4 -to r1_pin\r
+ set_location_assignment PIN_T7 -to r2_pin\r
+ set_location_assignment PIN_A5 -to reset\r
+ set_location_assignment PIN_F2 -to vsync_pin\r
+ set_location_assignment PIN_Y5 -to d_hsync_state[0]\r
+ set_location_assignment PIN_F19 -to d_hsync_state[1]\r
+ set_location_assignment PIN_F17 -to d_hsync_state[2]\r
+ set_location_assignment PIN_Y2 -to d_hsync_state[3]\r
+ set_location_assignment PIN_F10 -to d_hsync_state[4]\r
+ set_location_assignment PIN_F9 -to d_hsync_state[5]\r
+ set_location_assignment PIN_F6 -to d_hsync_state[6]\r
+ set_location_assignment PIN_H4 -to d_hsync_counter[0]\r
+ set_location_assignment PIN_G25 -to d_hsync_counter[7]\r
+ set_location_assignment PIN_G22 -to d_hsync_counter[8]\r
+ set_location_assignment PIN_G18 -to d_hsync_counter[9]\r
+ set_location_assignment PIN_F5 -to d_vsync_state[0]\r
+ set_location_assignment PIN_F4 -to d_vsync_state[1]\r
+ set_location_assignment PIN_F3 -to d_vsync_state[2]\r
+ set_location_assignment PIN_M19 -to d_vsync_state[3]\r
+ set_location_assignment PIN_M18 -to d_vsync_state[4]\r
+ set_location_assignment PIN_M7 -to d_vsync_state[5]\r
+ set_location_assignment PIN_M4 -to d_vsync_state[6]\r
+ set_location_assignment PIN_G9 -to d_vsync_counter[0]\r
+ set_location_assignment PIN_G6 -to d_vsync_counter[7]\r
+ set_location_assignment PIN_G4 -to d_vsync_counter[8]\r
+ set_location_assignment PIN_G2 -to d_vsync_counter[9]\r
+ set_location_assignment PIN_K6 -to d_line_counter[0]\r
+ set_location_assignment PIN_K4 -to d_line_counter[1]\r
+ set_location_assignment PIN_J22 -to d_line_counter[2]\r
+ set_location_assignment PIN_M9 -to d_line_counter[3]\r
+ set_location_assignment PIN_M8 -to d_line_counter[4]\r
+ set_location_assignment PIN_M6 -to d_line_counter[5]\r
+ set_location_assignment PIN_M5 -to d_line_counter[6]\r
+ set_location_assignment PIN_L24 -to d_line_counter[7]\r
+ set_location_assignment PIN_L25 -to d_line_counter[8]\r
+ set_location_assignment PIN_L23 -to d_column_counter[0]\r
+ set_location_assignment PIN_L22 -to d_column_counter[1]\r
+ set_location_assignment PIN_L21 -to d_column_counter[2]\r
+ set_location_assignment PIN_L20 -to d_column_counter[3]\r
+ set_location_assignment PIN_L6 -to d_column_counter[4]\r
+ set_location_assignment PIN_L4 -to d_column_counter[5]\r
+ set_location_assignment PIN_L2 -to d_column_counter[6]\r
+ set_location_assignment PIN_K23 -to d_column_counter[7]\r
+ set_location_assignment PIN_K19 -to d_column_counter[8]\r
+ set_location_assignment PIN_K5 -to d_column_counter[9]\r
+ set_location_assignment PIN_L7 -to d_hsync\r
+ set_location_assignment PIN_L5 -to d_vsync\r
+ set_location_assignment PIN_F26 -to d_set_hsync_counter\r
+ set_location_assignment PIN_F24 -to d_set_vsync_counter\r
+ set_location_assignment PIN_F21 -to d_set_line_counter\r
+ set_location_assignment PIN_Y23 -to d_set_column_counter\r
+ set_location_assignment PIN_L3 -to d_r\r
+ set_location_assignment PIN_K24 -to d_g\r
+ set_location_assignment PIN_K20 -to d_b\r
+ set_location_assignment PIN_H18 -to d_v_enable\r
+ set_location_assignment PIN_J21 -to d_h_enable\r
+ set_location_assignment PIN_R8 -to seven_seg_pin[0]\r
+ set_location_assignment PIN_R9 -to seven_seg_pin[1]\r
+ set_location_assignment PIN_R19 -to seven_seg_pin[2]\r
+ set_location_assignment PIN_R20 -to seven_seg_pin[3]\r
+ set_location_assignment PIN_R21 -to seven_seg_pin[4]\r
+ set_location_assignment PIN_R22 -to seven_seg_pin[5]\r
+ set_location_assignment PIN_R23 -to seven_seg_pin[6]\r
+ set_location_assignment PIN_Y11 -to seven_seg_pin[7]\r
+ set_location_assignment PIN_N7 -to seven_seg_pin[8]\r
+ set_location_assignment PIN_N8 -to seven_seg_pin[9]\r
+ set_location_assignment PIN_R4 -to seven_seg_pin[10]\r
+ set_location_assignment PIN_R6 -to seven_seg_pin[11]\r
+ set_location_assignment PIN_AA11 -to seven_seg_pin[12]\r
+ set_location_assignment PIN_T2 -to seven_seg_pin[13]\r
+ set_location_assignment PIN_K3 -to d_state_clk\r
+ set_location_assignment PIN_H3 -to d_toggle\r
+ set_location_assignment PIN_H26 -to d_toggle_counter[0]\r
+ set_location_assignment PIN_G24 -to d_toggle_counter[15]\r
+ set_location_assignment PIN_G23 -to d_toggle_counter[16]\r
+ set_location_assignment PIN_G21 -to d_toggle_counter[17]\r
+ set_location_assignment PIN_G20 -to d_toggle_counter[18]\r
+ set_location_assignment PIN_G5 -to d_toggle_counter[19]\r
+ set_location_assignment PIN_G3 -to d_toggle_counter[20]\r
+ set_location_assignment PIN_G1 -to d_toggle_counter[21]\r
+ set_location_assignment PIN_F25 -to d_toggle_counter[22]\r
+ set_location_assignment PIN_F23 -to d_toggle_counter[23]\r
+ set_location_assignment PIN_T19 -to d_toggle_counter[24]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin\r
+\r
+\r
+ # Commit assignments\r
+ export_assignments\r
+\r
+execute_flow -compile\r
+\r
+ # Close project\r
+ if {$need_to_close_project} {\r
+ project_close\r
+ }\r
+}\r
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Full Version
+# Date created = 14:54:36 October 28, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+# automatically by the Quartus II software and is used
+# to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family ACEX1K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KA
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KC
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX6000
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "APEX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS Off
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL93
+set_global_assignment -name FAMILY -value Stratix
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name PARALLEL_SYNTHESIS Off
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
+set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS Off
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value OFF
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family ACEX1K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KA
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KC
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX6000
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "APEX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY -value ON
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION -value ON
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name INCREMENTAL_COMPILATION -value OFF
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name OPTIMIZE_SSN Off -entity ? -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_SSN Off -entity ? -family "Stratix III"
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:19:28 2009 " "Info: Processing started: Wed Oct 28 14:19:28 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off vga -c vga " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off vga -c vga" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "269 " "Info: Peak virtual memory: 269 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:19:47 2009 " "Info: Processing ended: Wed Oct 28 14:19:47 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Info: Total CPU time (on all processors): 00:00:18" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="vga">
+ </PROJECT>
+</LOG_ROOT>
--- /dev/null
+<kpt_db name="vga.cmp" kpt_version="1.1">
+ <key_points_set type="reference" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transition" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transformed" hier_sep="|">
+ </key_points_set>
+ <transformations_set hier_sep="|">
+ </transformations_set>
+</kpt_db>
--- /dev/null
+<kpt_db name="vga.cmp_merge" kpt_version="1.1">
+ <key_points_set type="reference" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transition" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transformed" hier_sep="|">
+ </key_points_set>
+ <transformations_set hier_sep="|">
+ </transformations_set>
+</kpt_db>
--- /dev/null
+Quartus_Version = Version 9.0 Build 132 02/25/2009 SJ Full Version
+Version_Index = 167805952
+Creation_Time = Wed Oct 28 14:18:28 2009
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:19:54 2009 " "Info: Processing started: Wed Oct 28 14:19:54 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off vga -c vga " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vga -c vga" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "vga.vho vga_vhd.sdo /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/ simulation " "Info: Generated files \"vga.vho\" and \"vga_vhd.sdo\" in directory \"/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/\" for EDA simulation tool" { } { } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Peak virtual memory: 163 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:19:55 2009 " "Info: Processing ended: Wed Oct 28 14:19:55 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:18:53 2009 " "Info: Processing started: Wed Oct 28 14:18:53 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "vga EP1S25F672C6 " "Info: Selected device EP1S25F672C6 for design \"vga\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F672C6 " "Info: Device EP1S10F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F672C6 " "Info: Device EP1S20F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE " "Info: Device EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ F16 " "Info: Pin ~DATA0~ is reserved at location F16" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { ~DATA0~ } } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "117 117 " "Warning: No exact pin location assignment(s) for 117 pins of 117 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r0_pin " "Info: Pin r0_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { r0_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6080 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { r0_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r1_pin " "Info: Pin r1_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { r1_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6067 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { r1_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_pin " "Info: Pin r2_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { r2_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6054 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { r2_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "g0_pin " "Info: Pin g0_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { g0_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6041 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { g0_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "g1_pin " "Info: Pin g1_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { g1_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6028 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { g1_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "g2_pin " "Info: Pin g2_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { g2_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6015 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { g2_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b0_pin " "Info: Pin b0_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { b0_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6002 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { b0_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b1_pin " "Info: Pin b1_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { b1_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5989 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { b1_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hsync_pin " "Info: Pin hsync_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { hsync_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5976 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { hsync_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vsync_pin " "Info: Pin vsync_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { vsync_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5963 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vsync_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[0\] " "Info: Pin seven_seg_pin\[0\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[0] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5950 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[1\] " "Info: Pin seven_seg_pin\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[1] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5937 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[2\] " "Info: Pin seven_seg_pin\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[2] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5924 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[3\] " "Info: Pin seven_seg_pin\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5911 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[4\] " "Info: Pin seven_seg_pin\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5898 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[5\] " "Info: Pin seven_seg_pin\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5885 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[6\] " "Info: Pin seven_seg_pin\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5872 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[7\] " "Info: Pin seven_seg_pin\[7\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[7] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5859 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[8\] " "Info: Pin seven_seg_pin\[8\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[8] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5846 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[9\] " "Info: Pin seven_seg_pin\[9\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[9] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5833 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[10\] " "Info: Pin seven_seg_pin\[10\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[10] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5820 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[11\] " "Info: Pin seven_seg_pin\[11\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[11] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5807 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[12\] " "Info: Pin seven_seg_pin\[12\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[12] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5794 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "seven_seg_pin\[13\] " "Info: Pin seven_seg_pin\[13\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[13] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5781 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync " "Info: Pin d_hsync not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5768 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync " "Info: Pin d_vsync not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5755 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[0\] " "Info: Pin d_column_counter\[0\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[0] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5742 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[1\] " "Info: Pin d_column_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[1] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5729 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[2\] " "Info: Pin d_column_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[2] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5716 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[3\] " "Info: Pin d_column_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5703 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[4\] " "Info: Pin d_column_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5690 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[5\] " "Info: Pin d_column_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5677 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[6\] " "Info: Pin d_column_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5664 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[7\] " "Info: Pin d_column_counter\[7\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[7] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5651 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[8\] " "Info: Pin d_column_counter\[8\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[8] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5638 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_column_counter\[9\] " "Info: Pin d_column_counter\[9\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_column_counter[9] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5625 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_column_counter[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_line_counter\[0\] " "Info: Pin d_line_counter\[0\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_line_counter[0] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5612 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_line_counter[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_line_counter\[1\] " "Info: Pin d_line_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_line_counter[1] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5599 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_line_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_line_counter\[2\] " "Info: Pin d_line_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_line_counter[2] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5586 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_line_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_line_counter\[3\] " "Info: Pin d_line_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_line_counter[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5573 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_line_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_line_counter\[4\] " "Info: Pin d_line_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_line_counter[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5560 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_line_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_line_counter\[5\] " "Info: Pin d_line_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_line_counter[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5547 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_line_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_line_counter\[6\] " "Info: Pin d_line_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_line_counter[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5534 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_line_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_line_counter\[7\] " "Info: Pin d_line_counter\[7\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_line_counter[7] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5521 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_line_counter[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_line_counter\[8\] " "Info: Pin d_line_counter\[8\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_line_counter[8] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5508 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_line_counter[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_set_column_counter " "Info: Pin d_set_column_counter not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_set_column_counter } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5495 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_set_column_counter } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_set_line_counter " "Info: Pin d_set_line_counter not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_set_line_counter } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5482 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_set_line_counter } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[0\] " "Info: Pin d_hsync_counter\[0\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[0] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5469 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[1\] " "Info: Pin d_hsync_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[1] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5456 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[2\] " "Info: Pin d_hsync_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[2] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5443 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[3\] " "Info: Pin d_hsync_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5430 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[4\] " "Info: Pin d_hsync_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5417 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[5\] " "Info: Pin d_hsync_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5404 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[6\] " "Info: Pin d_hsync_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5391 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[7\] " "Info: Pin d_hsync_counter\[7\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[7] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5378 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[8\] " "Info: Pin d_hsync_counter\[8\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[8] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5365 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[9\] " "Info: Pin d_hsync_counter\[9\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[9] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5352 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[0\] " "Info: Pin d_vsync_counter\[0\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[0] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5339 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[1\] " "Info: Pin d_vsync_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[1] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5326 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[2\] " "Info: Pin d_vsync_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[2] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5313 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[3\] " "Info: Pin d_vsync_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5300 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[4\] " "Info: Pin d_vsync_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5287 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[5\] " "Info: Pin d_vsync_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5274 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[6\] " "Info: Pin d_vsync_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5261 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[7\] " "Info: Pin d_vsync_counter\[7\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[7] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5248 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[8\] " "Info: Pin d_vsync_counter\[8\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[8] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5235 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[9\] " "Info: Pin d_vsync_counter\[9\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[9] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5222 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_set_hsync_counter " "Info: Pin d_set_hsync_counter not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_set_hsync_counter } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5209 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_set_hsync_counter } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_set_vsync_counter " "Info: Pin d_set_vsync_counter not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_set_vsync_counter } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5196 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_set_vsync_counter } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_h_enable " "Info: Pin d_h_enable not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_h_enable } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5183 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_h_enable } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_v_enable " "Info: Pin d_v_enable not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_v_enable } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5170 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_v_enable } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_r " "Info: Pin d_r not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_r } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5157 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_r } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_g " "Info: Pin d_g not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_g } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5144 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_g } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_b " "Info: Pin d_b not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_b } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5131 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_b } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_state\[6\] " "Info: Pin d_hsync_state\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_state[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5118 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_state[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_state\[5\] " "Info: Pin d_hsync_state\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_state[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5105 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_state[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_state\[4\] " "Info: Pin d_hsync_state\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_state[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5092 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_state[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_state\[3\] " "Info: Pin d_hsync_state\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_state[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5079 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_state[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_state\[2\] " "Info: Pin d_hsync_state\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_state[2] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5066 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_state[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_state\[1\] " "Info: Pin d_hsync_state\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_state[1] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5053 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_state[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_state\[0\] " "Info: Pin d_hsync_state\[0\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_state[0] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5040 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_state[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_state\[6\] " "Info: Pin d_vsync_state\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_state[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5027 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_state[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_state\[5\] " "Info: Pin d_vsync_state\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_state[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5014 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_state[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_state\[4\] " "Info: Pin d_vsync_state\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_state[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5001 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_state[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_state\[3\] " "Info: Pin d_vsync_state\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_state[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4988 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_state[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_state\[2\] " "Info: Pin d_vsync_state\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_state[2] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4975 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_state[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_state\[1\] " "Info: Pin d_vsync_state\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_state[1] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4962 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_state[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_state\[0\] " "Info: Pin d_vsync_state\[0\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_state[0] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4949 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_state[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_state_clk " "Info: Pin d_state_clk not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_state_clk } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4936 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_state_clk } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle " "Info: Pin d_toggle not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4923 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[0\] " "Info: Pin d_toggle_counter\[0\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[0] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4910 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[1\] " "Info: Pin d_toggle_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[1] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4897 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[2\] " "Info: Pin d_toggle_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[2] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4884 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[3\] " "Info: Pin d_toggle_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4871 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[4\] " "Info: Pin d_toggle_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4858 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[5\] " "Info: Pin d_toggle_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4845 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[6\] " "Info: Pin d_toggle_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4832 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[7\] " "Info: Pin d_toggle_counter\[7\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[7] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4819 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[8\] " "Info: Pin d_toggle_counter\[8\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[8] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4806 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[9\] " "Info: Pin d_toggle_counter\[9\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[9] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4793 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[10\] " "Info: Pin d_toggle_counter\[10\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[10] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4780 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[11\] " "Info: Pin d_toggle_counter\[11\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[11] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4767 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[12\] " "Info: Pin d_toggle_counter\[12\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[12] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4754 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[13\] " "Info: Pin d_toggle_counter\[13\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[13] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4741 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[14\] " "Info: Pin d_toggle_counter\[14\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[14] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4728 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[15\] " "Info: Pin d_toggle_counter\[15\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[15] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4715 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[16\] " "Info: Pin d_toggle_counter\[16\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[16] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4702 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[17\] " "Info: Pin d_toggle_counter\[17\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[17] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4689 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[18\] " "Info: Pin d_toggle_counter\[18\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[18] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4676 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[19\] " "Info: Pin d_toggle_counter\[19\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[19] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4663 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[20\] " "Info: Pin d_toggle_counter\[20\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[20] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4650 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[21\] " "Info: Pin d_toggle_counter\[21\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[21] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4637 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[22\] " "Info: Pin d_toggle_counter\[22\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[22] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4624 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[23\] " "Info: Pin d_toggle_counter\[23\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[23] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4611 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_toggle_counter\[24\] " "Info: Pin d_toggle_counter\[24\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[24] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4598 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_pin " "Info: Pin clk_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { clk_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4585 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "reset_pin " "Info: Pin reset_pin not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { reset_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4571 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk_pin Global clock in PIN R3 " "Info: Automatically promoted some destinations of signal \"clk_pin\" to use Global clock in PIN R3" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "d_state_clk_out " "Info: Destination \"d_state_clk_out\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4462 21 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "vga_driver:vga_driver_unit\|un6_dly_counter_0_x Global clock " "Info: Automatically promoted some destinations of signal \"vga_driver:vga_driver_unit\|un6_dly_counter_0_x\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "seven_seg_pin_out_12_ " "Info: Destination \"seven_seg_pin_out_12_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "seven_seg_pin_out_11_ " "Info: Destination \"seven_seg_pin_out_11_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "seven_seg_pin_out_10_ " "Info: Destination \"seven_seg_pin_out_10_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "seven_seg_pin_out_9_ " "Info: Destination \"seven_seg_pin_out_9_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "seven_seg_pin_out_8_ " "Info: Destination \"seven_seg_pin_out_8_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "seven_seg_pin_out_7_ " "Info: Destination \"seven_seg_pin_out_7_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "seven_seg_pin_out_2_ " "Info: Destination \"seven_seg_pin_out_2_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "seven_seg_pin_out_1_ " "Info: Destination \"seven_seg_pin_out_1_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga_driver:vga_driver_unit\|hsync_state_1_ " "Info: Destination \"vga_driver:vga_driver_unit\|hsync_state_1_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 114 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga_driver:vga_driver_unit\|vsync_state_1_ " "Info: Destination \"vga_driver:vga_driver_unit\|vsync_state_1_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 108 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" { } { } 0 0 "Limited to %1!d! non-global destinations" 0 0 "" 0 -1} } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Start inferring scan chains for DSP blocks" { } { } 1 0 "Start inferring scan chains for DSP blocks" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Inferring scan chains for DSP blocks is complete" { } { } 1 0 "Inferring scan chains for DSP blocks is complete" 1 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "116 unused 3.3V 1 115 0 " "Info: Number of I/O pins in group: 116 (unused VREF, 3.3V VCCIO, 1 input, 115 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 60 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 60 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 59 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 59 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 54 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 54 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 1 55 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 55 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 59 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 59 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 61 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 61 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 57 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 57 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 54 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 54 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use undetermined 0 6 " "Info: I/O bank number 11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Info: Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register vga_control:vga_control_unit\|toggle_counter_sig_5 register vga_control:vga_control_unit\|toggle_counter_sig_10 -4.354 ns " "Info: Slack time is -4.354 ns between source register \"vga_control:vga_control_unit\|toggle_counter_sig_5\" and destination register \"vga_control:vga_control_unit\|toggle_counter_sig_10\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.814 ns + Largest register register " "Info: + Largest register to register requirement is 0.814 ns" { } { } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.707 ns Shortest register " "Info: Shortest clock path from clock \"clk_pin\" to destination register is 3.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns clk_pin 1 CLK Unassigned 84 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.006 ns) + CELL(0.560 ns) 3.707 ns vga_control:vga_control_unit\|toggle_counter_sig_10 2 REG Unassigned 8 " "Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 8; REG Node = 'vga_control:vga_control_unit\|toggle_counter_sig_10'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.566 ns" { clk_pin vga_control:vga_control_unit|toggle_counter_sig_10 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3207 31 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.701 ns ( 45.89 % ) " "Info: Total cell delay = 1.701 ns ( 45.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.006 ns ( 54.11 % ) " "Info: Total interconnect delay = 2.006 ns ( 54.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.707 ns Longest register " "Info: Longest clock path from clock \"clk_pin\" to destination register is 3.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns clk_pin 1 CLK Unassigned 84 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.006 ns) + CELL(0.560 ns) 3.707 ns vga_control:vga_control_unit\|toggle_counter_sig_10 2 REG Unassigned 8 " "Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 8; REG Node = 'vga_control:vga_control_unit\|toggle_counter_sig_10'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.566 ns" { clk_pin vga_control:vga_control_unit|toggle_counter_sig_10 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3207 31 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.701 ns ( 45.89 % ) " "Info: Total cell delay = 1.701 ns ( 45.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.006 ns ( 54.11 % ) " "Info: Total interconnect delay = 2.006 ns ( 54.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.707 ns Shortest register " "Info: Shortest clock path from clock \"clk_pin\" to source register is 3.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns clk_pin 1 CLK Unassigned 84 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.006 ns) + CELL(0.560 ns) 3.707 ns vga_control:vga_control_unit\|toggle_counter_sig_5 2 REG Unassigned 7 " "Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 7; REG Node = 'vga_control:vga_control_unit\|toggle_counter_sig_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.566 ns" { clk_pin vga_control:vga_control_unit|toggle_counter_sig_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3202 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.701 ns ( 45.89 % ) " "Info: Total cell delay = 1.701 ns ( 45.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.006 ns ( 54.11 % ) " "Info: Total interconnect delay = 2.006 ns ( 54.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.707 ns Longest register " "Info: Longest clock path from clock \"clk_pin\" to source register is 3.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns clk_pin 1 CLK Unassigned 84 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.006 ns) + CELL(0.560 ns) 3.707 ns vga_control:vga_control_unit\|toggle_counter_sig_5 2 REG Unassigned 7 " "Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 7; REG Node = 'vga_control:vga_control_unit\|toggle_counter_sig_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.566 ns" { clk_pin vga_control:vga_control_unit|toggle_counter_sig_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3202 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.701 ns ( 45.89 % ) " "Info: Total cell delay = 1.701 ns ( 45.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.006 ns ( 54.11 % ) " "Info: Total interconnect delay = 2.006 ns ( 54.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns " "Info: Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3202 30 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns " "Info: Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3207 31 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.168 ns - Longest register register " "Info: - Longest register to register delay is 5.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_control:vga_control_unit\|toggle_counter_sig_5 1 REG Unassigned 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 7; REG Node = 'vga_control:vga_control_unit\|toggle_counter_sig_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_control:vga_control_unit|toggle_counter_sig_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3202 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.332 ns) 0.765 ns vga_control:vga_control_unit\|un1_toggle_counter_siglt6 2 COMB Unassigned 1 " "Info: 2: + IC(0.433 ns) + CELL(0.332 ns) = 0.765 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglt6'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.765 ns" { vga_control:vga_control_unit|toggle_counter_sig_5 vga_control:vga_control_unit|un1_toggle_counter_siglt6 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3303 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 1.279 ns vga_control:vga_control_unit\|un1_toggle_counter_siglto9 3 COMB Unassigned 1 " "Info: 3: + IC(0.427 ns) + CELL(0.087 ns) = 1.279 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglto9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglt6 vga_control:vga_control_unit|un1_toggle_counter_siglto9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3300 34 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 1.793 ns vga_control:vga_control_unit\|un1_toggle_counter_siglto12 4 COMB Unassigned 1 " "Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 1.793 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglto12'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglto9 vga_control:vga_control_unit|un1_toggle_counter_siglto12 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3298 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 2.307 ns vga_control:vga_control_unit\|un1_toggle_counter_siglto15 5 COMB Unassigned 1 " "Info: 5: + IC(0.427 ns) + CELL(0.087 ns) = 2.307 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglto15'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglto12 vga_control:vga_control_unit|un1_toggle_counter_siglto15 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3290 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 2.821 ns vga_control:vga_control_unit\|un1_toggle_counter_siglto18 6 COMB Unassigned 1 " "Info: 6: + IC(0.427 ns) + CELL(0.087 ns) = 2.821 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglto18'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglto15 vga_control:vga_control_unit|un1_toggle_counter_siglto18 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3289 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 3.335 ns vga_control:vga_control_unit\|toggle_sig_0_0_0_g1 7 COMB Unassigned 22 " "Info: 7: + IC(0.427 ns) + CELL(0.087 ns) = 3.335 ns; Loc. = Unassigned; Fanout = 22; COMB Node = 'vga_control:vga_control_unit\|toggle_sig_0_0_0_g1'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglto18 vga_control:vga_control_unit|toggle_sig_0_0_0_g1 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3285 27 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.782 ns) 5.168 ns vga_control:vga_control_unit\|toggle_counter_sig_10 8 REG Unassigned 8 " "Info: 8: + IC(1.051 ns) + CELL(0.782 ns) = 5.168 ns; Loc. = Unassigned; Fanout = 8; REG Node = 'vga_control:vga_control_unit\|toggle_counter_sig_10'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.833 ns" { vga_control:vga_control_unit|toggle_sig_0_0_0_g1 vga_control:vga_control_unit|toggle_counter_sig_10 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3207 31 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.549 ns ( 29.97 % ) " "Info: Total cell delay = 1.549 ns ( 29.97 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.619 ns ( 70.03 % ) " "Info: Total interconnect delay = 3.619 ns ( 70.03 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.168 ns" { vga_control:vga_control_unit|toggle_counter_sig_5 vga_control:vga_control_unit|un1_toggle_counter_siglt6 vga_control:vga_control_unit|un1_toggle_counter_siglto9 vga_control:vga_control_unit|un1_toggle_counter_siglto12 vga_control:vga_control_unit|un1_toggle_counter_siglto15 vga_control:vga_control_unit|un1_toggle_counter_siglto18 vga_control:vga_control_unit|toggle_sig_0_0_0_g1 vga_control:vga_control_unit|toggle_counter_sig_10 } "NODE_NAME" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.168 ns" { vga_control:vga_control_unit|toggle_counter_sig_5 vga_control:vga_control_unit|un1_toggle_counter_siglt6 vga_control:vga_control_unit|un1_toggle_counter_siglto9 vga_control:vga_control_unit|un1_toggle_counter_siglto12 vga_control:vga_control_unit|un1_toggle_counter_siglto15 vga_control:vga_control_unit|un1_toggle_counter_siglto18 vga_control:vga_control_unit|toggle_sig_0_0_0_g1 vga_control:vga_control_unit|toggle_counter_sig_10 } "NODE_NAME" } } } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.168 ns register register " "Info: Estimated most critical path is register to register delay of 5.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_control:vga_control_unit\|toggle_counter_sig_5 1 REG LAB_X33_Y35 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X33_Y35; Fanout = 7; REG Node = 'vga_control:vga_control_unit\|toggle_counter_sig_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_control:vga_control_unit|toggle_counter_sig_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3202 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.332 ns) 0.765 ns vga_control:vga_control_unit\|un1_toggle_counter_siglt6 2 COMB LAB_X32_Y35 1 " "Info: 2: + IC(0.433 ns) + CELL(0.332 ns) = 0.765 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglt6'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.765 ns" { vga_control:vga_control_unit|toggle_counter_sig_5 vga_control:vga_control_unit|un1_toggle_counter_siglt6 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3303 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 1.279 ns vga_control:vga_control_unit\|un1_toggle_counter_siglto9 3 COMB LAB_X32_Y35 1 " "Info: 3: + IC(0.427 ns) + CELL(0.087 ns) = 1.279 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglto9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglt6 vga_control:vga_control_unit|un1_toggle_counter_siglto9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3300 34 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 1.793 ns vga_control:vga_control_unit\|un1_toggle_counter_siglto12 4 COMB LAB_X32_Y35 1 " "Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 1.793 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglto12'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglto9 vga_control:vga_control_unit|un1_toggle_counter_siglto12 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3298 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 2.307 ns vga_control:vga_control_unit\|un1_toggle_counter_siglto15 5 COMB LAB_X32_Y35 1 " "Info: 5: + IC(0.427 ns) + CELL(0.087 ns) = 2.307 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglto15'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglto12 vga_control:vga_control_unit|un1_toggle_counter_siglto15 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3290 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 2.821 ns vga_control:vga_control_unit\|un1_toggle_counter_siglto18 6 COMB LAB_X32_Y35 1 " "Info: 6: + IC(0.427 ns) + CELL(0.087 ns) = 2.821 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit\|un1_toggle_counter_siglto18'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglto15 vga_control:vga_control_unit|un1_toggle_counter_siglto18 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3289 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 3.335 ns vga_control:vga_control_unit\|toggle_sig_0_0_0_g1 7 COMB LAB_X32_Y35 22 " "Info: 7: + IC(0.427 ns) + CELL(0.087 ns) = 3.335 ns; Loc. = LAB_X32_Y35; Fanout = 22; COMB Node = 'vga_control:vga_control_unit\|toggle_sig_0_0_0_g1'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.514 ns" { vga_control:vga_control_unit|un1_toggle_counter_siglto18 vga_control:vga_control_unit|toggle_sig_0_0_0_g1 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3285 27 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.782 ns) 5.168 ns vga_control:vga_control_unit\|toggle_counter_sig_10 8 REG LAB_X31_Y34 8 " "Info: 8: + IC(1.051 ns) + CELL(0.782 ns) = 5.168 ns; Loc. = LAB_X31_Y34; Fanout = 8; REG Node = 'vga_control:vga_control_unit\|toggle_counter_sig_10'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.833 ns" { vga_control:vga_control_unit|toggle_sig_0_0_0_g1 vga_control:vga_control_unit|toggle_counter_sig_10 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3207 31 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.549 ns ( 29.97 % ) " "Info: Total cell delay = 1.549 ns ( 29.97 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.619 ns ( 70.03 % ) " "Info: Total interconnect delay = 3.619 ns ( 70.03 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.168 ns" { vga_control:vga_control_unit|toggle_counter_sig_5 vga_control:vga_control_unit|un1_toggle_counter_siglt6 vga_control:vga_control_unit|un1_toggle_counter_siglto9 vga_control:vga_control_unit|un1_toggle_counter_siglto12 vga_control:vga_control_unit|un1_toggle_counter_siglto15 vga_control:vga_control_unit|un1_toggle_counter_siglto18 vga_control:vga_control_unit|toggle_sig_0_0_0_g1 vga_control:vga_control_unit|toggle_counter_sig_10 } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X34_Y24 X44_Y35 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X34_Y24 to location X44_Y35" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "14 " "Warning: Following 14 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "g0_pin GND " "Info: Pin g0_pin has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { g0_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6041 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { g0_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "g1_pin GND " "Info: Pin g1_pin has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { g1_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6028 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { g1_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "g2_pin GND " "Info: Pin g2_pin has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { g2_pin } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6015 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { g2_pin } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[0\] GND " "Info: Pin seven_seg_pin\[0\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[0] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5950 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[3\] GND " "Info: Pin seven_seg_pin\[3\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[3] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5911 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[4\] GND " "Info: Pin seven_seg_pin\[4\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[4] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5898 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[5\] GND " "Info: Pin seven_seg_pin\[5\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[5] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5885 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[6\] GND " "Info: Pin seven_seg_pin\[6\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[6] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5872 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[13\] GND " "Info: Pin seven_seg_pin\[13\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[13] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5781 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_g GND " "Info: Pin d_g has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_g } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 5144 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_g } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_toggle_counter\[21\] GND " "Info: Pin d_toggle_counter\[21\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[21] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4637 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_toggle_counter\[22\] GND " "Info: Pin d_toggle_counter\[22\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[22] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4624 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_toggle_counter\[23\] GND " "Info: Pin d_toggle_counter\[23\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[23] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4611 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_toggle_counter\[24\] GND " "Info: Pin d_toggle_counter\[24\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_toggle_counter[24] } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4598 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_toggle_counter[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/vga.fit.smsg " "Info: Generated suppressed messages file /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/vga.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "320 " "Info: Peak virtual memory: 320 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:19:25 2009 " "Info: Processing ended: Wed Oct 28 14:19:25 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Info: Elapsed time: 00:00:32" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:30 " "Info: Total CPU time (on all processors): 00:00:30" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+|vga
+clk_pin => clk_pin_in.PADIO
+reset_pin => reset_pin_in.PADIO
+r0_pin <= r0_pin_out.PADIO
+r1_pin <= r1_pin_out.PADIO
+r2_pin <= r2_pin_out.PADIO
+g0_pin <= g0_pin_out.PADIO
+g1_pin <= g1_pin_out.PADIO
+g2_pin <= g2_pin_out.PADIO
+b0_pin <= b0_pin_out.PADIO
+b1_pin <= b1_pin_out.PADIO
+hsync_pin <= hsync_pin_out.PADIO
+vsync_pin <= vsync_pin_out.PADIO
+seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO
+seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO
+seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO
+seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO
+seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO
+seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO
+seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO
+seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO
+seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO
+seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO
+seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO
+seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO
+seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO
+seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO
+d_hsync <= d_hsync_out.PADIO
+d_vsync <= d_vsync_out.PADIO
+d_column_counter[0] <= d_column_counter_out_0_.PADIO
+d_column_counter[1] <= d_column_counter_out_1_.PADIO
+d_column_counter[2] <= d_column_counter_out_2_.PADIO
+d_column_counter[3] <= d_column_counter_out_3_.PADIO
+d_column_counter[4] <= d_column_counter_out_4_.PADIO
+d_column_counter[5] <= d_column_counter_out_5_.PADIO
+d_column_counter[6] <= d_column_counter_out_6_.PADIO
+d_column_counter[7] <= d_column_counter_out_7_.PADIO
+d_column_counter[8] <= d_column_counter_out_8_.PADIO
+d_column_counter[9] <= d_column_counter_out_9_.PADIO
+d_line_counter[0] <= d_line_counter_out_0_.PADIO
+d_line_counter[1] <= d_line_counter_out_1_.PADIO
+d_line_counter[2] <= d_line_counter_out_2_.PADIO
+d_line_counter[3] <= d_line_counter_out_3_.PADIO
+d_line_counter[4] <= d_line_counter_out_4_.PADIO
+d_line_counter[5] <= d_line_counter_out_5_.PADIO
+d_line_counter[6] <= d_line_counter_out_6_.PADIO
+d_line_counter[7] <= d_line_counter_out_7_.PADIO
+d_line_counter[8] <= d_line_counter_out_8_.PADIO
+d_set_column_counter <= d_set_column_counter_out.PADIO
+d_set_line_counter <= d_set_line_counter_out.PADIO
+d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO
+d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO
+d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO
+d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO
+d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO
+d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO
+d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO
+d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO
+d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO
+d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO
+d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO
+d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO
+d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO
+d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO
+d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO
+d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO
+d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO
+d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO
+d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO
+d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO
+d_set_hsync_counter <= d_set_hsync_counter_out.PADIO
+d_set_vsync_counter <= d_set_vsync_counter_out.PADIO
+d_h_enable <= d_h_enable_out.PADIO
+d_v_enable <= d_v_enable_out.PADIO
+d_r <= d_r_out.PADIO
+d_g <= d_g_out.PADIO
+d_b <= d_b_out.PADIO
+d_hsync_state[6] <= d_hsync_state_out_6_.PADIO
+d_hsync_state[5] <= d_hsync_state_out_5_.PADIO
+d_hsync_state[4] <= d_hsync_state_out_4_.PADIO
+d_hsync_state[3] <= d_hsync_state_out_3_.PADIO
+d_hsync_state[2] <= d_hsync_state_out_2_.PADIO
+d_hsync_state[1] <= d_hsync_state_out_1_.PADIO
+d_hsync_state[0] <= d_hsync_state_out_0_.PADIO
+d_vsync_state[6] <= d_vsync_state_out_6_.PADIO
+d_vsync_state[5] <= d_vsync_state_out_5_.PADIO
+d_vsync_state[4] <= d_vsync_state_out_4_.PADIO
+d_vsync_state[3] <= d_vsync_state_out_3_.PADIO
+d_vsync_state[2] <= d_vsync_state_out_2_.PADIO
+d_vsync_state[1] <= d_vsync_state_out_1_.PADIO
+d_vsync_state[0] <= d_vsync_state_out_0_.PADIO
+d_state_clk <= d_state_clk_out.PADIO
+d_toggle <= d_toggle_out.PADIO
+d_toggle_counter[0] <= d_toggle_counter_out_0_.PADIO
+d_toggle_counter[1] <= d_toggle_counter_out_1_.PADIO
+d_toggle_counter[2] <= d_toggle_counter_out_2_.PADIO
+d_toggle_counter[3] <= d_toggle_counter_out_3_.PADIO
+d_toggle_counter[4] <= d_toggle_counter_out_4_.PADIO
+d_toggle_counter[5] <= d_toggle_counter_out_5_.PADIO
+d_toggle_counter[6] <= d_toggle_counter_out_6_.PADIO
+d_toggle_counter[7] <= d_toggle_counter_out_7_.PADIO
+d_toggle_counter[8] <= d_toggle_counter_out_8_.PADIO
+d_toggle_counter[9] <= d_toggle_counter_out_9_.PADIO
+d_toggle_counter[10] <= d_toggle_counter_out_10_.PADIO
+d_toggle_counter[11] <= d_toggle_counter_out_11_.PADIO
+d_toggle_counter[12] <= d_toggle_counter_out_12_.PADIO
+d_toggle_counter[13] <= d_toggle_counter_out_13_.PADIO
+d_toggle_counter[14] <= d_toggle_counter_out_14_.PADIO
+d_toggle_counter[15] <= d_toggle_counter_out_15_.PADIO
+d_toggle_counter[16] <= d_toggle_counter_out_16_.PADIO
+d_toggle_counter[17] <= d_toggle_counter_out_17_.PADIO
+d_toggle_counter[18] <= d_toggle_counter_out_18_.PADIO
+d_toggle_counter[19] <= d_toggle_counter_out_19_.PADIO
+d_toggle_counter[20] <= d_toggle_counter_out_20_.PADIO
+d_toggle_counter[21] <= d_toggle_counter_out_21_.PADIO
+d_toggle_counter[22] <= d_toggle_counter_out_22_.PADIO
+d_toggle_counter[23] <= d_toggle_counter_out_23_.PADIO
+d_toggle_counter[24] <= d_toggle_counter_out_24_.PADIO
+
+
+|vga|vga_driver:vga_driver_unit
+line_counter_sig_0 <= line_counter_sig_0_.REGOUT
+line_counter_sig_1 <= line_counter_sig_1_.REGOUT
+line_counter_sig_2 <= line_counter_sig_2_.REGOUT
+line_counter_sig_3 <= line_counter_sig_3_.REGOUT
+line_counter_sig_4 <= line_counter_sig_4_.REGOUT
+line_counter_sig_5 <= line_counter_sig_5_.REGOUT
+line_counter_sig_6 <= line_counter_sig_6_.REGOUT
+line_counter_sig_7 <= line_counter_sig_7_.REGOUT
+line_counter_sig_8 <= line_counter_sig_8_.REGOUT
+dly_counter_1 => vsync_state_6_.DATAC
+dly_counter_1 => h_sync_Z.DATAC
+dly_counter_1 => v_sync_Z.DATAC
+dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC
+dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC
+dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC
+dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC
+dly_counter_0 => vsync_state_6_.DATAB
+dly_counter_0 => h_sync_Z.DATAB
+dly_counter_0 => v_sync_Z.DATAB
+dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB
+dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB
+dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB
+dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB
+vsync_state_2 <= vsync_state_2_.REGOUT
+vsync_state_5 <= vsync_state_5_.REGOUT
+vsync_state_3 <= vsync_state_3_.REGOUT
+vsync_state_6 <= vsync_state_6_.REGOUT
+vsync_state_4 <= vsync_state_4_.REGOUT
+vsync_state_1 <= vsync_state_1_.REGOUT
+vsync_state_0 <= vsync_state_0_.REGOUT
+hsync_state_2 <= hsync_state_2_.REGOUT
+hsync_state_4 <= hsync_state_4_.REGOUT
+hsync_state_0 <= hsync_state_0_.REGOUT
+hsync_state_5 <= hsync_state_5_.REGOUT
+hsync_state_1 <= hsync_state_1_.REGOUT
+hsync_state_3 <= hsync_state_3_.REGOUT
+hsync_state_6 <= hsync_state_6_.REGOUT
+column_counter_sig_0 <= column_counter_sig_0_.REGOUT
+column_counter_sig_1 <= column_counter_sig_1_.REGOUT
+column_counter_sig_2 <= column_counter_sig_2_.REGOUT
+column_counter_sig_3 <= column_counter_sig_3_.REGOUT
+column_counter_sig_4 <= column_counter_sig_4_.REGOUT
+column_counter_sig_5 <= column_counter_sig_5_.REGOUT
+column_counter_sig_6 <= column_counter_sig_6_.REGOUT
+column_counter_sig_7 <= column_counter_sig_7_.REGOUT
+column_counter_sig_8 <= column_counter_sig_8_.REGOUT
+column_counter_sig_9 <= column_counter_sig_9_.REGOUT
+vsync_counter_9 <= vsync_counter_9_.REGOUT
+vsync_counter_8 <= vsync_counter_8_.REGOUT
+vsync_counter_7 <= vsync_counter_7_.REGOUT
+vsync_counter_6 <= vsync_counter_6_.REGOUT
+vsync_counter_5 <= vsync_counter_5_.REGOUT
+vsync_counter_4 <= vsync_counter_4_.REGOUT
+vsync_counter_3 <= vsync_counter_3_.REGOUT
+vsync_counter_2 <= vsync_counter_2_.REGOUT
+vsync_counter_1 <= vsync_counter_1_.REGOUT
+vsync_counter_0 <= vsync_counter_0_.REGOUT
+hsync_counter_9 <= hsync_counter_9_.REGOUT
+hsync_counter_8 <= hsync_counter_8_.REGOUT
+hsync_counter_7 <= hsync_counter_7_.REGOUT
+hsync_counter_6 <= hsync_counter_6_.REGOUT
+hsync_counter_5 <= hsync_counter_5_.REGOUT
+hsync_counter_4 <= hsync_counter_4_.REGOUT
+hsync_counter_3 <= hsync_counter_3_.REGOUT
+hsync_counter_2 <= hsync_counter_2_.REGOUT
+hsync_counter_1 <= hsync_counter_1_.REGOUT
+hsync_counter_0 <= hsync_counter_0_.REGOUT
+d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT
+v_sync <= v_sync_Z.REGOUT
+h_sync <= h_sync_Z.REGOUT
+h_enable_sig <= h_enable_sig_Z.REGOUT
+v_enable_sig <= v_enable_sig_Z.REGOUT
+reset_pin_c => vsync_state_6_.DATAA
+reset_pin_c => h_sync_Z.DATAA
+reset_pin_c => v_sync_Z.DATAA
+reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA
+reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA
+reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA
+reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA
+un6_dly_counter_0_x <= vsync_state_6_.COMBOUT
+d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT
+clk_pin_c => hsync_counter_0_.CLK
+clk_pin_c => hsync_counter_1_.CLK
+clk_pin_c => hsync_counter_2_.CLK
+clk_pin_c => hsync_counter_3_.CLK
+clk_pin_c => hsync_counter_4_.CLK
+clk_pin_c => hsync_counter_5_.CLK
+clk_pin_c => hsync_counter_6_.CLK
+clk_pin_c => hsync_counter_7_.CLK
+clk_pin_c => hsync_counter_8_.CLK
+clk_pin_c => hsync_counter_9_.CLK
+clk_pin_c => vsync_counter_0_.CLK
+clk_pin_c => vsync_counter_1_.CLK
+clk_pin_c => vsync_counter_2_.CLK
+clk_pin_c => vsync_counter_3_.CLK
+clk_pin_c => vsync_counter_4_.CLK
+clk_pin_c => vsync_counter_5_.CLK
+clk_pin_c => vsync_counter_6_.CLK
+clk_pin_c => vsync_counter_7_.CLK
+clk_pin_c => vsync_counter_8_.CLK
+clk_pin_c => vsync_counter_9_.CLK
+clk_pin_c => column_counter_sig_9_.CLK
+clk_pin_c => column_counter_sig_8_.CLK
+clk_pin_c => column_counter_sig_7_.CLK
+clk_pin_c => column_counter_sig_6_.CLK
+clk_pin_c => column_counter_sig_5_.CLK
+clk_pin_c => column_counter_sig_4_.CLK
+clk_pin_c => column_counter_sig_3_.CLK
+clk_pin_c => column_counter_sig_2_.CLK
+clk_pin_c => column_counter_sig_1_.CLK
+clk_pin_c => column_counter_sig_0_.CLK
+clk_pin_c => hsync_state_6_.CLK
+clk_pin_c => vsync_state_0_.CLK
+clk_pin_c => vsync_state_1_.CLK
+clk_pin_c => vsync_state_6_.CLK
+clk_pin_c => line_counter_sig_8_.CLK
+clk_pin_c => line_counter_sig_7_.CLK
+clk_pin_c => line_counter_sig_6_.CLK
+clk_pin_c => line_counter_sig_5_.CLK
+clk_pin_c => line_counter_sig_4_.CLK
+clk_pin_c => line_counter_sig_3_.CLK
+clk_pin_c => line_counter_sig_2_.CLK
+clk_pin_c => line_counter_sig_1_.CLK
+clk_pin_c => line_counter_sig_0_.CLK
+clk_pin_c => v_enable_sig_Z.CLK
+clk_pin_c => h_enable_sig_Z.CLK
+clk_pin_c => h_sync_Z.CLK
+clk_pin_c => v_sync_Z.CLK
+clk_pin_c => vsync_state_5_.CLK
+clk_pin_c => vsync_state_4_.CLK
+clk_pin_c => vsync_state_3_.CLK
+clk_pin_c => vsync_state_2_.CLK
+clk_pin_c => hsync_state_5_.CLK
+clk_pin_c => hsync_state_4_.CLK
+clk_pin_c => hsync_state_3_.CLK
+clk_pin_c => hsync_state_2_.CLK
+clk_pin_c => hsync_state_1_.CLK
+clk_pin_c => hsync_state_0_.CLK
+
+
+|vga|vga_control:vga_control_unit
+line_counter_sig_0 => DRAW_SQUARE_next_un17_v_enablelto3.DATAC
+line_counter_sig_2 => DRAW_SQUARE_next_un17_v_enablelto3.DATAB
+line_counter_sig_2 => DRAW_SQUARE_next_un13_v_enablelto4_0.DATAB
+line_counter_sig_1 => DRAW_SQUARE_next_un17_v_enablelto3.DATAA
+line_counter_sig_3 => DRAW_SQUARE_next_un13_v_enablelto6.DATAC
+line_counter_sig_3 => DRAW_SQUARE_next_un17_v_enablelto3.DATAD
+line_counter_sig_6 => b_next_0_sqmuxa_7_4_a_cZ.DATAC
+line_counter_sig_6 => DRAW_SQUARE_next_un13_v_enablelto6.DATAB
+line_counter_sig_5 => b_next_0_sqmuxa_7_4_a_cZ.DATAB
+line_counter_sig_5 => DRAW_SQUARE_next_un13_v_enablelto6.DATAA
+line_counter_sig_4 => b_next_0_sqmuxa_7_4_a_cZ.DATAA
+line_counter_sig_4 => DRAW_SQUARE_next_un13_v_enablelto4_0.DATAA
+line_counter_sig_7 => b_next_0_sqmuxa_7_4_cZ.DATAB
+line_counter_sig_8 => b_next_0_sqmuxa_7_4_cZ.DATAA
+line_counter_sig_8 => b_next_0_sqmuxa_7_2_cZ.DATAD
+column_counter_sig_0 => DRAW_SQUARE_next_un5_v_enablelt2.DATAC
+column_counter_sig_1 => DRAW_SQUARE_next_un5_v_enablelt2.DATAA
+column_counter_sig_2 => DRAW_SQUARE_next_un9_v_enablelto4.DATAC
+column_counter_sig_2 => DRAW_SQUARE_next_un5_v_enablelt2.DATAB
+column_counter_sig_8 => b_next_0_sqmuxa_7_2_cZ.DATAA
+column_counter_sig_3 => DRAW_SQUARE_next_un5_v_enablelto5.DATAC
+column_counter_sig_3 => DRAW_SQUARE_next_un9_v_enablelto4.DATAA
+column_counter_sig_5 => DRAW_SQUARE_next_un5_v_enablelto5.DATAB
+column_counter_sig_5 => DRAW_SQUARE_next_un9_v_enablelto6.DATAA
+column_counter_sig_4 => DRAW_SQUARE_next_un5_v_enablelto5.DATAA
+column_counter_sig_4 => DRAW_SQUARE_next_un9_v_enablelto4.DATAB
+column_counter_sig_9 => b_next_0_sqmuxa_7_3_cZ.DATAB
+column_counter_sig_9 => b_next_0_sqmuxa_7_2_cZ.DATAC
+column_counter_sig_7 => b_next_0_sqmuxa_7_5_cZ.DATAB
+column_counter_sig_7 => b_next_0_sqmuxa_7_3_cZ.DATAA
+column_counter_sig_6 => b_next_0_sqmuxa_7_5_cZ.DATAA
+column_counter_sig_6 => DRAW_SQUARE_next_un9_v_enablelto6.DATAB
+toggle_counter_sig_0 <= toggle_counter_sig_0_.REGOUT
+toggle_counter_sig_1 <= toggle_counter_sig_1_.REGOUT
+toggle_counter_sig_2 <= toggle_counter_sig_2_.REGOUT
+toggle_counter_sig_3 <= toggle_counter_sig_3_.REGOUT
+toggle_counter_sig_4 <= toggle_counter_sig_4_.REGOUT
+toggle_counter_sig_5 <= toggle_counter_sig_5_.REGOUT
+toggle_counter_sig_6 <= toggle_counter_sig_6_.REGOUT
+toggle_counter_sig_7 <= toggle_counter_sig_7_.REGOUT
+toggle_counter_sig_8 <= toggle_counter_sig_8_.REGOUT
+toggle_counter_sig_9 <= toggle_counter_sig_9_.REGOUT
+toggle_counter_sig_10 <= toggle_counter_sig_10_.REGOUT
+toggle_counter_sig_11 <= toggle_counter_sig_11_.REGOUT
+toggle_counter_sig_12 <= toggle_counter_sig_12_.REGOUT
+toggle_counter_sig_13 <= toggle_counter_sig_13_.REGOUT
+toggle_counter_sig_14 <= toggle_counter_sig_14_.REGOUT
+toggle_counter_sig_15 <= toggle_counter_sig_15_.REGOUT
+toggle_counter_sig_16 <= toggle_counter_sig_16_.REGOUT
+toggle_counter_sig_17 <= toggle_counter_sig_17_.REGOUT
+toggle_counter_sig_18 <= toggle_counter_sig_18_.REGOUT
+toggle_counter_sig_19 <= toggle_counter_sig_19_.REGOUT
+toggle_counter_sig_20 <= toggle_counter_sig_20_.REGOUT
+toggle_counter_sig_21 <= toggle_counter_sig_21_.REGOUT
+toggle_counter_sig_22 <= toggle_counter_sig_22_.REGOUT
+toggle_counter_sig_23 <= toggle_counter_sig_23_.REGOUT
+toggle_counter_sig_24 <= toggle_counter_sig_24_.REGOUT
+h_enable_sig => b_next_0_sqmuxa_7_2_cZ.DATAB
+g <= g_Z.REGOUT
+b <= b_Z.REGOUT
+v_enable_sig => r_Z.DATAB
+v_enable_sig => b_Z.DATAB
+r <= r_Z.REGOUT
+toggle_sig <= toggle_sig_Z.REGOUT
+un6_dly_counter_0_x => toggle_counter_sig_24_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_23_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_22_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_21_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_20_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_19_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_18_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_17_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_16_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_15_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_14_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_13_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_12_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_11_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_10_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_9_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_8_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_7_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_6_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_5_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_4_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_3_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_2_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_1_.ACLR
+un6_dly_counter_0_x => toggle_counter_sig_0_.ACLR
+un6_dly_counter_0_x => toggle_sig_Z.ACLR
+un6_dly_counter_0_x => r_Z.ACLR
+un6_dly_counter_0_x => b_Z.ACLR
+un6_dly_counter_0_x => g_Z.ACLR
+clk_pin_c => toggle_counter_sig_24_.CLK
+clk_pin_c => toggle_counter_sig_23_.CLK
+clk_pin_c => toggle_counter_sig_22_.CLK
+clk_pin_c => toggle_counter_sig_21_.CLK
+clk_pin_c => toggle_counter_sig_20_.CLK
+clk_pin_c => toggle_counter_sig_19_.CLK
+clk_pin_c => toggle_counter_sig_18_.CLK
+clk_pin_c => toggle_counter_sig_17_.CLK
+clk_pin_c => toggle_counter_sig_16_.CLK
+clk_pin_c => toggle_counter_sig_15_.CLK
+clk_pin_c => toggle_counter_sig_14_.CLK
+clk_pin_c => toggle_counter_sig_13_.CLK
+clk_pin_c => toggle_counter_sig_12_.CLK
+clk_pin_c => toggle_counter_sig_11_.CLK
+clk_pin_c => toggle_counter_sig_10_.CLK
+clk_pin_c => toggle_counter_sig_9_.CLK
+clk_pin_c => toggle_counter_sig_8_.CLK
+clk_pin_c => toggle_counter_sig_7_.CLK
+clk_pin_c => toggle_counter_sig_6_.CLK
+clk_pin_c => toggle_counter_sig_5_.CLK
+clk_pin_c => toggle_counter_sig_4_.CLK
+clk_pin_c => toggle_counter_sig_3_.CLK
+clk_pin_c => toggle_counter_sig_2_.CLK
+clk_pin_c => toggle_counter_sig_1_.CLK
+clk_pin_c => toggle_counter_sig_0_.CLK
+clk_pin_c => toggle_sig_Z.CLK
+clk_pin_c => r_Z.CLK
+clk_pin_c => b_Z.CLK
+clk_pin_c => g_Z.CLK
+
+
--- /dev/null
+Version 9.0 Build 132 02/25/2009 SJ Full Version
+45
+3235
+OFF
+OFF
+OFF
+ON
+ON
+ON
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+synplcty.lmf
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+vga
+# storage
+db|vga.(0).cnf
+db|vga.(0).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+a69bdf2838bc2ddfa265318d6caf919c
+28
+# hierarchies {
+|
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga_driver
+# storage
+db|vga.(1).cnf
+db|vga.(1).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+a69bdf2838bc2ddfa265318d6caf919c
+28
+# hierarchies {
+vga_driver:vga_driver_unit
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga_control
+# storage
+db|vga.(2).cnf
+db|vga.(2).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+a69bdf2838bc2ddfa265318d6caf919c
+28
+# hierarchies {
+vga_control:vga_control_unit
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# complete
+\r
\ No newline at end of file
--- /dev/null
+<TABLE BORDER="1" cellspacing="1" cellpadding="2">
+<TR valign="middle" bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">vga_control_unit</TD>
+<TD ALIGN="LEFT">23</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">29</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">vga_driver_unit</TD>
+<TD ALIGN="LEFT">4</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">60</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+</TABLE>
--- /dev/null
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; vga_control_unit ; 23 ; 0 ; 0 ; 0 ; 29 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; vga_driver_unit ; 4 ; 0 ; 0 ; 0 ; 60 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
--- /dev/null
+<kpt_db name="vga.map" kpt_version="1.1">
+ <key_points_set type="reference" hier_sep="/">
+ <key_point id="1" type="register">
+ <name>vga_driver_unit/column_counter_sig_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="2" type="register">
+ <name>vga_driver_unit/hsync_counter_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="3" type="register">
+ <name>vga_driver_unit/hsync_state_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="4" type="register">
+ <name>vga_control_unit/toggle_counter_sig_24_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="5" type="register">
+ <name>vga_driver_unit/vsync_state_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="6" type="register">
+ <name>vga_control_unit/g_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="7" type="register">
+ <name>vga_control_unit/toggle_counter_sig_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="8" type="register">
+ <name>vga_driver_unit/hsync_state_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="9" type="register">
+ <name>vga_driver_unit/hsync_state_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="10" type="register">
+ <name>vga_driver_unit/v_enable_sig_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="11" type="register">
+ <name>vga_driver_unit/column_counter_sig_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="12" type="register">
+ <name>vga_driver_unit/column_counter_sig_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="13" type="register">
+ <name>vga_control_unit/toggle_counter_sig_14_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="14" type="register">
+ <name>vga_control_unit/toggle_counter_sig_13_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="15" type="register">
+ <name>vga_control_unit/toggle_counter_sig_21_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="16" type="register">
+ <name>vga_control_unit/toggle_counter_sig_16_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="17" type="register">
+ <name>vga_driver_unit/hsync_state_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="18" type="register">
+ <name>vga_driver_unit/vsync_counter_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="19" type="register">
+ <name>vga_driver_unit/hsync_counter_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="20" type="register">
+ <name>vga_driver_unit/vsync_counter_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="21" type="register">
+ <name>vga_driver_unit/vsync_counter_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="22" type="register">
+ <name>vga_driver_unit/vsync_counter_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="23" type="register">
+ <name>vga_driver_unit/line_counter_sig_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="24" type="register">
+ <name>vga_control_unit/toggle_counter_sig_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="25" type="register">
+ <name>vga_driver_unit/column_counter_sig_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="26" type="register">
+ <name>vga_driver_unit/hsync_counter_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="27" type="register">
+ <name>vga_driver_unit/hsync_counter_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="28" type="register">
+ <name>vga_driver_unit/h_enable_sig_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="29" type="register">
+ <name>vga_driver_unit/vsync_state_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="30" type="register">
+ <name>vga_control_unit/toggle_counter_sig_23_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="31" type="register">
+ <name>vga_driver_unit/hsync_state_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="32" type="register">
+ <name>vga_driver_unit/column_counter_sig_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="33" type="register">
+ <name>vga_driver_unit/hsync_state_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="34" type="register">
+ <name>vga_control_unit/toggle_counter_sig_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="35" type="register">
+ <name>vga_driver_unit/hsync_counter_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="36" type="register">
+ <name>vga_driver_unit/hsync_counter_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="37" type="register">
+ <name>vga_driver_unit/line_counter_sig_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="38" type="register">
+ <name>vga_driver_unit/hsync_counter_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="39" type="register">
+ <name>vga_control_unit/toggle_counter_sig_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="40" type="register">
+ <name>vga_control_unit/toggle_counter_sig_15_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="41" type="register">
+ <name>vga_control_unit/toggle_counter_sig_12_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="42" type="register">
+ <name>vga_control_unit/toggle_counter_sig_19_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="43" type="register">
+ <name>vga_driver_unit/column_counter_sig_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="44" type="register">
+ <name>vga_driver_unit/hsync_counter_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="45" type="register">
+ <name>vga_control_unit/toggle_counter_sig_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="46" type="register">
+ <name>vga_driver_unit/line_counter_sig_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="47" type="register">
+ <name>vga_driver_unit/vsync_state_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="48" type="register">
+ <name>vga_driver_unit/hsync_counter_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="49" type="register">
+ <name>dly_counter_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="50" type="register">
+ <name>vga_control_unit/toggle_counter_sig_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="51" type="register">
+ <name>vga_driver_unit/vsync_counter_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="52" type="register">
+ <name>vga_driver_unit/vsync_counter_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="53" type="register">
+ <name>vga_driver_unit/column_counter_sig_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="54" type="register">
+ <name>vga_control_unit/toggle_sig_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="55" type="register">
+ <name>vga_driver_unit/line_counter_sig_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="56" type="register">
+ <name>vga_driver_unit/vsync_state_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="57" type="register">
+ <name>vga_driver_unit/h_sync_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="58" type="register">
+ <name>vga_driver_unit/vsync_counter_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="59" type="register">
+ <name>vga_control_unit/toggle_counter_sig_11_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="60" type="register">
+ <name>dly_counter_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="61" type="register">
+ <name>vga_driver_unit/vsync_counter_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="62" type="register">
+ <name>vga_control_unit/r_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="63" type="register">
+ <name>vga_driver_unit/vsync_counter_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="64" type="register">
+ <name>vga_driver_unit/column_counter_sig_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="65" type="register">
+ <name>vga_driver_unit/v_sync_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="66" type="register">
+ <name>vga_control_unit/toggle_counter_sig_20_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="67" type="register">
+ <name>vga_driver_unit/line_counter_sig_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="68" type="register">
+ <name>vga_control_unit/toggle_counter_sig_18_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="69" type="register">
+ <name>vga_control_unit/toggle_counter_sig_17_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="70" type="register">
+ <name>vga_control_unit/toggle_counter_sig_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="71" type="register">
+ <name>vga_driver_unit/vsync_state_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="72" type="register">
+ <name>vga_driver_unit/column_counter_sig_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="73" type="register">
+ <name>vga_control_unit/toggle_counter_sig_22_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="74" type="register">
+ <name>vga_driver_unit/vsync_state_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="75" type="register">
+ <name>vga_control_unit/toggle_counter_sig_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="76" type="register">
+ <name>vga_control_unit/toggle_counter_sig_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="77" type="register">
+ <name>vga_control_unit/b_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="78" type="register">
+ <name>vga_control_unit/toggle_counter_sig_10_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="79" type="register">
+ <name>vga_control_unit/toggle_counter_sig_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="80" type="register">
+ <name>vga_driver_unit/line_counter_sig_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="81" type="register">
+ <name>vga_driver_unit/line_counter_sig_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="82" type="register">
+ <name>vga_driver_unit/hsync_state_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="83" type="register">
+ <name>vga_driver_unit/line_counter_sig_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="84" type="register">
+ <name>vga_driver_unit/vsync_counter_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="85" type="register">
+ <name>vga_driver_unit/column_counter_sig_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="86" type="register">
+ <name>vga_driver_unit/hsync_counter_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="87" type="register">
+ <name>vga_driver_unit/vsync_state_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="88" type="register">
+ <name>vga_driver_unit/line_counter_sig_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ </key_points_set>
+ <key_points_set type="transition" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transformed" hier_sep="|">
+ <key_point id="89" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_7</name>
+ </key_point>
+ <key_point id="90" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_10</name>
+ </key_point>
+ <key_point id="91" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_11</name>
+ </key_point>
+ <key_point id="92" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_0</name>
+ </key_point>
+ <key_point id="93" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_0</name>
+ </key_point>
+ <key_point id="94" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_1</name>
+ </key_point>
+ <key_point id="95" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_14</name>
+ </key_point>
+ <key_point id="96" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_1</name>
+ </key_point>
+ <key_point id="97" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_15</name>
+ </key_point>
+ <key_point id="98" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_2</name>
+ </key_point>
+ <key_point id="99" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_12</name>
+ </key_point>
+ <key_point id="100" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_4</name>
+ </key_point>
+ <key_point id="101" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_5</name>
+ </key_point>
+ <key_point id="102" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_13</name>
+ </key_point>
+ <key_point id="103" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_2</name>
+ </key_point>
+ <key_point id="104" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_3</name>
+ </key_point>
+ <key_point id="105" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_6</name>
+ </key_point>
+ <key_point id="106" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_5</name>
+ </key_point>
+ <key_point id="107" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_4</name>
+ </key_point>
+ <key_point id="108" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_4</name>
+ </key_point>
+ <key_point id="109" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_3</name>
+ </key_point>
+ <key_point id="110" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_3</name>
+ </key_point>
+ <key_point id="111" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_2</name>
+ </key_point>
+ <key_point id="112" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_2</name>
+ </key_point>
+ <key_point id="113" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_1</name>
+ </key_point>
+ <key_point id="114" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_1</name>
+ </key_point>
+ <key_point id="115" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_8</name>
+ </key_point>
+ <key_point id="116" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_0</name>
+ </key_point>
+ <key_point id="117" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_0</name>
+ </key_point>
+ <key_point id="118" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_7</name>
+ </key_point>
+ <key_point id="119" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_9</name>
+ </key_point>
+ <key_point id="120" type="register">
+ <name>vga_driver:vga_driver_unit|v_enable_sig</name>
+ </key_point>
+ <key_point id="121" type="register">
+ <name>vga_driver:vga_driver_unit|h_sync</name>
+ </key_point>
+ <key_point id="122" type="register">
+ <name>vga_control:vga_control_unit|toggle_sig</name>
+ </key_point>
+ <key_point id="123" type="register">
+ <name>vga_control:vga_control_unit|b</name>
+ </key_point>
+ <key_point id="124" type="register">
+ <name>vga_driver:vga_driver_unit|h_enable_sig</name>
+ </key_point>
+ <key_point id="125" type="register">
+ <name>dly_counter[1]</name>
+ </key_point>
+ <key_point id="126" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_9</name>
+ </key_point>
+ <key_point id="127" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_8</name>
+ </key_point>
+ <key_point id="128" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_7</name>
+ </key_point>
+ <key_point id="129" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_6</name>
+ </key_point>
+ <key_point id="130" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_5</name>
+ </key_point>
+ <key_point id="131" type="register">
+ <name>vga_control:vga_control_unit|r</name>
+ </key_point>
+ <key_point id="132" type="register">
+ <name>vga_driver:vga_driver_unit|v_sync</name>
+ </key_point>
+ <key_point id="133" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_18</name>
+ </key_point>
+ <key_point id="134" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_19</name>
+ </key_point>
+ <key_point id="135" type="register">
+ <name>dly_counter[0]</name>
+ </key_point>
+ <key_point id="136" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_16</name>
+ </key_point>
+ <key_point id="137" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_17</name>
+ </key_point>
+ <key_point id="138" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_0</name>
+ </key_point>
+ <key_point id="139" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_1</name>
+ </key_point>
+ <key_point id="140" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_2</name>
+ </key_point>
+ <key_point id="141" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_4</name>
+ </key_point>
+ <key_point id="142" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_3</name>
+ </key_point>
+ <key_point id="143" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_3</name>
+ </key_point>
+ <key_point id="144" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_state_2</name>
+ </key_point>
+ <key_point id="145" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_4</name>
+ </key_point>
+ <key_point id="146" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_6</name>
+ </key_point>
+ <key_point id="147" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_5</name>
+ </key_point>
+ <key_point id="148" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_5</name>
+ </key_point>
+ <key_point id="149" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_20</name>
+ </key_point>
+ <key_point id="150" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_state_3</name>
+ </key_point>
+ <key_point id="151" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_state_0</name>
+ </key_point>
+ <key_point id="152" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_6</name>
+ </key_point>
+ <key_point id="153" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_0</name>
+ </key_point>
+ <key_point id="154" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_state_1</name>
+ </key_point>
+ <key_point id="155" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_7</name>
+ </key_point>
+ <key_point id="156" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_2</name>
+ </key_point>
+ <key_point id="157" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_state_6</name>
+ </key_point>
+ <key_point id="158" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_8</name>
+ </key_point>
+ <key_point id="159" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_1</name>
+ </key_point>
+ <key_point id="160" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_9</name>
+ </key_point>
+ <key_point id="161" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_state_4</name>
+ </key_point>
+ <key_point id="162" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_state_5</name>
+ </key_point>
+ <key_point id="163" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_7</name>
+ </key_point>
+ <key_point id="164" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_8</name>
+ </key_point>
+ <key_point id="165" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_9</name>
+ </key_point>
+ <key_point id="166" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_3</name>
+ </key_point>
+ <key_point id="167" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_4</name>
+ </key_point>
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+ <name>vga_control:vga_control_unit|toggle_counter_sig_5</name>
+ </key_point>
+ <key_point id="169" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_6</name>
+ </key_point>
+ <key_point id="170" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_8</name>
+ </key_point>
+ <key_point id="171" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_6</name>
+ </key_point>
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--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:18:43 2009 " "Info: Processing started: Wed Oct 28 14:18:43 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga -c vga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../syn/rev_1/vga.vqm 3 3 " "Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm" { { "Info" "ISGN_ENTITY_NAME" "1 vga_driver " "Info: Found entity 1: vga_driver" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 25 18 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 vga_control " "Info: Found entity 2: vga_control" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 3123 19 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 vga " "Info: Found entity 3: vga" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4396 11 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "vga " "Info: Elaborating entity \"vga\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_driver vga_driver:vga_driver_unit " "Info: Elaborating entity \"vga_driver\" for hierarchy \"vga_driver:vga_driver_unit\"" { } { { "../../syn/rev_1/vga.vqm" "vga_driver_unit" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6149 3 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_control vga_control:vga_control_unit " "Info: Elaborating entity \"vga_control\" for hierarchy \"vga_control:vga_control_unit\"" { } { { "../../syn/rev_1/vga.vqm" "vga_control_unit" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 6204 3 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "292 " "Info: Implemented 292 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "115 " "Info: Implemented 115 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "175 " "Info: Implemented 175 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:18:49 2009 " "Info: Processing ended: Wed Oct 28 14:18:49 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:19:50 2009 " "Info: Processing started: Wed Oct 28 14:19:50 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_pin " "Info: Assuming node \"clk_pin\" is an undefined clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "clk_pin" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_pin register vga_driver:vga_driver_unit\|hsync_counter_8 register vga_driver:vga_driver_unit\|hsync_state_5 191.9 MHz 5.211 ns Internal " "Info: Clock \"clk_pin\" has Internal fmax of 191.9 MHz between source register \"vga_driver:vga_driver_unit\|hsync_counter_8\" and destination register \"vga_driver:vga_driver_unit\|hsync_state_5\" (period= 5.211 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.018 ns + Longest register register " "Info: + Longest register to register delay is 5.018 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_driver:vga_driver_unit\|hsync_counter_8 1 REG LC_X38_Y28_N8 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y28_N8; Fanout = 8; REG Node = 'vga_driver:vga_driver_unit\|hsync_counter_8'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 138 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.332 ns) 1.322 ns vga_driver:vga_driver_unit\|un10_hsync_counter_1 2 COMB LC_X41_Y28_N3 4 " "Info: 2: + IC(0.990 ns) + CELL(0.332 ns) = 1.322 ns; Loc. = LC_X41_Y28_N3; Fanout = 4; COMB Node = 'vga_driver:vga_driver_unit\|un10_hsync_counter_1'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.322 ns" { vga_driver:vga_driver_unit|hsync_counter_8 vga_driver:vga_driver_unit|un10_hsync_counter_1 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 248 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.087 ns) 2.447 ns vga_driver:vga_driver_unit\|hsync_state_next_1_sqmuxa_1 3 COMB LC_X36_Y28_N3 1 " "Info: 3: + IC(1.038 ns) + CELL(0.087 ns) = 2.447 ns; Loc. = LC_X36_Y28_N3; Fanout = 1; COMB Node = 'vga_driver:vga_driver_unit\|hsync_state_next_1_sqmuxa_1'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.125 ns" { vga_driver:vga_driver_unit|un10_hsync_counter_1 vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 257 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.213 ns) 3.222 ns vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0 4 COMB LC_X37_Y28_N4 6 " "Info: 4: + IC(0.562 ns) + CELL(0.213 ns) = 3.222 ns; Loc. = LC_X37_Y28_N4; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.775 ns" { vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 246 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.726 ns) 5.018 ns vga_driver:vga_driver_unit\|hsync_state_5 5 REG LC_X37_Y29_N6 4 " "Info: 5: + IC(1.070 ns) + CELL(0.726 ns) = 5.018 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.796 ns" { vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.358 ns ( 27.06 % ) " "Info: Total cell delay = 1.358 ns ( 27.06 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.660 ns ( 72.94 % ) " "Info: Total interconnect delay = 3.660 ns ( 72.94 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.018 ns" { vga_driver:vga_driver_unit|hsync_counter_8 vga_driver:vga_driver_unit|un10_hsync_counter_1 vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.018 ns" { vga_driver:vga_driver_unit|hsync_counter_8 {} vga_driver:vga_driver_unit|un10_hsync_counter_1 {} vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.990ns 1.038ns 0.562ns 1.070ns } { 0.000ns 0.332ns 0.087ns 0.213ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.007 ns - Smallest " "Info: - Smallest clock skew is -0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.255 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_pin\" to destination register is 3.255 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.827 ns) + CELL(0.560 ns) 3.255 ns vga_driver:vga_driver_unit\|hsync_state_5 2 REG LC_X37_Y29_N6 4 " "Info: 2: + IC(1.827 ns) + CELL(0.560 ns) = 3.255 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.387 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.87 % ) " "Info: Total cell delay = 1.428 ns ( 43.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.827 ns ( 56.13 % ) " "Info: Total interconnect delay = 1.827 ns ( 56.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.262 ns - Longest register " "Info: - Longest clock path from clock \"clk_pin\" to source register is 3.262 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.834 ns) + CELL(0.560 ns) 3.262 ns vga_driver:vga_driver_unit\|hsync_counter_8 2 REG LC_X38_Y28_N8 8 " "Info: 2: + IC(1.834 ns) + CELL(0.560 ns) = 3.262 ns; Loc. = LC_X38_Y28_N8; Fanout = 8; REG Node = 'vga_driver:vga_driver_unit\|hsync_counter_8'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.394 ns" { clk_pin vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 138 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.78 % ) " "Info: Total cell delay = 1.428 ns ( 43.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.834 ns ( 56.22 % ) " "Info: Total interconnect delay = 1.834 ns ( 56.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.262 ns" { clk_pin vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.262 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_counter_8 {} } { 0.000ns 0.000ns 1.834ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.262 ns" { clk_pin vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.262 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_counter_8 {} } { 0.000ns 0.000ns 1.834ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 138 25 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.018 ns" { vga_driver:vga_driver_unit|hsync_counter_8 vga_driver:vga_driver_unit|un10_hsync_counter_1 vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.018 ns" { vga_driver:vga_driver_unit|hsync_counter_8 {} vga_driver:vga_driver_unit|un10_hsync_counter_1 {} vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.990ns 1.038ns 0.562ns 1.070ns } { 0.000ns 0.332ns 0.087ns 0.213ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.262 ns" { clk_pin vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.262 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_counter_8 {} } { 0.000ns 0.000ns 1.834ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "vga_driver:vga_driver_unit\|hsync_state_5 reset_pin clk_pin 6.543 ns register " "Info: tsu for register \"vga_driver:vga_driver_unit\|hsync_state_5\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is 6.543 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.788 ns + Longest pin register " "Info: + Longest pin to register delay is 9.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns reset_pin 1 PIN PIN_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4433 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.016 ns) + CELL(0.213 ns) 5.989 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X38_Y30_N2 53 " "Info: 2: + IC(5.016 ns) + CELL(0.213 ns) = 5.989 ns; Loc. = LC_X38_Y30_N2; Fanout = 53; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.229 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.544 ns) + CELL(0.459 ns) 7.992 ns vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0 3 COMB LC_X37_Y28_N4 6 " "Info: 3: + IC(1.544 ns) + CELL(0.459 ns) = 7.992 ns; Loc. = LC_X37_Y28_N4; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.003 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 246 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.726 ns) 9.788 ns vga_driver:vga_driver_unit\|hsync_state_5 4 REG LC_X37_Y29_N6 4 " "Info: 4: + IC(1.070 ns) + CELL(0.726 ns) = 9.788 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.796 ns" { vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns ( 22.05 % ) " "Info: Total cell delay = 2.158 ns ( 22.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.630 ns ( 77.95 % ) " "Info: Total interconnect delay = 7.630 ns ( 77.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.788 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "9.788 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 5.016ns 1.544ns 1.070ns } { 0.000ns 0.760ns 0.213ns 0.459ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.255 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_pin\" to destination register is 3.255 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.827 ns) + CELL(0.560 ns) 3.255 ns vga_driver:vga_driver_unit\|hsync_state_5 2 REG LC_X37_Y29_N6 4 " "Info: 2: + IC(1.827 ns) + CELL(0.560 ns) = 3.255 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.387 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.87 % ) " "Info: Total cell delay = 1.428 ns ( 43.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.827 ns ( 56.13 % ) " "Info: Total interconnect delay = 1.827 ns ( 56.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.788 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "9.788 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 5.016ns 1.544ns 1.070ns } { 0.000ns 0.760ns 0.213ns 0.459ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "clk_pin d_set_vsync_counter vga_driver:vga_driver_unit\|vsync_state_0 10.494 ns register " "Info: tco from clock \"clk_pin\" to destination pin \"d_set_vsync_counter\" through register \"vga_driver:vga_driver_unit\|vsync_state_0\" is 10.494 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.247 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to source register is 3.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.819 ns) + CELL(0.560 ns) 3.247 ns vga_driver:vga_driver_unit\|vsync_state_0 2 REG LC_X38_Y30_N9 5 " "Info: 2: + IC(1.819 ns) + CELL(0.560 ns) = 3.247 ns; Loc. = LC_X38_Y30_N9; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.379 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 109 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.98 % ) " "Info: Total cell delay = 1.428 ns ( 43.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.819 ns ( 56.02 % ) " "Info: Total interconnect delay = 1.819 ns ( 56.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.247 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.247 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_0 {} } { 0.000ns 0.000ns 1.819ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 109 23 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.071 ns + Longest register pin " "Info: + Longest register to pin delay is 7.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_driver:vga_driver_unit\|vsync_state_0 1 REG LC_X38_Y30_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y30_N9; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 109 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.944 ns) + CELL(0.332 ns) 1.276 ns vga_driver:vga_driver_unit\|d_set_vsync_counter 2 COMB LC_X35_Y30_N4 2 " "Info: 2: + IC(0.944 ns) + CELL(0.332 ns) = 1.276 ns; Loc. = LC_X35_Y30_N4; Fanout = 2; COMB Node = 'vga_driver:vga_driver_unit\|d_set_vsync_counter'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.276 ns" { vga_driver:vga_driver_unit|vsync_state_0 vga_driver:vga_driver_unit|d_set_vsync_counter } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 147 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.291 ns) + CELL(2.504 ns) 7.071 ns d_set_vsync_counter 3 PIN PIN_Y11 0 " "Info: 3: + IC(3.291 ns) + CELL(2.504 ns) = 7.071 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'd_set_vsync_counter'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.795 ns" { vga_driver:vga_driver_unit|d_set_vsync_counter d_set_vsync_counter } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4454 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.836 ns ( 40.11 % ) " "Info: Total cell delay = 2.836 ns ( 40.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.235 ns ( 59.89 % ) " "Info: Total interconnect delay = 4.235 ns ( 59.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.071 ns" { vga_driver:vga_driver_unit|vsync_state_0 vga_driver:vga_driver_unit|d_set_vsync_counter d_set_vsync_counter } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.071 ns" { vga_driver:vga_driver_unit|vsync_state_0 {} vga_driver:vga_driver_unit|d_set_vsync_counter {} d_set_vsync_counter {} } { 0.000ns 0.944ns 3.291ns } { 0.000ns 0.332ns 2.504ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.247 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.247 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_0 {} } { 0.000ns 0.000ns 1.819ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.071 ns" { vga_driver:vga_driver_unit|vsync_state_0 vga_driver:vga_driver_unit|d_set_vsync_counter d_set_vsync_counter } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.071 ns" { vga_driver:vga_driver_unit|vsync_state_0 {} vga_driver:vga_driver_unit|d_set_vsync_counter {} d_set_vsync_counter {} } { 0.000ns 0.944ns 3.291ns } { 0.000ns 0.332ns 2.504ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "reset_pin seven_seg_pin\[9\] 11.756 ns Longest " "Info: Longest tpd from source pin \"reset_pin\" to destination pin \"seven_seg_pin\[9\]\" is 11.756 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns reset_pin 1 PIN PIN_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4433 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.016 ns) + CELL(0.213 ns) 5.989 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X38_Y30_N2 53 " "Info: 2: + IC(5.016 ns) + CELL(0.213 ns) = 5.989 ns; Loc. = LC_X38_Y30_N2; Fanout = 53; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.229 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.263 ns) + CELL(2.504 ns) 11.756 ns seven_seg_pin\[9\] 3 PIN PIN_A7 0 " "Info: 3: + IC(3.263 ns) + CELL(2.504 ns) = 11.756 ns; Loc. = PIN_A7; Fanout = 0; PIN Node = 'seven_seg_pin\[9\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.767 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[9] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.477 ns ( 29.58 % ) " "Info: Total cell delay = 3.477 ns ( 29.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.279 ns ( 70.42 % ) " "Info: Total interconnect delay = 8.279 ns ( 70.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "11.756 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[9] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "11.756 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[9] {} } { 0.000ns 0.000ns 5.016ns 3.263ns } { 0.000ns 0.760ns 0.213ns 2.504ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "dly_counter\[1\] reset_pin clk_pin -2.787 ns register " "Info: th for register \"dly_counter\[1\]\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is -2.787 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.247 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to destination register is 3.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.819 ns) + CELL(0.560 ns) 3.247 ns dly_counter\[1\] 2 REG LC_X38_Y30_N6 10 " "Info: 2: + IC(1.819 ns) + CELL(0.560 ns) = 3.247 ns; Loc. = LC_X38_Y30_N6; Fanout = 10; REG Node = 'dly_counter\[1\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.379 ns" { clk_pin dly_counter[1] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.98 % ) " "Info: Total cell delay = 1.428 ns ( 43.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.819 ns ( 56.02 % ) " "Info: Total interconnect delay = 1.819 ns ( 56.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.247 ns" { clk_pin dly_counter[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.247 ns" { clk_pin {} clk_pin~out0 {} dly_counter[1] {} } { 0.000ns 0.000ns 1.819ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.134 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.134 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns reset_pin 1 PIN PIN_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4433 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.010 ns) + CELL(0.364 ns) 6.134 ns dly_counter\[1\] 2 REG LC_X38_Y30_N6 10 " "Info: 2: + IC(5.010 ns) + CELL(0.364 ns) = 6.134 ns; Loc. = LC_X38_Y30_N6; Fanout = 10; REG Node = 'dly_counter\[1\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.374 ns" { reset_pin dly_counter[1] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.124 ns ( 18.32 % ) " "Info: Total cell delay = 1.124 ns ( 18.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.010 ns ( 81.68 % ) " "Info: Total interconnect delay = 5.010 ns ( 81.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.134 ns" { reset_pin dly_counter[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.134 ns" { reset_pin {} reset_pin~out0 {} dly_counter[1] {} } { 0.000ns 0.000ns 5.010ns } { 0.000ns 0.760ns 0.364ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.247 ns" { clk_pin dly_counter[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.247 ns" { clk_pin {} clk_pin~out0 {} dly_counter[1] {} } { 0.000ns 0.000ns 1.819ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.134 ns" { reset_pin dly_counter[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.134 ns" { reset_pin {} reset_pin~out0 {} dly_counter[1] {} } { 0.000ns 0.000ns 5.010ns } { 0.000ns 0.760ns 0.364ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Peak virtual memory: 141 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:19:50 2009 " "Info: Processing ended: Wed Oct 28 14:19:50 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
--- /dev/null
+start_full_compilation:s:00:01:22
+start_analysis_synthesis:s:00:00:17-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:35-start_full_compilation
+start_assembler:s:00:00:22-start_full_compilation
+start_timing_analyzer:s:00:00:03-start_full_compilation
+start_eda_netlist_writer:s:00:00:05-start_full_compilation
--- /dev/null
+Version:
+ 9.0 Build 132 02/25/2009 SJ Full Version
+
+Chip Device Options:
+ Device Name: EP1S25F672C6
+ Device JTAG code: ffffffff
+ Programming_mode: Passive Serial
+ NWS_NRS_NCS: UNRESERVED
+ RDYNBUSY: UNRESERVED
+ DATA 7 to 1: UNRESERVED
+ nCEO: UNRESERVED
+ UNUSED PINS: RESERVED_GND
+ Default IO Standard:: 3.3-V LVTTL
+ User Start-up Clock: 0
+ Auto Restart on Error: 1
+ Release Clears Before Tristates: 0
+ Device Clear: 0
+ Test And Scan: 0
+ Device OE: 0
+ Enable Lock Output: 0
+ Enable Init Done: 0
+ Enable JTAG BST: 0
+ Enable Vref A: 0
+ Enable Vref B: 0
+
+
+
+****************************
+******Individual Atoms******
+****************************
+
+- ATOM ------------------------
+ ATOM_NAME: r0_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 0
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] r0_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: r1_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 1
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] r1_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: r2_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 2
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] r2_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: g0_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 3
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] g0_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: g1_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 4
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] g1_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: g2_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 5
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] g2_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: b0_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 6
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] b0_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: b1_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 7
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] b1_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: hsync_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 8
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] hsync_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vsync_pin_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 9
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] vsync_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_tri_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 10
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 11
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 12
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_tri_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 13
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_tri_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 14
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_tri_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 15
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_tri_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 16
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 17
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 18
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 19
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_out_10_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 20
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[10] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_out_11_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 21
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[11] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_out_12_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 22
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[12] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: seven_seg_pin_tri_13_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 23
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] !(~STRATIX_FITTER_CREATED_GND~I) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] seven_seg_pin[13] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 24
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 25
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 26
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 27
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 28
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 29
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 30
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 31
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 32
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 33
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 34
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_column_counter_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 35
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_column_counter[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_line_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 36
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_line_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 37
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_line_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 38
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_line_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 39
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_line_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 40
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_line_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 41
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_line_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 42
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_line_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 43
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_line_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 44
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_line_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_set_column_counter_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 45
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_set_column_counter LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_set_line_counter_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 46
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_set_line_counter LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 47
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 48
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 49
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 50
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 51
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 52
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 53
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 54
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 55
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_counter_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 56
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_counter[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 57
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 58
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 59
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 60
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 61
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 62
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 63
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 64
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 65
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_counter_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 66
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_counter[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_set_hsync_counter_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 67
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_set_hsync_counter LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_set_vsync_counter_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 68
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_set_vsync_counter LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_h_enable_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 69
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_h_enable LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_v_enable_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 70
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_v_enable LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_r_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 71
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|r LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_r LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_g_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 72
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_g LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_b_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 73
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|b LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_b LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_state_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 74
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_state_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 75
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_state_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 76
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_state_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 77
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_state_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 78
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_state_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 79
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_hsync_state_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 80
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_hsync_state[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_state_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 81
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_state_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 82
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_state_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 83
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_state_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 84
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_state_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 85
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_state_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 86
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_vsync_state_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 87
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_vsync_state[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_state_clk_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 88
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_state_clk LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_out -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 89
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 90
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[0] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 91
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[1] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 92
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[2] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 93
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[3] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 94
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[4] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 95
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[5] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 96
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[6] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 97
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[7] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 98
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[8] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 99
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[9] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_10_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 100
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[10] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_11_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 101
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[11] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_12_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 102
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[12] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_13_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 103
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[13] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_14_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 104
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[14] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_15_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 105
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[15] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_16_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 106
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[16] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_17_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 107
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[17] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_18_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 108
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[18] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_19_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 109
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[19] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_20_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 110
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] vga_control:vga_control_unit|toggle_counter_sig_20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[20] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_21_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 111
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[21] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_22_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 112
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[22] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_23_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 113
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[23] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: d_toggle_counter_out_24_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 114
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: [DATAIN] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] d_toggle_counter[24] LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = output
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|r_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 115
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|b_next_0_sqmuxa_7_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|r LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|b_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 116
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|b_next_0_sqmuxa_7_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|b LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 4000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|h_sync_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 117
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|h_sync LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|v_sync_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 118
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|v_sync LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 119
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 FANOUTS 53
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f7f
+ output_mode = reg_and_comb
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 120
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7777
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 121
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 122
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 123
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 124
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 125
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 126
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 127
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 128
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_sig_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 129
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un2_column_counter_next_combout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 130
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = bbbb
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 131
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 132
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 133
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 134
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 135
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 136
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 137
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_sig_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 138
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = dddd
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 139
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 140
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 141
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[0] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 55aa
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 142
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 143
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 144
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 145
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 FANOUTS 7 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 146
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 147
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 FANOUTS 7 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 148
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 FANOUTS 7 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 149
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|hsync_counter_cout[8] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 150
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_2_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_hsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|hsync_counter_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 FANOUTS 6 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 151
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 FANOUTS 9 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[0] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 6688
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 152
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 153
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 154
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 155
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 156
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 157
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 158
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 159
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: [COUT] vga_driver:vga_driver_unit|vsync_counter_cout[8] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a50a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 160
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: [SYNCH_DATA] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_driver:vga_driver_unit|G_16_i) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: [SLOAD] !(vga_driver:vga_driver_unit|un9_vsync_counterlt9) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_driver:vga_driver_unit|vsync_counter_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 FANOUTS 9 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a5a
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|d_set_hsync_counter_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 161
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 FANOUTS 5
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|d_set_vsync_counter_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 162
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|h_enable_sig_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 163
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 FANOUTS 2 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|v_enable_sig_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 164
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|v_enable_sig LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 165
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: [DATAD] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff00
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 166
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 167
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 168
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = aaaa
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 169
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8888
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 170
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8888
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 171
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 172
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 2000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 173
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = aaaa
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 174
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 175
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 FANOUTS 5 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0cae
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: clk_pin_in -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 176
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [PADIO] DISCONNECTED
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] clk_pin LIT INDEX 0 FANOUTS 84
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] clk_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = input
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_sig_Z -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 177
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_sig_0_0_0_g1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_sig LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 9999
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 178
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 5555
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 179
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_1 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 6688
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 180
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|un2_toggle_counter_next_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_2 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 181
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_3 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 182
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_4 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 183
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 184
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 185
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 186
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[8] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 187
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[9] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_10_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 188
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[10] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_11_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 189
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[11] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_12_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 190
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[10] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[12] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_13_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 191
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[11] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[13] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_14_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 192
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[12] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[14] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_15_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 193
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[13] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[15] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_16_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 194
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[14] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[16] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_17_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 195
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[15] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[17] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_18_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 196
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[16] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: [COUT] vga_control:vga_control_unit|toggle_counter_sig_cout[18] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_19_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 197
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[17] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 FANOUTS 4 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c6c
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_counter_sig_20_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 198
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: [ACLR] ~ !(vga_driver:vga_driver_unit|un6_dly_counter_0_x) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: [SCLR] !(vga_control:vga_control_unit|toggle_sig_0_0_0_g1) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: [CIN] vga_control:vga_control_unit|toggle_counter_sig_cout[18] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] vga_control:vga_control_unit|toggle_counter_sig_20 LIT INDEX 0 FANOUTS 3 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = on
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a5a5
+ cin_used = true
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 199
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|un13_v_enablelto6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|b_next_0_sqmuxa_7_4 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ef23
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|b_next_0_sqmuxa_7_5_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 200
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|un5_v_enablelto5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|b_next_0_sqmuxa_7_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|b_next_0_sqmuxa_7_5 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f00
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: reset_pin_in -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 201
+ Atom Type: stratix_io (WYSIWYG)
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [PADIO] DISCONNECTED
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] reset_pin LIT INDEX 0 FANOUTS 9
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] reset_pin LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = input
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
+- ATOM ------------------------
+ ATOM_NAME: dly_counter_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 202
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] dly_counter[0] LIT INDEX 0 FANOUTS 9 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = a2a2
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: dly_counter_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 203
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: [CLK] clk_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: [ENA] DISCONNECTED
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: [REGOUT] dly_counter[1] LIT INDEX 0 FANOUTS 9 REGED POS
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = a8a8
+ output_mode = reg_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 204
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|h_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un1_hsync_state_3_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|h_sync_1_0_0_0_g1 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ccd8
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 205
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|v_sync LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un1_vsync_state_2_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|v_sync_1_0_0_0_g1 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ccd8
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 206
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un10_column_counter_siglt6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un10_column_counter_siglto9 LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 1f0f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 207
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 208
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[1] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 6688
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 209
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[2] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 210
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[3] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 211
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[4] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 212
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[5] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 213
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[6] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 214
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[7] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 215
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[8] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a5a5
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 216
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un2_column_counter_next_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_combout[9] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c6c6
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 217
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[1] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 6688
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 218
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un10_line_counter_siglto5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un10_line_counter_siglto8 LIT INDEX 0 FANOUTS 9
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 219
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 LIT INDEX 0 FANOUTS 9
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_2_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 220
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_a_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[2] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[2] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_3_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 221
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[3] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[3] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_4_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 222
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[4] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[4] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a508
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_5_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 223
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[5] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[5] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c608
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_6_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 224
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[6] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[6] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 5a7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_7_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 225
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[7] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[7] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = 6c7f
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_8_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 226
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[8] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = a5a5
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_9_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 227
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: [CIN] vga_driver:vga_driver_unit|un1_line_counter_sig_cout[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_combout[9] LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = cin
+ lut_mask = c6c6
+ cin_used = true
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 228
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0808
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 229
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 FANOUTS 4
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0101
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 230
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0008
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 231
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 LIT INDEX 0 FANOUTS 6
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f0f1
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 232
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 FANOUTS 3
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0001
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 233
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un13_vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 234
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|G_2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 235
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un9_hsync_counterlt9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|G_2_i LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0f1f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 236
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un9_hsync_counterlt9_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un9_hsync_counterlt9 LIT INDEX 0 FANOUTS 11
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f7ff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 237
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] reset_pin LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] dly_counter[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] dly_counter[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|d_set_vsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|G_16 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 238
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un9_vsync_counterlt9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|G_16_i LIT INDEX 0 FANOUTS 10
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0f1f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 239
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un9_vsync_counterlt9_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un9_vsync_counterlt9_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un9_vsync_counterlt9 LIT INDEX 0 FANOUTS 11
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = fff7
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 240
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f1f1
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 241
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f1f1
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 242
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0101
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 243
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 244
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un12_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un12_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 245
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un13_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 1000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 246
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|un6_dly_counter_0_x LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa LIT INDEX 0 FANOUTS 5
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = aaab
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 247
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 FANOUTS 4
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8888
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 248
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|toggle_sig_0_0_0_g1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 249
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: [DATAD] vga_control:vga_control_unit|un1_toggle_counter_siglto18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|toggle_sig_0_0_0_g1 LIT INDEX 0 FANOUTS 22
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7733
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|un2_toggle_counter_next_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 250
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un2_toggle_counter_next_0_~COMBOUT LIT INDEX 0 FANOUTS 0
+ 1: NONE
+ 2: [COUT] vga_control:vga_control_unit|un2_toggle_counter_next_cout[0] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff88
+ output_mode = none
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 251
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|un13_v_enablelto4_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un13_v_enablelto6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f77
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 252
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|line_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|un17_v_enablelto3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|b_next_0_sqmuxa_7_4_a LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0f1f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 253
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|un5_v_enablelt2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un5_v_enablelto5 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = feee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|b_next_0_sqmuxa_7_3_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 254
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|b_next_0_sqmuxa_7_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|un9_v_enablelto6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|b_next_0_sqmuxa_7_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = e0f0
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_hsync_state_3_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 255
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_hsync_state_3_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_vsync_state_2_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 256
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_state_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_vsync_state_2_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = eeee
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 257
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un10_column_counter_siglt6_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un10_column_counter_siglt6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un2_column_counter_next_0_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 258
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un2_column_counter_next_0_~COMBOUT LIT INDEX 0 FANOUTS 0
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un2_column_counter_next_cout[0] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff88
+ output_mode = none
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 259
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|line_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un10_line_counter_siglt4_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un10_line_counter_siglto5 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0f07
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_line_counter_sig_a_1_ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 260
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|d_set_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT LIT INDEX 0 FANOUTS 0
+ 1: NONE
+ 2: [COUT] vga_driver:vga_driver_unit|un1_line_counter_sig_a_cout[1] LIT INDEX 0 FANOUTS 1
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = arithmetic
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff88
+ output_mode = none
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 261
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un10_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un10_hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 2aaa
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 262
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un11_hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un10_hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un11_hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 2aaa
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 263
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un13_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un12_hsync_counter LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0ace
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 264
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un13_vsync_counter_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0001
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 265
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un9_hsync_counterlt9_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7fff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 266
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un13_hsync_counter_7 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 8000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 267
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un9_vsync_counterlt9_5 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7fff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 268
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un9_vsync_counterlt9_6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7fff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 269
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un12_hsync_counter_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0008
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 270
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un12_hsync_counter_4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0010
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 271
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|hsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|hsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|hsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|hsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un13_hsync_counter_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0080
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 272
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_1 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = d0f0
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 273
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_state_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|un14_vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 70f0
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 274
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff2a
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 275
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un12_vsync_counter_6 LIT INDEX 0 FANOUTS 3
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0001
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 276
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un15_vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un15_vsync_counter_4 LIT INDEX 0 FANOUTS 2
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 1010
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 277
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|toggle_counter_sig_16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|un1_toggle_counter_siglto15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un1_toggle_counter_siglto18 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f77
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 278
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un13_v_enablelto4_0 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 1111
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 279
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un17_v_enablelto3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = fe00
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 280
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un5_v_enablelt2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = fefe
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|b_next_0_sqmuxa_7_2_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 281
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|h_enable_sig LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|line_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|b_next_0_sqmuxa_7_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0004
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 282
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|un9_v_enablelto4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un9_v_enablelto6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = f7f7
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 283
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|column_counter_sig_1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un10_column_counter_siglt6_4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7fff
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 284
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|line_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|line_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|line_counter_sig_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un10_line_counter_siglt4_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f7f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 285
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_state_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|un12_vsync_counter_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|un13_vsync_counter_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_2 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 2a2a
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_driver:vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 286
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|vsync_counter_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|vsync_counter_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|vsync_counter_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_driver:vga_driver_unit|vsync_counter_0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_driver:vga_driver_unit|un15_vsync_counter_3 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0020
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 287
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|toggle_counter_sig_15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|un1_toggle_counter_siglto12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un1_toggle_counter_siglto15 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = ff7f
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 288
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_driver:vga_driver_unit|column_counter_sig_3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_driver:vga_driver_unit|column_counter_sig_4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_driver:vga_driver_unit|column_counter_sig_2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un9_v_enablelto4 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0101
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 289
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|toggle_counter_sig_12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|un1_toggle_counter_siglto9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un1_toggle_counter_siglto12 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0100
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 290
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: [DATAC] vga_control:vga_control_unit|toggle_counter_sig_7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 4: [DATAD] vga_control:vga_control_unit|un1_toggle_counter_siglt6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un1_toggle_counter_siglto9 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7f77
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: vga_control:vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6 -- UNIQUE
+ Atom Hier Name:
+ Atom Id: 291
+ Atom Type: stratix_lcell (WYSIWYG)
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: [DATAA] vga_control:vga_control_unit|toggle_counter_sig_6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 2: [DATAB] vga_control:vga_control_unit|toggle_counter_sig_5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] vga_control:vga_control_unit|un1_toggle_counter_siglt6 LIT INDEX 0 FANOUTS 1
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 7777
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: ~STRATIX_FITTER_CREATED_GND~I -- NON-UNIQUE
+ Atom Hier Name:
+ Atom Id: 292
+ Atom Type: stratix_lcell
+
+ Assembler Lutmask : I very much like HEX numbers.
+ power up = low
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ 11: NO ITERM
+ 12: NO ITERM
+ 13: NO ITERM
+ 14: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: [COMBOUT] ~STRATIX_FITTER_CREATED_GND~I LIT INDEX 0 FANOUTS 14
+ 1: NONE
+ 2: NONE
+ 3: NONE
+ 4: NONE
+
+ PARAMETER LIST:
+ operation_mode = normal
+ synch_mode = off
+ register_cascade_mode = off
+ sum_lutc_input = datac
+ lut_mask = 0000
+ output_mode = comb_only
+
+
+- ATOM ------------------------
+ ATOM_NAME: ~DATA0~ -- NON-UNIQUE
+ Atom Hier Name:
+ Atom Id: 293
+ Atom Type: stratix_io
+
+ INPUTS (Driven By):
+ 0: NO ITERM
+ 1: NO ITERM
+ 2: NO ITERM
+ 3: NO ITERM
+ 4: NO ITERM
+ 5: NO ITERM
+ 6: NO ITERM
+ 7: NO ITERM
+ 8: NO ITERM
+ 9: NO ITERM
+ 10: NO ITERM
+ OUTPUTS (Int. Connections):
+ 0: NONE
+ 1: NONE
+ 2: NONE
+ 3: [PADIO] ~DATA0~ LIT INDEX 0 FANOUTS 0
+ 4: NONE
+ 5: NONE
+ 6: NONE
+ 7: NONE
+
+ PARAMETER LIST:
+ operation_mode = input
+ ddio_mode = none
+ input_register_mode = none
+ output_register_mode = none
+ oe_register_mode = none
+ input_async_reset = none
+ output_async_reset = none
+ oe_async_reset = none
+ input_sync_reset = none
+ output_sync_reset = none
+ oe_sync_reset = none
+ input_power_up = low
+ output_power_up = low
+ oe_power_up = low
+
+ DELAY CHAINS:
+ PAD TO CORE 0: OFF
+ PAD TO CORE 1: OFF
+ TCO CHAIN: OFF
+ TCOE CHAIN: OFF
+ PAD TO INPUT REG: OFF
+ CORE TO OUTPUT REG: OFF
+ ZBT: OFF
+ CE TO INPUT_REG: OFF
+ CE TO OUTPUT_REG: OFF
+ CE TO OE_REG: OFF
+
+ IO STANDARD: 3.3-V LVTTL
+ CURRENT STRENGTH: DEFAULT
+ PCI DIODE: OFF
+ TERMINATION: OFF
+ DQS INFORMATION:
+ Not a DQS atom.
+ DQS system clock: False
+ PLL COMPENSATED: False
+
--- /dev/null
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
--- /dev/null
+<kpt_db name="root_partition" kpt_version="1.1">
+ <key_points_set type="reference" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transition" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transformed" hier_sep="|">
+ </key_points_set>
+ <transformations_set hier_sep="|">
+ </transformations_set>
+</kpt_db>
--- /dev/null
+<kpt_db name="vga.map_bb" kpt_version="1.1">
+ <key_points_set type="reference" hier_sep="/">
+ <key_point id="1" type="register">
+ <name>vga_driver_unit/column_counter_sig_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="2" type="register">
+ <name>vga_driver_unit/hsync_counter_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="3" type="register">
+ <name>vga_driver_unit/hsync_state_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="4" type="register">
+ <name>vga_control_unit/toggle_counter_sig_24_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="5" type="register">
+ <name>vga_driver_unit/vsync_state_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="6" type="register">
+ <name>vga_control_unit/g_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="7" type="register">
+ <name>vga_control_unit/toggle_counter_sig_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="8" type="register">
+ <name>vga_driver_unit/hsync_state_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="9" type="register">
+ <name>vga_driver_unit/hsync_state_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="10" type="register">
+ <name>vga_driver_unit/v_enable_sig_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="11" type="register">
+ <name>vga_driver_unit/column_counter_sig_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="12" type="register">
+ <name>vga_driver_unit/column_counter_sig_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="13" type="register">
+ <name>vga_control_unit/toggle_counter_sig_14_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="14" type="register">
+ <name>vga_control_unit/toggle_counter_sig_13_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="15" type="register">
+ <name>vga_control_unit/toggle_counter_sig_21_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="16" type="register">
+ <name>vga_control_unit/toggle_counter_sig_16_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="17" type="register">
+ <name>vga_driver_unit/hsync_state_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="18" type="register">
+ <name>vga_driver_unit/vsync_counter_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="19" type="register">
+ <name>vga_driver_unit/hsync_counter_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="20" type="register">
+ <name>vga_driver_unit/vsync_counter_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="21" type="register">
+ <name>vga_driver_unit/vsync_counter_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="22" type="register">
+ <name>vga_driver_unit/vsync_counter_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="23" type="register">
+ <name>vga_driver_unit/line_counter_sig_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="24" type="register">
+ <name>vga_control_unit/toggle_counter_sig_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="25" type="register">
+ <name>vga_driver_unit/column_counter_sig_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="26" type="register">
+ <name>vga_driver_unit/hsync_counter_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="27" type="register">
+ <name>vga_driver_unit/hsync_counter_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="28" type="register">
+ <name>vga_driver_unit/h_enable_sig_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="29" type="register">
+ <name>vga_driver_unit/vsync_state_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="30" type="register">
+ <name>vga_control_unit/toggle_counter_sig_23_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="31" type="register">
+ <name>vga_driver_unit/hsync_state_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="32" type="register">
+ <name>vga_driver_unit/column_counter_sig_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="33" type="register">
+ <name>vga_driver_unit/hsync_state_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="34" type="register">
+ <name>vga_control_unit/toggle_counter_sig_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="35" type="register">
+ <name>vga_driver_unit/hsync_counter_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="36" type="register">
+ <name>vga_driver_unit/hsync_counter_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="37" type="register">
+ <name>vga_driver_unit/line_counter_sig_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="38" type="register">
+ <name>vga_driver_unit/hsync_counter_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="39" type="register">
+ <name>vga_control_unit/toggle_counter_sig_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="40" type="register">
+ <name>vga_control_unit/toggle_counter_sig_15_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="41" type="register">
+ <name>vga_control_unit/toggle_counter_sig_12_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="42" type="register">
+ <name>vga_control_unit/toggle_counter_sig_19_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="43" type="register">
+ <name>vga_driver_unit/column_counter_sig_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="44" type="register">
+ <name>vga_driver_unit/hsync_counter_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="45" type="register">
+ <name>vga_control_unit/toggle_counter_sig_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="46" type="register">
+ <name>vga_driver_unit/line_counter_sig_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="47" type="register">
+ <name>vga_driver_unit/vsync_state_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="48" type="register">
+ <name>vga_driver_unit/hsync_counter_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="49" type="register">
+ <name>dly_counter_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="50" type="register">
+ <name>vga_control_unit/toggle_counter_sig_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="51" type="register">
+ <name>vga_driver_unit/vsync_counter_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="52" type="register">
+ <name>vga_driver_unit/vsync_counter_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="53" type="register">
+ <name>vga_driver_unit/column_counter_sig_7_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="54" type="register">
+ <name>vga_control_unit/toggle_sig_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="55" type="register">
+ <name>vga_driver_unit/line_counter_sig_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="56" type="register">
+ <name>vga_driver_unit/vsync_state_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="57" type="register">
+ <name>vga_driver_unit/h_sync_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="58" type="register">
+ <name>vga_driver_unit/vsync_counter_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="59" type="register">
+ <name>vga_control_unit/toggle_counter_sig_11_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="60" type="register">
+ <name>dly_counter_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="61" type="register">
+ <name>vga_driver_unit/vsync_counter_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="62" type="register">
+ <name>vga_control_unit/r_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="63" type="register">
+ <name>vga_driver_unit/vsync_counter_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="64" type="register">
+ <name>vga_driver_unit/column_counter_sig_9_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="65" type="register">
+ <name>vga_driver_unit/v_sync_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="66" type="register">
+ <name>vga_control_unit/toggle_counter_sig_20_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="67" type="register">
+ <name>vga_driver_unit/line_counter_sig_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="68" type="register">
+ <name>vga_control_unit/toggle_counter_sig_18_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="69" type="register">
+ <name>vga_control_unit/toggle_counter_sig_17_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="70" type="register">
+ <name>vga_control_unit/toggle_counter_sig_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="71" type="register">
+ <name>vga_driver_unit/vsync_state_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="72" type="register">
+ <name>vga_driver_unit/column_counter_sig_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="73" type="register">
+ <name>vga_control_unit/toggle_counter_sig_22_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ <attributes_list>
+ <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
+ </attributes_list>
+ </key_point>
+ <key_point id="74" type="register">
+ <name>vga_driver_unit/vsync_state_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="75" type="register">
+ <name>vga_control_unit/toggle_counter_sig_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="76" type="register">
+ <name>vga_control_unit/toggle_counter_sig_1_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="77" type="register">
+ <name>vga_control_unit/b_Z</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="78" type="register">
+ <name>vga_control_unit/toggle_counter_sig_10_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="79" type="register">
+ <name>vga_control_unit/toggle_counter_sig_0_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="80" type="register">
+ <name>vga_driver_unit/line_counter_sig_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="81" type="register">
+ <name>vga_driver_unit/line_counter_sig_3_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="82" type="register">
+ <name>vga_driver_unit/hsync_state_6_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="83" type="register">
+ <name>vga_driver_unit/line_counter_sig_8_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="84" type="register">
+ <name>vga_driver_unit/vsync_counter_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="85" type="register">
+ <name>vga_driver_unit/column_counter_sig_5_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="86" type="register">
+ <name>vga_driver_unit/hsync_counter_2_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="87" type="register">
+ <name>vga_driver_unit/vsync_state_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ <key_point id="88" type="register">
+ <name>vga_driver_unit/line_counter_sig_4_</name>
+ <entity>stratix_lcell</entity>
+ <reg_type>le</reg_type>
+ </key_point>
+ </key_points_set>
+ <key_points_set type="transition" hier_sep="|">
+ </key_points_set>
+ <key_points_set type="transformed" hier_sep="|">
+ <key_point id="89" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_7</name>
+ </key_point>
+ <key_point id="90" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_10</name>
+ </key_point>
+ <key_point id="91" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_11</name>
+ </key_point>
+ <key_point id="92" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_0</name>
+ </key_point>
+ <key_point id="93" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_0</name>
+ </key_point>
+ <key_point id="94" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_1</name>
+ </key_point>
+ <key_point id="95" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_14</name>
+ </key_point>
+ <key_point id="96" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_1</name>
+ </key_point>
+ <key_point id="97" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_15</name>
+ </key_point>
+ <key_point id="98" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_2</name>
+ </key_point>
+ <key_point id="99" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_12</name>
+ </key_point>
+ <key_point id="100" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_4</name>
+ </key_point>
+ <key_point id="101" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_5</name>
+ </key_point>
+ <key_point id="102" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_13</name>
+ </key_point>
+ <key_point id="103" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_2</name>
+ </key_point>
+ <key_point id="104" type="register">
+ <name>vga_driver:vga_driver_unit|line_counter_sig_3</name>
+ </key_point>
+ <key_point id="105" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_6</name>
+ </key_point>
+ <key_point id="106" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_5</name>
+ </key_point>
+ <key_point id="107" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_4</name>
+ </key_point>
+ <key_point id="108" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_4</name>
+ </key_point>
+ <key_point id="109" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_3</name>
+ </key_point>
+ <key_point id="110" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_3</name>
+ </key_point>
+ <key_point id="111" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_2</name>
+ </key_point>
+ <key_point id="112" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_2</name>
+ </key_point>
+ <key_point id="113" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_1</name>
+ </key_point>
+ <key_point id="114" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_1</name>
+ </key_point>
+ <key_point id="115" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_8</name>
+ </key_point>
+ <key_point id="116" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_state_0</name>
+ </key_point>
+ <key_point id="117" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_0</name>
+ </key_point>
+ <key_point id="118" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_7</name>
+ </key_point>
+ <key_point id="119" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_9</name>
+ </key_point>
+ <key_point id="120" type="register">
+ <name>vga_driver:vga_driver_unit|v_enable_sig</name>
+ </key_point>
+ <key_point id="121" type="register">
+ <name>vga_driver:vga_driver_unit|h_sync</name>
+ </key_point>
+ <key_point id="122" type="register">
+ <name>vga_control:vga_control_unit|toggle_sig</name>
+ </key_point>
+ <key_point id="123" type="register">
+ <name>vga_control:vga_control_unit|b</name>
+ </key_point>
+ <key_point id="124" type="register">
+ <name>vga_driver:vga_driver_unit|h_enable_sig</name>
+ </key_point>
+ <key_point id="125" type="register">
+ <name>dly_counter[1]</name>
+ </key_point>
+ <key_point id="126" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_9</name>
+ </key_point>
+ <key_point id="127" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_8</name>
+ </key_point>
+ <key_point id="128" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_7</name>
+ </key_point>
+ <key_point id="129" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_6</name>
+ </key_point>
+ <key_point id="130" type="register">
+ <name>vga_driver:vga_driver_unit|column_counter_sig_5</name>
+ </key_point>
+ <key_point id="131" type="register">
+ <name>vga_control:vga_control_unit|r</name>
+ </key_point>
+ <key_point id="132" type="register">
+ <name>vga_driver:vga_driver_unit|v_sync</name>
+ </key_point>
+ <key_point id="133" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_18</name>
+ </key_point>
+ <key_point id="134" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_19</name>
+ </key_point>
+ <key_point id="135" type="register">
+ <name>dly_counter[0]</name>
+ </key_point>
+ <key_point id="136" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_16</name>
+ </key_point>
+ <key_point id="137" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_17</name>
+ </key_point>
+ <key_point id="138" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_0</name>
+ </key_point>
+ <key_point id="139" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_1</name>
+ </key_point>
+ <key_point id="140" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_2</name>
+ </key_point>
+ <key_point id="141" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_4</name>
+ </key_point>
+ <key_point id="142" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_3</name>
+ </key_point>
+ <key_point id="143" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_3</name>
+ </key_point>
+ <key_point id="144" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_state_2</name>
+ </key_point>
+ <key_point id="145" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_4</name>
+ </key_point>
+ <key_point id="146" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_6</name>
+ </key_point>
+ <key_point id="147" type="register">
+ <name>vga_driver:vga_driver_unit|vsync_counter_5</name>
+ </key_point>
+ <key_point id="148" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_counter_5</name>
+ </key_point>
+ <key_point id="149" type="register">
+ <name>vga_control:vga_control_unit|toggle_counter_sig_20</name>
+ </key_point>
+ <key_point id="150" type="register">
+ <name>vga_driver:vga_driver_unit|hsync_state_3</name>
+ </key_point>
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+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="42" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="134" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="78" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="90" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="66" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="149" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="17" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="154" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="35" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="119" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="77" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="123" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="28" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="124" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="29" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="116" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="76" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="96" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="54" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="122" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="61" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="139" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="59" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="91" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="23" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="89" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="27" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="115" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="87" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="107" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="22" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="142" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="9" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="151" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="51" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="138" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="70" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="98" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="41" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="99" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="62" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="131" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="58" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="147" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="53" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="128" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ <transformation>
+ <kp_set type="reference">
+ <kp_state index="0">
+ <kp id="84" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ <kp_set type="transformed">
+ <kp_state index="0">
+ <kp id="140" type="proxy"></kp>
+ </kp_state>
+ </kp_set>
+ </transformation>
+ </transformations_set>
+</kpt_db>
--- /dev/null
+set tool_name "ModelSim (VHDL)"
+set corner_file_list {
+ {{"Slow Model"} {vga.vho vga_vhd.sdo}}
+}
--- /dev/null
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II"
+-- VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version"
+
+-- DATE "10/28/2009 14:19:55"
+
+--
+-- Device: Altera EP1S25F672C6 Package FBGA672
+--
+
+--
+-- This VHDL file should be used for ModelSim (VHDL) only
+--
+
+LIBRARY IEEE, stratix;
+USE IEEE.std_logic_1164.all;
+USE stratix.stratix_components.all;
+
+ENTITY vga IS
+ PORT (
+ clk_pin : IN std_logic;
+ reset_pin : IN std_logic;
+ r0_pin : OUT std_logic;
+ r1_pin : OUT std_logic;
+ r2_pin : OUT std_logic;
+ g0_pin : OUT std_logic;
+ g1_pin : OUT std_logic;
+ g2_pin : OUT std_logic;
+ b0_pin : OUT std_logic;
+ b1_pin : OUT std_logic;
+ hsync_pin : OUT std_logic;
+ vsync_pin : OUT std_logic;
+ seven_seg_pin : OUT std_logic_vector(13 DOWNTO 0);
+ d_hsync : OUT std_logic;
+ d_vsync : OUT std_logic;
+ d_column_counter : OUT std_logic_vector(9 DOWNTO 0);
+ d_line_counter : OUT std_logic_vector(8 DOWNTO 0);
+ d_set_column_counter : OUT std_logic;
+ d_set_line_counter : OUT std_logic;
+ d_hsync_counter : OUT std_logic_vector(9 DOWNTO 0);
+ d_vsync_counter : OUT std_logic_vector(9 DOWNTO 0);
+ d_set_hsync_counter : OUT std_logic;
+ d_set_vsync_counter : OUT std_logic;
+ d_h_enable : OUT std_logic;
+ d_v_enable : OUT std_logic;
+ d_r : OUT std_logic;
+ d_g : OUT std_logic;
+ d_b : OUT std_logic;
+ d_hsync_state : OUT std_logic_vector(0 TO 6);
+ d_vsync_state : OUT std_logic_vector(0 TO 6);
+ d_state_clk : OUT std_logic;
+ d_toggle : OUT std_logic;
+ d_toggle_counter : OUT std_logic_vector(24 DOWNTO 0)
+ );
+END vga;
+
+ARCHITECTURE structure OF vga IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_clk_pin : std_logic;
+SIGNAL ww_reset_pin : std_logic;
+SIGNAL ww_r0_pin : std_logic;
+SIGNAL ww_r1_pin : std_logic;
+SIGNAL ww_r2_pin : std_logic;
+SIGNAL ww_g0_pin : std_logic;
+SIGNAL ww_g1_pin : std_logic;
+SIGNAL ww_g2_pin : std_logic;
+SIGNAL ww_b0_pin : std_logic;
+SIGNAL ww_b1_pin : std_logic;
+SIGNAL ww_hsync_pin : std_logic;
+SIGNAL ww_vsync_pin : std_logic;
+SIGNAL ww_seven_seg_pin : std_logic_vector(13 DOWNTO 0);
+SIGNAL ww_d_hsync : std_logic;
+SIGNAL ww_d_vsync : std_logic;
+SIGNAL ww_d_column_counter : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_d_line_counter : std_logic_vector(8 DOWNTO 0);
+SIGNAL ww_d_set_column_counter : std_logic;
+SIGNAL ww_d_set_line_counter : std_logic;
+SIGNAL ww_d_hsync_counter : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_d_vsync_counter : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_d_set_hsync_counter : std_logic;
+SIGNAL ww_d_set_vsync_counter : std_logic;
+SIGNAL ww_d_h_enable : std_logic;
+SIGNAL ww_d_v_enable : std_logic;
+SIGNAL ww_d_r : std_logic;
+SIGNAL ww_d_g : std_logic;
+SIGNAL ww_d_b : std_logic;
+SIGNAL ww_d_hsync_state : std_logic_vector(0 TO 6);
+SIGNAL ww_d_vsync_state : std_logic_vector(0 TO 6);
+SIGNAL ww_d_state_clk : std_logic;
+SIGNAL ww_d_toggle : std_logic;
+SIGNAL ww_d_toggle_counter : std_logic_vector(24 DOWNTO 0);
+SIGNAL \vga_control_unit|un2_toggle_counter_next_0_~COMBOUT\ : std_logic;
+SIGNAL \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\ : std_logic;
+SIGNAL \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\ : std_logic;
+SIGNAL \clk_pin~combout\ : std_logic;
+SIGNAL \reset_pin~combout\ : std_logic;
+SIGNAL \vga_driver_unit|un6_dly_counter_0_x\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_6\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_0\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_2\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_3\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_4\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_5\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_6\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_8\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_9\ : std_logic;
+SIGNAL \vga_driver_unit|un9_hsync_counterlt9_3\ : std_logic;
+SIGNAL \vga_driver_unit|un13_hsync_counter_7\ : std_logic;
+SIGNAL \vga_driver_unit|un9_hsync_counterlt9\ : std_logic;
+SIGNAL \vga_driver_unit|G_2_i\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_7\ : std_logic;
+SIGNAL \vga_driver_unit|un13_hsync_counter_2\ : std_logic;
+SIGNAL \vga_driver_unit|un13_hsync_counter\ : std_logic;
+SIGNAL \vga_driver_unit|un11_hsync_counter_3\ : std_logic;
+SIGNAL \vga_driver_unit|un11_hsync_counter_2\ : std_logic;
+SIGNAL \vga_driver_unit|un10_hsync_counter_1\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_5\ : std_logic;
+SIGNAL \vga_driver_unit|un10_hsync_counter_4\ : std_logic;
+SIGNAL \vga_driver_unit|un10_hsync_counter_3\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_4\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_1\ : std_logic;
+SIGNAL \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_0\ : std_logic;
+SIGNAL \vga_driver_unit|d_set_hsync_counter\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_next_1_sqmuxa\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_counter_1\ : std_logic;
+SIGNAL \vga_driver_unit|un12_hsync_counter_4\ : std_logic;
+SIGNAL \vga_driver_unit|un12_hsync_counter_3\ : std_logic;
+SIGNAL \vga_driver_unit|un12_hsync_counter\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_2\ : std_logic;
+SIGNAL \vga_driver_unit|hsync_state_3\ : std_logic;
+SIGNAL \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ : std_logic;
+SIGNAL \vga_driver_unit|v_enable_sig\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_0\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_1\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_3\ : std_logic;
+SIGNAL \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_2\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_4\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_5\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_7\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_6\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_8\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_9\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_11\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_10\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_13\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_12\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_15\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_14\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_16\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_17\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_19\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_18\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_20\ : std_logic;
+SIGNAL \vga_control_unit|un1_toggle_counter_siglt6\ : std_logic;
+SIGNAL \vga_control_unit|un1_toggle_counter_siglto9\ : std_logic;
+SIGNAL \vga_control_unit|un1_toggle_counter_siglto12\ : std_logic;
+SIGNAL \vga_control_unit|un1_toggle_counter_siglto15\ : std_logic;
+SIGNAL \vga_control_unit|un1_toggle_counter_siglto18\ : std_logic;
+SIGNAL \vga_control_unit|toggle_sig_0_0_0_g1\ : std_logic;
+SIGNAL \vga_control_unit|toggle_sig\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_6\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_2\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_3\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_4\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_5\ : std_logic;
+SIGNAL \vga_driver_unit|un9_vsync_counterlt9_6\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_6\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_7\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_8\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_9\ : std_logic;
+SIGNAL \vga_driver_unit|un9_vsync_counterlt9_5\ : std_logic;
+SIGNAL \vga_driver_unit|un9_vsync_counterlt9\ : std_logic;
+SIGNAL \vga_driver_unit|G_16_i\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_0\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_5\ : std_logic;
+SIGNAL \vga_driver_unit|un12_vsync_counter_6\ : std_logic;
+SIGNAL \vga_driver_unit|un14_vsync_counter_8\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_3\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_2\ : std_logic;
+SIGNAL \vga_driver_unit|un15_vsync_counter_3\ : std_logic;
+SIGNAL \vga_driver_unit|un15_vsync_counter_4\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_4\ : std_logic;
+SIGNAL \vga_driver_unit|un13_vsync_counter_3\ : std_logic;
+SIGNAL \vga_driver_unit|un13_vsync_counter_4\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ : std_logic;
+SIGNAL \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_next_2_sqmuxa\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_0\ : std_logic;
+SIGNAL \vga_driver_unit|d_set_vsync_counter\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_next_1_sqmuxa\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_counter_1\ : std_logic;
+SIGNAL \vga_driver_unit|un12_vsync_counter_7\ : std_logic;
+SIGNAL \vga_driver_unit|vsync_state_1\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_sig_0\ : std_logic;
+SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_sig_1\ : std_logic;
+SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_sig_2\ : std_logic;
+SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_sig_3\ : std_logic;
+SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_sig_4\ : std_logic;
+SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_sig_5\ : std_logic;
+SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_sig_6\ : std_logic;
+SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_sig_7\ : std_logic;
+SIGNAL \vga_driver_unit|un10_line_counter_siglt4_2\ : std_logic;
+SIGNAL \vga_driver_unit|un10_line_counter_siglto5\ : std_logic;
+SIGNAL \vga_driver_unit|un10_line_counter_siglto8\ : std_logic;
+SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ : std_logic;
+SIGNAL \vga_driver_unit|line_counter_sig_8\ : std_logic;
+SIGNAL \vga_control_unit|un17_v_enablelto3\ : std_logic;
+SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_4_a\ : std_logic;
+SIGNAL \vga_control_unit|un13_v_enablelto4_0\ : std_logic;
+SIGNAL \vga_control_unit|un13_v_enablelto6\ : std_logic;
+SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_4\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_0\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_1\ : std_logic;
+SIGNAL \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_3\ : std_logic;
+SIGNAL \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_2\ : std_logic;
+SIGNAL \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_5\ : std_logic;
+SIGNAL \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_4\ : std_logic;
+SIGNAL \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ : std_logic;
+SIGNAL \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_8\ : std_logic;
+SIGNAL \vga_driver_unit|un10_column_counter_siglt6_4\ : std_logic;
+SIGNAL \vga_driver_unit|un10_column_counter_siglt6\ : std_logic;
+SIGNAL \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ : std_logic;
+SIGNAL \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_9\ : std_logic;
+SIGNAL \vga_driver_unit|un10_column_counter_siglto9\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_7\ : std_logic;
+SIGNAL \vga_driver_unit|column_counter_sig_6\ : std_logic;
+SIGNAL \vga_control_unit|un5_v_enablelt2\ : std_logic;
+SIGNAL \vga_control_unit|un5_v_enablelto5\ : std_logic;
+SIGNAL \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ : std_logic;
+SIGNAL \vga_driver_unit|h_enable_sig\ : std_logic;
+SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_2\ : std_logic;
+SIGNAL \vga_control_unit|un9_v_enablelto4\ : std_logic;
+SIGNAL \vga_control_unit|un9_v_enablelto6\ : std_logic;
+SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_3\ : std_logic;
+SIGNAL \vga_control_unit|b_next_0_sqmuxa_7_5\ : std_logic;
+SIGNAL \vga_control_unit|r\ : std_logic;
+SIGNAL \~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic;
+SIGNAL \vga_control_unit|b\ : std_logic;
+SIGNAL \vga_driver_unit|un1_hsync_state_3_0\ : std_logic;
+SIGNAL \vga_driver_unit|h_sync_1_0_0_0_g1\ : std_logic;
+SIGNAL \vga_driver_unit|h_sync\ : std_logic;
+SIGNAL \vga_driver_unit|un1_vsync_state_2_0\ : std_logic;
+SIGNAL \vga_driver_unit|v_sync_1_0_0_0_g1\ : std_logic;
+SIGNAL \vga_driver_unit|v_sync\ : std_logic;
+SIGNAL \vga_control_unit|toggle_counter_sig_cout\ : std_logic_vector(18 DOWNTO 1);
+SIGNAL \vga_control_unit|un2_toggle_counter_next_cout\ : std_logic_vector(0 DOWNTO 0);
+SIGNAL \vga_driver_unit|hsync_counter_cout\ : std_logic_vector(8 DOWNTO 0);
+SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout\ : std_logic_vector(1 DOWNTO 1);
+SIGNAL \vga_driver_unit|un1_line_counter_sig_combout\ : std_logic_vector(9 DOWNTO 1);
+SIGNAL \vga_driver_unit|un1_line_counter_sig_cout\ : std_logic_vector(7 DOWNTO 1);
+SIGNAL \vga_driver_unit|un2_column_counter_next_combout\ : std_logic_vector(9 DOWNTO 1);
+SIGNAL \vga_driver_unit|un2_column_counter_next_cout\ : std_logic_vector(7 DOWNTO 0);
+SIGNAL \vga_driver_unit|vsync_counter_cout\ : std_logic_vector(8 DOWNTO 0);
+SIGNAL dly_counter : std_logic_vector(1 DOWNTO 0);
+SIGNAL \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ : std_logic;
+SIGNAL \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ : std_logic;
+SIGNAL \vga_driver_unit|ALT_INV_G_2_i\ : std_logic;
+SIGNAL \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ : std_logic;
+SIGNAL \vga_driver_unit|ALT_INV_G_16_i\ : std_logic;
+SIGNAL \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ : std_logic;
+SIGNAL \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\ : std_logic;
+SIGNAL \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic;
+
+BEGIN
+
+ww_clk_pin <= clk_pin;
+ww_reset_pin <= reset_pin;
+r0_pin <= ww_r0_pin;
+r1_pin <= ww_r1_pin;
+r2_pin <= ww_r2_pin;
+g0_pin <= ww_g0_pin;
+g1_pin <= ww_g1_pin;
+g2_pin <= ww_g2_pin;
+b0_pin <= ww_b0_pin;
+b1_pin <= ww_b1_pin;
+hsync_pin <= ww_hsync_pin;
+vsync_pin <= ww_vsync_pin;
+seven_seg_pin <= ww_seven_seg_pin;
+d_hsync <= ww_d_hsync;
+d_vsync <= ww_d_vsync;
+d_column_counter <= ww_d_column_counter;
+d_line_counter <= ww_d_line_counter;
+d_set_column_counter <= ww_d_set_column_counter;
+d_set_line_counter <= ww_d_set_line_counter;
+d_hsync_counter <= ww_d_hsync_counter;
+d_vsync_counter <= ww_d_vsync_counter;
+d_set_hsync_counter <= ww_d_set_hsync_counter;
+d_set_vsync_counter <= ww_d_set_vsync_counter;
+d_h_enable <= ww_d_h_enable;
+d_v_enable <= ww_d_v_enable;
+d_r <= ww_d_r;
+d_g <= ww_d_g;
+d_b <= ww_d_b;
+d_hsync_state <= ww_d_hsync_state;
+d_vsync_state <= ww_d_vsync_state;
+d_state_clk <= ww_d_state_clk;
+d_toggle <= ww_d_toggle;
+d_toggle_counter <= ww_d_toggle_counter;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+\vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\;
+\vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\;
+\vga_driver_unit|ALT_INV_G_2_i\ <= NOT \vga_driver_unit|G_2_i\;
+\vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ <= NOT \vga_driver_unit|un9_hsync_counterlt9\;
+\vga_driver_unit|ALT_INV_G_16_i\ <= NOT \vga_driver_unit|G_16_i\;
+\vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ <= NOT \vga_driver_unit|un9_vsync_counterlt9\;
+\vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\ <= NOT \vga_control_unit|toggle_sig_0_0_0_g1\;
+\ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ <= NOT \~STRATIX_FITTER_CREATED_GND~I_combout\;
+
+clk_pin_in : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "input",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => GND,
+ padio => ww_clk_pin,
+ combout => \clk_pin~combout\);
+
+reset_pin_in : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "input",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => GND,
+ padio => ww_reset_pin,
+ combout => \reset_pin~combout\);
+
+\dly_counter_0_\ : stratix_lcell
+-- Equation(s):
+-- dly_counter(0) = DFFEAS(\reset_pin~combout\ & (dly_counter(1) # !dly_counter(0)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "a0f0",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => dly_counter(1),
+ datac => \reset_pin~combout\,
+ datad => dly_counter(0),
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => dly_counter(0));
+
+\dly_counter_1_\ : stratix_lcell
+-- Equation(s):
+-- dly_counter(1) = DFFEAS(\reset_pin~combout\ & (dly_counter(0) # dly_counter(1)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "e0e0",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => dly_counter(0),
+ datab => dly_counter(1),
+ datac => \reset_pin~combout\,
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => dly_counter(1));
+
+\vga_driver_unit|vsync_state_6_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un6_dly_counter_0_x\ = !dly_counter(0) # !\reset_pin~combout\ # !dly_counter(1)
+-- \vga_driver_unit|vsync_state_6\ = DFFEAS(\vga_driver_unit|un6_dly_counter_0_x\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "3fff",
+ operation_mode => "normal",
+ output_mode => "reg_and_comb",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => dly_counter(1),
+ datac => \reset_pin~combout\,
+ datad => dly_counter(0),
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un6_dly_counter_0_x\,
+ regout => \vga_driver_unit|vsync_state_6\);
+
+\vga_driver_unit|hsync_state_6_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|d_set_hsync_counter\ = C1_hsync_state_6 # \vga_driver_unit|hsync_state_0\
+-- \vga_driver_unit|hsync_state_6\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|un6_dly_counter_0_x\, , , VCC)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "fff0",
+ operation_mode => "normal",
+ output_mode => "reg_and_comb",
+ register_cascade_mode => "off",
+ sum_lutc_input => "qfbk",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|un6_dly_counter_0_x\,
+ datad => \vga_driver_unit|hsync_state_0\,
+ aclr => GND,
+ sload => VCC,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|d_set_hsync_counter\,
+ regout => \vga_driver_unit|hsync_state_6\);
+
+\vga_driver_unit|hsync_counter_0_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_0\ = DFFEAS(!\vga_driver_unit|hsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
+-- \vga_driver_unit|hsync_counter_cout\(0) = CARRY(\vga_driver_unit|hsync_counter_0\)
+-- \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|hsync_counter_0\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "33cc",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|hsync_counter_0\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_0\,
+ cout0 => \vga_driver_unit|hsync_counter_cout\(0),
+ cout1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\);
+
+\vga_driver_unit|hsync_counter_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_1\ = DFFEAS(\vga_driver_unit|hsync_counter_1\ $ \vga_driver_unit|hsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
+-- !\vga_driver_unit|un9_hsync_counterlt9\)
+-- \vga_driver_unit|hsync_counter_cout\(1) = CARRY(!\vga_driver_unit|hsync_counter_cout\(0) # !\vga_driver_unit|hsync_counter_1\)
+-- \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|hsync_counter_1\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "3c3f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|hsync_counter_1\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ cin0 => \vga_driver_unit|hsync_counter_cout\(0),
+ cin1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_1\,
+ cout0 => \vga_driver_unit|hsync_counter_cout\(1),
+ cout1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\);
+
+\vga_driver_unit|hsync_counter_2_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_2\ = DFFEAS(\vga_driver_unit|hsync_counter_2\ $ (!\vga_driver_unit|hsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
+-- !\vga_driver_unit|un9_hsync_counterlt9\)
+-- \vga_driver_unit|hsync_counter_cout\(2) = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout\(1)))
+-- \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout[1]~COUT1_12\))
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "a50a",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|hsync_counter_2\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ cin0 => \vga_driver_unit|hsync_counter_cout\(1),
+ cin1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_2\,
+ cout0 => \vga_driver_unit|hsync_counter_cout\(2),
+ cout1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\);
+
+\vga_driver_unit|hsync_counter_3_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_3\ = DFFEAS(\vga_driver_unit|hsync_counter_3\ $ (\vga_driver_unit|hsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
+-- !\vga_driver_unit|un9_hsync_counterlt9\)
+-- \vga_driver_unit|hsync_counter_cout\(3) = CARRY(!\vga_driver_unit|hsync_counter_cout\(2) # !\vga_driver_unit|hsync_counter_3\)
+-- \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|hsync_counter_3\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "5a5f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|hsync_counter_3\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ cin0 => \vga_driver_unit|hsync_counter_cout\(2),
+ cin1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_3\,
+ cout0 => \vga_driver_unit|hsync_counter_cout\(3),
+ cout1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\);
+
+\vga_driver_unit|hsync_counter_4_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_4\ = DFFEAS(\vga_driver_unit|hsync_counter_4\ $ (!\vga_driver_unit|hsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
+-- !\vga_driver_unit|un9_hsync_counterlt9\)
+-- \vga_driver_unit|hsync_counter_cout\(4) = CARRY(\vga_driver_unit|hsync_counter_4\ & (!\vga_driver_unit|hsync_counter_cout[3]~COUT1_16\))
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "a50a",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|hsync_counter_4\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ cin0 => \vga_driver_unit|hsync_counter_cout\(3),
+ cin1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_4\,
+ cout => \vga_driver_unit|hsync_counter_cout\(4));
+
+\vga_driver_unit|hsync_counter_5_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_5\ = DFFEAS(\vga_driver_unit|hsync_counter_5\ $ \vga_driver_unit|hsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
+-- !\vga_driver_unit|un9_hsync_counterlt9\)
+-- \vga_driver_unit|hsync_counter_cout\(5) = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\)
+-- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin_used => "true",
+ lut_mask => "3c3f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|hsync_counter_5\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ cin => \vga_driver_unit|hsync_counter_cout\(4),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_5\,
+ cout0 => \vga_driver_unit|hsync_counter_cout\(5),
+ cout1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\);
+
+\vga_driver_unit|hsync_counter_6_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_6\ = DFFEAS(\vga_driver_unit|hsync_counter_6\ $ !(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(5)) # (\vga_driver_unit|hsync_counter_cout\(4) &
+-- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
+-- \vga_driver_unit|hsync_counter_cout\(6) = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout\(5))
+-- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout[5]~COUT1_18\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "c30c",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|hsync_counter_6\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ cin => \vga_driver_unit|hsync_counter_cout\(4),
+ cin0 => \vga_driver_unit|hsync_counter_cout\(5),
+ cin1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_6\,
+ cout0 => \vga_driver_unit|hsync_counter_cout\(6),
+ cout1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\);
+
+\vga_driver_unit|hsync_counter_7_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_7\ = DFFEAS(\vga_driver_unit|hsync_counter_7\ $ ((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(6)) # (\vga_driver_unit|hsync_counter_cout\(4) &
+-- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
+-- \vga_driver_unit|hsync_counter_cout\(7) = CARRY(!\vga_driver_unit|hsync_counter_cout\(6) # !\vga_driver_unit|hsync_counter_7\)
+-- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|hsync_counter_7\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "5a5f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|hsync_counter_7\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ cin => \vga_driver_unit|hsync_counter_cout\(4),
+ cin0 => \vga_driver_unit|hsync_counter_cout\(6),
+ cin1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_7\,
+ cout0 => \vga_driver_unit|hsync_counter_cout\(7),
+ cout1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\);
+
+\vga_driver_unit|hsync_counter_8_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_8\ = DFFEAS(\vga_driver_unit|hsync_counter_8\ $ (!(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(7)) # (\vga_driver_unit|hsync_counter_cout\(4) &
+-- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
+-- \vga_driver_unit|hsync_counter_cout\(8) = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout\(7)))
+-- \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout[7]~COUT1_22\))
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "a50a",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|hsync_counter_8\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ cin => \vga_driver_unit|hsync_counter_cout\(4),
+ cin0 => \vga_driver_unit|hsync_counter_cout\(7),
+ cin1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_8\,
+ cout0 => \vga_driver_unit|hsync_counter_cout\(8),
+ cout1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\);
+
+\vga_driver_unit|hsync_counter_9_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_9\ = DFFEAS((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(8)) # (\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\) $
+-- \vga_driver_unit|hsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "0ff0",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
+ datad => \vga_driver_unit|hsync_counter_9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_2_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
+ cin => \vga_driver_unit|hsync_counter_cout\(4),
+ cin0 => \vga_driver_unit|hsync_counter_cout\(8),
+ cin1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_counter_9\);
+
+\vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un9_hsync_counterlt9_3\ = !\vga_driver_unit|hsync_counter_5\ # !\vga_driver_unit|hsync_counter_7\ # !\vga_driver_unit|hsync_counter_6\ # !\vga_driver_unit|hsync_counter_4\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "7fff",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_4\,
+ datab => \vga_driver_unit|hsync_counter_6\,
+ datac => \vga_driver_unit|hsync_counter_7\,
+ datad => \vga_driver_unit|hsync_counter_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un9_hsync_counterlt9_3\);
+
+\vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un13_hsync_counter_7\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_2\ & \vga_driver_unit|hsync_counter_0\ & \vga_driver_unit|hsync_counter_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "8000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_1\,
+ datab => \vga_driver_unit|hsync_counter_2\,
+ datac => \vga_driver_unit|hsync_counter_0\,
+ datad => \vga_driver_unit|hsync_counter_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un13_hsync_counter_7\);
+
+\vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un9_hsync_counterlt9\ = \vga_driver_unit|un9_hsync_counterlt9_3\ # !\vga_driver_unit|un13_hsync_counter_7\ # !\vga_driver_unit|hsync_counter_9\ # !\vga_driver_unit|hsync_counter_8\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "f7ff",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_8\,
+ datab => \vga_driver_unit|hsync_counter_9\,
+ datac => \vga_driver_unit|un9_hsync_counterlt9_3\,
+ datad => \vga_driver_unit|un13_hsync_counter_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un9_hsync_counterlt9\);
+
+\vga_driver_unit|G_2\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|G_2_i\ = !\vga_driver_unit|hsync_state_0\ & !\vga_driver_unit|hsync_state_6\ & !\vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un9_hsync_counterlt9\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0f1f",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_state_0\,
+ datab => \vga_driver_unit|hsync_state_6\,
+ datac => \vga_driver_unit|un9_hsync_counterlt9\,
+ datad => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|G_2_i\);
+
+\vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un13_hsync_counter_2\ = \vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_9\ & \vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_5\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0080",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_4\,
+ datab => \vga_driver_unit|hsync_counter_9\,
+ datac => \vga_driver_unit|hsync_counter_8\,
+ datad => \vga_driver_unit|hsync_counter_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un13_hsync_counter_2\);
+
+\vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un13_hsync_counter\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|un13_hsync_counter_2\ & \vga_driver_unit|un13_hsync_counter_7\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_7\,
+ datab => \vga_driver_unit|hsync_counter_6\,
+ datac => \vga_driver_unit|un13_hsync_counter_2\,
+ datad => \vga_driver_unit|un13_hsync_counter_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un13_hsync_counter\);
+
+\vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un11_hsync_counter_3\ = \vga_driver_unit|hsync_counter_1\ & !\vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_0\ & !\vga_driver_unit|hsync_counter_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0020",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_1\,
+ datab => \vga_driver_unit|hsync_counter_4\,
+ datac => \vga_driver_unit|hsync_counter_0\,
+ datad => \vga_driver_unit|hsync_counter_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un11_hsync_counter_3\);
+
+\vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un11_hsync_counter_2\ = !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_7\ & \vga_driver_unit|hsync_counter_2\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "3000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|hsync_counter_6\,
+ datac => \vga_driver_unit|hsync_counter_7\,
+ datad => \vga_driver_unit|hsync_counter_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un11_hsync_counter_2\);
+
+\vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un10_hsync_counter_1\ = !\vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_5\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0003",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|hsync_counter_8\,
+ datac => \vga_driver_unit|hsync_counter_9\,
+ datad => \vga_driver_unit|hsync_counter_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un10_hsync_counter_1\);
+
+\vga_driver_unit|hsync_state_5_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_state_5\ = DFFEAS(\vga_driver_unit|hsync_state_0\ # \vga_driver_unit|hsync_state_6\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "fafa",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|hsync_state_0\,
+ datac => \vga_driver_unit|hsync_state_6\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_state_5\);
+
+\vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un10_hsync_counter_4\ = \vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "8000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_4\,
+ datab => \vga_driver_unit|hsync_counter_6\,
+ datac => \vga_driver_unit|hsync_counter_1\,
+ datad => \vga_driver_unit|hsync_counter_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un10_hsync_counter_4\);
+
+\vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un10_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_0\ & !\vga_driver_unit|hsync_counter_2\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0003",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|hsync_counter_7\,
+ datac => \vga_driver_unit|hsync_counter_0\,
+ datad => \vga_driver_unit|hsync_counter_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un10_hsync_counter_3\);
+
+\vga_driver_unit|hsync_state_4_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_state_4\ = DFFEAS(\vga_driver_unit|hsync_state_5\ & \vga_driver_unit|un10_hsync_counter_4\ & \vga_driver_unit|un10_hsync_counter_1\ & \vga_driver_unit|un10_hsync_counter_3\, GLOBAL(\clk_pin~combout\), VCC, ,
+-- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "8000",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|hsync_state_5\,
+ datab => \vga_driver_unit|un10_hsync_counter_4\,
+ datac => \vga_driver_unit|un10_hsync_counter_1\,
+ datad => \vga_driver_unit|un10_hsync_counter_3\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_state_4\);
+
+\vga_driver_unit|hsync_state_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_state_1\ = DFFEAS(\vga_driver_unit|un11_hsync_counter_3\ & \vga_driver_unit|un11_hsync_counter_2\ & \vga_driver_unit|un10_hsync_counter_1\ & \vga_driver_unit|hsync_state_4\, GLOBAL(\clk_pin~combout\), VCC, ,
+-- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "8000",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|un11_hsync_counter_3\,
+ datab => \vga_driver_unit|un11_hsync_counter_2\,
+ datac => \vga_driver_unit|un10_hsync_counter_1\,
+ datad => \vga_driver_unit|hsync_state_4\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_state_1\);
+
+\vga_driver_unit|hsync_state_3_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|hsync_state_2\ & (!\vga_driver_unit|un12_hsync_counter\ & C1_hsync_state_3 # !\vga_driver_unit|un13_hsync_counter\) # !\vga_driver_unit|hsync_state_2\ &
+-- !\vga_driver_unit|un12_hsync_counter\ & C1_hsync_state_3
+-- \vga_driver_unit|hsync_state_3\ = DFFEAS(\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, \vga_driver_unit|hsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "30ba",
+ operation_mode => "normal",
+ output_mode => "reg_and_comb",
+ register_cascade_mode => "off",
+ sum_lutc_input => "qfbk",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|hsync_state_2\,
+ datab => \vga_driver_unit|un12_hsync_counter\,
+ datac => \vga_driver_unit|hsync_state_1\,
+ datad => \vga_driver_unit|un13_hsync_counter\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sload => VCC,
+ ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\,
+ regout => \vga_driver_unit|hsync_state_3\);
+
+\vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|hsync_state_5\ & (!\vga_driver_unit|un10_hsync_counter_1\ # !\vga_driver_unit|un10_hsync_counter_3\ # !\vga_driver_unit|un10_hsync_counter_4\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "2aaa",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_state_5\,
+ datab => \vga_driver_unit|un10_hsync_counter_4\,
+ datac => \vga_driver_unit|un10_hsync_counter_3\,
+ datad => \vga_driver_unit|un10_hsync_counter_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\);
+
+\vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|hsync_state_4\ & (!\vga_driver_unit|un10_hsync_counter_1\ # !\vga_driver_unit|un11_hsync_counter_3\ # !\vga_driver_unit|un11_hsync_counter_2\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "2aaa",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_state_4\,
+ datab => \vga_driver_unit|un11_hsync_counter_2\,
+ datac => \vga_driver_unit|un11_hsync_counter_3\,
+ datad => \vga_driver_unit|un10_hsync_counter_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\);
+
+\vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_2\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "aaab",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|un6_dly_counter_0_x\,
+ datab => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\,
+ datac => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\,
+ datad => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\);
+
+\vga_driver_unit|hsync_state_0_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_state_0\ = DFFEAS(\vga_driver_unit|un13_hsync_counter\ & \vga_driver_unit|hsync_state_2\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "c0c0",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|un13_hsync_counter\,
+ datac => \vga_driver_unit|hsync_state_2\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_state_0\);
+
+\vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_counter_next_1_sqmuxa\ = \reset_pin~combout\ & dly_counter(1) & dly_counter(0) & !\vga_driver_unit|d_set_hsync_counter\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0080",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \reset_pin~combout\,
+ datab => dly_counter(1),
+ datac => dly_counter(0),
+ datad => \vga_driver_unit|d_set_hsync_counter\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|hsync_counter_next_1_sqmuxa\);
+
+\vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un12_hsync_counter_4\ = !\vga_driver_unit|hsync_counter_7\ & \vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0004",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_7\,
+ datab => \vga_driver_unit|hsync_counter_9\,
+ datac => \vga_driver_unit|hsync_counter_6\,
+ datad => \vga_driver_unit|hsync_counter_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un12_hsync_counter_4\);
+
+\vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un12_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_2\ & \vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_5\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0040",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_4\,
+ datab => \vga_driver_unit|hsync_counter_2\,
+ datac => \vga_driver_unit|hsync_counter_8\,
+ datad => \vga_driver_unit|hsync_counter_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un12_hsync_counter_3\);
+
+\vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un12_hsync_counter\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_0\ & \vga_driver_unit|un12_hsync_counter_4\ & \vga_driver_unit|un12_hsync_counter_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "8000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_counter_1\,
+ datab => \vga_driver_unit|hsync_counter_0\,
+ datac => \vga_driver_unit|un12_hsync_counter_4\,
+ datad => \vga_driver_unit|un12_hsync_counter_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un12_hsync_counter\);
+
+\vga_driver_unit|hsync_state_2_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|hsync_state_2\ = DFFEAS(\vga_driver_unit|hsync_state_3\ & \vga_driver_unit|un12_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "c0c0",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|hsync_state_3\,
+ datac => \vga_driver_unit|un12_hsync_counter\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|hsync_state_2\);
+
+\vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|hsync_state_4\ & !\vga_driver_unit|hsync_state_5\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff03",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|hsync_state_4\,
+ datac => \vga_driver_unit|hsync_state_5\,
+ datad => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\);
+
+\vga_driver_unit|v_enable_sig_Z\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|v_enable_sig\ = DFFEAS(\vga_driver_unit|hsync_state_3\ # \vga_driver_unit|hsync_state_1\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "fcfc",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|hsync_state_3\,
+ datac => \vga_driver_unit|hsync_state_1\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|v_enable_sig\);
+
+\vga_control_unit|toggle_counter_sig_0_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_0\ = DFFEAS(!\vga_control_unit|toggle_counter_sig_0\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0f0f",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_control_unit|toggle_counter_sig_0\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_0\);
+
+\vga_control_unit|toggle_counter_sig_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_1\ = DFFEAS(\vga_control_unit|toggle_counter_sig_0\ $ \vga_control_unit|toggle_counter_sig_1\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\,
+-- )
+-- \vga_control_unit|toggle_counter_sig_cout\(1) = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
+-- \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\ = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "6688",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_0\,
+ datab => \vga_control_unit|toggle_counter_sig_1\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_1\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(1),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\);
+
+\vga_control_unit|toggle_counter_sig_3_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_3\ = DFFEAS(\vga_control_unit|toggle_counter_sig_3\ $ (\vga_control_unit|toggle_counter_sig_2\ & \vga_control_unit|toggle_counter_sig_cout\(1)), GLOBAL(\clk_pin~combout\),
+-- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(3) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(1) # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
+-- \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\ # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "6c7f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_2\,
+ datab => \vga_control_unit|toggle_counter_sig_3\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(1),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_3\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(3),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\);
+
+\vga_control_unit|un2_toggle_counter_next_0_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un2_toggle_counter_next_cout\(0) = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
+-- \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\ = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff88",
+ operation_mode => "arithmetic",
+ output_mode => "none",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_control_unit|toggle_counter_sig_0\,
+ datab => \vga_control_unit|toggle_counter_sig_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un2_toggle_counter_next_0_~COMBOUT\,
+ cout0 => \vga_control_unit|un2_toggle_counter_next_cout\(0),
+ cout1 => \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\);
+
+\vga_control_unit|toggle_counter_sig_2_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_2\ = DFFEAS(\vga_control_unit|toggle_counter_sig_2\ $ (\vga_control_unit|un2_toggle_counter_next_cout\(0)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
+-- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(2) = CARRY(!\vga_control_unit|un2_toggle_counter_next_cout\(0) # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
+-- \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\ = CARRY(!\vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\ # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "5a7f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_2\,
+ datab => \vga_control_unit|toggle_counter_sig_3\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin0 => \vga_control_unit|un2_toggle_counter_next_cout\(0),
+ cin1 => \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_2\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(2),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\);
+
+\vga_control_unit|toggle_counter_sig_4_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_4\ = DFFEAS(\vga_control_unit|toggle_counter_sig_4\ $ (!\vga_control_unit|toggle_counter_sig_cout\(2)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
+-- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(4) = CARRY(\vga_control_unit|toggle_counter_sig_4\ & \vga_control_unit|toggle_counter_sig_5\ & !\vga_control_unit|toggle_counter_sig_cout\(2))
+-- \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\ = CARRY(\vga_control_unit|toggle_counter_sig_4\ & \vga_control_unit|toggle_counter_sig_5\ & !\vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "a508",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_4\,
+ datab => \vga_control_unit|toggle_counter_sig_5\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(2),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_4\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(4),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\);
+
+\vga_control_unit|toggle_counter_sig_5_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_5\ = DFFEAS(\vga_control_unit|toggle_counter_sig_5\ $ (\vga_control_unit|toggle_counter_sig_4\ & !\vga_control_unit|toggle_counter_sig_cout\(3)), GLOBAL(\clk_pin~combout\),
+-- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(5) = CARRY(\vga_control_unit|toggle_counter_sig_5\ & \vga_control_unit|toggle_counter_sig_4\ & !\vga_control_unit|toggle_counter_sig_cout\(3))
+-- \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\ = CARRY(\vga_control_unit|toggle_counter_sig_5\ & \vga_control_unit|toggle_counter_sig_4\ & !\vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "a608",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_5\,
+ datab => \vga_control_unit|toggle_counter_sig_4\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(3),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_5\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(5),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\);
+
+\vga_control_unit|toggle_counter_sig_7_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_7\ = DFFEAS(\vga_control_unit|toggle_counter_sig_7\ $ (\vga_control_unit|toggle_counter_sig_6\ & \vga_control_unit|toggle_counter_sig_cout\(5)), GLOBAL(\clk_pin~combout\),
+-- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(7) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(5) # !\vga_control_unit|toggle_counter_sig_6\ # !\vga_control_unit|toggle_counter_sig_7\)
+-- \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\ # !\vga_control_unit|toggle_counter_sig_6\ # !\vga_control_unit|toggle_counter_sig_7\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "6a7f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_7\,
+ datab => \vga_control_unit|toggle_counter_sig_6\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(5),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_7\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(7),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\);
+
+\vga_control_unit|toggle_counter_sig_6_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_6\ = DFFEAS(\vga_control_unit|toggle_counter_sig_6\ $ (\vga_control_unit|toggle_counter_sig_cout\(4)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
+-- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(6) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(4) # !\vga_control_unit|toggle_counter_sig_7\ # !\vga_control_unit|toggle_counter_sig_6\)
+-- \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\ # !\vga_control_unit|toggle_counter_sig_7\ # !\vga_control_unit|toggle_counter_sig_6\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "5a7f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_6\,
+ datab => \vga_control_unit|toggle_counter_sig_7\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(4),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_6\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(6),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\);
+
+\vga_control_unit|toggle_counter_sig_8_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_8\ = DFFEAS(\vga_control_unit|toggle_counter_sig_8\ $ !\vga_control_unit|toggle_counter_sig_cout\(6), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
+-- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(8) = CARRY(\vga_control_unit|toggle_counter_sig_9\ & \vga_control_unit|toggle_counter_sig_8\ & !\vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "c308",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_9\,
+ datab => \vga_control_unit|toggle_counter_sig_8\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(6),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_8\,
+ cout => \vga_control_unit|toggle_counter_sig_cout\(8));
+
+\vga_control_unit|toggle_counter_sig_9_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_9\ = DFFEAS(\vga_control_unit|toggle_counter_sig_9\ $ (\vga_control_unit|toggle_counter_sig_8\ & !\vga_control_unit|toggle_counter_sig_cout\(7)), GLOBAL(\clk_pin~combout\),
+-- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(9) = CARRY(\vga_control_unit|toggle_counter_sig_9\ & \vga_control_unit|toggle_counter_sig_8\ & !\vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "a608",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_9\,
+ datab => \vga_control_unit|toggle_counter_sig_8\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(7),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_9\,
+ cout => \vga_control_unit|toggle_counter_sig_cout\(9));
+
+\vga_control_unit|toggle_counter_sig_11_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_11\ = DFFEAS(\vga_control_unit|toggle_counter_sig_11\ $ (\vga_control_unit|toggle_counter_sig_10\ & \vga_control_unit|toggle_counter_sig_cout\(9)), GLOBAL(\clk_pin~combout\),
+-- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(11) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(9) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
+-- \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(9) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin_used => "true",
+ lut_mask => "6c7f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_10\,
+ datab => \vga_control_unit|toggle_counter_sig_11\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(9),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_11\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(11),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\);
+
+\vga_control_unit|toggle_counter_sig_10_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_10\ = DFFEAS(\vga_control_unit|toggle_counter_sig_10\ $ (\vga_control_unit|toggle_counter_sig_cout\(8)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
+-- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(10) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(8) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
+-- \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(8) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin_used => "true",
+ lut_mask => "5a7f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_10\,
+ datab => \vga_control_unit|toggle_counter_sig_11\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(8),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_10\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(10),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\);
+
+\vga_control_unit|toggle_counter_sig_13_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_13\ = DFFEAS(\vga_control_unit|toggle_counter_sig_13\ $ (\vga_control_unit|toggle_counter_sig_12\ & !(!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(11)) #
+-- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(13) = CARRY(\vga_control_unit|toggle_counter_sig_12\ & \vga_control_unit|toggle_counter_sig_13\ & !\vga_control_unit|toggle_counter_sig_cout\(11))
+-- \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\ = CARRY(\vga_control_unit|toggle_counter_sig_12\ & \vga_control_unit|toggle_counter_sig_13\ & !\vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "c608",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_12\,
+ datab => \vga_control_unit|toggle_counter_sig_13\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(9),
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(11),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_13\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(13),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\);
+
+\vga_control_unit|toggle_counter_sig_12_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_12\ = DFFEAS(\vga_control_unit|toggle_counter_sig_12\ $ !(!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(10)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
+-- \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(12) = CARRY(\vga_control_unit|toggle_counter_sig_13\ & \vga_control_unit|toggle_counter_sig_12\ & !\vga_control_unit|toggle_counter_sig_cout\(10))
+-- \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\ = CARRY(\vga_control_unit|toggle_counter_sig_13\ & \vga_control_unit|toggle_counter_sig_12\ & !\vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "c308",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_13\,
+ datab => \vga_control_unit|toggle_counter_sig_12\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(8),
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(10),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_12\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(12),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\);
+
+\vga_control_unit|toggle_counter_sig_15_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_15\ = DFFEAS(\vga_control_unit|toggle_counter_sig_15\ $ (\vga_control_unit|toggle_counter_sig_14\ & (!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(13)) #
+-- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(15) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(13) # !\vga_control_unit|toggle_counter_sig_14\ # !\vga_control_unit|toggle_counter_sig_15\)
+-- \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\ # !\vga_control_unit|toggle_counter_sig_14\ # !\vga_control_unit|toggle_counter_sig_15\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "6a7f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_15\,
+ datab => \vga_control_unit|toggle_counter_sig_14\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(9),
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(13),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_15\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(15),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\);
+
+\vga_control_unit|toggle_counter_sig_14_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_14\ = DFFEAS(\vga_control_unit|toggle_counter_sig_14\ $ ((!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(12)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
+-- \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(14) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(12) # !\vga_control_unit|toggle_counter_sig_15\ # !\vga_control_unit|toggle_counter_sig_14\)
+-- \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\ # !\vga_control_unit|toggle_counter_sig_15\ # !\vga_control_unit|toggle_counter_sig_14\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "5a7f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_14\,
+ datab => \vga_control_unit|toggle_counter_sig_15\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(8),
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(12),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_14\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(14),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\);
+
+\vga_control_unit|toggle_counter_sig_16_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_16\ = DFFEAS(\vga_control_unit|toggle_counter_sig_16\ $ !(!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(14)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
+-- \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(16) = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout\(14))
+-- \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\ = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "c308",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_17\,
+ datab => \vga_control_unit|toggle_counter_sig_16\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(8),
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(14),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_16\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(16),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\);
+
+\vga_control_unit|toggle_counter_sig_17_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_17\ = DFFEAS(\vga_control_unit|toggle_counter_sig_17\ $ (\vga_control_unit|toggle_counter_sig_16\ & !(!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(15)) #
+-- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(17) = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout\(15))
+-- \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\ = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "a608",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_17\,
+ datab => \vga_control_unit|toggle_counter_sig_16\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(9),
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(15),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_17\,
+ cout0 => \vga_control_unit|toggle_counter_sig_cout\(17),
+ cout1 => \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\);
+
+\vga_control_unit|toggle_counter_sig_19_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_19\ = DFFEAS(\vga_control_unit|toggle_counter_sig_19\ $ (\vga_control_unit|toggle_counter_sig_18\ & (!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(17)) #
+-- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "3fc0",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_control_unit|toggle_counter_sig_18\,
+ datad => \vga_control_unit|toggle_counter_sig_19\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(9),
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(17),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_19\);
+
+\vga_control_unit|toggle_counter_sig_18_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_18\ = DFFEAS(\vga_control_unit|toggle_counter_sig_18\ $ ((!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(16)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
+-- \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+-- \vga_control_unit|toggle_counter_sig_cout\(18) = CARRY(!\vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\ # !\vga_control_unit|toggle_counter_sig_19\ # !\vga_control_unit|toggle_counter_sig_18\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "5a7f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_control_unit|toggle_counter_sig_18\,
+ datab => \vga_control_unit|toggle_counter_sig_19\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(8),
+ cin0 => \vga_control_unit|toggle_counter_sig_cout\(16),
+ cin1 => \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_18\,
+ cout => \vga_control_unit|toggle_counter_sig_cout\(18));
+
+\vga_control_unit|toggle_counter_sig_20_\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_counter_sig_20\ = DFFEAS(\vga_control_unit|toggle_counter_sig_20\ $ !\vga_control_unit|toggle_counter_sig_cout\(18), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
+-- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ cin_used => "true",
+ lut_mask => "c3c3",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_control_unit|toggle_counter_sig_20\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
+ cin => \vga_control_unit|toggle_counter_sig_cout\(18),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_counter_sig_20\);
+
+\vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un1_toggle_counter_siglt6\ = !\vga_control_unit|toggle_counter_sig_5\ # !\vga_control_unit|toggle_counter_sig_6\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "33ff",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_control_unit|toggle_counter_sig_6\,
+ datad => \vga_control_unit|toggle_counter_sig_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un1_toggle_counter_siglt6\);
+
+\vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un1_toggle_counter_siglto9\ = !\vga_control_unit|toggle_counter_sig_7\ & \vga_control_unit|un1_toggle_counter_siglt6\ # !\vga_control_unit|toggle_counter_sig_9\ # !\vga_control_unit|toggle_counter_sig_8\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "7f3f",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_control_unit|toggle_counter_sig_7\,
+ datab => \vga_control_unit|toggle_counter_sig_8\,
+ datac => \vga_control_unit|toggle_counter_sig_9\,
+ datad => \vga_control_unit|un1_toggle_counter_siglt6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un1_toggle_counter_siglto9\);
+
+\vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un1_toggle_counter_siglto12\ = !\vga_control_unit|toggle_counter_sig_11\ & !\vga_control_unit|toggle_counter_sig_12\ & !\vga_control_unit|toggle_counter_sig_10\ & \vga_control_unit|un1_toggle_counter_siglto9\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0100",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_control_unit|toggle_counter_sig_11\,
+ datab => \vga_control_unit|toggle_counter_sig_12\,
+ datac => \vga_control_unit|toggle_counter_sig_10\,
+ datad => \vga_control_unit|un1_toggle_counter_siglto9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un1_toggle_counter_siglto12\);
+
+\vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un1_toggle_counter_siglto15\ = \vga_control_unit|un1_toggle_counter_siglto12\ # !\vga_control_unit|toggle_counter_sig_15\ # !\vga_control_unit|toggle_counter_sig_13\ # !\vga_control_unit|toggle_counter_sig_14\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff7f",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_control_unit|toggle_counter_sig_14\,
+ datab => \vga_control_unit|toggle_counter_sig_13\,
+ datac => \vga_control_unit|toggle_counter_sig_15\,
+ datad => \vga_control_unit|un1_toggle_counter_siglto12\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un1_toggle_counter_siglto15\);
+
+\vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un1_toggle_counter_siglto18\ = !\vga_control_unit|toggle_counter_sig_16\ & \vga_control_unit|un1_toggle_counter_siglto15\ # !\vga_control_unit|toggle_counter_sig_18\ # !\vga_control_unit|toggle_counter_sig_17\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "7f3f",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_control_unit|toggle_counter_sig_16\,
+ datab => \vga_control_unit|toggle_counter_sig_17\,
+ datac => \vga_control_unit|toggle_counter_sig_18\,
+ datad => \vga_control_unit|un1_toggle_counter_siglto15\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un1_toggle_counter_siglto18\);
+
+\vga_control_unit|toggle_sig_0_0_0_g1_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_sig_0_0_0_g1\ = !\vga_control_unit|toggle_counter_sig_19\ & (\vga_control_unit|un1_toggle_counter_siglto18\) # !\vga_control_unit|toggle_counter_sig_20\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "7755",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_control_unit|toggle_counter_sig_20\,
+ datab => \vga_control_unit|toggle_counter_sig_19\,
+ datad => \vga_control_unit|un1_toggle_counter_siglto18\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|toggle_sig_0_0_0_g1\);
+
+\vga_control_unit|toggle_sig_Z\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|toggle_sig\ = DFFEAS(\vga_control_unit|toggle_sig\ $ (!\vga_control_unit|toggle_sig_0_0_0_g1\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "cc33",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_control_unit|toggle_sig\,
+ datad => \vga_control_unit|toggle_sig_0_0_0_g1\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|toggle_sig\);
+
+\vga_driver_unit|vsync_counter_0_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_0\ = DFFEAS(\vga_driver_unit|vsync_counter_0\ $ \vga_driver_unit|d_set_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
+-- !\vga_driver_unit|un9_vsync_counterlt9\)
+-- \vga_driver_unit|vsync_counter_cout\(0) = CARRY(\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|d_set_hsync_counter\)
+-- \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|d_set_hsync_counter\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "6688",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|vsync_counter_0\,
+ datab => \vga_driver_unit|d_set_hsync_counter\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_0\,
+ cout0 => \vga_driver_unit|vsync_counter_cout\(0),
+ cout1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\);
+
+\vga_driver_unit|vsync_counter_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_1\ = DFFEAS(\vga_driver_unit|vsync_counter_1\ $ \vga_driver_unit|vsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
+-- !\vga_driver_unit|un9_vsync_counterlt9\)
+-- \vga_driver_unit|vsync_counter_cout\(1) = CARRY(!\vga_driver_unit|vsync_counter_cout\(0) # !\vga_driver_unit|vsync_counter_1\)
+-- \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|vsync_counter_1\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "3c3f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|vsync_counter_1\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ cin0 => \vga_driver_unit|vsync_counter_cout\(0),
+ cin1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_1\,
+ cout0 => \vga_driver_unit|vsync_counter_cout\(1),
+ cout1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\);
+
+\vga_driver_unit|vsync_counter_2_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_2\ = DFFEAS(\vga_driver_unit|vsync_counter_2\ $ (!\vga_driver_unit|vsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
+-- !\vga_driver_unit|un9_vsync_counterlt9\)
+-- \vga_driver_unit|vsync_counter_cout\(2) = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout\(1)))
+-- \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout[1]~COUT1_12\))
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "a50a",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|vsync_counter_2\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ cin0 => \vga_driver_unit|vsync_counter_cout\(1),
+ cin1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_2\,
+ cout0 => \vga_driver_unit|vsync_counter_cout\(2),
+ cout1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\);
+
+\vga_driver_unit|vsync_counter_3_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_3\ = DFFEAS(\vga_driver_unit|vsync_counter_3\ $ (\vga_driver_unit|vsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
+-- !\vga_driver_unit|un9_vsync_counterlt9\)
+-- \vga_driver_unit|vsync_counter_cout\(3) = CARRY(!\vga_driver_unit|vsync_counter_cout\(2) # !\vga_driver_unit|vsync_counter_3\)
+-- \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|vsync_counter_3\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "5a5f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|vsync_counter_3\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ cin0 => \vga_driver_unit|vsync_counter_cout\(2),
+ cin1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_3\,
+ cout0 => \vga_driver_unit|vsync_counter_cout\(3),
+ cout1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\);
+
+\vga_driver_unit|vsync_counter_4_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_4\ = DFFEAS(\vga_driver_unit|vsync_counter_4\ $ (!\vga_driver_unit|vsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
+-- !\vga_driver_unit|un9_vsync_counterlt9\)
+-- \vga_driver_unit|vsync_counter_cout\(4) = CARRY(\vga_driver_unit|vsync_counter_4\ & (!\vga_driver_unit|vsync_counter_cout[3]~COUT1_16\))
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "a50a",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|vsync_counter_4\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ cin0 => \vga_driver_unit|vsync_counter_cout\(3),
+ cin1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_4\,
+ cout => \vga_driver_unit|vsync_counter_cout\(4));
+
+\vga_driver_unit|vsync_counter_5_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_5\ = DFFEAS(\vga_driver_unit|vsync_counter_5\ $ \vga_driver_unit|vsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
+-- !\vga_driver_unit|un9_vsync_counterlt9\)
+-- \vga_driver_unit|vsync_counter_cout\(5) = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\)
+-- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin_used => "true",
+ lut_mask => "3c3f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|vsync_counter_5\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ cin => \vga_driver_unit|vsync_counter_cout\(4),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_5\,
+ cout0 => \vga_driver_unit|vsync_counter_cout\(5),
+ cout1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\);
+
+\vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un9_vsync_counterlt9_6\ = !\vga_driver_unit|vsync_counter_1\ # !\vga_driver_unit|vsync_counter_0\ # !\vga_driver_unit|vsync_counter_2\ # !\vga_driver_unit|vsync_counter_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "7fff",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_counter_3\,
+ datab => \vga_driver_unit|vsync_counter_2\,
+ datac => \vga_driver_unit|vsync_counter_0\,
+ datad => \vga_driver_unit|vsync_counter_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un9_vsync_counterlt9_6\);
+
+\vga_driver_unit|vsync_counter_6_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_6\ = DFFEAS(\vga_driver_unit|vsync_counter_6\ $ !(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(5)) # (\vga_driver_unit|vsync_counter_cout\(4) &
+-- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
+-- \vga_driver_unit|vsync_counter_cout\(6) = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout\(5))
+-- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout[5]~COUT1_18\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "c30c",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|vsync_counter_6\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ cin => \vga_driver_unit|vsync_counter_cout\(4),
+ cin0 => \vga_driver_unit|vsync_counter_cout\(5),
+ cin1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_6\,
+ cout0 => \vga_driver_unit|vsync_counter_cout\(6),
+ cout1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\);
+
+\vga_driver_unit|vsync_counter_7_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_7\ = DFFEAS(\vga_driver_unit|vsync_counter_7\ $ ((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(6)) # (\vga_driver_unit|vsync_counter_cout\(4) &
+-- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
+-- \vga_driver_unit|vsync_counter_cout\(7) = CARRY(!\vga_driver_unit|vsync_counter_cout\(6) # !\vga_driver_unit|vsync_counter_7\)
+-- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|vsync_counter_7\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "5a5f",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|vsync_counter_7\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ cin => \vga_driver_unit|vsync_counter_cout\(4),
+ cin0 => \vga_driver_unit|vsync_counter_cout\(6),
+ cin1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_7\,
+ cout0 => \vga_driver_unit|vsync_counter_cout\(7),
+ cout1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\);
+
+\vga_driver_unit|vsync_counter_8_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_8\ = DFFEAS(\vga_driver_unit|vsync_counter_8\ $ (!(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(7)) # (\vga_driver_unit|vsync_counter_cout\(4) &
+-- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
+-- \vga_driver_unit|vsync_counter_cout\(8) = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout\(7)))
+-- \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout[7]~COUT1_22\))
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "a50a",
+ operation_mode => "arithmetic",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|vsync_counter_8\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ cin => \vga_driver_unit|vsync_counter_cout\(4),
+ cin0 => \vga_driver_unit|vsync_counter_cout\(7),
+ cin1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_8\,
+ cout0 => \vga_driver_unit|vsync_counter_cout\(8),
+ cout1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\);
+
+\vga_driver_unit|vsync_counter_9_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_9\ = DFFEAS((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(8)) # (\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\) $
+-- \vga_driver_unit|vsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ cin_used => "true",
+ lut_mask => "0ff0",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
+ datad => \vga_driver_unit|vsync_counter_9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_G_16_i\,
+ sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
+ cin => \vga_driver_unit|vsync_counter_cout\(4),
+ cin0 => \vga_driver_unit|vsync_counter_cout\(8),
+ cin1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_counter_9\);
+
+\vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un9_vsync_counterlt9_5\ = !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_6\ # !\vga_driver_unit|vsync_counter_8\ # !\vga_driver_unit|vsync_counter_7\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "7fff",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_counter_7\,
+ datab => \vga_driver_unit|vsync_counter_8\,
+ datac => \vga_driver_unit|vsync_counter_6\,
+ datad => \vga_driver_unit|vsync_counter_9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un9_vsync_counterlt9_5\);
+
+\vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un9_vsync_counterlt9\ = \vga_driver_unit|un9_vsync_counterlt9_6\ # \vga_driver_unit|un9_vsync_counterlt9_5\ # !\vga_driver_unit|vsync_counter_4\ # !\vga_driver_unit|vsync_counter_5\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ffdf",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_counter_5\,
+ datab => \vga_driver_unit|un9_vsync_counterlt9_6\,
+ datac => \vga_driver_unit|vsync_counter_4\,
+ datad => \vga_driver_unit|un9_vsync_counterlt9_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un9_vsync_counterlt9\);
+
+\vga_driver_unit|G_16\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|G_16_i\ = !\vga_driver_unit|vsync_state_6\ & !\vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un9_vsync_counterlt9\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "01ff",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_state_6\,
+ datab => \vga_driver_unit|vsync_state_0\,
+ datac => \vga_driver_unit|un6_dly_counter_0_x\,
+ datad => \vga_driver_unit|un9_vsync_counterlt9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|G_16_i\);
+
+\vga_driver_unit|vsync_state_5_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_5\ = DFFEAS(\vga_driver_unit|vsync_state_6\ # \vga_driver_unit|vsync_state_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "fff0",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|vsync_state_6\,
+ datad => \vga_driver_unit|vsync_state_0\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_state_5\);
+
+\vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un12_vsync_counter_6\ = !\vga_driver_unit|vsync_counter_5\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_7\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0001",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_counter_5\,
+ datab => \vga_driver_unit|vsync_counter_6\,
+ datac => \vga_driver_unit|vsync_counter_8\,
+ datad => \vga_driver_unit|vsync_counter_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un12_vsync_counter_6\);
+
+\vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un14_vsync_counter_8\ = \vga_driver_unit|un12_vsync_counter_6\ & \vga_driver_unit|un12_vsync_counter_7\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "f000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datac => \vga_driver_unit|un12_vsync_counter_6\,
+ datad => \vga_driver_unit|un12_vsync_counter_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un14_vsync_counter_8\);
+
+\vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|vsync_state_5\ & (\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_0\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "d0f0",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_counter_0\,
+ datab => \vga_driver_unit|vsync_counter_9\,
+ datac => \vga_driver_unit|vsync_state_5\,
+ datad => \vga_driver_unit|un14_vsync_counter_8\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\);
+
+\vga_driver_unit|vsync_state_3_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ = C1_vsync_state_3 & (!\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_0\)
+-- \vga_driver_unit|vsync_state_3\ = DFFEAS(\vga_driver_unit|vsync_state_next_1_sqmuxa_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, \vga_driver_unit|vsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "70f0",
+ operation_mode => "normal",
+ output_mode => "reg_and_comb",
+ register_cascade_mode => "off",
+ sum_lutc_input => "qfbk",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|vsync_counter_0\,
+ datab => \vga_driver_unit|vsync_counter_9\,
+ datac => \vga_driver_unit|vsync_state_1\,
+ datad => \vga_driver_unit|un14_vsync_counter_8\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ sload => VCC,
+ ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\,
+ regout => \vga_driver_unit|vsync_state_3\);
+
+\vga_driver_unit|vsync_state_2_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_2\ = DFFEAS(\vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|vsync_state_3\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un14_vsync_counter_8\, GLOBAL(\clk_pin~combout\), VCC, ,
+-- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "8000",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|vsync_counter_9\,
+ datab => \vga_driver_unit|vsync_state_3\,
+ datac => \vga_driver_unit|vsync_counter_0\,
+ datad => \vga_driver_unit|un14_vsync_counter_8\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_state_2\);
+
+\vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un15_vsync_counter_3\ = \vga_driver_unit|vsync_counter_3\ & \vga_driver_unit|vsync_counter_9\ & !\vga_driver_unit|vsync_counter_0\ & !\vga_driver_unit|vsync_counter_2\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0008",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_counter_3\,
+ datab => \vga_driver_unit|vsync_counter_9\,
+ datac => \vga_driver_unit|vsync_counter_0\,
+ datad => \vga_driver_unit|vsync_counter_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un15_vsync_counter_3\);
+
+\vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un15_vsync_counter_4\ = !\vga_driver_unit|vsync_counter_1\ & !\vga_driver_unit|vsync_counter_4\ & \vga_driver_unit|un15_vsync_counter_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0300",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|vsync_counter_1\,
+ datac => \vga_driver_unit|vsync_counter_4\,
+ datad => \vga_driver_unit|un15_vsync_counter_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un15_vsync_counter_4\);
+
+\vga_driver_unit|vsync_state_4_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_4\ = DFFEAS(\vga_driver_unit|vsync_state_5\ & !\vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un14_vsync_counter_8\, GLOBAL(\clk_pin~combout\), VCC, ,
+-- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "2000",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|vsync_state_5\,
+ datab => \vga_driver_unit|vsync_counter_9\,
+ datac => \vga_driver_unit|vsync_counter_0\,
+ datad => \vga_driver_unit|un14_vsync_counter_8\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_state_4\);
+
+\vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un13_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_9\ & !\vga_driver_unit|vsync_counter_8\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0001",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_counter_7\,
+ datab => \vga_driver_unit|vsync_counter_6\,
+ datac => \vga_driver_unit|vsync_counter_9\,
+ datad => \vga_driver_unit|vsync_counter_8\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un13_vsync_counter_3\);
+
+\vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un13_vsync_counter_4\ = \vga_driver_unit|vsync_counter_5\ & (\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un13_vsync_counter_3\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "a000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_counter_5\,
+ datac => \vga_driver_unit|vsync_counter_0\,
+ datad => \vga_driver_unit|un13_vsync_counter_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un13_vsync_counter_4\);
+
+\vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|vsync_state_4\ & (!\vga_driver_unit|un12_vsync_counter_7\ # !\vga_driver_unit|un13_vsync_counter_4\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0aaa",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_state_4\,
+ datac => \vga_driver_unit|un13_vsync_counter_4\,
+ datad => \vga_driver_unit|un12_vsync_counter_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\);
+
+\vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ # \vga_driver_unit|vsync_state_2\ & (!\vga_driver_unit|un15_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_6\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff4c",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|un12_vsync_counter_6\,
+ datab => \vga_driver_unit|vsync_state_2\,
+ datac => \vga_driver_unit|un15_vsync_counter_4\,
+ datad => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\);
+
+\vga_driver_unit|vsync_state_next_2_sqmuxa_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_next_2_sqmuxa\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|vsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|vsync_state_next_1_sqmuxa_3\ & !\vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "aaab",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|un6_dly_counter_0_x\,
+ datab => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\,
+ datac => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\,
+ datad => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|vsync_state_next_2_sqmuxa\);
+
+\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ = \vga_driver_unit|vsync_state_2\ & \vga_driver_unit|un15_vsync_counter_4\ & \vga_driver_unit|un12_vsync_counter_6\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "c000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|vsync_state_2\,
+ datac => \vga_driver_unit|un15_vsync_counter_4\,
+ datad => \vga_driver_unit|un12_vsync_counter_6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\);
+
+\vga_driver_unit|vsync_state_0_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_0\ = DFFEAS(\vga_driver_unit|un6_dly_counter_0_x\ & \vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\ # !\vga_driver_unit|un6_dly_counter_0_x\ & (\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ #
+-- \vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "5d0c",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|un6_dly_counter_0_x\,
+ datab => \vga_driver_unit|vsync_state_0\,
+ datac => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
+ datad => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\,
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_state_0\);
+
+\vga_driver_unit|d_set_vsync_counter_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|d_set_vsync_counter\ = \vga_driver_unit|vsync_state_0\ # \vga_driver_unit|vsync_state_6\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ffcc",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|vsync_state_0\,
+ datad => \vga_driver_unit|vsync_state_6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|d_set_vsync_counter\);
+
+\vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_counter_next_1_sqmuxa\ = !\vga_driver_unit|d_set_vsync_counter\ & dly_counter(1) & \reset_pin~combout\ & dly_counter(0)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "4000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|d_set_vsync_counter\,
+ datab => dly_counter(1),
+ datac => \reset_pin~combout\,
+ datad => dly_counter(0),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|vsync_counter_next_1_sqmuxa\);
+
+\vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un12_vsync_counter_7\ = !\vga_driver_unit|vsync_counter_1\ & !\vga_driver_unit|vsync_counter_2\ & !\vga_driver_unit|vsync_counter_3\ & !\vga_driver_unit|vsync_counter_4\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0001",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_counter_1\,
+ datab => \vga_driver_unit|vsync_counter_2\,
+ datac => \vga_driver_unit|vsync_counter_3\,
+ datad => \vga_driver_unit|vsync_counter_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un12_vsync_counter_7\);
+
+\vga_driver_unit|vsync_state_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|vsync_state_1\ = DFFEAS(\vga_driver_unit|un12_vsync_counter_7\ & \vga_driver_unit|un13_vsync_counter_4\ & !\vga_driver_unit|un6_dly_counter_0_x\ & \vga_driver_unit|vsync_state_4\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0800",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|un12_vsync_counter_7\,
+ datab => \vga_driver_unit|un13_vsync_counter_4\,
+ datac => \vga_driver_unit|un6_dly_counter_0_x\,
+ datad => \vga_driver_unit|vsync_state_4\,
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|vsync_state_1\);
+
+\vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ = \reset_pin~combout\ & dly_counter(0) & !\vga_driver_unit|vsync_state_1\ & dly_counter(1)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0800",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \reset_pin~combout\,
+ datab => dly_counter(0),
+ datac => \vga_driver_unit|vsync_state_1\,
+ datad => dly_counter(1),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\);
+
+\vga_driver_unit|un1_line_counter_sig_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_combout\(1) = \vga_driver_unit|d_set_hsync_counter\ $ \vga_driver_unit|line_counter_sig_0\
+-- \vga_driver_unit|un1_line_counter_sig_cout\(1) = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|line_counter_sig_0\)
+-- \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|line_counter_sig_0\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "6688",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|d_set_hsync_counter\,
+ datab => \vga_driver_unit|line_counter_sig_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_combout\(1),
+ cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(1),
+ cout1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\);
+
+\vga_driver_unit|line_counter_sig_0_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_sig_0\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(1) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff0f",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|un10_line_counter_siglto8\,
+ datad => \vga_driver_unit|un1_line_counter_sig_combout\(1),
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|line_counter_sig_0\);
+
+\vga_driver_unit|un1_line_counter_sig_a_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_a_cout\(1) = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
+-- \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff88",
+ operation_mode => "arithmetic",
+ output_mode => "none",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_0\,
+ datab => \vga_driver_unit|d_set_hsync_counter\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\,
+ cout0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1),
+ cout1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\);
+
+\vga_driver_unit|un1_line_counter_sig_2_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_combout\(2) = \vga_driver_unit|line_counter_sig_1\ $ \vga_driver_unit|un1_line_counter_sig_a_cout\(1)
+-- \vga_driver_unit|un1_line_counter_sig_cout\(2) = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout\(1) # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
+-- \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "3c7f",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_2\,
+ datab => \vga_driver_unit|line_counter_sig_1\,
+ cin0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1),
+ cin1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_combout\(2),
+ cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(2),
+ cout1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\);
+
+\vga_driver_unit|line_counter_sig_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_sig_1\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(2) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "cfcf",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|un1_line_counter_sig_combout\(2),
+ datac => \vga_driver_unit|un10_line_counter_siglto8\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|line_counter_sig_1\);
+
+\vga_driver_unit|un1_line_counter_sig_3_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_combout\(3) = \vga_driver_unit|line_counter_sig_2\ $ (\vga_driver_unit|line_counter_sig_1\ & \vga_driver_unit|un1_line_counter_sig_cout\(1))
+-- \vga_driver_unit|un1_line_counter_sig_cout\(3) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(1) # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
+-- \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "6a7f",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_2\,
+ datab => \vga_driver_unit|line_counter_sig_1\,
+ cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(1),
+ cin1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_combout\(3),
+ cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(3),
+ cout1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\);
+
+\vga_driver_unit|line_counter_sig_2_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_sig_2\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(3) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff0f",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|un10_line_counter_siglto8\,
+ datad => \vga_driver_unit|un1_line_counter_sig_combout\(3),
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|line_counter_sig_2\);
+
+\vga_driver_unit|un1_line_counter_sig_4_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_combout\(4) = \vga_driver_unit|line_counter_sig_3\ $ !\vga_driver_unit|un1_line_counter_sig_cout\(2)
+-- \vga_driver_unit|un1_line_counter_sig_cout\(4) = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(2))
+-- \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "c308",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_4\,
+ datab => \vga_driver_unit|line_counter_sig_3\,
+ cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(2),
+ cin1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_combout\(4),
+ cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(4),
+ cout1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\);
+
+\vga_driver_unit|line_counter_sig_3_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_sig_3\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(4) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "f5f5",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|un10_line_counter_siglto8\,
+ datac => \vga_driver_unit|un1_line_counter_sig_combout\(4),
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|line_counter_sig_3\);
+
+\vga_driver_unit|un1_line_counter_sig_5_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_combout\(5) = \vga_driver_unit|line_counter_sig_4\ $ (\vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3))
+-- \vga_driver_unit|un1_line_counter_sig_cout\(5) = CARRY(\vga_driver_unit|line_counter_sig_3\ & \vga_driver_unit|line_counter_sig_4\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3))
+-- \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ = CARRY(\vga_driver_unit|line_counter_sig_3\ & \vga_driver_unit|line_counter_sig_4\ & !\vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "c608",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_3\,
+ datab => \vga_driver_unit|line_counter_sig_4\,
+ cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(3),
+ cin1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_combout\(5),
+ cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(5),
+ cout1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\);
+
+\vga_driver_unit|line_counter_sig_4_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_sig_4\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(5) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff33",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|un10_line_counter_siglto8\,
+ datad => \vga_driver_unit|un1_line_counter_sig_combout\(5),
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|line_counter_sig_4\);
+
+\vga_driver_unit|un1_line_counter_sig_6_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_combout\(6) = \vga_driver_unit|line_counter_sig_5\ $ (\vga_driver_unit|un1_line_counter_sig_cout\(4))
+-- \vga_driver_unit|un1_line_counter_sig_cout\(6) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(4) # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
+-- \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "5a7f",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_5\,
+ datab => \vga_driver_unit|line_counter_sig_6\,
+ cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(4),
+ cin1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_combout\(6),
+ cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(6),
+ cout1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\);
+
+\vga_driver_unit|line_counter_sig_5_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_sig_5\ = DFFEAS(\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ & (\vga_driver_unit|un1_line_counter_sig_combout\(6) & \vga_driver_unit|un10_line_counter_siglto8\), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "a000",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\,
+ datac => \vga_driver_unit|un1_line_counter_sig_combout\(6),
+ datad => \vga_driver_unit|un10_line_counter_siglto8\,
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|line_counter_sig_5\);
+
+\vga_driver_unit|un1_line_counter_sig_7_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_combout\(7) = \vga_driver_unit|line_counter_sig_6\ $ (\vga_driver_unit|line_counter_sig_5\ & \vga_driver_unit|un1_line_counter_sig_cout\(5))
+-- \vga_driver_unit|un1_line_counter_sig_cout\(7) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(5) # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
+-- \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "6c7f",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_5\,
+ datab => \vga_driver_unit|line_counter_sig_6\,
+ cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(5),
+ cin1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_combout\(7),
+ cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(7),
+ cout1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\);
+
+\vga_driver_unit|line_counter_sig_6_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_sig_6\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(7) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "f0ff",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|un1_line_counter_sig_combout\(7),
+ datad => \vga_driver_unit|un10_line_counter_siglto8\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|line_counter_sig_6\);
+
+\vga_driver_unit|un1_line_counter_sig_8_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_combout\(8) = \vga_driver_unit|line_counter_sig_7\ $ !\vga_driver_unit|un1_line_counter_sig_cout\(6)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "c3c3",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|line_counter_sig_7\,
+ cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(6),
+ cin1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_combout\(8));
+
+\vga_driver_unit|line_counter_sig_7_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_sig_7\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(8) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "f0ff",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|un1_line_counter_sig_combout\(8),
+ datad => \vga_driver_unit|un10_line_counter_siglto8\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|line_counter_sig_7\);
+
+\vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un10_line_counter_siglt4_2\ = !\vga_driver_unit|line_counter_sig_4\ # !\vga_driver_unit|line_counter_sig_0\ # !\vga_driver_unit|line_counter_sig_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "5fff",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_3\,
+ datac => \vga_driver_unit|line_counter_sig_0\,
+ datad => \vga_driver_unit|line_counter_sig_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un10_line_counter_siglt4_2\);
+
+\vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un10_line_counter_siglto5\ = !\vga_driver_unit|line_counter_sig_5\ & (\vga_driver_unit|un10_line_counter_siglt4_2\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "00f7",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_2\,
+ datab => \vga_driver_unit|line_counter_sig_1\,
+ datac => \vga_driver_unit|un10_line_counter_siglt4_2\,
+ datad => \vga_driver_unit|line_counter_sig_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un10_line_counter_siglto5\);
+
+\vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un10_line_counter_siglto8\ = \vga_driver_unit|un10_line_counter_siglto5\ # !\vga_driver_unit|line_counter_sig_7\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_8\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff7f",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_8\,
+ datab => \vga_driver_unit|line_counter_sig_6\,
+ datac => \vga_driver_unit|line_counter_sig_7\,
+ datad => \vga_driver_unit|un10_line_counter_siglto5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un10_line_counter_siglto8\);
+
+\vga_driver_unit|un1_line_counter_sig_9_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_line_counter_sig_combout\(9) = \vga_driver_unit|line_counter_sig_8\ $ (!\vga_driver_unit|un1_line_counter_sig_cout\(7) & \vga_driver_unit|line_counter_sig_7\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "c3cc",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|line_counter_sig_8\,
+ datad => \vga_driver_unit|line_counter_sig_7\,
+ cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(7),
+ cin1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_line_counter_sig_combout\(9));
+
+\vga_driver_unit|line_counter_sig_8_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|line_counter_sig_8\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(9) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff33",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|un10_line_counter_siglto8\,
+ datad => \vga_driver_unit|un1_line_counter_sig_combout\(9),
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|line_counter_sig_8\);
+
+\vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un17_v_enablelto3\ = \vga_driver_unit|line_counter_sig_3\ & (\vga_driver_unit|line_counter_sig_0\ # \vga_driver_unit|line_counter_sig_1\ # \vga_driver_unit|line_counter_sig_2\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "f0e0",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_0\,
+ datab => \vga_driver_unit|line_counter_sig_1\,
+ datac => \vga_driver_unit|line_counter_sig_3\,
+ datad => \vga_driver_unit|line_counter_sig_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un17_v_enablelto3\);
+
+\vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|b_next_0_sqmuxa_7_4_a\ = !\vga_driver_unit|line_counter_sig_4\ & !\vga_control_unit|un17_v_enablelto3\ & !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "3337",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_4\,
+ datab => \vga_driver_unit|line_counter_sig_6\,
+ datac => \vga_control_unit|un17_v_enablelto3\,
+ datad => \vga_driver_unit|line_counter_sig_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|b_next_0_sqmuxa_7_4_a\);
+
+\vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un13_v_enablelto4_0\ = !\vga_driver_unit|line_counter_sig_2\ & (!\vga_driver_unit|line_counter_sig_4\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0033",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|line_counter_sig_2\,
+ datad => \vga_driver_unit|line_counter_sig_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un13_v_enablelto4_0\);
+
+\vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un13_v_enablelto6\ = !\vga_driver_unit|line_counter_sig_3\ & \vga_control_unit|un13_v_enablelto4_0\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "7f5f",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_5\,
+ datab => \vga_driver_unit|line_counter_sig_3\,
+ datac => \vga_driver_unit|line_counter_sig_6\,
+ datad => \vga_control_unit|un13_v_enablelto4_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un13_v_enablelto6\);
+
+\vga_control_unit|b_next_0_sqmuxa_7_4_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|b_next_0_sqmuxa_7_4\ = \vga_driver_unit|line_counter_sig_7\ & (\vga_control_unit|b_next_0_sqmuxa_7_4_a\) # !\vga_driver_unit|line_counter_sig_7\ & (\vga_driver_unit|line_counter_sig_8\ # !\vga_control_unit|un13_v_enablelto6\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "e2f3",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_8\,
+ datab => \vga_driver_unit|line_counter_sig_7\,
+ datac => \vga_control_unit|b_next_0_sqmuxa_7_4_a\,
+ datad => \vga_control_unit|un13_v_enablelto6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|b_next_0_sqmuxa_7_4\);
+
+\vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ = !\vga_driver_unit|hsync_state_1\ & dly_counter(1) & \reset_pin~combout\ & dly_counter(0)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "4000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_state_1\,
+ datab => dly_counter(1),
+ datac => \reset_pin~combout\,
+ datad => dly_counter(0),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\);
+
+\vga_driver_unit|column_counter_sig_0_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_0\ = DFFEAS(!\vga_driver_unit|un10_column_counter_siglto9\ # !\vga_driver_unit|column_counter_sig_0\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0fff",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|column_counter_sig_0\,
+ datad => \vga_driver_unit|un10_column_counter_siglto9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_0\);
+
+\vga_driver_unit|un2_column_counter_next_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_combout\(1) = \vga_driver_unit|column_counter_sig_1\ $ \vga_driver_unit|column_counter_sig_0\
+-- \vga_driver_unit|un2_column_counter_next_cout\(1) = CARRY(\vga_driver_unit|column_counter_sig_1\ & \vga_driver_unit|column_counter_sig_0\)
+-- \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ = CARRY(\vga_driver_unit|column_counter_sig_1\ & \vga_driver_unit|column_counter_sig_0\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "6688",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_1\,
+ datab => \vga_driver_unit|column_counter_sig_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_combout\(1),
+ cout0 => \vga_driver_unit|un2_column_counter_next_cout\(1),
+ cout1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\);
+
+\vga_driver_unit|column_counter_sig_1_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_1\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(1) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "f0ff",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|un2_column_counter_next_combout\(1),
+ datad => \vga_driver_unit|un10_column_counter_siglto9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_1\);
+
+\vga_driver_unit|un2_column_counter_next_3_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_combout\(3) = \vga_driver_unit|column_counter_sig_3\ $ (\vga_driver_unit|column_counter_sig_2\ & \vga_driver_unit|un2_column_counter_next_cout\(1))
+-- \vga_driver_unit|un2_column_counter_next_cout\(3) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(1) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
+-- \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "6c7f",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_2\,
+ datab => \vga_driver_unit|column_counter_sig_3\,
+ cin0 => \vga_driver_unit|un2_column_counter_next_cout\(1),
+ cin1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_combout\(3),
+ cout0 => \vga_driver_unit|un2_column_counter_next_cout\(3),
+ cout1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\);
+
+\vga_driver_unit|column_counter_sig_3_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_3\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(3) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "f0ff",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|un2_column_counter_next_combout\(3),
+ datad => \vga_driver_unit|un10_column_counter_siglto9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_3\);
+
+\vga_driver_unit|un2_column_counter_next_0_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_cout\(0) = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\)
+-- \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff88",
+ operation_mode => "arithmetic",
+ output_mode => "none",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_0\,
+ datab => \vga_driver_unit|column_counter_sig_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\,
+ cout0 => \vga_driver_unit|un2_column_counter_next_cout\(0),
+ cout1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\);
+
+\vga_driver_unit|un2_column_counter_next_2_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_combout\(2) = \vga_driver_unit|column_counter_sig_2\ $ (\vga_driver_unit|un2_column_counter_next_cout\(0))
+-- \vga_driver_unit|un2_column_counter_next_cout\(2) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(0) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
+-- \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "5a7f",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_2\,
+ datab => \vga_driver_unit|column_counter_sig_3\,
+ cin0 => \vga_driver_unit|un2_column_counter_next_cout\(0),
+ cin1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_combout\(2),
+ cout0 => \vga_driver_unit|un2_column_counter_next_cout\(2),
+ cout1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\);
+
+\vga_driver_unit|column_counter_sig_2_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_2\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(2) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ccff",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|un2_column_counter_next_combout\(2),
+ datad => \vga_driver_unit|un10_column_counter_siglto9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_2\);
+
+\vga_driver_unit|un2_column_counter_next_5_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_combout\(5) = \vga_driver_unit|column_counter_sig_5\ $ (\vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3))
+-- \vga_driver_unit|un2_column_counter_next_cout\(5) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3))
+-- \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "a608",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_5\,
+ datab => \vga_driver_unit|column_counter_sig_4\,
+ cin0 => \vga_driver_unit|un2_column_counter_next_cout\(3),
+ cin1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_combout\(5),
+ cout0 => \vga_driver_unit|un2_column_counter_next_cout\(5),
+ cout1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\);
+
+\vga_driver_unit|column_counter_sig_5_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_5\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(5) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "afaf",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|un2_column_counter_next_combout\(5),
+ datac => \vga_driver_unit|un10_column_counter_siglto9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_5\);
+
+\vga_driver_unit|un2_column_counter_next_4_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_combout\(4) = \vga_driver_unit|column_counter_sig_4\ $ (!\vga_driver_unit|un2_column_counter_next_cout\(2))
+-- \vga_driver_unit|un2_column_counter_next_cout\(4) = CARRY(\vga_driver_unit|column_counter_sig_4\ & \vga_driver_unit|column_counter_sig_5\ & !\vga_driver_unit|un2_column_counter_next_cout\(2))
+-- \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ = CARRY(\vga_driver_unit|column_counter_sig_4\ & \vga_driver_unit|column_counter_sig_5\ & !\vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "a508",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_4\,
+ datab => \vga_driver_unit|column_counter_sig_5\,
+ cin0 => \vga_driver_unit|un2_column_counter_next_cout\(2),
+ cin1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_combout\(4),
+ cout0 => \vga_driver_unit|un2_column_counter_next_cout\(4),
+ cout1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\);
+
+\vga_driver_unit|column_counter_sig_4_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_4\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(4) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "f0ff",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|un2_column_counter_next_combout\(4),
+ datad => \vga_driver_unit|un10_column_counter_siglto9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_4\);
+
+\vga_driver_unit|un2_column_counter_next_6_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_combout\(6) = \vga_driver_unit|column_counter_sig_6\ $ (\vga_driver_unit|un2_column_counter_next_cout\(4))
+-- \vga_driver_unit|un2_column_counter_next_cout\(6) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(4) # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
+-- \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "5a7f",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_6\,
+ datab => \vga_driver_unit|column_counter_sig_7\,
+ cin0 => \vga_driver_unit|un2_column_counter_next_cout\(4),
+ cin1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_combout\(6),
+ cout0 => \vga_driver_unit|un2_column_counter_next_cout\(6),
+ cout1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\);
+
+\vga_driver_unit|un2_column_counter_next_8_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_combout\(8) = \vga_driver_unit|un2_column_counter_next_cout\(6) $ !\vga_driver_unit|column_counter_sig_8\
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "f00f",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datad => \vga_driver_unit|column_counter_sig_8\,
+ cin0 => \vga_driver_unit|un2_column_counter_next_cout\(6),
+ cin1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_combout\(8));
+
+\vga_driver_unit|column_counter_sig_8_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_8\ = DFFEAS(\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ & (\vga_driver_unit|un2_column_counter_next_combout\(8) & \vga_driver_unit|un10_column_counter_siglto9\), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "a000",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\,
+ datac => \vga_driver_unit|un2_column_counter_next_combout\(8),
+ datad => \vga_driver_unit|un10_column_counter_siglto9\,
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_8\);
+
+\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un10_column_counter_siglt6_4\ = !\vga_driver_unit|column_counter_sig_1\ # !\vga_driver_unit|column_counter_sig_2\ # !\vga_driver_unit|column_counter_sig_0\ # !\vga_driver_unit|column_counter_sig_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "7fff",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_3\,
+ datab => \vga_driver_unit|column_counter_sig_0\,
+ datac => \vga_driver_unit|column_counter_sig_2\,
+ datad => \vga_driver_unit|column_counter_sig_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un10_column_counter_siglt6_4\);
+
+\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un10_column_counter_siglt6\ = \vga_driver_unit|un10_column_counter_siglt6_4\ # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_4\ # !\vga_driver_unit|column_counter_sig_5\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff7f",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_5\,
+ datab => \vga_driver_unit|column_counter_sig_4\,
+ datac => \vga_driver_unit|column_counter_sig_6\,
+ datad => \vga_driver_unit|un10_column_counter_siglt6_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un10_column_counter_siglt6\);
+
+\vga_driver_unit|un2_column_counter_next_7_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_combout\(7) = \vga_driver_unit|column_counter_sig_7\ $ (\vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|un2_column_counter_next_cout\(5))
+-- \vga_driver_unit|un2_column_counter_next_cout\(7) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(5) # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
+-- \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "6c7f",
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_6\,
+ datab => \vga_driver_unit|column_counter_sig_7\,
+ cin0 => \vga_driver_unit|un2_column_counter_next_cout\(5),
+ cin1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_combout\(7),
+ cout0 => \vga_driver_unit|un2_column_counter_next_cout\(7),
+ cout1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\);
+
+\vga_driver_unit|un2_column_counter_next_9_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un2_column_counter_next_combout\(9) = \vga_driver_unit|column_counter_sig_9\ $ (\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|un2_column_counter_next_cout\(7))
+
+-- pragma translate_off
+GENERIC MAP (
+ cin0_used => "true",
+ cin1_used => "true",
+ lut_mask => "c6c6",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "cin",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_8\,
+ datab => \vga_driver_unit|column_counter_sig_9\,
+ cin0 => \vga_driver_unit|un2_column_counter_next_cout\(7),
+ cin1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un2_column_counter_next_combout\(9));
+
+\vga_driver_unit|column_counter_sig_9_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_9\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(9) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "cfcf",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|un2_column_counter_next_combout\(9),
+ datac => \vga_driver_unit|un10_column_counter_siglto9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_9\);
+
+\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un10_column_counter_siglto9\ = !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\ & \vga_driver_unit|un10_column_counter_siglt6\ # !\vga_driver_unit|column_counter_sig_9\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "10ff",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_8\,
+ datab => \vga_driver_unit|column_counter_sig_7\,
+ datac => \vga_driver_unit|un10_column_counter_siglt6\,
+ datad => \vga_driver_unit|column_counter_sig_9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un10_column_counter_siglto9\);
+
+\vga_driver_unit|column_counter_sig_7_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_7\ = DFFEAS(\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ & \vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|un2_column_counter_next_combout\(7), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "c000",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datab => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\,
+ datac => \vga_driver_unit|un10_column_counter_siglto9\,
+ datad => \vga_driver_unit|un2_column_counter_next_combout\(7),
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_7\);
+
+\vga_driver_unit|column_counter_sig_6_\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|column_counter_sig_6\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(6) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "aaff",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|un2_column_counter_next_combout\(6),
+ datad => \vga_driver_unit|un10_column_counter_siglto9\,
+ aclr => GND,
+ sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|column_counter_sig_6\);
+
+\vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un5_v_enablelt2\ = \vga_driver_unit|column_counter_sig_2\ # \vga_driver_unit|column_counter_sig_1\ # \vga_driver_unit|column_counter_sig_0\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ffee",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_2\,
+ datab => \vga_driver_unit|column_counter_sig_1\,
+ datad => \vga_driver_unit|column_counter_sig_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un5_v_enablelt2\);
+
+\vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un5_v_enablelto5\ = \vga_driver_unit|column_counter_sig_4\ # \vga_driver_unit|column_counter_sig_5\ # \vga_control_unit|un5_v_enablelt2\ & \vga_driver_unit|column_counter_sig_3\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "fefc",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_control_unit|un5_v_enablelt2\,
+ datab => \vga_driver_unit|column_counter_sig_4\,
+ datac => \vga_driver_unit|column_counter_sig_5\,
+ datad => \vga_driver_unit|column_counter_sig_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un5_v_enablelto5\);
+
+\vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|vsync_state_4\ & !\vga_driver_unit|vsync_state_5\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff03",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|vsync_state_4\,
+ datac => \vga_driver_unit|vsync_state_5\,
+ datad => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\);
+
+\vga_driver_unit|h_enable_sig_Z\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|h_enable_sig\ = DFFEAS(\vga_driver_unit|vsync_state_1\ # \vga_driver_unit|vsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "fff0",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "on")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ datac => \vga_driver_unit|vsync_state_1\,
+ datad => \vga_driver_unit|vsync_state_3\,
+ aclr => GND,
+ sclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ ena => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|h_enable_sig\);
+
+\vga_control_unit|b_next_0_sqmuxa_7_2_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|b_next_0_sqmuxa_7_2\ = !\vga_driver_unit|line_counter_sig_8\ & \vga_driver_unit|h_enable_sig\ & !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_9\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0004",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|line_counter_sig_8\,
+ datab => \vga_driver_unit|h_enable_sig\,
+ datac => \vga_driver_unit|column_counter_sig_8\,
+ datad => \vga_driver_unit|column_counter_sig_9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|b_next_0_sqmuxa_7_2\);
+
+\vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un9_v_enablelto4\ = !\vga_driver_unit|column_counter_sig_3\ & (!\vga_driver_unit|column_counter_sig_2\ & !\vga_driver_unit|column_counter_sig_4\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0005",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_3\,
+ datac => \vga_driver_unit|column_counter_sig_2\,
+ datad => \vga_driver_unit|column_counter_sig_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un9_v_enablelto4\);
+
+\vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|un9_v_enablelto6\ = \vga_control_unit|un9_v_enablelto4\ # !\vga_driver_unit|column_counter_sig_5\ # !\vga_driver_unit|column_counter_sig_6\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff77",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_6\,
+ datab => \vga_driver_unit|column_counter_sig_5\,
+ datad => \vga_control_unit|un9_v_enablelto4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|un9_v_enablelto6\);
+
+\vga_control_unit|b_next_0_sqmuxa_7_3_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|b_next_0_sqmuxa_7_3\ = \vga_control_unit|b_next_0_sqmuxa_7_2\ & (\vga_driver_unit|column_counter_sig_9\ # \vga_driver_unit|column_counter_sig_7\ # !\vga_control_unit|un9_v_enablelto6\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "c8cc",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_9\,
+ datab => \vga_control_unit|b_next_0_sqmuxa_7_2\,
+ datac => \vga_driver_unit|column_counter_sig_7\,
+ datad => \vga_control_unit|un9_v_enablelto6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|b_next_0_sqmuxa_7_3\);
+
+\vga_control_unit|b_next_0_sqmuxa_7_5_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|b_next_0_sqmuxa_7_5\ = \vga_control_unit|b_next_0_sqmuxa_7_3\ & (!\vga_control_unit|un5_v_enablelto5\ # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "7f00",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|column_counter_sig_6\,
+ datab => \vga_driver_unit|column_counter_sig_7\,
+ datac => \vga_control_unit|un5_v_enablelto5\,
+ datad => \vga_control_unit|b_next_0_sqmuxa_7_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_control_unit|b_next_0_sqmuxa_7_5\);
+
+\vga_control_unit|r_Z\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|r\ = DFFEAS(\vga_driver_unit|v_enable_sig\ & \vga_control_unit|toggle_sig\ & \vga_control_unit|b_next_0_sqmuxa_7_4\ & \vga_control_unit|b_next_0_sqmuxa_7_5\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , ,
+-- , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "8000",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|v_enable_sig\,
+ datab => \vga_control_unit|toggle_sig\,
+ datac => \vga_control_unit|b_next_0_sqmuxa_7_4\,
+ datad => \vga_control_unit|b_next_0_sqmuxa_7_5\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|r\);
+
+\~STRATIX_FITTER_CREATED_GND~I\ : stratix_lcell
+-- Equation(s):
+-- \~STRATIX_FITTER_CREATED_GND~I_combout\ = GND
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \~STRATIX_FITTER_CREATED_GND~I_combout\);
+
+\vga_control_unit|b_Z\ : stratix_lcell
+-- Equation(s):
+-- \vga_control_unit|b\ = DFFEAS(\vga_driver_unit|v_enable_sig\ & !\vga_control_unit|toggle_sig\ & \vga_control_unit|b_next_0_sqmuxa_7_4\ & \vga_control_unit|b_next_0_sqmuxa_7_5\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , ,
+-- , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "2000",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => \vga_driver_unit|v_enable_sig\,
+ datab => \vga_control_unit|toggle_sig\,
+ datac => \vga_control_unit|b_next_0_sqmuxa_7_4\,
+ datad => \vga_control_unit|b_next_0_sqmuxa_7_5\,
+ aclr => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_control_unit|b\);
+
+\vga_driver_unit|un1_hsync_state_3_0_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_hsync_state_3_0\ = \vga_driver_unit|hsync_state_3\ # \vga_driver_unit|hsync_state_1\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "fcfc",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ datab => \vga_driver_unit|hsync_state_3\,
+ datac => \vga_driver_unit|hsync_state_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_hsync_state_3_0\);
+
+\vga_driver_unit|h_sync_1_0_0_0_g1_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|h_sync_1_0_0_0_g1\ = \vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|un1_hsync_state_3_0\ &
+-- \vga_driver_unit|hsync_state_4\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "fe04",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|hsync_state_2\,
+ datab => \vga_driver_unit|hsync_state_4\,
+ datac => \vga_driver_unit|un1_hsync_state_3_0\,
+ datad => \vga_driver_unit|h_sync\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|h_sync_1_0_0_0_g1\);
+
+\vga_driver_unit|h_sync_Z\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|h_sync\ = DFFEAS(\vga_driver_unit|h_sync_1_0_0_0_g1\ # !dly_counter(0) # !\reset_pin~combout\ # !dly_counter(1), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ff7f",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => dly_counter(1),
+ datab => \reset_pin~combout\,
+ datac => dly_counter(0),
+ datad => \vga_driver_unit|h_sync_1_0_0_0_g1\,
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|h_sync\);
+
+\vga_driver_unit|un1_vsync_state_2_0_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|un1_vsync_state_2_0\ = \vga_driver_unit|vsync_state_3\ # \vga_driver_unit|vsync_state_1\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "ffaa",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_state_3\,
+ datad => \vga_driver_unit|vsync_state_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|un1_vsync_state_2_0\);
+
+\vga_driver_unit|v_sync_1_0_0_0_g1_cZ\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|v_sync_1_0_0_0_g1\ = \vga_driver_unit|vsync_state_2\ & (\vga_driver_unit|v_sync\) # !\vga_driver_unit|vsync_state_2\ & (\vga_driver_unit|un1_vsync_state_2_0\ & (\vga_driver_unit|v_sync\) # !\vga_driver_unit|un1_vsync_state_2_0\ &
+-- \vga_driver_unit|vsync_state_4\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "fe02",
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ dataa => \vga_driver_unit|vsync_state_4\,
+ datab => \vga_driver_unit|vsync_state_2\,
+ datac => \vga_driver_unit|un1_vsync_state_2_0\,
+ datad => \vga_driver_unit|v_sync\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ combout => \vga_driver_unit|v_sync_1_0_0_0_g1\);
+
+\vga_driver_unit|v_sync_Z\ : stratix_lcell
+-- Equation(s):
+-- \vga_driver_unit|v_sync\ = DFFEAS(\vga_driver_unit|v_sync_1_0_0_0_g1\ # !dly_counter(1) # !\reset_pin~combout\ # !dly_counter(0), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "dfff",
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ register_cascade_mode => "off",
+ sum_lutc_input => "datac",
+ synch_mode => "off")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk_pin~combout\,
+ dataa => dly_counter(0),
+ datab => \vga_driver_unit|v_sync_1_0_0_0_g1\,
+ datac => \reset_pin~combout\,
+ datad => dly_counter(1),
+ aclr => GND,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \vga_driver_unit|v_sync\);
+
+r0_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|r\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_r0_pin);
+
+r1_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|r\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_r1_pin);
+
+r2_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|r\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_r2_pin);
+
+g0_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_g0_pin);
+
+g1_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_g1_pin);
+
+g2_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_g2_pin);
+
+b0_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|b\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_b0_pin);
+
+b1_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|b\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_b1_pin);
+
+hsync_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|h_sync\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_hsync_pin);
+
+vsync_pin_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|v_sync\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_vsync_pin);
+
+\seven_seg_pin_tri_0_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(0));
+
+\seven_seg_pin_out_1_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(1));
+
+\seven_seg_pin_out_2_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(2));
+
+\seven_seg_pin_tri_3_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(3));
+
+\seven_seg_pin_tri_4_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(4));
+
+\seven_seg_pin_tri_5_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(5));
+
+\seven_seg_pin_tri_6_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(6));
+
+\seven_seg_pin_out_7_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(7));
+
+\seven_seg_pin_out_8_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(8));
+
+\seven_seg_pin_out_9_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(9));
+
+\seven_seg_pin_out_10_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(10));
+
+\seven_seg_pin_out_11_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(11));
+
+\seven_seg_pin_out_12_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|un6_dly_counter_0_x\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(12));
+
+\seven_seg_pin_tri_13_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_seven_seg_pin(13));
+
+d_hsync_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|h_sync\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync);
+
+d_vsync_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|v_sync\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync);
+
+\d_column_counter_out_0_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(0));
+
+\d_column_counter_out_1_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(1));
+
+\d_column_counter_out_2_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(2));
+
+\d_column_counter_out_3_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(3));
+
+\d_column_counter_out_4_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(4));
+
+\d_column_counter_out_5_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(5));
+
+\d_column_counter_out_6_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(6));
+
+\d_column_counter_out_7_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(7));
+
+\d_column_counter_out_8_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_8\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(8));
+
+\d_column_counter_out_9_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|column_counter_sig_9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_column_counter(9));
+
+\d_line_counter_out_0_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|line_counter_sig_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_line_counter(0));
+
+\d_line_counter_out_1_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|line_counter_sig_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_line_counter(1));
+
+\d_line_counter_out_2_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|line_counter_sig_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_line_counter(2));
+
+\d_line_counter_out_3_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|line_counter_sig_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_line_counter(3));
+
+\d_line_counter_out_4_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|line_counter_sig_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_line_counter(4));
+
+\d_line_counter_out_5_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|line_counter_sig_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_line_counter(5));
+
+\d_line_counter_out_6_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|line_counter_sig_6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_line_counter(6));
+
+\d_line_counter_out_7_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|line_counter_sig_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_line_counter(7));
+
+\d_line_counter_out_8_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|line_counter_sig_8\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_line_counter(8));
+
+d_set_column_counter_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_state_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_set_column_counter);
+
+d_set_line_counter_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_state_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_set_line_counter);
+
+\d_hsync_counter_out_0_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(0));
+
+\d_hsync_counter_out_1_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(1));
+
+\d_hsync_counter_out_2_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(2));
+
+\d_hsync_counter_out_3_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(3));
+
+\d_hsync_counter_out_4_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(4));
+
+\d_hsync_counter_out_5_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(5));
+
+\d_hsync_counter_out_6_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(6));
+
+\d_hsync_counter_out_7_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(7));
+
+\d_hsync_counter_out_8_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_8\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(8));
+
+\d_hsync_counter_out_9_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_counter_9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_counter(9));
+
+\d_vsync_counter_out_0_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(0));
+
+\d_vsync_counter_out_1_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(1));
+
+\d_vsync_counter_out_2_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(2));
+
+\d_vsync_counter_out_3_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(3));
+
+\d_vsync_counter_out_4_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(4));
+
+\d_vsync_counter_out_5_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(5));
+
+\d_vsync_counter_out_6_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(6));
+
+\d_vsync_counter_out_7_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(7));
+
+\d_vsync_counter_out_8_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_8\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(8));
+
+\d_vsync_counter_out_9_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_counter_9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_counter(9));
+
+d_set_hsync_counter_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|d_set_hsync_counter\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_set_hsync_counter);
+
+d_set_vsync_counter_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|d_set_vsync_counter\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_set_vsync_counter);
+
+d_h_enable_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|h_enable_sig\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_h_enable);
+
+d_v_enable_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|v_enable_sig\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_v_enable);
+
+d_r_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|r\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_r);
+
+d_g_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_g);
+
+d_b_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|b\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_b);
+
+\d_hsync_state_out_6_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_state_6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_state(6));
+
+\d_hsync_state_out_5_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_state_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_state(5));
+
+\d_hsync_state_out_4_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_state_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_state(4));
+
+\d_hsync_state_out_3_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_state_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_state(3));
+
+\d_hsync_state_out_2_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_state_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_state(2));
+
+\d_hsync_state_out_1_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_state_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_state(1));
+
+\d_hsync_state_out_0_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|hsync_state_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_hsync_state(0));
+
+\d_vsync_state_out_6_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_state_6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_state(6));
+
+\d_vsync_state_out_5_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_state_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_state(5));
+
+\d_vsync_state_out_4_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_state_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_state(4));
+
+\d_vsync_state_out_3_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_state_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_state(3));
+
+\d_vsync_state_out_2_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_state_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_state(2));
+
+\d_vsync_state_out_1_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_state_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_state(1));
+
+\d_vsync_state_out_0_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_driver_unit|vsync_state_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_vsync_state(0));
+
+d_state_clk_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \clk_pin~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_state_clk);
+
+d_toggle_out : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_sig\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle);
+
+\d_toggle_counter_out_0_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_0\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(0));
+
+\d_toggle_counter_out_1_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_1\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(1));
+
+\d_toggle_counter_out_2_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_2\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(2));
+
+\d_toggle_counter_out_3_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_3\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(3));
+
+\d_toggle_counter_out_4_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_4\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(4));
+
+\d_toggle_counter_out_5_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_5\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(5));
+
+\d_toggle_counter_out_6_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_6\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(6));
+
+\d_toggle_counter_out_7_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_7\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(7));
+
+\d_toggle_counter_out_8_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_8\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(8));
+
+\d_toggle_counter_out_9_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_9\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(9));
+
+\d_toggle_counter_out_10_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_10\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(10));
+
+\d_toggle_counter_out_11_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_11\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(11));
+
+\d_toggle_counter_out_12_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_12\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(12));
+
+\d_toggle_counter_out_13_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_13\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(13));
+
+\d_toggle_counter_out_14_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_14\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(14));
+
+\d_toggle_counter_out_15_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_15\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(15));
+
+\d_toggle_counter_out_16_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_16\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(16));
+
+\d_toggle_counter_out_17_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_17\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(17));
+
+\d_toggle_counter_out_18_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_18\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(18));
+
+\d_toggle_counter_out_19_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_19\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(19));
+
+\d_toggle_counter_out_20_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \vga_control_unit|toggle_counter_sig_20\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(20));
+
+\d_toggle_counter_out_21_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(21));
+
+\d_toggle_counter_out_22_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(22));
+
+\d_toggle_counter_out_23_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(23));
+
+\d_toggle_counter_out_24_\ : stratix_io
+-- pragma translate_off
+GENERIC MAP (
+ ddio_mode => "none",
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_d_toggle_counter(24));
+END structure;
+
+
--- /dev/null
+vendor_name = ModelSim
+source_file = 1, /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm
+source_file = 1, /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/db/vga.cbx.xml
+design_name = vga
+instance = comp, \dly_counter_0_\, dly_counter_0_, vga, 1
+instance = comp, \dly_counter_1_\, dly_counter_1_, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_6_\, vga_driver_unit|vsync_state_6_, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_6_\, vga_driver_unit|hsync_state_6_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_0_\, vga_driver_unit|hsync_counter_0_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_1_\, vga_driver_unit|hsync_counter_1_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_2_\, vga_driver_unit|hsync_counter_2_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_3_\, vga_driver_unit|hsync_counter_3_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_4_\, vga_driver_unit|hsync_counter_4_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_5_\, vga_driver_unit|hsync_counter_5_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_6_\, vga_driver_unit|hsync_counter_6_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_7_\, vga_driver_unit|hsync_counter_7_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_8_\, vga_driver_unit|hsync_counter_8_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_9_\, vga_driver_unit|hsync_counter_9_, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3\, vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7\, vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9\, vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9, vga, 1
+instance = comp, \vga_driver_unit|G_2\, vga_driver_unit|G_2, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2\, vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter\, vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3\, vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2\, vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1\, vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_5_\, vga_driver_unit|hsync_state_5_, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4\, vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3\, vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_4_\, vga_driver_unit|hsync_state_4_, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_1_\, vga_driver_unit|hsync_state_1_, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_3_\, vga_driver_unit|hsync_state_3_, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ\, vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ\, vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ\, vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_0_\, vga_driver_unit|hsync_state_0_, vga, 1
+instance = comp, \vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ\, vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4\, vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3\, vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3, vga, 1
+instance = comp, \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter\, vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter, vga, 1
+instance = comp, \vga_driver_unit|hsync_state_2_\, vga_driver_unit|hsync_state_2_, vga, 1
+instance = comp, \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ\, vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ, vga, 1
+instance = comp, \vga_driver_unit|v_enable_sig_Z\, vga_driver_unit|v_enable_sig_Z, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_0_\, vga_control_unit|toggle_counter_sig_0_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_1_\, vga_control_unit|toggle_counter_sig_1_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_3_\, vga_control_unit|toggle_counter_sig_3_, vga, 1
+instance = comp, \vga_control_unit|un2_toggle_counter_next_0_\, vga_control_unit|un2_toggle_counter_next_0_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_2_\, vga_control_unit|toggle_counter_sig_2_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_4_\, vga_control_unit|toggle_counter_sig_4_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_5_\, vga_control_unit|toggle_counter_sig_5_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_7_\, vga_control_unit|toggle_counter_sig_7_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_6_\, vga_control_unit|toggle_counter_sig_6_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_8_\, vga_control_unit|toggle_counter_sig_8_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_9_\, vga_control_unit|toggle_counter_sig_9_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_11_\, vga_control_unit|toggle_counter_sig_11_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_10_\, vga_control_unit|toggle_counter_sig_10_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_13_\, vga_control_unit|toggle_counter_sig_13_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_12_\, vga_control_unit|toggle_counter_sig_12_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_15_\, vga_control_unit|toggle_counter_sig_15_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_14_\, vga_control_unit|toggle_counter_sig_14_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_16_\, vga_control_unit|toggle_counter_sig_16_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_17_\, vga_control_unit|toggle_counter_sig_17_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_19_\, vga_control_unit|toggle_counter_sig_19_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_18_\, vga_control_unit|toggle_counter_sig_18_, vga, 1
+instance = comp, \vga_control_unit|toggle_counter_sig_20_\, vga_control_unit|toggle_counter_sig_20_, vga, 1
+instance = comp, \vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6\, vga_control_unit|BLINKER_next_un1_toggle_counter_siglt6, vga, 1
+instance = comp, \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9\, vga_control_unit|BLINKER_next_un1_toggle_counter_siglto9, vga, 1
+instance = comp, \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12\, vga_control_unit|BLINKER_next_un1_toggle_counter_siglto12, vga, 1
+instance = comp, \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15\, vga_control_unit|BLINKER_next_un1_toggle_counter_siglto15, vga, 1
+instance = comp, \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18\, vga_control_unit|BLINKER_next_un1_toggle_counter_siglto18, vga, 1
+instance = comp, \vga_control_unit|toggle_sig_0_0_0_g1_cZ\, vga_control_unit|toggle_sig_0_0_0_g1_cZ, vga, 1
+instance = comp, \vga_control_unit|toggle_sig_Z\, vga_control_unit|toggle_sig_Z, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_0_\, vga_driver_unit|vsync_counter_0_, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_1_\, vga_driver_unit|vsync_counter_1_, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_2_\, vga_driver_unit|vsync_counter_2_, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_3_\, vga_driver_unit|vsync_counter_3_, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_4_\, vga_driver_unit|vsync_counter_4_, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_5_\, vga_driver_unit|vsync_counter_5_, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6\, vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_6_\, vga_driver_unit|vsync_counter_6_, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_7_\, vga_driver_unit|vsync_counter_7_, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_8_\, vga_driver_unit|vsync_counter_8_, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_9_\, vga_driver_unit|vsync_counter_9_, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5\, vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9\, vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9, vga, 1
+instance = comp, \vga_driver_unit|G_16\, vga_driver_unit|G_16, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_5_\, vga_driver_unit|vsync_state_5_, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6\, vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8\, vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ\, vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_3_\, vga_driver_unit|vsync_state_3_, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_2_\, vga_driver_unit|vsync_state_2_, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3\, vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4\, vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_4_\, vga_driver_unit|vsync_state_4_, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3\, vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4\, vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ\, vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ, vga, 1
+instance = comp, \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ\, vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_next_2_sqmuxa_cZ\, vga_driver_unit|vsync_state_next_2_sqmuxa_cZ, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\, vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_0_\, vga_driver_unit|vsync_state_0_, vga, 1
+instance = comp, \vga_driver_unit|d_set_vsync_counter_cZ\, vga_driver_unit|d_set_vsync_counter_cZ, vga, 1
+instance = comp, \vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ\, vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ, vga, 1
+instance = comp, \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7\, vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7, vga, 1
+instance = comp, \vga_driver_unit|vsync_state_1_\, vga_driver_unit|vsync_state_1_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ\, vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_1_\, vga_driver_unit|un1_line_counter_sig_1_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_sig_0_\, vga_driver_unit|line_counter_sig_0_, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_a_1_\, vga_driver_unit|un1_line_counter_sig_a_1_, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_2_\, vga_driver_unit|un1_line_counter_sig_2_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_sig_1_\, vga_driver_unit|line_counter_sig_1_, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_3_\, vga_driver_unit|un1_line_counter_sig_3_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_sig_2_\, vga_driver_unit|line_counter_sig_2_, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_4_\, vga_driver_unit|un1_line_counter_sig_4_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_sig_3_\, vga_driver_unit|line_counter_sig_3_, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_5_\, vga_driver_unit|un1_line_counter_sig_5_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_sig_4_\, vga_driver_unit|line_counter_sig_4_, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_6_\, vga_driver_unit|un1_line_counter_sig_6_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_sig_5_\, vga_driver_unit|line_counter_sig_5_, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_7_\, vga_driver_unit|un1_line_counter_sig_7_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_sig_6_\, vga_driver_unit|line_counter_sig_6_, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_8_\, vga_driver_unit|un1_line_counter_sig_8_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_sig_7_\, vga_driver_unit|line_counter_sig_7_, vga, 1
+instance = comp, \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2\, vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2, vga, 1
+instance = comp, \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5\, vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5, vga, 1
+instance = comp, \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8\, vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8, vga, 1
+instance = comp, \vga_driver_unit|un1_line_counter_sig_9_\, vga_driver_unit|un1_line_counter_sig_9_, vga, 1
+instance = comp, \vga_driver_unit|line_counter_sig_8_\, vga_driver_unit|line_counter_sig_8_, vga, 1
+instance = comp, \vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3\, vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto3, vga, 1
+instance = comp, \vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ\, vga_control_unit|b_next_0_sqmuxa_7_4_a_cZ, vga, 1
+instance = comp, \vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0\, vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto4_0, vga, 1
+instance = comp, \vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6\, vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto6, vga, 1
+instance = comp, \vga_control_unit|b_next_0_sqmuxa_7_4_cZ\, vga_control_unit|b_next_0_sqmuxa_7_4_cZ, vga, 1
+instance = comp, \vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ\, vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_0_\, vga_driver_unit|column_counter_sig_0_, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_1_\, vga_driver_unit|un2_column_counter_next_1_, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_1_\, vga_driver_unit|column_counter_sig_1_, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_3_\, vga_driver_unit|un2_column_counter_next_3_, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_3_\, vga_driver_unit|column_counter_sig_3_, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_0_\, vga_driver_unit|un2_column_counter_next_0_, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_2_\, vga_driver_unit|un2_column_counter_next_2_, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_2_\, vga_driver_unit|column_counter_sig_2_, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_5_\, vga_driver_unit|un2_column_counter_next_5_, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_5_\, vga_driver_unit|column_counter_sig_5_, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_4_\, vga_driver_unit|un2_column_counter_next_4_, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_4_\, vga_driver_unit|column_counter_sig_4_, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_6_\, vga_driver_unit|un2_column_counter_next_6_, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_8_\, vga_driver_unit|un2_column_counter_next_8_, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_8_\, vga_driver_unit|column_counter_sig_8_, vga, 1
+instance = comp, \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4\, vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_4, vga, 1
+instance = comp, \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6\, vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_7_\, vga_driver_unit|un2_column_counter_next_7_, vga, 1
+instance = comp, \vga_driver_unit|un2_column_counter_next_9_\, vga_driver_unit|un2_column_counter_next_9_, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_9_\, vga_driver_unit|column_counter_sig_9_, vga, 1
+instance = comp, \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9\, vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_7_\, vga_driver_unit|column_counter_sig_7_, vga, 1
+instance = comp, \vga_driver_unit|column_counter_sig_6_\, vga_driver_unit|column_counter_sig_6_, vga, 1
+instance = comp, \vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2\, vga_control_unit|DRAW_SQUARE_next_un5_v_enablelt2, vga, 1
+instance = comp, \vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5\, vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5, vga, 1
+instance = comp, \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ\, vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ, vga, 1
+instance = comp, \vga_driver_unit|h_enable_sig_Z\, vga_driver_unit|h_enable_sig_Z, vga, 1
+instance = comp, \vga_control_unit|b_next_0_sqmuxa_7_2_cZ\, vga_control_unit|b_next_0_sqmuxa_7_2_cZ, vga, 1
+instance = comp, \vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4\, vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto4, vga, 1
+instance = comp, \vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6\, vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6, vga, 1
+instance = comp, \vga_control_unit|b_next_0_sqmuxa_7_3_cZ\, vga_control_unit|b_next_0_sqmuxa_7_3_cZ, vga, 1
+instance = comp, \vga_control_unit|b_next_0_sqmuxa_7_5_cZ\, vga_control_unit|b_next_0_sqmuxa_7_5_cZ, vga, 1
+instance = comp, \vga_control_unit|r_Z\, vga_control_unit|r_Z, vga, 1
+instance = comp, \~STRATIX_FITTER_CREATED_GND~I\, ~STRATIX_FITTER_CREATED_GND~I, vga, 1
+instance = comp, \vga_control_unit|b_Z\, vga_control_unit|b_Z, vga, 1
+instance = comp, \vga_driver_unit|un1_hsync_state_3_0_cZ\, vga_driver_unit|un1_hsync_state_3_0_cZ, vga, 1
+instance = comp, \vga_driver_unit|h_sync_1_0_0_0_g1_cZ\, vga_driver_unit|h_sync_1_0_0_0_g1_cZ, vga, 1
+instance = comp, \vga_driver_unit|h_sync_Z\, vga_driver_unit|h_sync_Z, vga, 1
+instance = comp, \vga_driver_unit|un1_vsync_state_2_0_cZ\, vga_driver_unit|un1_vsync_state_2_0_cZ, vga, 1
+instance = comp, \vga_driver_unit|v_sync_1_0_0_0_g1_cZ\, vga_driver_unit|v_sync_1_0_0_0_g1_cZ, vga, 1
+instance = comp, \vga_driver_unit|v_sync_Z\, vga_driver_unit|v_sync_Z, vga, 1
+instance = comp, \seven_seg_pin_tri_0_\, seven_seg_pin_tri_0_, vga, 1
+instance = comp, \seven_seg_pin_out_1_\, seven_seg_pin_out_1_, vga, 1
+instance = comp, \seven_seg_pin_out_2_\, seven_seg_pin_out_2_, vga, 1
+instance = comp, \seven_seg_pin_tri_3_\, seven_seg_pin_tri_3_, vga, 1
+instance = comp, \seven_seg_pin_tri_4_\, seven_seg_pin_tri_4_, vga, 1
+instance = comp, \seven_seg_pin_tri_5_\, seven_seg_pin_tri_5_, vga, 1
+instance = comp, \seven_seg_pin_tri_6_\, seven_seg_pin_tri_6_, vga, 1
+instance = comp, \seven_seg_pin_out_7_\, seven_seg_pin_out_7_, vga, 1
+instance = comp, \seven_seg_pin_out_8_\, seven_seg_pin_out_8_, vga, 1
+instance = comp, \seven_seg_pin_out_9_\, seven_seg_pin_out_9_, vga, 1
+instance = comp, \seven_seg_pin_out_10_\, seven_seg_pin_out_10_, vga, 1
+instance = comp, \seven_seg_pin_out_11_\, seven_seg_pin_out_11_, vga, 1
+instance = comp, \seven_seg_pin_out_12_\, seven_seg_pin_out_12_, vga, 1
+instance = comp, \seven_seg_pin_tri_13_\, seven_seg_pin_tri_13_, vga, 1
+instance = comp, \d_column_counter_out_0_\, d_column_counter_out_0_, vga, 1
+instance = comp, \d_column_counter_out_1_\, d_column_counter_out_1_, vga, 1
+instance = comp, \d_column_counter_out_2_\, d_column_counter_out_2_, vga, 1
+instance = comp, \d_column_counter_out_3_\, d_column_counter_out_3_, vga, 1
+instance = comp, \d_column_counter_out_4_\, d_column_counter_out_4_, vga, 1
+instance = comp, \d_column_counter_out_5_\, d_column_counter_out_5_, vga, 1
+instance = comp, \d_column_counter_out_6_\, d_column_counter_out_6_, vga, 1
+instance = comp, \d_column_counter_out_7_\, d_column_counter_out_7_, vga, 1
+instance = comp, \d_column_counter_out_8_\, d_column_counter_out_8_, vga, 1
+instance = comp, \d_column_counter_out_9_\, d_column_counter_out_9_, vga, 1
+instance = comp, \d_line_counter_out_0_\, d_line_counter_out_0_, vga, 1
+instance = comp, \d_line_counter_out_1_\, d_line_counter_out_1_, vga, 1
+instance = comp, \d_line_counter_out_2_\, d_line_counter_out_2_, vga, 1
+instance = comp, \d_line_counter_out_3_\, d_line_counter_out_3_, vga, 1
+instance = comp, \d_line_counter_out_4_\, d_line_counter_out_4_, vga, 1
+instance = comp, \d_line_counter_out_5_\, d_line_counter_out_5_, vga, 1
+instance = comp, \d_line_counter_out_6_\, d_line_counter_out_6_, vga, 1
+instance = comp, \d_line_counter_out_7_\, d_line_counter_out_7_, vga, 1
+instance = comp, \d_line_counter_out_8_\, d_line_counter_out_8_, vga, 1
+instance = comp, \d_hsync_counter_out_0_\, d_hsync_counter_out_0_, vga, 1
+instance = comp, \d_hsync_counter_out_1_\, d_hsync_counter_out_1_, vga, 1
+instance = comp, \d_hsync_counter_out_2_\, d_hsync_counter_out_2_, vga, 1
+instance = comp, \d_hsync_counter_out_3_\, d_hsync_counter_out_3_, vga, 1
+instance = comp, \d_hsync_counter_out_4_\, d_hsync_counter_out_4_, vga, 1
+instance = comp, \d_hsync_counter_out_5_\, d_hsync_counter_out_5_, vga, 1
+instance = comp, \d_hsync_counter_out_6_\, d_hsync_counter_out_6_, vga, 1
+instance = comp, \d_hsync_counter_out_7_\, d_hsync_counter_out_7_, vga, 1
+instance = comp, \d_hsync_counter_out_8_\, d_hsync_counter_out_8_, vga, 1
+instance = comp, \d_hsync_counter_out_9_\, d_hsync_counter_out_9_, vga, 1
+instance = comp, \d_vsync_counter_out_0_\, d_vsync_counter_out_0_, vga, 1
+instance = comp, \d_vsync_counter_out_1_\, d_vsync_counter_out_1_, vga, 1
+instance = comp, \d_vsync_counter_out_2_\, d_vsync_counter_out_2_, vga, 1
+instance = comp, \d_vsync_counter_out_3_\, d_vsync_counter_out_3_, vga, 1
+instance = comp, \d_vsync_counter_out_4_\, d_vsync_counter_out_4_, vga, 1
+instance = comp, \d_vsync_counter_out_5_\, d_vsync_counter_out_5_, vga, 1
+instance = comp, \d_vsync_counter_out_6_\, d_vsync_counter_out_6_, vga, 1
+instance = comp, \d_vsync_counter_out_7_\, d_vsync_counter_out_7_, vga, 1
+instance = comp, \d_vsync_counter_out_8_\, d_vsync_counter_out_8_, vga, 1
+instance = comp, \d_vsync_counter_out_9_\, d_vsync_counter_out_9_, vga, 1
+instance = comp, \d_hsync_state_out_6_\, d_hsync_state_out_6_, vga, 1
+instance = comp, \d_hsync_state_out_5_\, d_hsync_state_out_5_, vga, 1
+instance = comp, \d_hsync_state_out_4_\, d_hsync_state_out_4_, vga, 1
+instance = comp, \d_hsync_state_out_3_\, d_hsync_state_out_3_, vga, 1
+instance = comp, \d_hsync_state_out_2_\, d_hsync_state_out_2_, vga, 1
+instance = comp, \d_hsync_state_out_1_\, d_hsync_state_out_1_, vga, 1
+instance = comp, \d_hsync_state_out_0_\, d_hsync_state_out_0_, vga, 1
+instance = comp, \d_vsync_state_out_6_\, d_vsync_state_out_6_, vga, 1
+instance = comp, \d_vsync_state_out_5_\, d_vsync_state_out_5_, vga, 1
+instance = comp, \d_vsync_state_out_4_\, d_vsync_state_out_4_, vga, 1
+instance = comp, \d_vsync_state_out_3_\, d_vsync_state_out_3_, vga, 1
+instance = comp, \d_vsync_state_out_2_\, d_vsync_state_out_2_, vga, 1
+instance = comp, \d_vsync_state_out_1_\, d_vsync_state_out_1_, vga, 1
+instance = comp, \d_vsync_state_out_0_\, d_vsync_state_out_0_, vga, 1
+instance = comp, \d_toggle_counter_out_0_\, d_toggle_counter_out_0_, vga, 1
+instance = comp, \d_toggle_counter_out_1_\, d_toggle_counter_out_1_, vga, 1
+instance = comp, \d_toggle_counter_out_2_\, d_toggle_counter_out_2_, vga, 1
+instance = comp, \d_toggle_counter_out_3_\, d_toggle_counter_out_3_, vga, 1
+instance = comp, \d_toggle_counter_out_4_\, d_toggle_counter_out_4_, vga, 1
+instance = comp, \d_toggle_counter_out_5_\, d_toggle_counter_out_5_, vga, 1
+instance = comp, \d_toggle_counter_out_6_\, d_toggle_counter_out_6_, vga, 1
+instance = comp, \d_toggle_counter_out_7_\, d_toggle_counter_out_7_, vga, 1
+instance = comp, \d_toggle_counter_out_8_\, d_toggle_counter_out_8_, vga, 1
+instance = comp, \d_toggle_counter_out_9_\, d_toggle_counter_out_9_, vga, 1
+instance = comp, \d_toggle_counter_out_10_\, d_toggle_counter_out_10_, vga, 1
+instance = comp, \d_toggle_counter_out_11_\, d_toggle_counter_out_11_, vga, 1
+instance = comp, \d_toggle_counter_out_12_\, d_toggle_counter_out_12_, vga, 1
+instance = comp, \d_toggle_counter_out_13_\, d_toggle_counter_out_13_, vga, 1
+instance = comp, \d_toggle_counter_out_14_\, d_toggle_counter_out_14_, vga, 1
+instance = comp, \d_toggle_counter_out_15_\, d_toggle_counter_out_15_, vga, 1
+instance = comp, \d_toggle_counter_out_16_\, d_toggle_counter_out_16_, vga, 1
+instance = comp, \d_toggle_counter_out_17_\, d_toggle_counter_out_17_, vga, 1
+instance = comp, \d_toggle_counter_out_18_\, d_toggle_counter_out_18_, vga, 1
+instance = comp, \d_toggle_counter_out_19_\, d_toggle_counter_out_19_, vga, 1
+instance = comp, \d_toggle_counter_out_20_\, d_toggle_counter_out_20_, vga, 1
+instance = comp, \d_toggle_counter_out_21_\, d_toggle_counter_out_21_, vga, 1
+instance = comp, \d_toggle_counter_out_22_\, d_toggle_counter_out_22_, vga, 1
+instance = comp, \d_toggle_counter_out_23_\, d_toggle_counter_out_23_, vga, 1
+instance = comp, \d_toggle_counter_out_24_\, d_toggle_counter_out_24_, vga, 1
--- /dev/null
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+
+
+//
+// Device: Altera EP1S25F672C6 Package FBGA672
+//
+
+//
+// This SDF file should be used for ModelSim (VHDL) only
+//
+
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "vga")
+ (DATE "10/28/2009 14:19:55")
+ (VENDOR "Altera")
+ (PROGRAM "Quartus II")
+ (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version")
+ (DIVIDER .)
+ (TIMESCALE 1 ps)
+
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE clk_pin_in.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (868:868:868) (868:868:868))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE reset_pin_in.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (760:760:760) (760:760:760))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\dly_counter_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1030:1030:1030) (1030:1030:1030))
+ (PORT datac (5264:5264:5264) (5264:5264:5264))
+ (PORT datad (447:447:447) (447:447:447))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\dly_counter_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\dly_counter_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1107:1107:1107) (1107:1107:1107))
+ (PORT datab (2654:2654:2654) (2654:2654:2654))
+ (PORT datac (5010:5010:5010) (5010:5010:5010))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\dly_counter_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (427:427:427) (427:427:427))
+ (PORT datac (5016:5016:5016) (5016:5016:5016))
+ (PORT datad (1088:1088:1088) (1088:1088:1088))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1535:1535:1535) (1535:1535:1535))
+ (PORT datad (1150:1150:1150) (1150:1150:1150))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1625:1625:1625) (1625:1625:1625))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (423:423:423) (423:423:423))
+ (PORT datac (1506:1506:1506) (1506:1506:1506))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1596:1596:1596) (1596:1596:1596))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (1505:1505:1505) (1505:1505:1505))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1595:1595:1595) (1595:1595:1595))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (1503:1503:1503) (1503:1503:1503))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1593:1593:1593) (1593:1593:1593))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (1506:1506:1506) (1506:1506:1506))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1596:1596:1596) (1596:1596:1596))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1509:1509:1509) (1509:1509:1509))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1599:1599:1599) (1599:1599:1599))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (1516:1516:1516) (1516:1516:1516))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1606:1606:1606) (1606:1606:1606))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (422:422:422) (422:422:422))
+ (PORT datac (1514:1514:1514) (1514:1514:1514))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1604:1604:1604) (1604:1604:1604))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (1513:1513:1513) (1513:1513:1513))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1603:1603:1603) (1603:1603:1603))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1513:1513:1513) (1513:1513:1513))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1603:1603:1603) (1603:1603:1603))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1512:1512:1512) (1512:1512:1512))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1602:1602:1602) (1602:1602:1602))
+ (PORT sclr (1861:1861:1861) (1861:1861:1861))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (663:663:663) (663:663:663))
+ (PORT datab (608:608:608) (608:608:608))
+ (PORT datac (653:653:653) (653:653:653))
+ (PORT datad (986:986:986) (986:986:986))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (638:638:638) (638:638:638))
+ (PORT datab (591:591:591) (591:591:591))
+ (PORT datac (641:641:641) (641:641:641))
+ (PORT datad (641:641:641) (641:641:641))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (975:975:975) (975:975:975))
+ (PORT datab (624:624:624) (624:624:624))
+ (PORT datac (366:366:366) (366:366:366))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|G_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (447:447:447) (447:447:447))
+ (PORT datab (1613:1613:1613) (1613:1613:1613))
+ (PORT datac (1074:1074:1074) (1074:1074:1074))
+ (PORT datad (1479:1479:1479) (1479:1479:1479))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (662:662:662) (662:662:662))
+ (PORT datab (626:626:626) (626:626:626))
+ (PORT datac (970:970:970) (970:970:970))
+ (PORT datad (991:991:991) (991:991:991))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (924:924:924) (924:924:924))
+ (PORT datab (609:609:609) (609:609:609))
+ (PORT datac (370:370:370) (370:370:370))
+ (PORT datad (351:351:351) (351:351:351))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (936:936:936) (936:936:936))
+ (PORT datab (924:924:924) (924:924:924))
+ (PORT datac (922:922:922) (922:922:922))
+ (PORT datad (923:923:923) (923:923:923))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (927:927:927) (927:927:927))
+ (PORT datac (921:921:921) (921:921:921))
+ (PORT datad (938:938:938) (938:938:938))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (990:990:990) (990:990:990))
+ (PORT datac (1013:1013:1013) (1013:1013:1013))
+ (PORT datad (1020:1020:1020) (1020:1020:1020))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (447:447:447) (447:447:447))
+ (PORT datac (1641:1641:1641) (1641:1641:1641))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2555:2555:2555) (2555:2555:2555))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2387:2387:2387) (2387:2387:2387))
+ (PORT ena (1796:1796:1796) (1796:1796:1796))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (922:922:922) (922:922:922))
+ (PORT datab (927:927:927) (927:927:927))
+ (PORT datac (958:958:958) (958:958:958))
+ (PORT datad (925:925:925) (925:925:925))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (926:926:926) (926:926:926))
+ (PORT datac (924:924:924) (924:924:924))
+ (PORT datad (938:938:938) (938:938:938))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1226:1226:1226) (1226:1226:1226))
+ (PORT datab (856:856:856) (856:856:856))
+ (PORT datac (1030:1030:1030) (1030:1030:1030))
+ (PORT datad (856:856:856) (856:856:856))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2570:2570:2570) (2570:2570:2570))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (PORT ena (1299:1299:1299) (1299:1299:1299))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (565:565:565) (565:565:565))
+ (PORT datab (565:565:565) (565:565:565))
+ (PORT datac (1029:1029:1029) (1029:1029:1029))
+ (PORT datad (440:440:440) (440:440:440))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2570:2570:2570) (2570:2570:2570))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (PORT ena (1299:1299:1299) (1299:1299:1299))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (984:984:984) (984:984:984))
+ (PORT datab (343:343:343) (343:343:343))
+ (PORT datac (1016:1016:1016) (1016:1016:1016))
+ (PORT datad (353:353:353) (353:353:353))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1106:1106:1106) (1106:1106:1106))
+ (PORT sclr (2308:2308:2308) (2308:2308:2308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (PORT ena (1091:1091:1091) (1091:1091:1091))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1228:1228:1228) (1228:1228:1228))
+ (PORT datab (547:547:547) (547:547:547))
+ (PORT datac (552:552:552) (552:552:552))
+ (PORT datad (1038:1038:1038) (1038:1038:1038))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (638:638:638) (638:638:638))
+ (PORT datab (560:560:560) (560:560:560))
+ (PORT datac (367:367:367) (367:367:367))
+ (PORT datad (1041:1041:1041) (1041:1041:1041))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1544:1544:1544) (1544:1544:1544))
+ (PORT datab (343:343:343) (343:343:343))
+ (PORT datac (562:562:562) (562:562:562))
+ (PORT datad (544:544:544) (544:544:544))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1051:1051:1051) (1051:1051:1051))
+ (PORT datac (1129:1129:1129) (1129:1129:1129))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2555:2555:2555) (2555:2555:2555))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2387:2387:2387) (2387:2387:2387))
+ (PORT ena (1796:1796:1796) (1796:1796:1796))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (5249:5249:5249) (5249:5249:5249))
+ (PORT datab (1448:1448:1448) (1448:1448:1448))
+ (PORT datac (1232:1232:1232) (1232:1232:1232))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (654:654:654) (654:654:654))
+ (PORT datab (622:622:622) (622:622:622))
+ (PORT datac (623:623:623) (623:623:623))
+ (PORT datad (642:642:642) (642:642:642))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (667:667:667) (667:667:667))
+ (PORT datab (592:592:592) (592:592:592))
+ (PORT datac (971:971:971) (971:971:971))
+ (PORT datad (986:986:986) (986:986:986))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (638:638:638) (638:638:638))
+ (PORT datab (624:624:624) (624:624:624))
+ (PORT datac (369:369:369) (369:369:369))
+ (PORT datad (351:351:351) (351:351:351))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (951:951:951) (951:951:951))
+ (PORT datac (561:561:561) (561:561:561))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2570:2570:2570) (2570:2570:2570))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (PORT ena (1299:1299:1299) (1299:1299:1299))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (435:435:435) (435:435:435))
+ (PORT datac (1220:1220:1220) (1220:1220:1220))
+ (PORT datad (1534:1534:1534) (1534:1534:1534))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1196:1196:1196) (1196:1196:1196))
+ (PORT datac (1173:1173:1173) (1173:1173:1173))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2271:2271:2271) (2271:2271:2271))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (PORT ena (1824:1824:1824) (1824:1824:1824))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (441:441:441) (441:441:441))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1149:1149:1149) (1149:1149:1149))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (607:607:607) (607:607:607))
+ (PORT datab (423:423:423) (423:423:423))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (939:939:939) (939:939:939))
+ (PORT datab (419:419:419) (419:419:419))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|un2_toggle_counter_next_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (618:618:618) (618:618:618))
+ (PORT datab (906:906:906) (906:906:906))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (634:634:634) (634:634:634))
+ (PORT datab (889:889:889) (889:889:889))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1348:1348:1348) (1348:1348:1348))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (429:429:429) (429:429:429))
+ (PORT datab (963:963:963) (963:963:963))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1348:1348:1348) (1348:1348:1348))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datab (894:894:894) (894:894:894))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datab (928:928:928) (928:928:928))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (432:432:432) (432:432:432))
+ (PORT datab (908:908:908) (908:908:908))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1348:1348:1348) (1348:1348:1348))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (947:947:947) (947:947:947))
+ (PORT datab (413:413:413) (413:413:413))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (644:644:644) (644:644:644))
+ (IOPATH datab cout (533:533:533) (533:533:533))
+ (IOPATH cin0 cout (219:219:219) (219:219:219))
+ (IOPATH cin1 cout (205:205:205) (205:205:205))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1348:1348:1348) (1348:1348:1348))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datab (922:922:922) (922:922:922))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH datab cout (460:460:460) (460:460:460))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_11_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1371:1371:1371) (1371:1371:1371))
+ (PORT datab (420:420:420) (420:420:420))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_11_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_10_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (607:607:607) (607:607:607))
+ (PORT datab (1355:1355:1355) (1355:1355:1355))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_10_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1852:1852:1852) (1852:1852:1852))
+ (PORT aclr (5079:5079:5079) (5079:5079:5079))
+ (PORT clk (2336:2336:2336) (2336:2336:2336))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_13_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1364:1364:1364) (1364:1364:1364))
+ (PORT datab (422:422:422) (422:422:422))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_13_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_12_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1362:1362:1362) (1362:1362:1362))
+ (PORT datab (419:419:419) (419:419:419))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_12_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1852:1852:1852) (1852:1852:1852))
+ (PORT aclr (5079:5079:5079) (5079:5079:5079))
+ (PORT clk (2336:2336:2336) (2336:2336:2336))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_15_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datab (1360:1360:1360) (1360:1360:1360))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_15_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_14_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (438:438:438) (438:438:438))
+ (PORT datab (1368:1368:1368) (1368:1368:1368))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_14_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1852:1852:1852) (1852:1852:1852))
+ (PORT aclr (5079:5079:5079) (5079:5079:5079))
+ (PORT clk (2336:2336:2336) (2336:2336:2336))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_16_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1370:1370:1370) (1370:1370:1370))
+ (PORT datab (957:957:957) (957:957:957))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_16_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1852:1852:1852) (1852:1852:1852))
+ (PORT aclr (5079:5079:5079) (5079:5079:5079))
+ (PORT clk (2336:2336:2336) (2336:2336:2336))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_17_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datab (1406:1406:1406) (1406:1406:1406))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_17_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_19_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1393:1393:1393) (1393:1393:1393))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_19_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1319:1319:1319) (1319:1319:1319))
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_18_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (439:439:439) (439:439:439))
+ (PORT datab (1365:1365:1365) (1365:1365:1365))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (628:628:628) (628:628:628))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH datab cout (460:460:460) (460:460:460))
+ (IOPATH cin cout (110:110:110) (110:110:110))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_18_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1852:1852:1852) (1852:1852:1852))
+ (PORT aclr (5079:5079:5079) (5079:5079:5079))
+ (PORT clk (2336:2336:2336) (2336:2336:2336))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_20_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_counter_sig_20_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1852:1852:1852) (1852:1852:1852))
+ (PORT aclr (5079:5079:5079) (5079:5079:5079))
+ (PORT clk (2336:2336:2336) (2336:2336:2336))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglt6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (581:581:581) (581:581:581))
+ (PORT datad (599:599:599) (599:599:599))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (605:605:605) (605:605:605))
+ (PORT datab (578:578:578) (578:578:578))
+ (PORT datac (595:595:595) (595:595:595))
+ (PORT datad (363:363:363) (363:363:363))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto12\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (651:651:651) (651:651:651))
+ (PORT datab (1098:1098:1098) (1098:1098:1098))
+ (PORT datac (1137:1137:1137) (1137:1137:1137))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto15\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1111:1111:1111) (1111:1111:1111))
+ (PORT datab (622:622:622) (622:622:622))
+ (PORT datac (679:679:679) (679:679:679))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto18\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1201:1201:1201) (1201:1201:1201))
+ (PORT datab (623:623:623) (623:623:623))
+ (PORT datac (1397:1397:1397) (1397:1397:1397))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_sig_0_0_0_g1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1137:1137:1137) (1137:1137:1137))
+ (PORT datab (635:635:635) (635:635:635))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|toggle_sig_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (438:438:438) (438:438:438))
+ (PORT datad (348:348:348) (348:348:348))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|toggle_sig_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (657:657:657) (657:657:657))
+ (PORT datab (1630:1630:1630) (1630:1630:1630))
+ (PORT datac (692:692:692) (692:692:692))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (782:782:782) (782:782:782))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (696:696:696) (696:696:696))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (786:786:786) (786:786:786))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (699:699:699) (699:699:699))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (789:789:789) (789:789:789))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (702:702:702) (702:702:702))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (792:792:792) (792:792:792))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (704:704:704) (704:704:704))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (794:794:794) (794:794:794))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (709:709:709) (709:709:709))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (799:799:799) (799:799:799))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (628:628:628) (628:628:628))
+ (PORT datab (611:611:611) (611:611:611))
+ (PORT datac (623:623:623) (623:623:623))
+ (PORT datad (937:937:937) (937:937:937))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (416:416:416) (416:416:416))
+ (PORT datac (709:709:709) (709:709:709))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (799:799:799) (799:799:799))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (708:708:708) (708:708:708))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (798:798:798) (798:798:798))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (708:708:708) (708:708:708))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (798:798:798) (798:798:798))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (706:706:706) (706:706:706))
+ (PORT datad (426:426:426) (426:426:426))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1434:1434:1434) (1434:1434:1434))
+ (PORT datac (796:796:796) (796:796:796))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (616:616:616) (616:616:616))
+ (PORT datab (607:607:607) (607:607:607))
+ (PORT datac (925:925:925) (925:925:925))
+ (PORT datad (958:958:958) (958:958:958))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (630:630:630) (630:630:630))
+ (PORT datab (348:348:348) (348:348:348))
+ (PORT datac (934:934:934) (934:934:934))
+ (PORT datad (352:352:352) (352:352:352))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|G_16\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (994:994:994) (994:994:994))
+ (PORT datab (945:945:945) (945:945:945))
+ (PORT datac (1070:1070:1070) (1070:1070:1070))
+ (PORT datad (353:353:353) (353:353:353))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (673:673:673) (673:673:673))
+ (PORT datad (438:438:438) (438:438:438))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1153:1153:1153) (1153:1153:1153))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (PORT ena (1287:1287:1287) (1287:1287:1287))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (634:634:634) (634:634:634))
+ (PORT datab (601:601:601) (601:601:601))
+ (PORT datac (932:932:932) (932:932:932))
+ (PORT datad (643:643:643) (643:643:643))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (377:377:377) (377:377:377))
+ (PORT datad (360:360:360) (360:360:360))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (687:687:687) (687:687:687))
+ (PORT datab (662:662:662) (662:662:662))
+ (PORT datac (993:993:993) (993:993:993))
+ (PORT datad (361:361:361) (361:361:361))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (688:688:688) (688:688:688))
+ (PORT datab (662:662:662) (662:662:662))
+ (PORT datac (1270:1270:1270) (1270:1270:1270))
+ (PORT datad (361:361:361) (361:361:361))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1360:1360:1360) (1360:1360:1360))
+ (PORT sclr (1885:1885:1885) (1885:1885:1885))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (PORT ena (1091:1091:1091) (1091:1091:1091))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (976:976:976) (976:976:976))
+ (PORT datab (990:990:990) (990:990:990))
+ (PORT datac (1023:1023:1023) (1023:1023:1023))
+ (PORT datad (576:576:576) (576:576:576))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1153:1153:1153) (1153:1153:1153))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (PORT ena (1287:1287:1287) (1287:1287:1287))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (630:630:630) (630:630:630))
+ (PORT datab (621:621:621) (621:621:621))
+ (PORT datac (624:624:624) (624:624:624))
+ (PORT datad (622:622:622) (622:622:622))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (930:930:930) (930:930:930))
+ (PORT datac (608:608:608) (608:608:608))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1037:1037:1037) (1037:1037:1037))
+ (PORT datab (987:987:987) (987:987:987))
+ (PORT datac (1025:1025:1025) (1025:1025:1025))
+ (PORT datad (575:575:575) (575:575:575))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1153:1153:1153) (1153:1153:1153))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (PORT ena (1287:1287:1287) (1287:1287:1287))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (657:657:657) (657:657:657))
+ (PORT datab (604:604:604) (604:604:604))
+ (PORT datac (683:683:683) (683:683:683))
+ (PORT datad (633:633:633) (633:633:633))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (639:639:639) (639:639:639))
+ (PORT datac (995:995:995) (995:995:995))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (708:708:708) (708:708:708))
+ (PORT datac (370:370:370) (370:370:370))
+ (PORT datad (360:360:360) (360:360:360))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (369:369:369) (369:369:369))
+ (PORT datab (934:934:934) (934:934:934))
+ (PORT datac (874:874:874) (874:874:874))
+ (PORT datad (348:348:348) (348:348:348))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1116:1116:1116) (1116:1116:1116))
+ (PORT datab (341:341:341) (341:341:341))
+ (PORT datac (371:371:371) (371:371:371))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (432:432:432) (432:432:432))
+ (PORT datac (877:877:877) (877:877:877))
+ (PORT datad (555:555:555) (555:555:555))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (366:366:366) (366:366:366))
+ (PORT datab (430:430:430) (430:430:430))
+ (PORT datac (571:571:571) (571:571:571))
+ (PORT datad (846:846:846) (846:846:846))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|d_set_vsync_counter_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (944:944:944) (944:944:944))
+ (PORT datad (983:983:983) (983:983:983))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (363:363:363) (363:363:363))
+ (PORT datab (2412:2412:2412) (2412:2412:2412))
+ (PORT datac (5264:5264:5264) (5264:5264:5264))
+ (PORT datad (451:451:451) (451:451:451))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (613:613:613) (613:613:613))
+ (PORT datab (626:626:626) (626:626:626))
+ (PORT datac (623:623:623) (623:623:623))
+ (PORT datad (644:644:644) (644:644:644))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1202:1202:1202) (1202:1202:1202))
+ (PORT datab (1172:1172:1172) (1172:1172:1172))
+ (PORT datac (2469:2469:2469) (2469:2469:2469))
+ (PORT datad (2008:2008:2008) (2008:2008:2008))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (5244:5244:5244) (5244:5244:5244))
+ (PORT datab (1216:1216:1216) (1216:1216:1216))
+ (PORT datac (1151:1151:1151) (1151:1151:1151))
+ (PORT datad (1419:1419:1419) (1419:1419:1419))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1160:1160:1160) (1160:1160:1160))
+ (PORT datab (935:935:935) (935:935:935))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (608:608:608) (608:608:608))
+ (PORT datad (851:851:851) (851:851:851))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1996:1996:1996) (1996:1996:1996))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_a_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (658:658:658) (658:658:658))
+ (PORT datab (951:951:951) (951:951:951))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (692:692:692) (692:692:692))
+ (PORT datab (685:685:685) (685:685:685))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (519:519:519) (519:519:519))
+ (PORT datac (601:601:601) (601:601:601))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1996:1996:1996) (1996:1996:1996))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (990:990:990) (990:990:990))
+ (PORT datab (999:999:999) (999:999:999))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (602:602:602) (602:602:602))
+ (PORT datad (846:846:846) (846:846:846))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1996:1996:1996) (1996:1996:1996))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (663:663:663) (663:663:663))
+ (PORT datab (645:645:645) (645:645:645))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (611:611:611) (611:611:611))
+ (PORT datac (540:540:540) (540:540:540))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1996:1996:1996) (1996:1996:1996))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (947:947:947) (947:947:947))
+ (PORT datab (875:875:875) (875:875:875))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (601:601:601) (601:601:601))
+ (PORT datad (341:341:341) (341:341:341))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1703:1703:1703) (1703:1703:1703))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1042:1042:1042) (1042:1042:1042))
+ (PORT datab (666:666:666) (666:666:666))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (354:354:354) (354:354:354))
+ (PORT datac (1110:1110:1110) (1110:1110:1110))
+ (PORT datad (1100:1100:1100) (1100:1100:1100))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1036:1036:1036) (1036:1036:1036))
+ (PORT datab (593:593:593) (593:593:593))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (360:360:360) (360:360:360))
+ (PORT datad (609:609:609) (609:609:609))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1703:1703:1703) (1703:1703:1703))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (718:718:718) (718:718:718))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (553:553:553) (553:553:553))
+ (PORT datad (610:610:610) (610:610:610))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1703:1703:1703) (1703:1703:1703))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (433:433:433) (433:433:433))
+ (PORT datac (444:444:444) (444:444:444))
+ (PORT datad (971:971:971) (971:971:971))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (989:989:989) (989:989:989))
+ (PORT datab (999:999:999) (999:999:999))
+ (PORT datac (868:868:868) (868:868:868))
+ (PORT datad (1026:1026:1026) (1026:1026:1026))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (625:625:625) (625:625:625))
+ (PORT datab (670:670:670) (670:670:670))
+ (PORT datac (735:735:735) (735:735:735))
+ (PORT datad (555:555:555) (555:555:555))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (416:416:416) (416:416:416))
+ (PORT datad (420:420:420) (420:420:420))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (602:602:602) (602:602:602))
+ (PORT datad (253:253:253) (253:253:253))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1703:1703:1703) (1703:1703:1703))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2369:2369:2369) (2369:2369:2369))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelto3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (662:662:662) (662:662:662))
+ (PORT datab (685:685:685) (685:685:685))
+ (PORT datac (944:944:944) (944:944:944))
+ (PORT datad (675:675:675) (675:675:675))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_4_a_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (667:667:667) (667:667:667))
+ (PORT datab (671:671:671) (671:671:671))
+ (PORT datac (364:364:364) (364:364:364))
+ (PORT datad (1028:1028:1028) (1028:1028:1028))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto4_0\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (417:417:417) (417:417:417))
+ (PORT datad (970:970:970) (970:970:970))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1038:1038:1038) (1038:1038:1038))
+ (PORT datab (651:651:651) (651:651:651))
+ (PORT datac (689:689:689) (689:689:689))
+ (PORT datad (558:558:558) (558:558:558))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_4_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (626:626:626) (626:626:626))
+ (PORT datab (721:721:721) (721:721:721))
+ (PORT datac (359:359:359) (359:359:359))
+ (PORT datad (340:340:340) (340:340:340))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1383:1383:1383) (1383:1383:1383))
+ (PORT datab (1010:1010:1010) (1010:1010:1010))
+ (PORT datac (5258:5258:5258) (5258:5258:5258))
+ (PORT datad (455:455:455) (455:455:455))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (441:441:441) (441:441:441))
+ (PORT datad (1121:1121:1121) (1121:1121:1121))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2276:2276:2276) (2276:2276:2276))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2311:2311:2311) (2311:2311:2311))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1142:1142:1142) (1142:1142:1142))
+ (PORT datab (1099:1099:1099) (1099:1099:1099))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1088:1088:1088) (1088:1088:1088))
+ (PORT datad (1118:1118:1118) (1118:1118:1118))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2276:2276:2276) (2276:2276:2276))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2311:2311:2311) (2311:2311:2311))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1183:1183:1183) (1183:1183:1183))
+ (PORT datab (1161:1161:1161) (1161:1161:1161))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1068:1068:1068) (1068:1068:1068))
+ (PORT datad (1153:1153:1153) (1153:1153:1153))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2266:2266:2266) (2266:2266:2266))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2311:2311:2311) (2311:2311:2311))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (651:651:651) (651:651:651))
+ (PORT datab (626:626:626) (626:626:626))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (450:450:450) (450:450:450))
+ (PORT datab (989:989:989) (989:989:989))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (336:336:336) (336:336:336))
+ (PORT datad (1150:1150:1150) (1150:1150:1150))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2266:2266:2266) (2266:2266:2266))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2311:2311:2311) (2311:2311:2311))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (448:448:448) (448:448:448))
+ (PORT datab (1111:1111:1111) (1111:1111:1111))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (351:351:351) (351:351:351))
+ (PORT datac (1102:1102:1102) (1102:1102:1102))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2252:2252:2252) (2252:2252:2252))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (720:720:720) (720:720:720))
+ (PORT datab (1119:1119:1119) (1119:1119:1119))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (362:362:362) (362:362:362))
+ (PORT datad (1154:1154:1154) (1154:1154:1154))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2266:2266:2266) (2266:2266:2266))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2311:2311:2311) (2311:2311:2311))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (639:639:639) (639:639:639))
+ (PORT datab (1135:1135:1135) (1135:1135:1135))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (585:585:585) (585:585:585))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1513:1513:1513) (1513:1513:1513))
+ (PORT datac (549:549:549) (549:549:549))
+ (PORT datad (1118:1118:1118) (1118:1118:1118))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2311:2311:2311) (2311:2311:2311))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1173:1173:1173) (1173:1173:1173))
+ (PORT datab (1101:1101:1101) (1101:1101:1101))
+ (PORT datac (1118:1118:1118) (1118:1118:1118))
+ (PORT datad (1129:1129:1129) (1129:1129:1129))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (448:448:448) (448:448:448))
+ (PORT datab (1108:1108:1108) (1108:1108:1108))
+ (PORT datac (1146:1146:1146) (1146:1146:1146))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1153:1153:1153) (1153:1153:1153))
+ (PORT datab (417:417:417) (417:417:417))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1224:1224:1224) (1224:1224:1224))
+ (PORT datab (422:422:422) (422:422:422))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (343:343:343) (343:343:343))
+ (PORT datac (1106:1106:1106) (1106:1106:1106))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2252:2252:2252) (2252:2252:2252))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2428:2428:2428) (2428:2428:2428))
+ (PORT datab (1196:1196:1196) (1196:1196:1196))
+ (PORT datac (1094:1094:1094) (1094:1094:1094))
+ (PORT datad (1196:1196:1196) (1196:1196:1196))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1469:1469:1469) (1469:1469:1469))
+ (PORT datac (1105:1105:1105) (1105:1105:1105))
+ (PORT datad (354:354:354) (354:354:354))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2319:2319:2319) (2319:2319:2319))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (367:367:367) (367:367:367))
+ (PORT datad (1154:1154:1154) (1154:1154:1154))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2266:2266:2266) (2266:2266:2266))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2311:2311:2311) (2311:2311:2311))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelt2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (450:450:450) (450:450:450))
+ (PORT datab (630:630:630) (630:630:630))
+ (PORT datad (639:639:639) (639:639:639))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto5\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1075:1075:1075) (1075:1075:1075))
+ (PORT datab (1222:1222:1222) (1222:1222:1222))
+ (PORT datac (1189:1189:1189) (1189:1189:1189))
+ (PORT datad (1403:1403:1403) (1403:1403:1403))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1917:1917:1917) (1917:1917:1917))
+ (PORT datac (1598:1598:1598) (1598:1598:1598))
+ (PORT datad (1966:1966:1966) (1966:1966:1966))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (443:443:443) (443:443:443))
+ (PORT datad (1589:1589:1589) (1589:1589:1589))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2747:2747:2747) (2747:2747:2747))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (PORT ena (1082:1082:1082) (1082:1082:1082))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_2_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1512:1512:1512) (1512:1512:1512))
+ (PORT datab (424:424:424) (424:424:424))
+ (PORT datac (1409:1409:1409) (1409:1409:1409))
+ (PORT datad (1197:1197:1197) (1197:1197:1197))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1178:1178:1178) (1178:1178:1178))
+ (PORT datac (1169:1169:1169) (1169:1169:1169))
+ (PORT datad (1226:1226:1226) (1226:1226:1226))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1141:1141:1141) (1141:1141:1141))
+ (PORT datab (1168:1168:1168) (1168:1168:1168))
+ (PORT datad (354:354:354) (354:354:354))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_3_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1206:1206:1206) (1206:1206:1206))
+ (PORT datab (347:347:347) (347:347:347))
+ (PORT datac (1216:1216:1216) (1216:1216:1216))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_5_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1143:1143:1143) (1143:1143:1143))
+ (PORT datab (1204:1204:1204) (1204:1204:1204))
+ (PORT datac (359:359:359) (359:359:359))
+ (PORT datad (253:253:253) (253:253:253))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|r_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1451:1451:1451) (1451:1451:1451))
+ (PORT datab (438:438:438) (438:438:438))
+ (PORT datac (1358:1358:1358) (1358:1358:1358))
+ (PORT datad (925:925:925) (925:925:925))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|r_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1450:1450:1450) (1450:1450:1450))
+ (PORT datab (438:438:438) (438:438:438))
+ (PORT datac (1359:1359:1359) (1359:1359:1359))
+ (PORT datad (927:927:927) (927:927:927))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|b_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5095:5095:5095) (5095:5095:5095))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_hsync_state_3_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (954:954:954) (954:954:954))
+ (PORT datac (447:447:447) (447:447:447))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_sync_1_0_0_0_g1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (443:443:443) (443:443:443))
+ (PORT datab (435:435:435) (435:435:435))
+ (PORT datac (865:865:865) (865:865:865))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1463:1463:1463) (1463:1463:1463))
+ (PORT datab (4923:4923:4923) (4923:4923:4923))
+ (PORT datac (1265:1265:1265) (1265:1265:1265))
+ (PORT datad (352:352:352) (352:352:352))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2394:2394:2394) (2394:2394:2394))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_vsync_state_2_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (620:620:620) (620:620:620))
+ (PORT datad (1246:1246:1246) (1246:1246:1246))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_sync_1_0_0_0_g1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1374:1374:1374) (1374:1374:1374))
+ (PORT datab (430:430:430) (430:430:430))
+ (PORT datac (378:378:378) (378:378:378))
+ (PORT datad (430:430:430) (430:430:430))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1106:1106:1106) (1106:1106:1106))
+ (PORT datab (550:550:550) (550:550:550))
+ (PORT datac (5013:5013:5013) (5013:5013:5013))
+ (PORT datad (2733:2733:2733) (2733:2733:2733))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2379:2379:2379) (2379:2379:2379))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE r0_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2578:2578:2578) (2578:2578:2578))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE r1_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2886:2886:2886) (2886:2886:2886))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE r2_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2578:2578:2578) (2578:2578:2578))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE g0_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1963:1963:1963) (1963:1963:1963))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE g1_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2024:2024:2024) (2024:2024:2024))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE g2_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2680:2680:2680) (2680:2680:2680))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE b0_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3590:3590:3590) (3590:3590:3590))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE b1_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3525:3525:3525) (3525:3525:3525))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE hsync_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2183:2183:2183) (2183:2183:2183))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE vsync_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2772:2772:2772) (2772:2772:2772))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2024:2024:2024) (2024:2024:2024))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3263:3263:3263) (3263:3263:3263))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2952:2952:2952) (2952:2952:2952))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1963:1963:1963) (1963:1963:1963))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2024:2024:2024) (2024:2024:2024))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2412:2412:2412) (2412:2412:2412))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1963:1963:1963) (1963:1963:1963))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3263:3263:3263) (3263:3263:3263))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2952:2952:2952) (2952:2952:2952))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3263:3263:3263) (3263:3263:3263))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_10_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3227:3227:3227) (3227:3227:3227))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_11_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3099:3099:3099) (3099:3099:3099))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_12_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3260:3260:3260) (3260:3260:3260))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_13_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2412:2412:2412) (2412:2412:2412))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_hsync_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2183:2183:2183) (2183:2183:2183))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_vsync_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2772:2772:2772) (2772:2772:2772))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2437:2437:2437) (2437:2437:2437))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2426:2426:2426) (2426:2426:2426))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2127:2127:2127) (2127:2127:2127))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2378:2378:2378) (2378:2378:2378))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1826:1826:1826) (1826:1826:1826))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3015:3015:3015) (3015:3015:3015))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2573:2573:2573) (2573:2573:2573))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2118:2118:2118) (2118:2118:2118))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2545:2545:2545) (2545:2545:2545))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2104:2104:2104) (2104:2104:2104))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1897:1897:1897) (1897:1897:1897))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1941:1941:1941) (1941:1941:1941))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2564:2564:2564) (2564:2564:2564))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1937:1937:1937) (1937:1937:1937))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2373:2373:2373) (2373:2373:2373))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2612:2612:2612) (2612:2612:2612))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2307:2307:2307) (2307:2307:2307))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2234:2234:2234) (2234:2234:2234))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2444:2444:2444) (2444:2444:2444))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_column_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3234:3234:3234) (3234:3234:3234))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_line_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3161:3161:3161) (3161:3161:3161))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2393:2393:2393) (2393:2393:2393))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3712:3712:3712) (3712:3712:3712))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1994:1994:1994) (1994:1994:1994))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2855:2855:2855) (2855:2855:2855))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3074:3074:3074) (3074:3074:3074))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2173:2173:2173) (2173:2173:2173))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3292:3292:3292) (3292:3292:3292))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2319:2319:2319) (2319:2319:2319))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3000:3000:3000) (3000:3000:3000))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3135:3135:3135) (3135:3135:3135))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1986:1986:1986) (1986:1986:1986))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2411:2411:2411) (2411:2411:2411))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2518:2518:2518) (2518:2518:2518))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2074:2074:2074) (2074:2074:2074))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2588:2588:2588) (2588:2588:2588))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2923:2923:2923) (2923:2923:2923))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2434:2434:2434) (2434:2434:2434))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2473:2473:2473) (2473:2473:2473))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2581:2581:2581) (2581:2581:2581))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1951:1951:1951) (1951:1951:1951))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_hsync_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2415:2415:2415) (2415:2415:2415))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_vsync_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3291:3291:3291) (3291:3291:3291))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_h_enable_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2923:2923:2923) (2923:2923:2923))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_v_enable_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2505:2505:2505) (2505:2505:2505))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_r_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2886:2886:2886) (2886:2886:2886))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_g_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2412:2412:2412) (2412:2412:2412))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_b_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3590:3590:3590) (3590:3590:3590))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2928:2928:2928) (2928:2928:2928))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2651:2651:2651) (2651:2651:2651))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2862:2862:2862) (2862:2862:2862))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2213:2213:2213) (2213:2213:2213))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2164:2164:2164) (2164:2164:2164))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3234:3234:3234) (3234:3234:3234))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1944:1944:1944) (1944:1944:1944))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2658:2658:2658) (2658:2658:2658))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2697:2697:2697) (2697:2697:2697))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3588:3588:3588) (3588:3588:3588))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2596:2596:2596) (2596:2596:2596))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3079:3079:3079) (3079:3079:3079))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3161:3161:3161) (3161:3161:3161))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2936:2936:2936) (2936:2936:2936))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_state_clk_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2635:2635:2635) (2635:2635:2635))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_toggle_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2984:2984:2984) (2984:2984:2984))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1954:1954:1954) (1954:1954:1954))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2344:2344:2344) (2344:2344:2344))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2071:2071:2071) (2071:2071:2071))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3103:3103:3103) (3103:3103:3103))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2140:2140:2140) (2140:2140:2140))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2117:2117:2117) (2117:2117:2117))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2137:2137:2137) (2137:2137:2137))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2366:2366:2366) (2366:2366:2366))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2395:2395:2395) (2395:2395:2395))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2410:2410:2410) (2410:2410:2410))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_10_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2098:2098:2098) (2098:2098:2098))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_11_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3664:3664:3664) (3664:3664:3664))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_12_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2134:2134:2134) (2134:2134:2134))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_13_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2805:2805:2805) (2805:2805:2805))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_14_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2158:2158:2158) (2158:2158:2158))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_15_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1677:1677:1677) (1677:1677:1677))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_16_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2162:2162:2162) (2162:2162:2162))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_17_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2526:2526:2526) (2526:2526:2526))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_18_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2189:2189:2189) (2189:2189:2189))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_19_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2650:2650:2650) (2650:2650:2650))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_20_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2503:2503:2503) (2503:2503:2503))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_21_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2412:2412:2412) (2412:2412:2412))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_22_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1963:1963:1963) (1963:1963:1963))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_23_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2680:2680:2680) (2680:2680:2680))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_toggle_counter_out_24_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2024:2024:2024) (2024:2024:2024))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+)
--- /dev/null
+Assembler report for vga
+Wed Oct 28 14:19:47 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: vga.sof
+ 6. Assembler Device Options: vga.pof
+ 7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Wed Oct 28 14:19:47 2009 ;
+; Revision Name ; vga ;
+; Top-level Entity Name ; vga ;
+; Family ; Stratix ;
+; Device ; EP1S25F672C6 ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option ; Setting ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation ; Off ; Off ;
+; Compression mode ; Off ; Off ;
+; Clock source for configuration device ; Internal ; Internal ;
+; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
+; Divide clock frequency by ; 1 ; 1 ;
+; Auto user code ; Off ; Off ;
+; Use configuration device ; On ; On ;
+; Configuration device ; Auto ; Auto ;
+; Configuration device auto user code ; Off ; Off ;
+; Auto-increment JTAG user code for multiple configuration devices ; On ; On ;
+; Disable CONF_DONE and nSTATUS pull-ups on configuration device ; Off ; Off ;
+; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
+; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
+; Hexadecimal Output File start address ; 0 ; 0 ;
+; Hexadecimal Output File count direction ; Up ; Up ;
+; Release clears before tri-states ; Off ; Off ;
+; Auto-restart configuration after error ; On ; On ;
+; Use Checkered Pattern as Uninitialized RAM Content ; Off ; Off ;
+; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------+
+; Assembler Generated Files ;
++---------------------------+
+; File Name ;
++---------------------------+
+; vga.sof ;
+; vga.pof ;
++---------------------------+
+
+
++-----------------------------------+
+; Assembler Device Options: vga.sof ;
++----------------+------------------+
+; Option ; Setting ;
++----------------+------------------+
+; Device ; EP1S25F672C6 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x002E5931 ;
++----------------+------------------+
+
+
++-----------------------------------+
+; Assembler Device Options: vga.pof ;
++--------------------+--------------+
+; Option ; Setting ;
++--------------------+--------------+
+; Device ; EPC8 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x0BFD1BE5 ;
+; Compression Ratio ; 1 ;
++--------------------+--------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:19:28 2009
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off vga -c vga
+Info: Assembler is generating device programming files
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 269 megabytes
+ Info: Processing ended: Wed Oct 28 14:19:47 2009
+ Info: Elapsed time: 00:00:19
+ Info: Total CPU time (on all processors): 00:00:18
+
+
--- /dev/null
+Wed Oct 28 14:19:56 2009
--- /dev/null
+EDA Netlist Writer report for vga
+Wed Oct 28 14:19:55 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. EDA Netlist Writer Summary
+ 3. Simulation Settings
+ 4. Simulation Generated Files
+ 5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Wed Oct 28 14:19:55 2009 ;
+; Revision Name ; vga ;
+; Top-level Entity Name ; vga ;
+; Family ; Stratix ;
+; Simulation Files Creation ; Successful ;
++---------------------------+---------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings ;
++---------------------------------------------------------------------------------------------------+-----------------+
+; Option ; Setting ;
++---------------------------------------------------------------------------------------------------+-----------------+
+; Tool Name ; ModelSim (VHDL) ;
+; Generate netlist for functional simulation only ; Off ;
+; Time scale ; 1 ps ;
+; Truncate long hierarchy paths ; Off ;
+; Map illegal HDL characters ; Off ;
+; Flatten buses into individual nodes ; Off ;
+; Maintain hierarchy ; Off ;
+; Bring out device-wide set/reset signals as ports ; Off ;
+; Enable glitch filtering ; Off ;
+; Do not write top level VHDL entity ; Off ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
+; Architecture name in VHDL output netlist ; structure ;
+; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
+; Generate third-party EDA tool command script for gate-level simulation ; Off ;
++---------------------------------------------------------------------------------------------------+-----------------+
+
+
++--------------------------------------------------------------------------------------+
+; Simulation Generated Files ;
++--------------------------------------------------------------------------------------+
+; Generated Files ;
++--------------------------------------------------------------------------------------+
+; /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga.vho ;
+; /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo ;
++--------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II EDA Netlist Writer
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:19:54 2009
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vga -c vga
+Info: Generated files "vga.vho" and "vga_vhd.sdo" in directory "/homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 163 megabytes
+ Info: Processing ended: Wed Oct 28 14:19:55 2009
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+
+
--- /dev/null
+Fitter report for vga
+Wed Oct 28 14:19:24 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Incremental Compilation Preservation Summary
+ 6. Incremental Compilation Partition Settings
+ 7. Incremental Compilation Placement Preservation
+ 8. Pin-Out File
+ 9. Fitter Resource Usage Summary
+ 10. Input Pins
+ 11. Output Pins
+ 12. I/O Bank Usage
+ 13. All Package Pins
+ 14. Output Pin Default Load For Reported TCO
+ 15. Fitter Resource Utilization by Entity
+ 16. Delay Chain Summary
+ 17. Pad To Core Delay Chain Fanout
+ 18. Control Signals
+ 19. Global & Other Fast Signals
+ 20. Non-Global High Fan-Out Signals
+ 21. Interconnect Usage Summary
+ 22. LAB Logic Elements
+ 23. LAB-wide Signals
+ 24. LAB Signals Sourced
+ 25. LAB Signals Sourced Out
+ 26. LAB Distinct Inputs
+ 27. Fitter Device Options
+ 28. Estimated Delay Added for Hold Timing
+ 29. Fitter Messages
+ 30. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------+
+; Fitter Summary ;
++--------------------------+------------------------------------------+
+; Fitter Status ; Successful - Wed Oct 28 14:19:24 2009 ;
+; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
+; Revision Name ; vga ;
+; Top-level Entity Name ; vga ;
+; Family ; Stratix ;
+; Device ; EP1S25F672C6 ;
+; Timing Models ; Final ;
+; Total logic elements ; 173 / 25,660 ( < 1 % ) ;
+; Total pins ; 117 / 474 ( 25 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 1,944,576 ( 0 % ) ;
+; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 2 ( 0 % ) ;
++--------------------------+------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; EP1S25F672C6 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Use smart compilation ; Off ; Off ;
+; Use TimeQuest Timing Analyzer ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate full fit report during ECO compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; On ; On ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Slow Slew Rate ; Off ; Off ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Save Intermediate Fitting Results ; Off ; Off ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 2 ;
+; Maximum allowed ; 2 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 2 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; 1 processor ; 100.0% ;
+; 2 processors ; < 0.1% ;
++----------------------------+-------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++-------------------------+--------------------+
+; Type ; Value ;
++-------------------------+--------------------+
+; Placement ; ;
+; -- Requested ; 0 / 292 ( 0.00 % ) ;
+; -- Achieved ; 0 / 292 ( 0.00 % ) ;
+; ; ;
+; Routing (by Connection) ; ;
+; -- Requested ; 0 / 0 ( 0.00 % ) ;
+; -- Achieved ; 0 / 0 ( 0.00 % ) ;
++-------------------------+--------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+
+
++--------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Top ; 292 ; 0 ; N/A ; Source File ;
++----------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/vga.pin.
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+--------------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+--------------------------------------------------+
+; Total logic elements ; 173 / 25,660 ( < 1 % ) ;
+; -- Combinational with no register ; 90 ;
+; -- Register only ; 0 ;
+; -- Combinational with a register ; 83 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 60 ;
+; -- 3 input functions ; 52 ;
+; -- 2 input functions ; 58 ;
+; -- 1 input functions ; 2 ;
+; -- 0 input functions ; 1 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 120 ;
+; -- arithmetic mode ; 53 ;
+; -- qfbk mode ; 3 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 70 ;
+; -- asynchronous clear/load mode ; 24 ;
+; ; ;
+; Total registers ; 83 / 28,424 ( < 1 % ) ;
+; Total LABs ; 24 / 2,566 ( < 1 % ) ;
+; Logic elements in carry chains ; 61 ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 117 / 474 ( 25 % ) ;
+; -- Clock pins ; 2 / 16 ( 13 % ) ;
+; Global signals ; 2 ;
+; M512s ; 0 / 224 ( 0 % ) ;
+; M4Ks ; 0 / 138 ( 0 % ) ;
+; M-RAMs ; 0 / 2 ( 0 % ) ;
+; Total memory bits ; 0 / 1,944,576 ( 0 % ) ;
+; Total RAM block bits ; 0 / 1,944,576 ( 0 % ) ;
+; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ;
+; PLLs ; 0 / 6 ( 0 % ) ;
+; Global clocks ; 2 / 16 ( 13 % ) ;
+; Regional clocks ; 0 / 16 ( 0 % ) ;
+; Fast regional clocks ; 0 / 8 ( 0 % ) ;
+; SERDES transmitters ; 0 / 78 ( 0 % ) ;
+; SERDES receivers ; 0 / 78 ( 0 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Remote update blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Peak interconnect usage (total/H/V) ; 1% / 2% / 1% ;
+; Maximum fan-out node ; clk_pin ;
+; Maximum fan-out ; 84 ;
+; Highest non-global fan-out signal ; vga_control:vga_control_unit|toggle_sig_0_0_0_g1 ;
+; Highest non-global fan-out ; 22 ;
+; Total fan-out ; 871 ;
+; Average fan-out ; 2.99 ;
++---------------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; clk_pin ; R3 ; 1 ; 0 ; 21 ; 0 ; 84 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; reset_pin ; N2 ; 2 ; 0 ; 27 ; 2 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
+; b0_pin ; AC15 ; 7 ; 50 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; b1_pin ; W15 ; 7 ; 46 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_b ; Y16 ; 7 ; 50 ; 0 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[0] ; B16 ; 4 ; 52 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[1] ; C15 ; 4 ; 50 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[2] ; H16 ; 4 ; 50 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[3] ; F12 ; 9 ; 37 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[4] ; E13 ; 9 ; 37 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[5] ; C16 ; 4 ; 54 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[6] ; D17 ; 4 ; 56 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[7] ; E16 ; 4 ; 54 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[8] ; E14 ; 9 ; 37 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_column_counter[9] ; H18 ; 4 ; 56 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_g ; T4 ; 1 ; 0 ; 15 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_h_enable ; AA13 ; 11 ; 37 ; 0 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync ; AF12 ; 8 ; 33 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[0] ; P8 ; 2 ; 0 ; 28 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[1] ; AB14 ; 11 ; 37 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[2] ; N8 ; 2 ; 0 ; 28 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[3] ; M8 ; 2 ; 0 ; 29 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[4] ; N6 ; 2 ; 0 ; 29 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[5] ; AB12 ; 11 ; 37 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[6] ; P6 ; 1 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[7] ; N21 ; 5 ; 79 ; 28 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[8] ; D16 ; 4 ; 54 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_counter[9] ; AB13 ; 11 ; 37 ; 0 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_state[0] ; M9 ; 2 ; 0 ; 29 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_state[1] ; B10 ; 3 ; 21 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_state[2] ; AA12 ; 11 ; 37 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_state[3] ; F14 ; 9 ; 37 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_state[4] ; R9 ; 1 ; 0 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_state[5] ; B17 ; 4 ; 58 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_hsync_state[6] ; C17 ; 4 ; 58 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_line_counter[0] ; M7 ; 2 ; 0 ; 31 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_line_counter[1] ; H10 ; 3 ; 27 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_line_counter[2] ; G10 ; 3 ; 23 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_line_counter[3] ; AC11 ; 8 ; 27 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_line_counter[4] ; L4 ; 2 ; 0 ; 33 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_line_counter[5] ; L7 ; 2 ; 0 ; 32 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_line_counter[6] ; L6 ; 2 ; 0 ; 32 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_line_counter[7] ; A9 ; 3 ; 21 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_line_counter[8] ; F9 ; 3 ; 21 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_r ; B8 ; 3 ; 14 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_set_column_counter ; D10 ; 3 ; 21 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_set_hsync_counter ; M6 ; 2 ; 0 ; 31 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_set_line_counter ; AA16 ; 7 ; 52 ; 0 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_set_vsync_counter ; Y11 ; 8 ; 29 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_state_clk ; P7 ; 1 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle ; K4 ; 2 ; 0 ; 37 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[0] ; J8 ; 2 ; 0 ; 35 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[10] ; E11 ; 3 ; 31 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[11] ; AA11 ; 8 ; 31 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[12] ; K5 ; 2 ; 0 ; 34 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[13] ; K7 ; 2 ; 0 ; 34 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[14] ; G9 ; 3 ; 23 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[15] ; G11 ; 3 ; 29 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[16] ; D11 ; 3 ; 25 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[17] ; K21 ; 5 ; 79 ; 34 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[18] ; C11 ; 3 ; 25 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[19] ; AD11 ; 8 ; 29 ; 0 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[1] ; K25 ; 5 ; 79 ; 35 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[20] ; G7 ; 3 ; 17 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[21] ; U5 ; 1 ; 0 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[22] ; U7 ; 1 ; 0 ; 14 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[23] ; T25 ; 6 ; 79 ; 15 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[24] ; U22 ; 6 ; 79 ; 14 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[2] ; E9 ; 3 ; 17 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[3] ; F10 ; 3 ; 23 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[4] ; K9 ; 2 ; 0 ; 35 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[5] ; B11 ; 3 ; 29 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[6] ; A10 ; 3 ; 23 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[7] ; K2 ; 2 ; 0 ; 35 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[8] ; K1 ; 2 ; 0 ; 35 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_toggle_counter[9] ; E10 ; 3 ; 23 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_v_enable ; C10 ; 3 ; 21 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync ; L23 ; 5 ; 79 ; 31 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[0] ; M5 ; 2 ; 0 ; 30 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[1] ; E12 ; 9 ; 37 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[2] ; C12 ; 3 ; 33 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[3] ; M22 ; 5 ; 79 ; 30 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[4] ; M23 ; 5 ; 79 ; 30 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[5] ; N7 ; 2 ; 0 ; 29 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[6] ; A12 ; 3 ; 33 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[7] ; L2 ; 2 ; 0 ; 33 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[8] ; F13 ; 9 ; 37 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_counter[9] ; M4 ; 2 ; 0 ; 30 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_state[0] ; F17 ; 4 ; 56 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_state[1] ; AD15 ; 7 ; 52 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_state[2] ; G18 ; 4 ; 58 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_state[3] ; AA14 ; 11 ; 37 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_state[4] ; A17 ; 4 ; 56 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_state[5] ; F15 ; 4 ; 46 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; d_vsync_state[6] ; G17 ; 4 ; 56 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; g0_pin ; U8 ; 1 ; 0 ; 14 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; g1_pin ; U18 ; 6 ; 79 ; 14 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; g2_pin ; T20 ; 6 ; 79 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; hsync_pin ; AD12 ; 8 ; 33 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; r0_pin ; B9 ; 3 ; 17 ; 47 ; 5 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; r1_pin ; E8 ; 3 ; 14 ; 47 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; r2_pin ; A8 ; 3 ; 17 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[0] ; U19 ; 6 ; 79 ; 14 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[10] ; C2 ; 3 ; 3 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[11] ; H6 ; 2 ; 0 ; 41 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[12] ; E7 ; 3 ; 12 ; 47 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[13] ; U6 ; 1 ; 0 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[1] ; A6 ; 3 ; 9 ; 47 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[2] ; L5 ; 2 ; 0 ; 33 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[3] ; U2 ; 1 ; 0 ; 14 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[4] ; U21 ; 6 ; 79 ; 14 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[5] ; T5 ; 1 ; 0 ; 15 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[6] ; U1 ; 1 ; 0 ; 14 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[7] ; F5 ; 3 ; 9 ; 47 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[8] ; L3 ; 2 ; 0 ; 33 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; seven_seg_pin[9] ; A7 ; 3 ; 14 ; 47 ; 4 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
+; vsync_pin ; L22 ; 5 ; 79 ; 31 ; 3 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 10 pF ;
++----------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1 ; 12 / 61 ( 20 % ) ; 3.3V ; -- ;
+; 2 ; 25 / 59 ( 42 % ) ; 3.3V ; -- ;
+; 3 ; 29 / 54 ( 54 % ) ; 3.3V ; -- ;
+; 4 ; 16 / 56 ( 29 % ) ; 3.3V ; -- ;
+; 5 ; 7 / 59 ( 12 % ) ; 3.3V ; -- ;
+; 6 ; 6 / 61 ( 10 % ) ; 3.3V ; -- ;
+; 7 ; 5 / 57 ( 9 % ) ; 3.3V ; -- ;
+; 8 ; 6 / 54 ( 11 % ) ; 3.3V ; -- ;
+; 9 ; 6 / 6 ( 100 % ) ; 3.3V ; -- ;
+; 11 ; 6 / 6 ( 100 % ) ; 3.3V ; -- ;
++----------+------------------+---------------+--------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; Termination ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+
+; A2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; A3 ; 733 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A4 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; A5 ; 725 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A6 ; 717 ; 3 ; seven_seg_pin[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; A7 ; 703 ; 3 ; seven_seg_pin[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; A8 ; 702 ; 3 ; r2_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; A9 ; 695 ; 3 ; d_line_counter[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; A10 ; 684 ; 3 ; d_toggle_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; A11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; A12 ; 656 ; 3 ; d_vsync_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; A13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; A14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; A15 ; 640 ; 4 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; A16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; A17 ; 602 ; 4 ; d_vsync_state[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; A18 ; 589 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A19 ; 579 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A20 ; 571 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A21 ; 564 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A22 ; 554 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; A24 ; 552 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; A25 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AA1 ; 158 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA2 ; 157 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA3 ; 160 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA4 ; 159 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA5 ; 155 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA6 ; 154 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA7 ; 195 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA8 ; 214 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA9 ; 223 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA10 ; 227 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA11 ; 251 ; 8 ; d_toggle_counter[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AA12 ; 269 ; 11 ; d_hsync_state[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AA13 ; 273 ; 11 ; d_h_enable ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AA14 ; 271 ; 11 ; d_vsync_state[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AA15 ; 283 ; 7 ; ^nIO_PULLUP ; ; ; ; -- ; -- ; ; -- ; -- ;
+; AA16 ; 304 ; 7 ; d_set_line_counter ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AA17 ; 316 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA18 ; 324 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA19 ; 334 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA20 ; 344 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA21 ; 350 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AA22 ; 386 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA23 ; 382 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA24 ; 381 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA25 ; 384 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AA26 ; 383 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB1 ; 162 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB2 ; 161 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB3 ; 164 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB4 ; 163 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB5 ; 181 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB6 ; 184 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB7 ; 191 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB8 ; 203 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB9 ; 217 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB10 ; 229 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB11 ; 231 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB12 ; 268 ; 11 ; d_hsync_counter[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AB13 ; 272 ; 11 ; d_hsync_counter[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AB14 ; 270 ; 11 ; d_hsync_counter[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AB15 ; 292 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AB16 ; 309 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB17 ; 322 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB18 ; 323 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AB19 ; 336 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB20 ; 346 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB21 ; 351 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB22 ; 365 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AB23 ; 378 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB24 ; 377 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB25 ; 380 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AB26 ; 379 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AC2 ; 165 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC3 ; 168 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC4 ; 167 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC5 ; 171 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC6 ; 185 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC7 ; 186 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC8 ; 201 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC9 ; 215 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC10 ; 224 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC11 ; 239 ; 8 ; d_line_counter[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AC12 ; 257 ; 8 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; AC13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AC14 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AC15 ; 293 ; 7 ; b0_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AC16 ; 307 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC17 ; 328 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC18 ; 338 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC19 ; 339 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC20 ; 349 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC21 ; 355 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC22 ; 369 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC23 ; 368 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AC24 ; 374 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC25 ; 376 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AC26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AD1 ; 166 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AD2 ; 172 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD3 ; 174 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD4 ; 178 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD5 ; 170 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD6 ; 188 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD7 ; 192 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD8 ; 204 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD9 ; 216 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD10 ; 220 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD11 ; 247 ; 8 ; d_toggle_counter[19] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AD12 ; 256 ; 8 ; hsync_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AD13 ; ; ; VCCG_PLL6 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; AD14 ; ; ; VCCA_PLL6 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; AD15 ; 302 ; 7 ; d_vsync_state[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AD16 ; 310 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD17 ; 329 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD18 ; 335 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD19 ; 337 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD20 ; 353 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD21 ; 354 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AD22 ; 370 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD23 ; 364 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD24 ; 367 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AD25 ; 373 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AD26 ; 375 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; AE1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AE2 ; 173 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE3 ; 179 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE4 ; 176 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE5 ; 187 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AE6 ; 194 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE7 ; 189 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE8 ; 206 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE9 ; 218 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; AE10 ; 222 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE11 ; 232 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE12 ; 259 ; 8 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; AE13 ; ; 11 ; VCC_PLL6_OUTA ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AE14 ; ; ; GNDG_PLL6 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AE15 ; 274 ; 7 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; AE16 ; 313 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE17 ; 319 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE18 ; 330 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE19 ; 340 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE20 ; 343 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE21 ; 352 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE22 ; 363 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE23 ; 366 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE24 ; 371 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE25 ; 358 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AE26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AF2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AF3 ; 183 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF4 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AF5 ; 190 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF6 ; 198 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF7 ; 197 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF8 ; 207 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF9 ; 219 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF10 ; 230 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AF12 ; 258 ; 8 ; d_hsync ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; AF13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AF14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; AF15 ; 276 ; 7 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; AF16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AF17 ; 315 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF18 ; 327 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF19 ; 331 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF20 ; 342 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF21 ; 347 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF22 ; 360 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF23 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; AF24 ; 362 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; AF25 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B2 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B3 ; 740 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B4 ; 736 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B5 ; 730 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B6 ; 716 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B7 ; 709 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B8 ; 704 ; 3 ; d_r ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B9 ; 698 ; 3 ; r0_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B10 ; 694 ; 3 ; d_hsync_state[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B11 ; 667 ; 3 ; d_toggle_counter[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B12 ; 655 ; 3 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; B13 ; ; ; GNDG_PLL5 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B14 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; B15 ; 638 ; 4 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; B16 ; 610 ; 4 ; d_column_counter[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B17 ; 596 ; 4 ; d_hsync_state[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; B18 ; 582 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B19 ; 577 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B20 ; 567 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B21 ; 563 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B22 ; 551 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B23 ; 548 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B24 ; 543 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B25 ; 544 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; B26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; C1 ; 0 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; C2 ; 738 ; 3 ; seven_seg_pin[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; C3 ; 731 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C4 ; 742 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C5 ; 743 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C6 ; 729 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C7 ; 728 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C8 ; 710 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C9 ; 699 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C10 ; 692 ; 3 ; d_v_enable ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; C11 ; 682 ; 3 ; d_toggle_counter[18] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; C12 ; 658 ; 3 ; d_vsync_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; C13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; C14 ; ; ; VCCG_PLL5 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; C15 ; 617 ; 4 ; d_column_counter[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; C16 ; 605 ; 4 ; d_column_counter[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; C17 ; 592 ; 4 ; d_hsync_state[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; C18 ; 581 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C19 ; 573 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C20 ; 559 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C21 ; 566 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C22 ; 556 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C23 ; 550 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C24 ; 547 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; C25 ; 539 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; C26 ; 541 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; D1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; D2 ; 1 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; D3 ; 744 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D4 ; 741 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D5 ; 735 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D6 ; 722 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D7 ; 727 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; D8 ; 712 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D9 ; 696 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; D10 ; 691 ; 3 ; d_set_column_counter ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; D11 ; 683 ; 3 ; d_toggle_counter[16] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; D12 ; 657 ; 3 ; GND+ ; ; ; ; Column I/O ; -- ; ; -- ; -- ;
+; D13 ; ; 9 ; VCC_PLL5_OUTA ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; D14 ; ; ; VCCA_PLL5 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; D15 ; 630 ; 4 ; #TRST ; input ; ; ; -- ; -- ; ; -- ; -- ;
+; D16 ; 604 ; 4 ; d_hsync_counter[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; D17 ; 600 ; 4 ; d_column_counter[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; D18 ; 583 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D19 ; 575 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D20 ; 562 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D21 ; 561 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D22 ; 546 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D23 ; 545 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; D24 ; 538 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; D25 ; 540 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; D26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; E1 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E2 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E5 ; 726 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E6 ; 723 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E7 ; 713 ; 3 ; seven_seg_pin[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; E8 ; 706 ; 3 ; r1_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; E9 ; 697 ; 3 ; d_toggle_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; E10 ; 685 ; 3 ; d_toggle_counter[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; E11 ; 662 ; 3 ; d_toggle_counter[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; E12 ; 646 ; 9 ; d_vsync_counter[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; E13 ; 642 ; 9 ; d_column_counter[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; E14 ; 644 ; 9 ; d_column_counter[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; E15 ; 629 ; 4 ; #TMS ; input ; ; ; -- ; -- ; ; -- ; -- ;
+; E16 ; 607 ; 4 ; d_column_counter[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; E17 ; 597 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E18 ; 586 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E19 ; 578 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E20 ; 576 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E21 ; 569 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E22 ; 549 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; E23 ; 534 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E24 ; 535 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E25 ; 536 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; E26 ; 537 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; F1 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; F2 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; F3 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; F4 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; F5 ; 720 ; 3 ; seven_seg_pin[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F6 ; 719 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F7 ; 707 ; 3 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F8 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; F9 ; 690 ; 3 ; d_line_counter[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F10 ; 687 ; 3 ; d_toggle_counter[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F11 ; 659 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; F12 ; 645 ; 9 ; d_column_counter[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F13 ; 641 ; 9 ; d_vsync_counter[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F14 ; 643 ; 9 ; d_hsync_state[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F15 ; 632 ; 4 ; d_vsync_state[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F16 ; 612 ; 4 ; ~DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F17 ; 599 ; 4 ; d_vsync_state[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; F18 ; 591 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; F19 ; 590 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F20 ; 584 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F21 ; 572 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; F22 ; 560 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; F23 ; 530 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; F24 ; 531 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; F25 ; 532 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; F26 ; 533 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G1 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G2 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G3 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G4 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G5 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G6 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G7 ; 700 ; 3 ; d_toggle_counter[20] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; G8 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; G9 ; 688 ; 3 ; d_toggle_counter[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; G10 ; 686 ; 3 ; d_line_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; G11 ; 670 ; 3 ; d_toggle_counter[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; G12 ; 653 ; 3 ; ^DCLK ; ; ; ; -- ; -- ; ; -- ; -- ;
+; G13 ; ; ; TEMPDIODEn ; ; ; ; -- ; -- ; ; -- ; -- ;
+; G14 ; 636 ; 4 ; #TDO ; output ; ; ; -- ; -- ; ; -- ; -- ;
+; G15 ; 631 ; 4 ; #TCK ; input ; ; ; -- ; -- ; ; -- ; -- ;
+; G16 ; 622 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; G17 ; 601 ; 4 ; d_vsync_state[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; G18 ; 594 ; 4 ; d_vsync_state[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; G19 ; 585 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; G20 ; 587 ; 4 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; G21 ; 522 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G22 ; 523 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G23 ; 526 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G24 ; 527 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G25 ; 528 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; G26 ; 529 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H1 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H2 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H3 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H4 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H5 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H6 ; 23 ; 2 ; seven_seg_pin[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; H7 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H8 ; 20 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; H9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; H10 ; 675 ; 3 ; d_line_counter[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; H11 ; 654 ; 3 ; ^CONF_DONE ; ; ; ; -- ; -- ; ; -- ; -- ;
+; H12 ; 652 ; 3 ; ^nCONFIG ; ; ; ; -- ; -- ; ; -- ; -- ;
+; H13 ; 651 ; 3 ; ^nSTATUS ; ; ; ; -- ; -- ; ; -- ; -- ;
+; H14 ; ; ; TEMPDIODEp ; ; ; ; -- ; -- ; ; -- ; -- ;
+; H15 ; 635 ; 4 ; #TDI ; input ; ; ; -- ; -- ; ; -- ; -- ;
+; H16 ; 621 ; 4 ; d_column_counter[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; H17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; H18 ; 603 ; 4 ; d_column_counter[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; H19 ; 506 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H20 ; 505 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H21 ; 514 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H22 ; 513 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H23 ; 518 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H24 ; 517 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H25 ; 524 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; H26 ; 525 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J1 ; 34 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J2 ; 33 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J3 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J4 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J5 ; 36 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J6 ; 35 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J7 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J8 ; 48 ; 2 ; d_toggle_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; J9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; J12 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; J13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J15 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; J16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; J17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; J18 ; 521 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; J19 ; 494 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J20 ; 493 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J21 ; 504 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J22 ; 503 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J23 ; 512 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J24 ; 511 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J25 ; 508 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; J26 ; 507 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K1 ; 46 ; 2 ; d_toggle_counter[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; K2 ; 45 ; 2 ; d_toggle_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; K3 ; 38 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K4 ; 37 ; 2 ; d_toggle ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; K5 ; 50 ; 2 ; d_toggle_counter[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; K6 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K7 ; 52 ; 2 ; d_toggle_counter[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; K8 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K9 ; 47 ; 2 ; d_toggle_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; K12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; K14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; K16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; K18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; K19 ; 486 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K20 ; 485 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K21 ; 490 ; 5 ; d_toggle_counter[17] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; K22 ; 489 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K23 ; 492 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K24 ; 491 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; K25 ; 496 ; 5 ; d_toggle_counter[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; K26 ; 495 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; L1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; L2 ; 54 ; 2 ; d_vsync_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; L3 ; 53 ; 2 ; seven_seg_pin[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; L4 ; 56 ; 2 ; d_line_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; L5 ; 55 ; 2 ; seven_seg_pin[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; L6 ; 60 ; 2 ; d_line_counter[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; L7 ; 59 ; 2 ; d_line_counter[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; L8 ; 61 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; L9 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; L10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; L12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; L14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; L16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; L18 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; L19 ; 480 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; L20 ; 482 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; L21 ; 481 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; L22 ; 478 ; 5 ; vsync_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; L23 ; 479 ; 5 ; d_vsync ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; L24 ; 488 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; L25 ; 487 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; L26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; M1 ; 81 ; 2 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; M2 ; ; ; VCCG_PLL1 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M3 ; ; ; VCCA_PLL1 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M4 ; 66 ; 2 ; d_vsync_counter[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; M5 ; 67 ; 2 ; d_vsync_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; M6 ; 62 ; 2 ; d_set_hsync_counter ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; M7 ; 63 ; 2 ; d_line_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; M8 ; 72 ; 2 ; d_hsync_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; M9 ; 73 ; 2 ; d_hsync_state[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; M11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; M13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; M15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; M17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; M18 ; 468 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; M19 ; 469 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; M20 ; 470 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; M21 ; 471 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; M22 ; 474 ; 5 ; d_vsync_counter[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; M23 ; 475 ; 5 ; d_vsync_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; M24 ; 462 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; M25 ; 463 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; M26 ; 460 ; 5 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; N1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N2 ; 78 ; 2 ; reset_pin ; input ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; N3 ; 79 ; 2 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; N4 ; ; ; GNDG_PLL1 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N5 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N6 ; 70 ; 2 ; d_hsync_counter[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; N7 ; 71 ; 2 ; d_vsync_counter[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; N8 ; 77 ; 2 ; d_hsync_counter[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N19 ; 453 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; N20 ; 464 ; 5 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; N21 ; 465 ; 5 ; d_hsync_counter[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; N22 ; ; ; GNDG_PLL4 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N23 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; N24 ; ; ; VCCG_PLL4 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N25 ; ; ; VCCA_PLL4 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; N26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P2 ; ; ; GNDG_PLL2 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P3 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P4 ; ; ; VCCG_PLL2 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P5 ; ; ; VCCA_PLL2 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P6 ; 88 ; 1 ; d_hsync_counter[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; P7 ; 89 ; 1 ; d_state_clk ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; P8 ; 76 ; 2 ; d_hsync_counter[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; P19 ; 452 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; P20 ; 448 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; P21 ; 449 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; P22 ; ; ; VCCA_PLL3 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P23 ; ; ; VCCG_PLL3 ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; P24 ; 457 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; P25 ; 458 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; P26 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R1 ; 82 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; R2 ; 83 ; 1 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; R3 ; 84 ; 1 ; clk_pin ; input ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; R4 ; 94 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R5 ; 95 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R6 ; 90 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R7 ; 91 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R8 ; 92 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R9 ; 93 ; 1 ; d_hsync_state[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; R10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R18 ; 443 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; R19 ; 436 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R20 ; 450 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R21 ; 451 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R22 ; 446 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R23 ; 447 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; R24 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R25 ; ; ; GNDG_PLL3 ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; R26 ; 459 ; 6 ; GND+ ; ; ; ; Row I/O ; -- ; ; -- ; -- ;
+; T1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; T2 ; 100 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T3 ; 99 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T4 ; 108 ; 1 ; d_g ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; T5 ; 107 ; 1 ; seven_seg_pin[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; T6 ; 106 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T7 ; 105 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T8 ; 98 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; T9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; T11 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; T13 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; T15 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; T17 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; T18 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; T19 ; 435 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T20 ; 432 ; 6 ; g2_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; T21 ; 431 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T22 ; 442 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T23 ; 441 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T24 ; 434 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; T25 ; 433 ; 6 ; d_toggle_counter[23] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; T26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; U1 ; 112 ; 1 ; seven_seg_pin[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U2 ; 111 ; 1 ; seven_seg_pin[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U3 ; 116 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U4 ; 115 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U5 ; 110 ; 1 ; d_toggle_counter[21] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U6 ; 109 ; 1 ; seven_seg_pin[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U7 ; 114 ; 1 ; d_toggle_counter[22] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U8 ; 113 ; 1 ; g0_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U9 ; 117 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U10 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; U12 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; U14 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; U16 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; U18 ; 428 ; 6 ; g1_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U19 ; 427 ; 6 ; seven_seg_pin[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U20 ; 424 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U21 ; 430 ; 6 ; seven_seg_pin[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U22 ; 429 ; 6 ; d_toggle_counter[24] ; output ; 3.3-V LVTTL ; ; Row I/O ; Off ; N ; no ; Off ;
+; U23 ; 418 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U24 ; 417 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U25 ; 426 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; U26 ; 425 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V1 ; 132 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V2 ; 133 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V3 ; 136 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V4 ; 137 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V5 ; 124 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V6 ; 123 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V7 ; 127 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; V8 ; 118 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V9 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; V12 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; V13 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V15 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; V16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; -- ; ; -- ; -- ;
+; V17 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V18 ; ; ; GND ; gnd ; ; ; -- ; -- ; ; -- ; -- ;
+; V19 ; 423 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V20 ; 414 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; V21 ; 406 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V22 ; 407 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V23 ; 404 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V24 ; 405 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V25 ; 408 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; V26 ; 409 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W1 ; 140 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W2 ; 141 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W3 ; 148 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W4 ; 149 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W5 ; 134 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W6 ; 135 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W7 ; 138 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W8 ; 139 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W9 ; 212 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; W10 ; 228 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; W11 ; 255 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; W12 ; 260 ; 8 ; PLL_ENA ; ; ; ; -- ; -- ; ; -- ; -- ;
+; W13 ; 263 ; 8 ; ^MSEL2 ; ; ; ; -- ; -- ; ; -- ; -- ;
+; W14 ; 279 ; 7 ; ^nCEO ; ; ; ; -- ; -- ; ; -- ; -- ;
+; W15 ; 282 ; 7 ; b1_pin ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; W16 ; 285 ; 7 ; ^PORSEL ; ; ; ; -- ; -- ; ; -- ; -- ;
+; W17 ; 311 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; W18 ; 321 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; W19 ; 402 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W20 ; 403 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W21 ; 394 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W22 ; 395 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W23 ; 392 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W24 ; 393 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W25 ; 400 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; W26 ; 401 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y1 ; 153 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y2 ; 152 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y3 ; 146 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y4 ; 147 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y5 ; 151 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y6 ; 150 ; 1 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y7 ; 156 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; Y8 ; 210 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y9 ; 209 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y10 ; 226 ; 8 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y11 ; 244 ; 8 ; d_set_vsync_counter ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; Y12 ; 261 ; 8 ; ^MSEL0 ; ; ; ; -- ; -- ; ; -- ; -- ;
+; Y13 ; 262 ; 8 ; ^MSEL1 ; ; ; ; -- ; -- ; ; -- ; -- ;
+; Y14 ; 278 ; 7 ; ^nCE ; ; ; ; -- ; -- ; ; -- ; -- ;
+; Y15 ; 284 ; 7 ; ^VCCSEL ; ; ; ; -- ; -- ; ; -- ; -- ;
+; Y16 ; 297 ; 7 ; d_b ; output ; 3.3-V LVTTL ; ; Column I/O ; Off ; N ; no ; Off ;
+; Y17 ; 314 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y18 ; 317 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y19 ; 325 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y20 ; 333 ; 7 ; GND* ; ; ; ; Column I/O ; -- ; ; no ; Off ;
+; Y21 ; 385 ; ; GND ; gnd ; ; ; -- ; -- ; ; no ; Off ;
+; Y22 ; 387 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y23 ; 391 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y24 ; 390 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y25 ; 389 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
+; Y26 ; 388 ; 6 ; GND* ; ; ; ; Row I/O ; -- ; ; no ; Off ;
++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++----------------------------------+-------+------------------------------------+
+; 3.3-V LVTTL ; 10 pF ; Not Available ;
+; 3.3-V LVCMOS ; 10 pF ; Not Available ;
+; 2.5 V ; 10 pF ; Not Available ;
+; 1.8 V ; 10 pF ; Not Available ;
+; 1.5 V ; 10 pF ; Not Available ;
+; GTL ; 30 pF ; 25 Ohm (Parallel) ;
+; GTL+ ; 30 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI-X ; 8 pF ; 25 Ohm (Parallel) ;
+; Compact PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; AGP 1X ; 10 pF ; Not Available ;
+; AGP 2X ; 10 pF ; Not Available ;
+; CTT ; 30 pF ; 50 Ohm (Parallel) ;
+; SSTL-3 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-3 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; 1.5-V HSTL Class I ; 20 pF ; 50 Ohm (Parallel) ;
+; 1.5-V HSTL Class II ; 20 pF ; 25 Ohm (Parallel) ;
+; 1.8-V HSTL Class I ; 20 pF ; 50 Ohm (Parallel) ;
+; 1.8-V HSTL Class II ; 20 pF ; 25 Ohm (Parallel) ;
+; LVDS ; 4 pF ; 100 Ohm (Differential) ;
+; Differential LVPECL ; 4 pF ; 100 Ohm (Differential) ;
+; 3.3-V PCML ; 4 pF ; 50 Ohm (Parallel) ;
+; HyperTransport ; 4 pF ; 100 Ohm (Differential) ;
+; Differential 1.5-V HSTL Class I ; 20 pF ; (See 1.5-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class I ; 20 pF ; (See 1.8-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class II ; 20 pF ; (See 1.8-V HSTL Class II) ;
+; Differential SSTL-2 ; 30 pF ; (See SSTL-2) ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++-----------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++-----------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+
+; |vga ; 173 (3) ; 83 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 117 ; 0 ; 90 (1) ; 0 (0) ; 83 (2) ; 61 (0) ; 3 (0) ; |vga ; work ;
+; |vga_control:vga_control_unit| ; 43 (43) ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 0 (0) ; 24 (24) ; 21 (21) ; 0 (0) ; |vga|vga_control:vga_control_unit ; work ;
+; |vga_driver:vga_driver_unit| ; 127 (127) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 70 (70) ; 0 (0) ; 57 (57) ; 40 (40) ; 3 (3) ; |vga|vga_driver:vga_driver_unit ; work ;
++-----------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; Core to Output Register ; Clock Enable to Output Enable Register ; Clock Enable to Output Register ; Clock Enable to Input Register ; TCO ; TCOE ; Falling Edge Output Enable ;
++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+
+; r0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; r1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; r2_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; g0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; g1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; g2_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; b0_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; b1_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; hsync_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; vsync_pin ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[10] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[11] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[12] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; seven_seg_pin[13] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_column_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_line_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_set_column_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_set_line_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_set_hsync_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_set_vsync_counter ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_h_enable ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_v_enable ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_r ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_g ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_b ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_hsync_state[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_vsync_state[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_state_clk ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[10] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[11] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[12] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[13] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[14] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[15] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[16] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[17] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[18] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[19] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[20] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[21] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[22] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[23] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; d_toggle_counter[24] ; Output ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; OFF ; OFF ;
+; clk_pin ; Input ; ON ; ON ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; reset_pin ; Input ; ON ; ON ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
++----------------------+----------+---------------+---------------+-----------------------+-------------------------+----------------------------------------+---------------------------------+--------------------------------+-----+------+----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-----------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-----------------------------------------------------------------------+-------------------+---------+
+; clk_pin_in ; ; ;
+; reset_pin_in ; ; ;
+; - vga_driver:vga_driver_unit|vsync_state_6_ ; 0 ; ON ;
+; - vga_driver:vga_driver_unit|h_sync_Z ; 0 ; ON ;
+; - vga_driver:vga_driver_unit|v_sync_Z ; 0 ; ON ;
+; - dly_counter_0_ ; 0 ; ON ;
+; - dly_counter_1_ ; 0 ; ON ;
+; - vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ ; 0 ; ON ;
+; - vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ ; 0 ; ON ;
+; - vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ ; 0 ; ON ;
+; - vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ ; 0 ; ON ;
++-----------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++-------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++-------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+; clk_pin ; PIN_R3 ; 84 ; Clock ; yes ; Global Clock ; GCLK3 ;
+; vga_control:vga_control_unit|toggle_sig_0_0_0_g1 ; LC_X32_Y35_N4 ; 22 ; Sync. clear ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|G_16_i ; LC_X35_Y30_N1 ; 10 ; Sync. clear ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|G_2_i ; LC_X37_Y29_N5 ; 10 ; Sync. clear ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; LC_X35_Y30_N5 ; 10 ; Sync. clear ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ; LC_X37_Y35_N2 ; 1 ; Clock enable ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; LC_X37_Y28_N4 ; 6 ; Clock enable ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; LC_X36_Y31_N2 ; 9 ; Sync. clear ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|un6_dly_counter_0_x ; LC_X38_Y30_N2 ; 53 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK12 ;
+; vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; LC_X37_Y28_N9 ; 11 ; Sync. load ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|un9_vsync_counterlt9 ; LC_X35_Y30_N8 ; 11 ; Sync. load ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ; LC_X36_Y28_N6 ; 1 ; Clock enable ; no ; -- ; -- ;
+; vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa ; LC_X37_Y30_N3 ; 5 ; Clock enable ; no ; -- ; -- ;
++-------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++------------------------------------------------+---------------+---------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
++------------------------------------------------+---------------+---------+----------------------+------------------+
+; clk_pin ; PIN_R3 ; 84 ; Global Clock ; GCLK3 ;
+; vga_driver:vga_driver_unit|un6_dly_counter_0_x ; LC_X38_Y30_N2 ; 53 ; Global Clock ; GCLK12 ;
++------------------------------------------------+---------------+---------+----------------------+------------------+
+
+
++-----------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++-------------------------------------------------------------+---------+
+; Name ; Fan-Out ;
++-------------------------------------------------------------+---------+
+; vga_control:vga_control_unit|toggle_sig_0_0_0_g1 ; 22 ;
+; ~STRATIX_FITTER_CREATED_GND~I ; 14 ;
+; vga_driver:vga_driver_unit|un9_vsync_counterlt9 ; 11 ;
+; vga_driver:vga_driver_unit|un9_hsync_counterlt9 ; 11 ;
+; vga_driver:vga_driver_unit|G_16_i ; 10 ;
+; vga_driver:vga_driver_unit|vsync_counter_next_1_sqmuxa ; 10 ;
+; vga_driver:vga_driver_unit|G_2_i ; 10 ;
+; vga_driver:vga_driver_unit|hsync_counter_next_1_sqmuxa ; 10 ;
+; vga_driver:vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; 10 ;
+; vga_driver:vga_driver_unit|un10_column_counter_siglto9 ; 10 ;
+; vga_driver:vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; 9 ;
+; vga_driver:vga_driver_unit|un10_line_counter_siglto8 ; 9 ;
+; dly_counter[1] ; 9 ;
+; dly_counter[0] ; 9 ;
+; reset_pin ; 9 ;
+; vga_driver:vga_driver_unit|vsync_counter_9 ; 9 ;
+; vga_driver:vga_driver_unit|vsync_counter_0 ; 9 ;
+; vga_driver:vga_driver_unit|hsync_counter_7 ; 7 ;
+; vga_driver:vga_driver_unit|hsync_counter_6 ; 7 ;
+; vga_driver:vga_driver_unit|hsync_counter_4 ; 7 ;
+; vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; 6 ;
+; vga_driver:vga_driver_unit|hsync_counter_9 ; 6 ;
+; vga_driver:vga_driver_unit|hsync_counter_8 ; 6 ;
+; vga_driver:vga_driver_unit|hsync_counter_5 ; 6 ;
+; vga_driver:vga_driver_unit|hsync_counter_3 ; 6 ;
+; vga_driver:vga_driver_unit|hsync_counter_2 ; 6 ;
+; vga_driver:vga_driver_unit|hsync_counter_1 ; 6 ;
+; vga_driver:vga_driver_unit|hsync_counter_0 ; 6 ;
+; vga_driver:vga_driver_unit|vsync_state_1 ; 6 ;
+; vga_driver:vga_driver_unit|hsync_state_1 ; 6 ;
+; vga_driver:vga_driver_unit|line_counter_sig_6 ; 6 ;
+; vga_driver:vga_driver_unit|line_counter_sig_5 ; 6 ;
+; vga_driver:vga_driver_unit|line_counter_sig_4 ; 6 ;
+; vga_driver:vga_driver_unit|line_counter_sig_3 ; 6 ;
+; vga_driver:vga_driver_unit|line_counter_sig_2 ; 6 ;
+; vga_driver:vga_driver_unit|column_counter_sig_7 ; 6 ;
+; vga_driver:vga_driver_unit|column_counter_sig_6 ; 6 ;
+; vga_driver:vga_driver_unit|column_counter_sig_5 ; 6 ;
+; vga_driver:vga_driver_unit|column_counter_sig_4 ; 6 ;
+; vga_driver:vga_driver_unit|column_counter_sig_3 ; 6 ;
+; vga_driver:vga_driver_unit|column_counter_sig_2 ; 6 ;
+; vga_driver:vga_driver_unit|column_counter_sig_0 ; 6 ;
+; vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa ; 5 ;
+; vga_control:vga_control_unit|toggle_counter_sig_cout[9] ; 5 ;
+; vga_control:vga_control_unit|toggle_counter_sig_cout[8] ; 5 ;
+; vga_driver:vga_driver_unit|vsync_state_0 ; 5 ;
+; vga_driver:vga_driver_unit|vsync_state_4 ; 5 ;
+; vga_driver:vga_driver_unit|hsync_state_4 ; 5 ;
+; vga_driver:vga_driver_unit|d_set_hsync_counter ; 5 ;
+; vga_driver:vga_driver_unit|vsync_counter_8 ; 5 ;
++-------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------+
+; Interconnect Usage Summary ;
++-----------------------------+-------------------------+
+; Interconnect Resource Type ; Usage ;
++-----------------------------+-------------------------+
+; C16 interconnects ; 51 / 4,620 ( 1 % ) ;
+; C4 interconnects ; 114 / 69,840 ( < 1 % ) ;
+; C8 interconnects ; 48 / 15,568 ( < 1 % ) ;
+; DIFFIOCLKs ; 0 / 16 ( 0 % ) ;
+; DQS bus muxes ; 0 / 102 ( 0 % ) ;
+; DQS-16 I/O buses ; 0 / 8 ( 0 % ) ;
+; DQS-32 I/O buses ; 0 / 4 ( 0 % ) ;
+; DQS-8 I/O buses ; 0 / 20 ( 0 % ) ;
+; Direct links ; 85 / 104,060 ( < 1 % ) ;
+; Fast regional clocks ; 0 / 8 ( 0 % ) ;
+; Global clocks ; 2 / 16 ( 13 % ) ;
+; I/O buses ; 13 / 320 ( 4 % ) ;
+; LUT chains ; 13 / 23,094 ( < 1 % ) ;
+; Local routing interconnects ; 103 / 25,660 ( < 1 % ) ;
+; R24 interconnects ; 64 / 4,692 ( 1 % ) ;
+; R4 interconnects ; 207 / 141,520 ( < 1 % ) ;
+; R8 interconnects ; 45 / 22,956 ( < 1 % ) ;
+; Regional clocks ; 0 / 16 ( 0 % ) ;
++-----------------------------+-------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements ;
++--------------------------------------------+------------------------------+
+; Number of Logic Elements (Average = 7.21) ; Number of LABs (Total = 24) ;
++--------------------------------------------+------------------------------+
+; 1 ; 3 ;
+; 2 ; 0 ;
+; 3 ; 3 ;
+; 4 ; 1 ;
+; 5 ; 1 ;
+; 6 ; 2 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 14 ;
++--------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+------------------------------+
+; LAB-wide Signals (Average = 1.79) ; Number of LABs (Total = 24) ;
++------------------------------------+------------------------------+
+; 1 Async. clear ; 4 ;
+; 1 Clock ; 20 ;
+; 1 Clock enable ; 4 ;
+; 1 Sync. clear ; 13 ;
+; 1 Sync. load ; 2 ;
++------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++---------------------------------------------+------------------------------+
+; Number of Signals Sourced (Average = 7.25) ; Number of LABs (Total = 24) ;
++---------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 3 ;
+; 2 ; 0 ;
+; 3 ; 3 ;
+; 4 ; 1 ;
+; 5 ; 1 ;
+; 6 ; 2 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 2 ;
+; 10 ; 9 ;
+; 11 ; 3 ;
++---------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out (Average = 5.42) ; Number of LABs (Total = 24) ;
++-------------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 3 ;
+; 2 ; 0 ;
+; 3 ; 3 ;
+; 4 ; 2 ;
+; 5 ; 3 ;
+; 6 ; 6 ;
+; 7 ; 3 ;
+; 8 ; 1 ;
+; 9 ; 0 ;
+; 10 ; 3 ;
++-------------------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+------------------------------+
+; Number of Distinct Inputs (Average = 10.12) ; Number of LABs (Total = 24) ;
++----------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
+; 5 ; 3 ;
+; 6 ; 0 ;
+; 7 ; 2 ;
+; 8 ; 1 ;
+; 9 ; 4 ;
+; 10 ; 1 ;
+; 11 ; 2 ;
+; 12 ; 1 ;
+; 13 ; 1 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 1 ;
+; 17 ; 3 ;
+; 18 ; 1 ;
+; 19 ; 0 ;
+; 20 ; 0 ;
+; 21 ; 1 ;
++----------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+--------------------------+
+; Option ; Setting ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Error detection CRC ; Off ;
+; nWS, nRS, nCS, CS ; Unreserved ;
+; RDYnBUSY ; Unreserved ;
+; Data[7..1] ; Unreserved ;
+; Data[0] ; As input tri-stated ;
+; Reserve all unused pins ; As output driving ground ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:18:53 2009
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga
+Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
+Info: Selected device EP1S25F672C6 for design "vga"
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP1S10F672C6 is compatible
+ Info: Device EP1S20F672C6 is compatible
+ Info: Device EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE is compatible
+Info: Fitter converted 1 user pins into dedicated programming pins
+ Info: Pin ~DATA0~ is reserved at location F16
+Warning: No exact pin location assignment(s) for 117 pins of 117 total pins
+ Info: Pin r0_pin not assigned to an exact location on the device
+ Info: Pin r1_pin not assigned to an exact location on the device
+ Info: Pin r2_pin not assigned to an exact location on the device
+ Info: Pin g0_pin not assigned to an exact location on the device
+ Info: Pin g1_pin not assigned to an exact location on the device
+ Info: Pin g2_pin not assigned to an exact location on the device
+ Info: Pin b0_pin not assigned to an exact location on the device
+ Info: Pin b1_pin not assigned to an exact location on the device
+ Info: Pin hsync_pin not assigned to an exact location on the device
+ Info: Pin vsync_pin not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[0] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[1] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[2] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[3] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[4] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[5] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[6] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[7] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[8] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[9] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[10] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[11] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[12] not assigned to an exact location on the device
+ Info: Pin seven_seg_pin[13] not assigned to an exact location on the device
+ Info: Pin d_hsync not assigned to an exact location on the device
+ Info: Pin d_vsync not assigned to an exact location on the device
+ Info: Pin d_column_counter[0] not assigned to an exact location on the device
+ Info: Pin d_column_counter[1] not assigned to an exact location on the device
+ Info: Pin d_column_counter[2] not assigned to an exact location on the device
+ Info: Pin d_column_counter[3] not assigned to an exact location on the device
+ Info: Pin d_column_counter[4] not assigned to an exact location on the device
+ Info: Pin d_column_counter[5] not assigned to an exact location on the device
+ Info: Pin d_column_counter[6] not assigned to an exact location on the device
+ Info: Pin d_column_counter[7] not assigned to an exact location on the device
+ Info: Pin d_column_counter[8] not assigned to an exact location on the device
+ Info: Pin d_column_counter[9] not assigned to an exact location on the device
+ Info: Pin d_line_counter[0] not assigned to an exact location on the device
+ Info: Pin d_line_counter[1] not assigned to an exact location on the device
+ Info: Pin d_line_counter[2] not assigned to an exact location on the device
+ Info: Pin d_line_counter[3] not assigned to an exact location on the device
+ Info: Pin d_line_counter[4] not assigned to an exact location on the device
+ Info: Pin d_line_counter[5] not assigned to an exact location on the device
+ Info: Pin d_line_counter[6] not assigned to an exact location on the device
+ Info: Pin d_line_counter[7] not assigned to an exact location on the device
+ Info: Pin d_line_counter[8] not assigned to an exact location on the device
+ Info: Pin d_set_column_counter not assigned to an exact location on the device
+ Info: Pin d_set_line_counter not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[0] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[1] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[2] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[3] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[4] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[5] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[6] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[7] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[8] not assigned to an exact location on the device
+ Info: Pin d_hsync_counter[9] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[0] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[1] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[2] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[3] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[4] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[5] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[6] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[7] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[8] not assigned to an exact location on the device
+ Info: Pin d_vsync_counter[9] not assigned to an exact location on the device
+ Info: Pin d_set_hsync_counter not assigned to an exact location on the device
+ Info: Pin d_set_vsync_counter not assigned to an exact location on the device
+ Info: Pin d_h_enable not assigned to an exact location on the device
+ Info: Pin d_v_enable not assigned to an exact location on the device
+ Info: Pin d_r not assigned to an exact location on the device
+ Info: Pin d_g not assigned to an exact location on the device
+ Info: Pin d_b not assigned to an exact location on the device
+ Info: Pin d_hsync_state[6] not assigned to an exact location on the device
+ Info: Pin d_hsync_state[5] not assigned to an exact location on the device
+ Info: Pin d_hsync_state[4] not assigned to an exact location on the device
+ Info: Pin d_hsync_state[3] not assigned to an exact location on the device
+ Info: Pin d_hsync_state[2] not assigned to an exact location on the device
+ Info: Pin d_hsync_state[1] not assigned to an exact location on the device
+ Info: Pin d_hsync_state[0] not assigned to an exact location on the device
+ Info: Pin d_vsync_state[6] not assigned to an exact location on the device
+ Info: Pin d_vsync_state[5] not assigned to an exact location on the device
+ Info: Pin d_vsync_state[4] not assigned to an exact location on the device
+ Info: Pin d_vsync_state[3] not assigned to an exact location on the device
+ Info: Pin d_vsync_state[2] not assigned to an exact location on the device
+ Info: Pin d_vsync_state[1] not assigned to an exact location on the device
+ Info: Pin d_vsync_state[0] not assigned to an exact location on the device
+ Info: Pin d_state_clk not assigned to an exact location on the device
+ Info: Pin d_toggle not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[0] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[1] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[2] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[3] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[4] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[5] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[6] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[7] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[8] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[9] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[10] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[11] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[12] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[13] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[14] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[15] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[16] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[17] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[18] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[19] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[20] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[21] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[22] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[23] not assigned to an exact location on the device
+ Info: Pin d_toggle_counter[24] not assigned to an exact location on the device
+ Info: Pin clk_pin not assigned to an exact location on the device
+ Info: Pin reset_pin not assigned to an exact location on the device
+Info: Fitter is using the Classic Timing Analyzer
+Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
+Info: Completed User Assigned Global Signals Promotion Operation
+Info: Automatically promoted some destinations of signal "clk_pin" to use Global clock in PIN R3
+ Info: Destination "d_state_clk_out" may be non-global or may not use global clock
+Info: Automatically promoted some destinations of signal "vga_driver:vga_driver_unit|un6_dly_counter_0_x" to use Global clock
+ Info: Destination "seven_seg_pin_out_12_" may be non-global or may not use global clock
+ Info: Destination "seven_seg_pin_out_11_" may be non-global or may not use global clock
+ Info: Destination "seven_seg_pin_out_10_" may be non-global or may not use global clock
+ Info: Destination "seven_seg_pin_out_9_" may be non-global or may not use global clock
+ Info: Destination "seven_seg_pin_out_8_" may be non-global or may not use global clock
+ Info: Destination "seven_seg_pin_out_7_" may be non-global or may not use global clock
+ Info: Destination "seven_seg_pin_out_2_" may be non-global or may not use global clock
+ Info: Destination "seven_seg_pin_out_1_" may be non-global or may not use global clock
+ Info: Destination "vga_driver:vga_driver_unit|hsync_state_1_" may be non-global or may not use global clock
+ Info: Destination "vga_driver:vga_driver_unit|vsync_state_1_" may be non-global or may not use global clock
+ Info: Limited to 10 non-global destinations
+Info: Completed Auto Global Promotion Operation
+Info: Starting register packing
+Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
+Info: Finished register packing
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 116 (unused VREF, 3.3V VCCIO, 1 input, 115 output, 0 bidirectional)
+ Info: I/O standards used: 3.3-V LVTTL.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 60 pins available
+ Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 59 pins available
+ Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 54 pins available
+ Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 55 pins available
+ Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 59 pins available
+ Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 61 pins available
+ Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 57 pins available
+ Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 54 pins available
+ Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
+ Info: I/O bank number 11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
+Info: Fitter preparation operations ending: elapsed time is 00:00:04
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:03
+Info: Slack time is -4.354 ns between source register "vga_control:vga_control_unit|toggle_counter_sig_5" and destination register "vga_control:vga_control_unit|toggle_counter_sig_10"
+ Info: + Largest register to register requirement is 0.814 ns
+ Info: Shortest clock path from clock "clk_pin" to destination register is 3.707 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 84; CLK Node = 'clk_pin'
+ Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 8; REG Node = 'vga_control:vga_control_unit|toggle_counter_sig_10'
+ Info: Total cell delay = 1.701 ns ( 45.89 % )
+ Info: Total interconnect delay = 2.006 ns ( 54.11 % )
+ Info: Longest clock path from clock "clk_pin" to destination register is 3.707 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 84; CLK Node = 'clk_pin'
+ Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 8; REG Node = 'vga_control:vga_control_unit|toggle_counter_sig_10'
+ Info: Total cell delay = 1.701 ns ( 45.89 % )
+ Info: Total interconnect delay = 2.006 ns ( 54.11 % )
+ Info: Shortest clock path from clock "clk_pin" to source register is 3.707 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 84; CLK Node = 'clk_pin'
+ Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 7; REG Node = 'vga_control:vga_control_unit|toggle_counter_sig_5'
+ Info: Total cell delay = 1.701 ns ( 45.89 % )
+ Info: Total interconnect delay = 2.006 ns ( 54.11 % )
+ Info: Longest clock path from clock "clk_pin" to source register is 3.707 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = Unassigned; Fanout = 84; CLK Node = 'clk_pin'
+ Info: 2: + IC(2.006 ns) + CELL(0.560 ns) = 3.707 ns; Loc. = Unassigned; Fanout = 7; REG Node = 'vga_control:vga_control_unit|toggle_counter_sig_5'
+ Info: Total cell delay = 1.701 ns ( 45.89 % )
+ Info: Total interconnect delay = 2.006 ns ( 54.11 % )
+ Info: Micro clock to output delay of source is 0.176 ns
+ Info: Micro setup delay of destination is 0.010 ns
+ Info: - Longest register to register delay is 5.168 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 7; REG Node = 'vga_control:vga_control_unit|toggle_counter_sig_5'
+ Info: 2: + IC(0.433 ns) + CELL(0.332 ns) = 0.765 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglt6'
+ Info: 3: + IC(0.427 ns) + CELL(0.087 ns) = 1.279 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglto9'
+ Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 1.793 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglto12'
+ Info: 5: + IC(0.427 ns) + CELL(0.087 ns) = 2.307 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglto15'
+ Info: 6: + IC(0.427 ns) + CELL(0.087 ns) = 2.821 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglto18'
+ Info: 7: + IC(0.427 ns) + CELL(0.087 ns) = 3.335 ns; Loc. = Unassigned; Fanout = 22; COMB Node = 'vga_control:vga_control_unit|toggle_sig_0_0_0_g1'
+ Info: 8: + IC(1.051 ns) + CELL(0.782 ns) = 5.168 ns; Loc. = Unassigned; Fanout = 8; REG Node = 'vga_control:vga_control_unit|toggle_counter_sig_10'
+ Info: Total cell delay = 1.549 ns ( 29.97 % )
+ Info: Total interconnect delay = 3.619 ns ( 70.03 % )
+Info: Estimated most critical path is register to register delay of 5.168 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X33_Y35; Fanout = 7; REG Node = 'vga_control:vga_control_unit|toggle_counter_sig_5'
+ Info: 2: + IC(0.433 ns) + CELL(0.332 ns) = 0.765 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglt6'
+ Info: 3: + IC(0.427 ns) + CELL(0.087 ns) = 1.279 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglto9'
+ Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 1.793 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglto12'
+ Info: 5: + IC(0.427 ns) + CELL(0.087 ns) = 2.307 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglto15'
+ Info: 6: + IC(0.427 ns) + CELL(0.087 ns) = 2.821 ns; Loc. = LAB_X32_Y35; Fanout = 1; COMB Node = 'vga_control:vga_control_unit|un1_toggle_counter_siglto18'
+ Info: 7: + IC(0.427 ns) + CELL(0.087 ns) = 3.335 ns; Loc. = LAB_X32_Y35; Fanout = 22; COMB Node = 'vga_control:vga_control_unit|toggle_sig_0_0_0_g1'
+ Info: 8: + IC(1.051 ns) + CELL(0.782 ns) = 5.168 ns; Loc. = LAB_X31_Y34; Fanout = 8; REG Node = 'vga_control:vga_control_unit|toggle_counter_sig_10'
+ Info: Total cell delay = 1.549 ns ( 29.97 % )
+ Info: Total interconnect delay = 3.619 ns ( 70.03 % )
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources
+ Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X34_Y24 to location X44_Y35
+Info: Fitter routing operations ending: elapsed time is 00:00:01
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Completed Fixed Delay Chain Operation
+Info: Started post-fitting delay annotation
+Info: Delay annotation completed successfully
+Info: Completed Auto Delay Chain Operation
+Warning: Following 14 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
+ Info: Pin g0_pin has GND driving its datain port
+ Info: Pin g1_pin has GND driving its datain port
+ Info: Pin g2_pin has GND driving its datain port
+ Info: Pin seven_seg_pin[0] has GND driving its datain port
+ Info: Pin seven_seg_pin[3] has GND driving its datain port
+ Info: Pin seven_seg_pin[4] has GND driving its datain port
+ Info: Pin seven_seg_pin[5] has GND driving its datain port
+ Info: Pin seven_seg_pin[6] has GND driving its datain port
+ Info: Pin seven_seg_pin[13] has GND driving its datain port
+ Info: Pin d_g has GND driving its datain port
+ Info: Pin d_toggle_counter[21] has GND driving its datain port
+ Info: Pin d_toggle_counter[22] has GND driving its datain port
+ Info: Pin d_toggle_counter[23] has GND driving its datain port
+ Info: Pin d_toggle_counter[24] has GND driving its datain port
+Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
+Info: Generated suppressed messages file /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/vga.fit.smsg
+Info: Quartus II Fitter was successful. 0 errors, 3 warnings
+ Info: Peak virtual memory: 320 megabytes
+ Info: Processing ended: Wed Oct 28 14:19:25 2009
+ Info: Elapsed time: 00:00:32
+ Info: Total CPU time (on all processors): 00:00:30
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /homes/burban/didelu/dide_16/bsp2/Designflow/ppr/sim/vga.fit.smsg.
+
+
--- /dev/null
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Start inferring scan chains for DSP blocks
+Extra Info: Inferring scan chains for DSP blocks is complete
+Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density
+Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks
--- /dev/null
+Fitter Status : Successful - Wed Oct 28 14:19:24 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga
+Top-level Entity Name : vga
+Family : Stratix
+Device : EP1S25F672C6
+Timing Models : Final
+Total logic elements : 173 / 25,660 ( < 1 % )
+Total pins : 117 / 474 ( 25 % )
+Total virtual pins : 0
+Total memory bits : 0 / 1,944,576 ( 0 % )
+DSP block 9-bit elements : 0 / 80 ( 0 % )
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 2 ( 0 % )
--- /dev/null
+Flow report for vga
+Wed Oct 28 14:19:55 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------+
+; Flow Summary ;
++--------------------------+------------------------------------------+
+; Flow Status ; Successful - Wed Oct 28 14:19:55 2009 ;
+; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
+; Revision Name ; vga ;
+; Top-level Entity Name ; vga ;
+; Family ; Stratix ;
+; Device ; EP1S25F672C6 ;
+; Timing Models ; Final ;
+; Met timing requirements ; Yes ;
+; Total logic elements ; 173 / 25,660 ( < 1 % ) ;
+; Total pins ; 117 / 474 ( 25 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 1,944,576 ( 0 % ) ;
+; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 2 ( 0 % ) ;
++--------------------------+------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 10/28/2009 14:18:47 ;
+; Main task ; Compilation ;
+; Revision Name ; vga ;
++-------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+-----------------------------+---------------+-------------+----------------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+-----------------------------+---------------+-------------+----------------------+
+; COMPILER_SIGNATURE_ID ; 91815332912.125673592628073 ; -- ; -- ; -- ;
+; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Synplify Pro ; <None> ; -- ; -- ;
+; EDA_INPUT_DATA_FORMAT ; Vqm ; -- ; -- ; eda_design_synthesis ;
+; EDA_LMF_FILE ; synplcty.lmf ; -- ; -- ; eda_design_synthesis ;
+; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
+; EDA_SIMULATION_TOOL ; ModelSim (VHDL) ; <None> ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+-----------------------------+---------------+-------------+----------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:05 ; 1.0 ; -- ; 00:00:02 ;
+; Fitter ; 00:00:31 ; 1.0 ; -- ; 00:00:29 ;
+; Assembler ; 00:00:19 ; 1.0 ; -- ; 00:00:18 ;
+; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; -- ; 00:00:00 ;
+; EDA Netlist Writer ; 00:00:01 ; 1.0 ; -- ; 00:00:01 ;
+; Total ; 00:00:56 ; -- ; -- ; 00:00:50 ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++-------------------------+------------------+---------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++-------------------------+------------------+---------+------------+----------------+
+; Analysis & Synthesis ; ti15 ; Red Hat ; 5 ; x86_64 ;
+; Fitter ; ti15 ; Red Hat ; 5 ; x86_64 ;
+; Assembler ; ti15 ; Red Hat ; 5 ; x86_64 ;
+; Classic Timing Analyzer ; ti15 ; Red Hat ; 5 ; x86_64 ;
+; EDA Netlist Writer ; ti15 ; Red Hat ; 5 ; x86_64 ;
++-------------------------+------------------+---------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off vga -c vga
+quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga
+quartus_asm --read_settings_files=off --write_settings_files=off vga -c vga
+quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only
+quartus_eda --read_settings_files=off --write_settings_files=off vga -c vga
+
+
+
--- /dev/null
+Analysis & Synthesis report for vga
+Wed Oct 28 14:18:49 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. Registers Removed During Synthesis
+ 8. General Register Statistics
+ 9. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++-----------------------------+------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Wed Oct 28 14:18:49 2009 ;
+; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
+; Revision Name ; vga ;
+; Top-level Entity Name ; vga ;
+; Family ; Stratix ;
+; Total logic elements ; 175 ;
+; Total pins ; 117 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 ;
+; DSP block 9-bit elements ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++-----------------------------+------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++----------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP1S25F672C6 ; ;
+; Top-level entity name ; vga ; vga ;
+; Family name ; Stratix ; Stratix II ;
+; Type of Retiming Performed During Resynthesis ; Full ; ;
+; Resynthesis Optimization Effort ; Normal ; ;
+; Physical Synthesis Level for Resynthesis ; Normal ; ;
+; Use Generated Physical Constraints File ; On ; ;
+; Use smart compilation ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL93 ; VHDL93 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Parallel Synthesis ; Off ; Off ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM Block Balancing ; On ; On ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Block Design Naming ; Auto ; Auto ;
+; Synthesis Effort ; Auto ; Auto ;
+; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
++----------------------------------------------------------------+--------------------+--------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
+; ../../syn/rev_1/vga.vqm ; yes ; User Verilog Quartus Mapping File ; /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
+
+
++-------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+---------+
+; Resource ; Usage ;
++---------------------------------------------+---------+
+; Total logic elements ; 175 ;
+; -- Combinational with no register ; 92 ;
+; -- Register only ; 3 ;
+; -- Combinational with a register ; 80 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 60 ;
+; -- 3 input functions ; 52 ;
+; -- 2 input functions ; 58 ;
+; -- 1 input functions ; 2 ;
+; -- 0 input functions ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 122 ;
+; -- arithmetic mode ; 53 ;
+; -- qfbk mode ; 0 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 69 ;
+; -- asynchronous clear/load mode ; 24 ;
+; ; ;
+; Total registers ; 83 ;
+; Total logic cells in carry chains ; 61 ;
+; I/O pins ; 117 ;
+; Maximum fan-out node ; clk_pin ;
+; Maximum fan-out ; 84 ;
+; Total fan-out ; 844 ;
+; Average fan-out ; 2.89 ;
++---------------------------------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+
+; |vga ; 175 (2) ; 83 ; 0 ; 0 ; 0 ; 0 ; 0 ; 117 ; 0 ; 92 (0) ; 3 (0) ; 80 (2) ; 61 (0) ; 0 (0) ; |vga ; work ;
+; |vga_control:vga_control_unit| ; 43 (43) ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 0 (0) ; 24 (24) ; 21 (21) ; 0 (0) ; |vga|vga_control:vga_control_unit ; work ;
+; |vga_driver:vga_driver_unit| ; 130 (130) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 73 (73) ; 3 (3) ; 54 (54) ; 40 (40) ; 0 (0) ; |vga|vga_driver:vga_driver_unit ; work ;
++-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++----------------------------------------------------+----------------------------------------+
+; Register name ; Reason for Removal ;
++----------------------------------------------------+----------------------------------------+
+; vga_control:vga_control_unit|toggle_counter_sig_24 ; Stuck at GND due to stuck port reg_out ;
+; vga_control:vga_control_unit|toggle_counter_sig_23 ; Stuck at GND due to stuck port reg_out ;
+; vga_control:vga_control_unit|toggle_counter_sig_22 ; Stuck at GND due to stuck port reg_out ;
+; vga_control:vga_control_unit|toggle_counter_sig_21 ; Stuck at GND due to stuck port reg_out ;
+; vga_control:vga_control_unit|g ; Stuck at GND due to stuck port reg_out ;
+; Total Number of Removed Registers = 5 ; ;
++----------------------------------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 83 ;
+; Number of registers using Synchronous Clear ; 69 ;
+; Number of registers using Synchronous Load ; 20 ;
+; Number of registers using Asynchronous Clear ; 24 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 12 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:18:43 2009
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga
+Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm
+ Info: Found entity 1: vga_driver
+ Info: Found entity 2: vga_control
+ Info: Found entity 3: vga
+Info: Elaborating entity "vga" for the top level hierarchy
+Info: Elaborating entity "vga_driver" for hierarchy "vga_driver:vga_driver_unit"
+Info: Elaborating entity "vga_control" for hierarchy "vga_control:vga_control_unit"
+Info: Implemented 292 device resources after synthesis - the final resource count might be different
+ Info: Implemented 2 input pins
+ Info: Implemented 115 output pins
+ Info: Implemented 175 logic cells
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 185 megabytes
+ Info: Processing ended: Wed Oct 28 14:18:49 2009
+ Info: Elapsed time: 00:00:06
+ Info: Total CPU time (on all processors): 00:00:02
+
+
--- /dev/null
+Analysis & Synthesis Status : Successful - Wed Oct 28 14:18:49 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga
+Top-level Entity Name : vga
+Family : Stratix
+Total logic elements : 175
+Total pins : 117
+Total virtual pins : 0
+Total memory bits : 0
+DSP block 9-bit elements : 0
+Total PLLs : 0
+Total DLLs : 0
--- /dev/null
+ -- Copyright (C) 1991-2009 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- Bank 5: 3.3V
+ -- Bank 6: 3.3V
+ -- Bank 7: 3.3V
+ -- Bank 8: 3.3V
+ -- Bank 9: 3.3V
+ -- Bank 11: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
+ -- connect each pin marked GND* either individually through a 10k Ohm resistor
+ -- to GND or tie all pins together and connect through a single 10k Ohm resistor
+ -- to GND.
+ -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+CHIP "vga" ASSIGNED TO AN: EP1S25F672C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+GND* : A3 : : : : 3 :
+VCCIO3 : A4 : power : : 3.3V : 3 :
+GND* : A5 : : : : 3 :
+seven_seg_pin[1] : A6 : output : 3.3-V LVTTL : : 3 : N
+seven_seg_pin[9] : A7 : output : 3.3-V LVTTL : : 3 : N
+r2_pin : A8 : output : 3.3-V LVTTL : : 3 : N
+d_line_counter[7] : A9 : output : 3.3-V LVTTL : : 3 : N
+d_toggle_counter[6] : A10 : output : 3.3-V LVTTL : : 3 : N
+VCCIO3 : A11 : power : : 3.3V : 3 :
+d_vsync_counter[6] : A12 : output : 3.3-V LVTTL : : 3 : N
+GND : A13 : gnd : : : :
+GND : A14 : gnd : : : :
+GND+ : A15 : : : : 4 :
+VCCIO4 : A16 : power : : 3.3V : 4 :
+d_vsync_state[4] : A17 : output : 3.3-V LVTTL : : 4 : N
+GND* : A18 : : : : 4 :
+GND* : A19 : : : : 4 :
+GND* : A20 : : : : 4 :
+GND* : A21 : : : : 4 :
+GND* : A22 : : : : 4 :
+VCCIO4 : A23 : power : : 3.3V : 4 :
+GND* : A24 : : : : 4 :
+GND : A25 : gnd : : : :
+GND* : AA1 : : : : 1 :
+GND* : AA2 : : : : 1 :
+GND* : AA3 : : : : 1 :
+GND* : AA4 : : : : 1 :
+GND* : AA5 : : : : 1 :
+GND* : AA6 : : : : 1 :
+GND* : AA7 : : : : 8 :
+GND* : AA8 : : : : 8 :
+GND* : AA9 : : : : 8 :
+GND* : AA10 : : : : 8 :
+d_toggle_counter[11] : AA11 : output : 3.3-V LVTTL : : 8 : N
+d_hsync_state[2] : AA12 : output : 3.3-V LVTTL : : 11 : N
+d_h_enable : AA13 : output : 3.3-V LVTTL : : 11 : N
+d_vsync_state[3] : AA14 : output : 3.3-V LVTTL : : 11 : N
+nIO_PULLUP : AA15 : : : : 7 :
+d_set_line_counter : AA16 : output : 3.3-V LVTTL : : 7 : N
+GND* : AA17 : : : : 7 :
+GND* : AA18 : : : : 7 :
+GND* : AA19 : : : : 7 :
+GND* : AA20 : : : : 7 :
+GND* : AA21 : : : : 7 :
+GND* : AA22 : : : : 6 :
+GND* : AA23 : : : : 6 :
+GND* : AA24 : : : : 6 :
+GND* : AA25 : : : : 6 :
+GND* : AA26 : : : : 6 :
+GND* : AB1 : : : : 1 :
+GND* : AB2 : : : : 1 :
+GND* : AB3 : : : : 1 :
+GND* : AB4 : : : : 1 :
+GND* : AB5 : : : : 8 :
+GND* : AB6 : : : : 8 :
+GND* : AB7 : : : : 8 :
+GND* : AB8 : : : : 8 :
+GND* : AB9 : : : : 8 :
+GND* : AB10 : : : : 8 :
+GND* : AB11 : : : : 8 :
+d_hsync_counter[5] : AB12 : output : 3.3-V LVTTL : : 11 : N
+d_hsync_counter[9] : AB13 : output : 3.3-V LVTTL : : 11 : N
+d_hsync_counter[1] : AB14 : output : 3.3-V LVTTL : : 11 : N
+GND : AB15 : gnd : : : :
+GND* : AB16 : : : : 7 :
+GND* : AB17 : : : : 7 :
+GND : AB18 : gnd : : : :
+GND* : AB19 : : : : 7 :
+GND* : AB20 : : : : 7 :
+GND* : AB21 : : : : 7 :
+GND* : AB22 : : : : 7 :
+GND* : AB23 : : : : 6 :
+GND* : AB24 : : : : 6 :
+GND* : AB25 : : : : 6 :
+GND* : AB26 : : : : 6 :
+VCCIO1 : AC1 : power : : 3.3V : 1 :
+GND* : AC2 : : : : 1 :
+GND* : AC3 : : : : 1 :
+GND* : AC4 : : : : 1 :
+GND* : AC5 : : : : 8 :
+GND* : AC6 : : : : 8 :
+GND* : AC7 : : : : 8 :
+GND* : AC8 : : : : 8 :
+GND* : AC9 : : : : 8 :
+GND* : AC10 : : : : 8 :
+d_line_counter[3] : AC11 : output : 3.3-V LVTTL : : 8 : N
+GND+ : AC12 : : : : 8 :
+GND : AC13 : gnd : : : :
+GNDA_PLL6 : AC14 : gnd : : : :
+b0_pin : AC15 : output : 3.3-V LVTTL : : 7 : N
+GND* : AC16 : : : : 7 :
+GND* : AC17 : : : : 7 :
+GND* : AC18 : : : : 7 :
+GND* : AC19 : : : : 7 :
+GND* : AC20 : : : : 7 :
+GND* : AC21 : : : : 7 :
+GND* : AC22 : : : : 7 :
+GND* : AC23 : : : : 7 :
+GND* : AC24 : : : : 6 :
+GND* : AC25 : : : : 6 :
+VCCIO6 : AC26 : power : : 3.3V : 6 :
+GND* : AD1 : : : : 1 :
+GND* : AD2 : : : : 8 :
+GND* : AD3 : : : : 8 :
+GND* : AD4 : : : : 8 :
+GND* : AD5 : : : : 8 :
+GND* : AD6 : : : : 8 :
+GND* : AD7 : : : : 8 :
+GND* : AD8 : : : : 8 :
+GND* : AD9 : : : : 8 :
+GND* : AD10 : : : : 8 :
+d_toggle_counter[19] : AD11 : output : 3.3-V LVTTL : : 8 : N
+hsync_pin : AD12 : output : 3.3-V LVTTL : : 8 : N
+VCCG_PLL6 : AD13 : power : : 1.5V : :
+VCCA_PLL6 : AD14 : power : : 1.5V : :
+d_vsync_state[1] : AD15 : output : 3.3-V LVTTL : : 7 : N
+GND* : AD16 : : : : 7 :
+GND* : AD17 : : : : 7 :
+GND* : AD18 : : : : 7 :
+GND* : AD19 : : : : 7 :
+GND* : AD20 : : : : 7 :
+GND : AD21 : gnd : : : :
+GND* : AD22 : : : : 7 :
+GND* : AD23 : : : : 7 :
+GND* : AD24 : : : : 7 :
+GND* : AD25 : : : : 6 :
+GND* : AD26 : : : : 6 :
+GND : AE1 : gnd : : : :
+GND* : AE2 : : : : 8 :
+GND* : AE3 : : : : 8 :
+GND* : AE4 : : : : 8 :
+GND : AE5 : gnd : : : :
+GND* : AE6 : : : : 8 :
+GND* : AE7 : : : : 8 :
+GND* : AE8 : : : : 8 :
+GND : AE9 : gnd : : : :
+GND* : AE10 : : : : 8 :
+GND* : AE11 : : : : 8 :
+GND+ : AE12 : : : : 8 :
+VCC_PLL6_OUTA : AE13 : power : : 3.3V : 11 :
+GNDG_PLL6 : AE14 : gnd : : : :
+GND+ : AE15 : : : : 7 :
+GND* : AE16 : : : : 7 :
+GND* : AE17 : : : : 7 :
+GND* : AE18 : : : : 7 :
+GND* : AE19 : : : : 7 :
+GND* : AE20 : : : : 7 :
+GND* : AE21 : : : : 7 :
+GND* : AE22 : : : : 7 :
+GND* : AE23 : : : : 7 :
+GND* : AE24 : : : : 7 :
+GND* : AE25 : : : : 7 :
+GND : AE26 : gnd : : : :
+GND : AF2 : gnd : : : :
+GND* : AF3 : : : : 8 :
+VCCIO8 : AF4 : power : : 3.3V : 8 :
+GND* : AF5 : : : : 8 :
+GND* : AF6 : : : : 8 :
+GND* : AF7 : : : : 8 :
+GND* : AF8 : : : : 8 :
+GND* : AF9 : : : : 8 :
+GND* : AF10 : : : : 8 :
+VCCIO8 : AF11 : power : : 3.3V : 8 :
+d_hsync : AF12 : output : 3.3-V LVTTL : : 8 : N
+GND : AF13 : gnd : : : :
+GND : AF14 : gnd : : : :
+GND+ : AF15 : : : : 7 :
+VCCIO7 : AF16 : power : : 3.3V : 7 :
+GND* : AF17 : : : : 7 :
+GND* : AF18 : : : : 7 :
+GND* : AF19 : : : : 7 :
+GND* : AF20 : : : : 7 :
+GND* : AF21 : : : : 7 :
+GND* : AF22 : : : : 7 :
+VCCIO7 : AF23 : power : : 3.3V : 7 :
+GND* : AF24 : : : : 7 :
+GND : AF25 : gnd : : : :
+GND : B1 : gnd : : : :
+GND : B2 : gnd : : : :
+GND* : B3 : : : : 3 :
+GND* : B4 : : : : 3 :
+GND* : B5 : : : : 3 :
+GND* : B6 : : : : 3 :
+GND* : B7 : : : : 3 :
+d_r : B8 : output : 3.3-V LVTTL : : 3 : N
+r0_pin : B9 : output : 3.3-V LVTTL : : 3 : N
+d_hsync_state[1] : B10 : output : 3.3-V LVTTL : : 3 : N
+d_toggle_counter[5] : B11 : output : 3.3-V LVTTL : : 3 : N
+GND+ : B12 : : : : 3 :
+GNDG_PLL5 : B13 : gnd : : : :
+GNDA_PLL5 : B14 : gnd : : : :
+GND+ : B15 : : : : 4 :
+d_column_counter[0] : B16 : output : 3.3-V LVTTL : : 4 : N
+d_hsync_state[5] : B17 : output : 3.3-V LVTTL : : 4 : N
+GND* : B18 : : : : 4 :
+GND* : B19 : : : : 4 :
+GND* : B20 : : : : 4 :
+GND* : B21 : : : : 4 :
+GND* : B22 : : : : 4 :
+GND* : B23 : : : : 4 :
+GND* : B24 : : : : 4 :
+GND* : B25 : : : : 4 :
+GND : B26 : gnd : : : :
+GND* : C1 : : : : 2 :
+seven_seg_pin[10] : C2 : output : 3.3-V LVTTL : : 3 : N
+GND* : C3 : : : : 3 :
+GND* : C4 : : : : 3 :
+GND* : C5 : : : : 3 :
+GND* : C6 : : : : 3 :
+GND* : C7 : : : : 3 :
+GND* : C8 : : : : 3 :
+GND* : C9 : : : : 3 :
+d_v_enable : C10 : output : 3.3-V LVTTL : : 3 : N
+d_toggle_counter[18] : C11 : output : 3.3-V LVTTL : : 3 : N
+d_vsync_counter[2] : C12 : output : 3.3-V LVTTL : : 3 : N
+GND : C13 : gnd : : : :
+VCCG_PLL5 : C14 : power : : 1.5V : :
+d_column_counter[1] : C15 : output : 3.3-V LVTTL : : 4 : N
+d_column_counter[5] : C16 : output : 3.3-V LVTTL : : 4 : N
+d_hsync_state[6] : C17 : output : 3.3-V LVTTL : : 4 : N
+GND* : C18 : : : : 4 :
+GND* : C19 : : : : 4 :
+GND* : C20 : : : : 4 :
+GND* : C21 : : : : 4 :
+GND* : C22 : : : : 4 :
+GND* : C23 : : : : 4 :
+GND* : C24 : : : : 4 :
+GND* : C25 : : : : 5 :
+GND* : C26 : : : : 5 :
+VCCIO2 : D1 : power : : 3.3V : 2 :
+GND* : D2 : : : : 2 :
+GND* : D3 : : : : 3 :
+GND* : D4 : : : : 3 :
+GND* : D5 : : : : 3 :
+GND* : D6 : : : : 3 :
+GND : D7 : gnd : : : :
+GND* : D8 : : : : 3 :
+GND : D9 : gnd : : : :
+d_set_column_counter : D10 : output : 3.3-V LVTTL : : 3 : N
+d_toggle_counter[16] : D11 : output : 3.3-V LVTTL : : 3 : N
+GND+ : D12 : : : : 3 :
+VCC_PLL5_OUTA : D13 : power : : 3.3V : 9 :
+VCCA_PLL5 : D14 : power : : 1.5V : :
+TRST : D15 : input : : : 4 :
+d_hsync_counter[8] : D16 : output : 3.3-V LVTTL : : 4 : N
+d_column_counter[6] : D17 : output : 3.3-V LVTTL : : 4 : N
+GND* : D18 : : : : 4 :
+GND* : D19 : : : : 4 :
+GND* : D20 : : : : 4 :
+GND* : D21 : : : : 4 :
+GND* : D22 : : : : 4 :
+GND* : D23 : : : : 4 :
+GND* : D24 : : : : 5 :
+GND* : D25 : : : : 5 :
+VCCIO5 : D26 : power : : 3.3V : 5 :
+GND* : E1 : : : : 2 :
+GND* : E2 : : : : 2 :
+GND* : E3 : : : : 2 :
+GND* : E4 : : : : 2 :
+GND* : E5 : : : : 3 :
+GND* : E6 : : : : 3 :
+seven_seg_pin[12] : E7 : output : 3.3-V LVTTL : : 3 : N
+r1_pin : E8 : output : 3.3-V LVTTL : : 3 : N
+d_toggle_counter[2] : E9 : output : 3.3-V LVTTL : : 3 : N
+d_toggle_counter[9] : E10 : output : 3.3-V LVTTL : : 3 : N
+d_toggle_counter[10] : E11 : output : 3.3-V LVTTL : : 3 : N
+d_vsync_counter[1] : E12 : output : 3.3-V LVTTL : : 9 : N
+d_column_counter[4] : E13 : output : 3.3-V LVTTL : : 9 : N
+d_column_counter[8] : E14 : output : 3.3-V LVTTL : : 9 : N
+TMS : E15 : input : : : 4 :
+d_column_counter[7] : E16 : output : 3.3-V LVTTL : : 4 : N
+GND* : E17 : : : : 4 :
+GND* : E18 : : : : 4 :
+GND* : E19 : : : : 4 :
+GND* : E20 : : : : 4 :
+GND* : E21 : : : : 4 :
+GND* : E22 : : : : 4 :
+GND* : E23 : : : : 5 :
+GND* : E24 : : : : 5 :
+GND* : E25 : : : : 5 :
+GND* : E26 : : : : 5 :
+GND* : F1 : : : : 2 :
+GND* : F2 : : : : 2 :
+GND* : F3 : : : : 2 :
+GND* : F4 : : : : 2 :
+seven_seg_pin[7] : F5 : output : 3.3-V LVTTL : : 3 : N
+GND* : F6 : : : : 3 :
+GND* : F7 : : : : 3 :
+GND : F8 : gnd : : : :
+d_line_counter[8] : F9 : output : 3.3-V LVTTL : : 3 : N
+d_toggle_counter[3] : F10 : output : 3.3-V LVTTL : : 3 : N
+GND : F11 : gnd : : : :
+d_column_counter[3] : F12 : output : 3.3-V LVTTL : : 9 : N
+d_vsync_counter[8] : F13 : output : 3.3-V LVTTL : : 9 : N
+d_hsync_state[3] : F14 : output : 3.3-V LVTTL : : 9 : N
+d_vsync_state[5] : F15 : output : 3.3-V LVTTL : : 4 : N
+~DATA0~ / RESERVED_INPUT : F16 : input : 3.3-V LVTTL : : 4 : N
+d_vsync_state[0] : F17 : output : 3.3-V LVTTL : : 4 : N
+GND : F18 : gnd : : : :
+GND* : F19 : : : : 4 :
+GND* : F20 : : : : 4 :
+GND* : F21 : : : : 4 :
+GND : F22 : gnd : : : :
+GND* : F23 : : : : 5 :
+GND* : F24 : : : : 5 :
+GND* : F25 : : : : 5 :
+GND* : F26 : : : : 5 :
+GND* : G1 : : : : 2 :
+GND* : G2 : : : : 2 :
+GND* : G3 : : : : 2 :
+GND* : G4 : : : : 2 :
+GND* : G5 : : : : 2 :
+GND* : G6 : : : : 2 :
+d_toggle_counter[20] : G7 : output : 3.3-V LVTTL : : 3 : N
+GND : G8 : gnd : : : :
+d_toggle_counter[14] : G9 : output : 3.3-V LVTTL : : 3 : N
+d_line_counter[2] : G10 : output : 3.3-V LVTTL : : 3 : N
+d_toggle_counter[15] : G11 : output : 3.3-V LVTTL : : 3 : N
+DCLK : G12 : : : : 3 :
+TEMPDIODEn : G13 : : : : :
+TDO : G14 : output : : : 4 :
+TCK : G15 : input : : : 4 :
+GND : G16 : gnd : : : :
+d_vsync_state[6] : G17 : output : 3.3-V LVTTL : : 4 : N
+d_vsync_state[2] : G18 : output : 3.3-V LVTTL : : 4 : N
+GND* : G19 : : : : 4 :
+GND* : G20 : : : : 4 :
+GND* : G21 : : : : 5 :
+GND* : G22 : : : : 5 :
+GND* : G23 : : : : 5 :
+GND* : G24 : : : : 5 :
+GND* : G25 : : : : 5 :
+GND* : G26 : : : : 5 :
+GND* : H1 : : : : 2 :
+GND* : H2 : : : : 2 :
+GND* : H3 : : : : 2 :
+GND* : H4 : : : : 2 :
+GND* : H5 : : : : 2 :
+seven_seg_pin[11] : H6 : output : 3.3-V LVTTL : : 2 : N
+GND* : H7 : : : : 2 :
+GND : H8 : gnd : : : :
+GND : H9 : gnd : : : :
+d_line_counter[1] : H10 : output : 3.3-V LVTTL : : 3 : N
+CONF_DONE : H11 : : : : 3 :
+nCONFIG : H12 : : : : 3 :
+nSTATUS : H13 : : : : 3 :
+TEMPDIODEp : H14 : : : : :
+TDI : H15 : input : : : 4 :
+d_column_counter[2] : H16 : output : 3.3-V LVTTL : : 4 : N
+GND : H17 : gnd : : : :
+d_column_counter[9] : H18 : output : 3.3-V LVTTL : : 4 : N
+GND* : H19 : : : : 5 :
+GND* : H20 : : : : 5 :
+GND* : H21 : : : : 5 :
+GND* : H22 : : : : 5 :
+GND* : H23 : : : : 5 :
+GND* : H24 : : : : 5 :
+GND* : H25 : : : : 5 :
+GND* : H26 : : : : 5 :
+GND* : J1 : : : : 2 :
+GND* : J2 : : : : 2 :
+GND* : J3 : : : : 2 :
+GND* : J4 : : : : 2 :
+GND* : J5 : : : : 2 :
+GND* : J6 : : : : 2 :
+GND* : J7 : : : : 2 :
+d_toggle_counter[0] : J8 : output : 3.3-V LVTTL : : 2 : N
+GND : J9 : gnd : : : :
+GND : J10 : gnd : : : :
+VCCIO3 : J11 : power : : 3.3V : 3 :
+VCCIO3 : J12 : power : : 3.3V : 3 :
+GND : J13 : gnd : : : :
+GND : J14 : gnd : : : :
+VCCIO4 : J15 : power : : 3.3V : 4 :
+VCCIO4 : J16 : power : : 3.3V : 4 :
+GND : J17 : gnd : : : :
+GND : J18 : gnd : : : :
+GND* : J19 : : : : 5 :
+GND* : J20 : : : : 5 :
+GND* : J21 : : : : 5 :
+GND* : J22 : : : : 5 :
+GND* : J23 : : : : 5 :
+GND* : J24 : : : : 5 :
+GND* : J25 : : : : 5 :
+GND* : J26 : : : : 5 :
+d_toggle_counter[8] : K1 : output : 3.3-V LVTTL : : 2 : N
+d_toggle_counter[7] : K2 : output : 3.3-V LVTTL : : 2 : N
+GND* : K3 : : : : 2 :
+d_toggle : K4 : output : 3.3-V LVTTL : : 2 : N
+d_toggle_counter[12] : K5 : output : 3.3-V LVTTL : : 2 : N
+GND* : K6 : : : : 2 :
+d_toggle_counter[13] : K7 : output : 3.3-V LVTTL : : 2 : N
+GND* : K8 : : : : 2 :
+d_toggle_counter[4] : K9 : output : 3.3-V LVTTL : : 2 : N
+GND : K10 : gnd : : : :
+VCCINT : K11 : power : : 1.5V : :
+GND : K12 : gnd : : : :
+VCCINT : K13 : power : : 1.5V : :
+GND : K14 : gnd : : : :
+VCCINT : K15 : power : : 1.5V : :
+GND : K16 : gnd : : : :
+VCCINT : K17 : power : : 1.5V : :
+GND : K18 : gnd : : : :
+GND* : K19 : : : : 5 :
+GND* : K20 : : : : 5 :
+d_toggle_counter[17] : K21 : output : 3.3-V LVTTL : : 5 : N
+GND* : K22 : : : : 5 :
+GND* : K23 : : : : 5 :
+GND* : K24 : : : : 5 :
+d_toggle_counter[1] : K25 : output : 3.3-V LVTTL : : 5 : N
+GND* : K26 : : : : 5 :
+VCCIO2 : L1 : power : : 3.3V : 2 :
+d_vsync_counter[7] : L2 : output : 3.3-V LVTTL : : 2 : N
+seven_seg_pin[8] : L3 : output : 3.3-V LVTTL : : 2 : N
+d_line_counter[4] : L4 : output : 3.3-V LVTTL : : 2 : N
+seven_seg_pin[2] : L5 : output : 3.3-V LVTTL : : 2 : N
+d_line_counter[6] : L6 : output : 3.3-V LVTTL : : 2 : N
+d_line_counter[5] : L7 : output : 3.3-V LVTTL : : 2 : N
+GND : L8 : gnd : : : :
+VCCIO2 : L9 : power : : 3.3V : 2 :
+VCCINT : L10 : power : : 1.5V : :
+GND : L11 : gnd : : : :
+VCCINT : L12 : power : : 1.5V : :
+GND : L13 : gnd : : : :
+VCCINT : L14 : power : : 1.5V : :
+GND : L15 : gnd : : : :
+VCCINT : L16 : power : : 1.5V : :
+GND : L17 : gnd : : : :
+VCCIO5 : L18 : power : : 3.3V : 5 :
+GND : L19 : gnd : : : :
+GND* : L20 : : : : 5 :
+GND* : L21 : : : : 5 :
+vsync_pin : L22 : output : 3.3-V LVTTL : : 5 : N
+d_vsync : L23 : output : 3.3-V LVTTL : : 5 : N
+GND* : L24 : : : : 5 :
+GND* : L25 : : : : 5 :
+VCCIO5 : L26 : power : : 3.3V : 5 :
+GND+ : M1 : : : : 2 :
+VCCG_PLL1 : M2 : power : : 1.5V : :
+VCCA_PLL1 : M3 : power : : 1.5V : :
+d_vsync_counter[9] : M4 : output : 3.3-V LVTTL : : 2 : N
+d_vsync_counter[0] : M5 : output : 3.3-V LVTTL : : 2 : N
+d_set_hsync_counter : M6 : output : 3.3-V LVTTL : : 2 : N
+d_line_counter[0] : M7 : output : 3.3-V LVTTL : : 2 : N
+d_hsync_counter[3] : M8 : output : 3.3-V LVTTL : : 2 : N
+d_hsync_state[0] : M9 : output : 3.3-V LVTTL : : 2 : N
+GND : M10 : gnd : : : :
+VCCINT : M11 : power : : 1.5V : :
+GND : M12 : gnd : : : :
+VCCINT : M13 : power : : 1.5V : :
+GND : M14 : gnd : : : :
+VCCINT : M15 : power : : 1.5V : :
+GND : M16 : gnd : : : :
+VCCINT : M17 : power : : 1.5V : :
+GND* : M18 : : : : 5 :
+GND* : M19 : : : : 5 :
+GND* : M20 : : : : 5 :
+GND* : M21 : : : : 5 :
+d_vsync_counter[3] : M22 : output : 3.3-V LVTTL : : 5 : N
+d_vsync_counter[4] : M23 : output : 3.3-V LVTTL : : 5 : N
+GND+ : M24 : : : : 5 :
+GND+ : M25 : : : : 5 :
+GND+ : M26 : : : : 5 :
+GND : N1 : gnd : : : :
+reset_pin : N2 : input : 3.3-V LVTTL : : 2 : N
+GND+ : N3 : : : : 2 :
+GNDG_PLL1 : N4 : gnd : : : :
+GNDA_PLL1 : N5 : gnd : : : :
+d_hsync_counter[4] : N6 : output : 3.3-V LVTTL : : 2 : N
+d_vsync_counter[5] : N7 : output : 3.3-V LVTTL : : 2 : N
+d_hsync_counter[2] : N8 : output : 3.3-V LVTTL : : 2 : N
+GND : N9 : gnd : : : :
+VCCINT : N10 : power : : 1.5V : :
+GND : N11 : gnd : : : :
+VCCINT : N12 : power : : 1.5V : :
+GND : N13 : gnd : : : :
+VCCINT : N14 : power : : 1.5V : :
+GND : N15 : gnd : : : :
+VCCINT : N16 : power : : 1.5V : :
+GND : N17 : gnd : : : :
+GND : N18 : gnd : : : :
+GND* : N19 : : : : 6 :
+GND* : N20 : : : : 5 :
+d_hsync_counter[7] : N21 : output : 3.3-V LVTTL : : 5 : N
+GNDG_PLL4 : N22 : gnd : : : :
+GNDA_PLL4 : N23 : gnd : : : :
+VCCG_PLL4 : N24 : power : : 1.5V : :
+VCCA_PLL4 : N25 : power : : 1.5V : :
+GND : N26 : gnd : : : :
+GND : P1 : gnd : : : :
+GNDG_PLL2 : P2 : gnd : : : :
+GNDA_PLL2 : P3 : gnd : : : :
+VCCG_PLL2 : P4 : power : : 1.5V : :
+VCCA_PLL2 : P5 : power : : 1.5V : :
+d_hsync_counter[6] : P6 : output : 3.3-V LVTTL : : 1 : N
+d_state_clk : P7 : output : 3.3-V LVTTL : : 1 : N
+d_hsync_counter[0] : P8 : output : 3.3-V LVTTL : : 2 : N
+GND : P9 : gnd : : : :
+GND : P10 : gnd : : : :
+VCCINT : P11 : power : : 1.5V : :
+GND : P12 : gnd : : : :
+VCCINT : P13 : power : : 1.5V : :
+GND : P14 : gnd : : : :
+VCCINT : P15 : power : : 1.5V : :
+GND : P16 : gnd : : : :
+VCCINT : P17 : power : : 1.5V : :
+GND : P18 : gnd : : : :
+GND* : P19 : : : : 6 :
+GND* : P20 : : : : 6 :
+GND* : P21 : : : : 6 :
+VCCA_PLL3 : P22 : power : : 1.5V : :
+VCCG_PLL3 : P23 : power : : 1.5V : :
+GND+ : P24 : : : : 6 :
+GND+ : P25 : : : : 6 :
+GND : P26 : gnd : : : :
+GND+ : R1 : : : : 1 :
+GND+ : R2 : : : : 1 :
+clk_pin : R3 : input : 3.3-V LVTTL : : 1 : N
+GND* : R4 : : : : 1 :
+GND* : R5 : : : : 1 :
+GND* : R6 : : : : 1 :
+GND* : R7 : : : : 1 :
+GND* : R8 : : : : 1 :
+d_hsync_state[4] : R9 : output : 3.3-V LVTTL : : 1 : N
+VCCINT : R10 : power : : 1.5V : :
+GND : R11 : gnd : : : :
+VCCINT : R12 : power : : 1.5V : :
+GND : R13 : gnd : : : :
+VCCINT : R14 : power : : 1.5V : :
+GND : R15 : gnd : : : :
+VCCINT : R16 : power : : 1.5V : :
+GND : R17 : gnd : : : :
+GND : R18 : gnd : : : :
+GND* : R19 : : : : 6 :
+GND* : R20 : : : : 6 :
+GND* : R21 : : : : 6 :
+GND* : R22 : : : : 6 :
+GND* : R23 : : : : 6 :
+GNDA_PLL3 : R24 : gnd : : : :
+GNDG_PLL3 : R25 : gnd : : : :
+GND+ : R26 : : : : 6 :
+VCCIO1 : T1 : power : : 3.3V : 1 :
+GND* : T2 : : : : 1 :
+GND* : T3 : : : : 1 :
+d_g : T4 : output : 3.3-V LVTTL : : 1 : N
+seven_seg_pin[5] : T5 : output : 3.3-V LVTTL : : 1 : N
+GND* : T6 : : : : 1 :
+GND* : T7 : : : : 1 :
+GND : T8 : gnd : : : :
+VCCIO1 : T9 : power : : 3.3V : 1 :
+GND : T10 : gnd : : : :
+VCCINT : T11 : power : : 1.5V : :
+GND : T12 : gnd : : : :
+VCCINT : T13 : power : : 1.5V : :
+GND : T14 : gnd : : : :
+VCCINT : T15 : power : : 1.5V : :
+GND : T16 : gnd : : : :
+VCCINT : T17 : power : : 1.5V : :
+VCCIO6 : T18 : power : : 3.3V : 6 :
+GND* : T19 : : : : 6 :
+g2_pin : T20 : output : 3.3-V LVTTL : : 6 : N
+GND* : T21 : : : : 6 :
+GND* : T22 : : : : 6 :
+GND* : T23 : : : : 6 :
+GND* : T24 : : : : 6 :
+d_toggle_counter[23] : T25 : output : 3.3-V LVTTL : : 6 : N
+VCCIO6 : T26 : power : : 3.3V : 6 :
+seven_seg_pin[6] : U1 : output : 3.3-V LVTTL : : 1 : N
+seven_seg_pin[3] : U2 : output : 3.3-V LVTTL : : 1 : N
+GND* : U3 : : : : 1 :
+GND* : U4 : : : : 1 :
+d_toggle_counter[21] : U5 : output : 3.3-V LVTTL : : 1 : N
+seven_seg_pin[13] : U6 : output : 3.3-V LVTTL : : 1 : N
+d_toggle_counter[22] : U7 : output : 3.3-V LVTTL : : 1 : N
+g0_pin : U8 : output : 3.3-V LVTTL : : 1 : N
+GND* : U9 : : : : 1 :
+VCCINT : U10 : power : : 1.5V : :
+GND : U11 : gnd : : : :
+VCCINT : U12 : power : : 1.5V : :
+GND : U13 : gnd : : : :
+VCCINT : U14 : power : : 1.5V : :
+GND : U15 : gnd : : : :
+VCCINT : U16 : power : : 1.5V : :
+GND : U17 : gnd : : : :
+g1_pin : U18 : output : 3.3-V LVTTL : : 6 : N
+seven_seg_pin[0] : U19 : output : 3.3-V LVTTL : : 6 : N
+GND* : U20 : : : : 6 :
+seven_seg_pin[4] : U21 : output : 3.3-V LVTTL : : 6 : N
+d_toggle_counter[24] : U22 : output : 3.3-V LVTTL : : 6 : N
+GND* : U23 : : : : 6 :
+GND* : U24 : : : : 6 :
+GND* : U25 : : : : 6 :
+GND* : U26 : : : : 6 :
+GND* : V1 : : : : 1 :
+GND* : V2 : : : : 1 :
+GND* : V3 : : : : 1 :
+GND* : V4 : : : : 1 :
+GND* : V5 : : : : 1 :
+GND* : V6 : : : : 1 :
+GND : V7 : gnd : : : :
+GND* : V8 : : : : 1 :
+GND : V9 : gnd : : : :
+GND : V10 : gnd : : : :
+VCCIO8 : V11 : power : : 3.3V : 8 :
+VCCIO8 : V12 : power : : 3.3V : 8 :
+GND : V13 : gnd : : : :
+GND : V14 : gnd : : : :
+VCCIO7 : V15 : power : : 3.3V : 7 :
+VCCIO7 : V16 : power : : 3.3V : 7 :
+GND : V17 : gnd : : : :
+GND : V18 : gnd : : : :
+GND* : V19 : : : : 6 :
+GND : V20 : gnd : : : :
+GND* : V21 : : : : 6 :
+GND* : V22 : : : : 6 :
+GND* : V23 : : : : 6 :
+GND* : V24 : : : : 6 :
+GND* : V25 : : : : 6 :
+GND* : V26 : : : : 6 :
+GND* : W1 : : : : 1 :
+GND* : W2 : : : : 1 :
+GND* : W3 : : : : 1 :
+GND* : W4 : : : : 1 :
+GND* : W5 : : : : 1 :
+GND* : W6 : : : : 1 :
+GND* : W7 : : : : 1 :
+GND* : W8 : : : : 1 :
+GND* : W9 : : : : 8 :
+GND* : W10 : : : : 8 :
+GND : W11 : gnd : : : :
+PLL_ENA : W12 : : : : 8 :
+MSEL2 : W13 : : : : 8 :
+nCEO : W14 : : : : 7 :
+b1_pin : W15 : output : 3.3-V LVTTL : : 7 : N
+PORSEL : W16 : : : : 7 :
+GND* : W17 : : : : 7 :
+GND* : W18 : : : : 7 :
+GND* : W19 : : : : 6 :
+GND* : W20 : : : : 6 :
+GND* : W21 : : : : 6 :
+GND* : W22 : : : : 6 :
+GND* : W23 : : : : 6 :
+GND* : W24 : : : : 6 :
+GND* : W25 : : : : 6 :
+GND* : W26 : : : : 6 :
+GND* : Y1 : : : : 1 :
+GND* : Y2 : : : : 1 :
+GND* : Y3 : : : : 1 :
+GND* : Y4 : : : : 1 :
+GND* : Y5 : : : : 1 :
+GND* : Y6 : : : : 1 :
+GND : Y7 : gnd : : : :
+GND* : Y8 : : : : 8 :
+GND* : Y9 : : : : 8 :
+GND* : Y10 : : : : 8 :
+d_set_vsync_counter : Y11 : output : 3.3-V LVTTL : : 8 : N
+MSEL0 : Y12 : : : : 8 :
+MSEL1 : Y13 : : : : 8 :
+nCE : Y14 : : : : 7 :
+VCCSEL : Y15 : : : : 7 :
+d_b : Y16 : output : 3.3-V LVTTL : : 7 : N
+GND* : Y17 : : : : 7 :
+GND* : Y18 : : : : 7 :
+GND* : Y19 : : : : 7 :
+GND* : Y20 : : : : 7 :
+GND : Y21 : gnd : : : :
+GND* : Y22 : : : : 6 :
+GND* : Y23 : : : : 6 :
+GND* : Y24 : : : : 6 :
+GND* : Y25 : : : : 6 :
+GND* : Y26 : : : : 6 :
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Full Version
+# Date created = 14:18:28 October 28, 2009
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "14:18:28 October 28, 2009"
+
+# Revisions
+
+PROJECT_REVISION = "vga"
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Full Version
+# Date created = 14:18:28 October 28, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# vga_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY Stratix
+set_global_assignment -name DEVICE EP1S25F672C6
+set_global_assignment -name TOP_LEVEL_ENTITY vga
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:18:28 OCTOBER 28, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION 9.0
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro"
+set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file
--- /dev/null
+
+
+[ProjectWorkspace]
+ptn_Child1=Frames
+
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
\ No newline at end of file
--- /dev/null
+Classic Timing Analyzer report for vga
+Wed Oct 28 14:19:50 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Timing Analyzer Summary
+ 3. Timing Analyzer Settings
+ 4. Clock Settings Summary
+ 5. Parallel Compilation
+ 6. Clock Setup: 'clk_pin'
+ 7. tsu
+ 8. tco
+ 9. tpd
+ 10. th
+ 11. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++------------------------------+-------+---------------+----------------------------------+--------------------------------------------+------------------------------------------+------------+----------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++------------------------------+-------+---------------+----------------------------------+--------------------------------------------+------------------------------------------+------------+----------+--------------+
+; Worst-case tsu ; N/A ; None ; 6.543 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_0 ; -- ; clk_pin ; 0 ;
+; Worst-case tco ; N/A ; None ; 10.494 ns ; vga_driver:vga_driver_unit|vsync_state_0 ; d_set_vsync_counter ; clk_pin ; -- ; 0 ;
+; Worst-case tpd ; N/A ; None ; 11.756 ns ; reset_pin ; seven_seg_pin[1] ; -- ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -2.787 ns ; reset_pin ; dly_counter[1] ; -- ; clk_pin ; 0 ;
+; Clock Setup: 'clk_pin' ; N/A ; None ; 191.90 MHz ( period = 5.211 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++------------------------------+-------+---------------+----------------------------------+--------------------------------------------+------------------------------------------+------------+----------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Option ; Setting ; From ; To ; Entity Name ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Device Name ; EP1S25F672C6 ; ; ; ;
+; Timing Models ; Final ; ; ; ;
+; Default hold multicycle ; Same as Multicycle ; ; ; ;
+; Cut paths between unrelated clock domains ; On ; ; ; ;
+; Cut off read during write signal paths ; On ; ; ; ;
+; Cut off feedback from I/O pins ; On ; ; ; ;
+; Report Combined Fast/Slow Timing ; Off ; ; ; ;
+; Ignore Clock Settings ; Off ; ; ; ;
+; Analyze latches as synchronous elements ; On ; ; ; ;
+; Enable Recovery/Removal analysis ; Off ; ; ; ;
+; Enable Clock Latency ; Off ; ; ; ;
+; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+; Minimum Core Junction Temperature ; 0 ; ; ; ;
+; Maximum Core Junction Temperature ; 85 ; ; ; ;
+; Number of source nodes to report per destination node ; 10 ; ; ; ;
+; Number of destination nodes to report ; 10 ; ; ; ;
+; Number of paths to report ; 200 ; ; ; ;
+; Report Minimum Timing Checks ; Off ; ; ; ;
+; Use Fast Timing Models ; Off ; ; ; ;
+; Report IO Paths Separately ; Off ; ; ; ;
+; Perform Multicorner Analysis ; Off ; ; ; ;
+; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+; Output I/O Timing Endpoint ; Near End ; ; ; ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Settings Summary ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+; clk_pin ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 2 ;
+; Maximum allowed ; 2 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 1 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; 1 processor ; 100.0% ;
+; 2 processors ; 0.0% ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'clk_pin' ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; N/A ; 191.90 MHz ( period = 5.211 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 5.018 ns ;
+; N/A ; 191.90 MHz ( period = 5.211 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 5.018 ns ;
+; N/A ; 194.10 MHz ( period = 5.152 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.974 ns ;
+; N/A ; 194.10 MHz ( period = 5.152 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.974 ns ;
+; N/A ; 195.50 MHz ( period = 5.115 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.922 ns ;
+; N/A ; 195.50 MHz ( period = 5.115 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.922 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.61 MHz ( period = 5.035 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.849 ns ;
+; N/A ; 198.65 MHz ( period = 5.034 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.841 ns ;
+; N/A ; 198.65 MHz ( period = 5.034 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.841 ns ;
+; N/A ; 199.04 MHz ( period = 5.024 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.831 ns ;
+; N/A ; 199.04 MHz ( period = 5.024 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.831 ns ;
+; N/A ; 200.16 MHz ( period = 4.996 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.803 ns ;
+; N/A ; 200.16 MHz ( period = 4.996 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.803 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 200.56 MHz ( period = 4.986 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.800 ns ;
+; N/A ; 204.00 MHz ( period = 4.902 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.709 ns ;
+; N/A ; 204.00 MHz ( period = 4.902 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.709 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 206.06 MHz ( period = 4.853 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.667 ns ;
+; N/A ; 207.21 MHz ( period = 4.826 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|v_enable_sig ; clk_pin ; clk_pin ; None ; None ; 4.620 ns ;
+; N/A ; 207.73 MHz ( period = 4.814 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.621 ns ;
+; N/A ; 207.73 MHz ( period = 4.814 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.621 ns ;
+; N/A ; 207.77 MHz ( period = 4.813 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ; clk_pin ; None ; None ; 4.635 ns ;
+; N/A ; 207.81 MHz ( period = 4.812 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ; clk_pin ; None ; None ; 4.634 ns ;
+; N/A ; 207.94 MHz ( period = 4.809 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ; clk_pin ; None ; None ; 4.631 ns ;
+; N/A ; 209.21 MHz ( period = 4.780 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|line_counter_sig_5 ; clk_pin ; clk_pin ; None ; None ; 4.576 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.25 MHz ( period = 4.779 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.593 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.51 MHz ( period = 4.773 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.602 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 209.73 MHz ( period = 4.768 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.582 ns ;
+; N/A ; 210.97 MHz ( period = 4.740 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ; clk_pin ; None ; None ; 4.554 ns ;
+; N/A ; 210.97 MHz ( period = 4.740 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ; clk_pin ; None ; None ; 4.554 ns ;
+; N/A ; 211.01 MHz ( period = 4.739 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ; clk_pin ; None ; None ; 4.553 ns ;
+; N/A ; 211.15 MHz ( period = 4.736 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ; clk_pin ; None ; None ; 4.550 ns ;
+; N/A ; 211.15 MHz ( period = 4.736 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.558 ns ;
+; N/A ; 211.15 MHz ( period = 4.736 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.558 ns ;
+; N/A ; 212.45 MHz ( period = 4.707 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.521 ns ;
+; N/A ; 212.45 MHz ( period = 4.707 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ; clk_pin ; None ; None ; 4.521 ns ;
+; N/A ; 212.45 MHz ( period = 4.707 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.521 ns ;
+; N/A ; 212.45 MHz ( period = 4.707 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.521 ns ;
+; N/A ; 212.59 MHz ( period = 4.704 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ; clk_pin ; None ; None ; 4.518 ns ;
+; N/A ; 212.59 MHz ( period = 4.704 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_3 ; vga_driver:vga_driver_unit|column_counter_sig_8 ; clk_pin ; clk_pin ; None ; None ; 4.518 ns ;
+; N/A ; 212.72 MHz ( period = 4.701 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.508 ns ;
+; N/A ; 212.72 MHz ( period = 4.701 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.508 ns ;
+; N/A ; 214.32 MHz ( period = 4.666 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.473 ns ;
+; N/A ; 214.32 MHz ( period = 4.666 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.473 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.73 MHz ( period = 4.657 ns ) ; vga_driver:vga_driver_unit|hsync_counter_1 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.471 ns ;
+; N/A ; 214.82 MHz ( period = 4.655 ns ) ; vga_driver:vga_driver_unit|hsync_counter_3 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.462 ns ;
+; N/A ; 214.82 MHz ( period = 4.655 ns ) ; vga_driver:vga_driver_unit|hsync_counter_3 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.462 ns ;
+; N/A ; 215.15 MHz ( period = 4.648 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.477 ns ;
+; N/A ; 215.15 MHz ( period = 4.648 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.477 ns ;
+; N/A ; 215.15 MHz ( period = 4.648 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.477 ns ;
+; N/A ; 216.73 MHz ( period = 4.614 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ; clk_pin ; None ; None ; 4.436 ns ;
+; N/A ; 216.78 MHz ( period = 4.613 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ; clk_pin ; None ; None ; 4.435 ns ;
+; N/A ; 216.87 MHz ( period = 4.611 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.425 ns ;
+; N/A ; 216.87 MHz ( period = 4.611 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.425 ns ;
+; N/A ; 216.87 MHz ( period = 4.611 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.425 ns ;
+; N/A ; 216.92 MHz ( period = 4.610 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ; clk_pin ; None ; None ; 4.432 ns ;
+; N/A ; 218.25 MHz ( period = 4.582 ns ) ; vga_driver:vga_driver_unit|hsync_state_0 ; vga_driver:vga_driver_unit|line_counter_sig_2 ; clk_pin ; clk_pin ; None ; None ; 4.378 ns ;
+; N/A ; 219.68 MHz ( period = 4.552 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|h_enable_sig ; clk_pin ; clk_pin ; None ; None ; 4.310 ns ;
+; N/A ; 220.22 MHz ( period = 4.541 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ; clk_pin ; None ; None ; 4.355 ns ;
+; N/A ; 220.22 MHz ( period = 4.541 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ; clk_pin ; None ; None ; 4.355 ns ;
+; N/A ; 220.26 MHz ( period = 4.540 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ; clk_pin ; None ; None ; 4.354 ns ;
+; N/A ; 220.41 MHz ( period = 4.537 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ; clk_pin ; None ; None ; 4.351 ns ;
+; N/A ; 220.51 MHz ( period = 4.535 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ; clk_pin ; None ; None ; 4.357 ns ;
+; N/A ; 220.56 MHz ( period = 4.534 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ; clk_pin ; None ; None ; 4.356 ns ;
+; N/A ; 220.70 MHz ( period = 4.531 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ; clk_pin ; None ; None ; 4.353 ns ;
+; N/A ; 220.75 MHz ( period = 4.530 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.344 ns ;
+; N/A ; 220.75 MHz ( period = 4.530 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.344 ns ;
+; N/A ; 220.75 MHz ( period = 4.530 ns ) ; vga_driver:vga_driver_unit|hsync_counter_7 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.344 ns ;
+; N/A ; 221.24 MHz ( period = 4.520 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.334 ns ;
+; N/A ; 221.24 MHz ( period = 4.520 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.334 ns ;
+; N/A ; 221.24 MHz ( period = 4.520 ns ) ; vga_driver:vga_driver_unit|hsync_counter_4 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.334 ns ;
+; N/A ; 221.63 MHz ( period = 4.512 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ; clk_pin ; None ; None ; 4.334 ns ;
+; N/A ; 221.68 MHz ( period = 4.511 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ; clk_pin ; None ; None ; 4.333 ns ;
+; N/A ; 221.83 MHz ( period = 4.508 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ; clk_pin ; None ; None ; 4.322 ns ;
+; N/A ; 221.83 MHz ( period = 4.508 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ; clk_pin ; None ; None ; 4.330 ns ;
+; N/A ; 221.98 MHz ( period = 4.505 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ; clk_pin ; None ; None ; 4.319 ns ;
+; N/A ; 221.98 MHz ( period = 4.505 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_0 ; vga_driver:vga_driver_unit|column_counter_sig_8 ; clk_pin ; clk_pin ; None ; None ; 4.319 ns ;
+; N/A ; 222.27 MHz ( period = 4.499 ns ) ; vga_driver:vga_driver_unit|hsync_counter_8 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.313 ns ;
+; N/A ; 222.62 MHz ( period = 4.492 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.306 ns ;
+; N/A ; 222.62 MHz ( period = 4.492 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.306 ns ;
+; N/A ; 222.62 MHz ( period = 4.492 ns ) ; vga_driver:vga_driver_unit|hsync_counter_5 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.306 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 223.06 MHz ( period = 4.483 ns ) ; vga_driver:vga_driver_unit|hsync_counter_2 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.297 ns ;
+; N/A ; 224.11 MHz ( period = 4.462 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ; clk_pin ; None ; None ; 4.276 ns ;
+; N/A ; 224.11 MHz ( period = 4.462 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ; clk_pin ; None ; None ; 4.276 ns ;
+; N/A ; 224.16 MHz ( period = 4.461 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ; clk_pin ; None ; None ; 4.275 ns ;
+; N/A ; 224.32 MHz ( period = 4.458 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ; clk_pin ; None ; None ; 4.272 ns ;
+; N/A ; 225.02 MHz ( period = 4.444 ns ) ; vga_driver:vga_driver_unit|hsync_state_5 ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ; clk_pin ; None ; None ; 4.258 ns ;
+; N/A ; 225.02 MHz ( period = 4.444 ns ) ; vga_driver:vga_driver_unit|hsync_state_5 ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ; clk_pin ; None ; None ; 4.258 ns ;
+; N/A ; 225.23 MHz ( period = 4.440 ns ) ; dly_counter[0] ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.269 ns ;
+; N/A ; 225.28 MHz ( period = 4.439 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ; clk_pin ; None ; None ; 4.253 ns ;
+; N/A ; 225.28 MHz ( period = 4.439 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ; clk_pin ; None ; None ; 4.253 ns ;
+; N/A ; 225.33 MHz ( period = 4.438 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ; clk_pin ; None ; None ; 4.252 ns ;
+; N/A ; 225.48 MHz ( period = 4.435 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ; clk_pin ; None ; None ; 4.249 ns ;
+; N/A ; 225.78 MHz ( period = 4.429 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ; clk_pin ; None ; None ; 4.243 ns ;
+; N/A ; 225.94 MHz ( period = 4.426 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ; clk_pin ; None ; None ; 4.240 ns ;
+; N/A ; 225.94 MHz ( period = 4.426 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_8 ; vga_driver:vga_driver_unit|column_counter_sig_8 ; clk_pin ; clk_pin ; None ; None ; 4.240 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.55 MHz ( period = 4.414 ns ) ; vga_driver:vga_driver_unit|hsync_counter_0 ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 226.76 MHz ( period = 4.410 ns ) ; dly_counter[1] ; vga_driver:vga_driver_unit|v_enable_sig ; clk_pin ; clk_pin ; None ; None ; 4.204 ns ;
+; N/A ; 226.96 MHz ( period = 4.406 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ; clk_pin ; None ; None ; 4.220 ns ;
+; N/A ; 227.07 MHz ( period = 4.404 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_1 ; vga_control:vga_control_unit|b ; clk_pin ; clk_pin ; None ; None ; 4.230 ns ;
+; N/A ; 227.12 MHz ( period = 4.403 ns ) ; vga_driver:vga_driver_unit|hsync_counter_9 ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ; clk_pin ; None ; None ; 4.217 ns ;
+; N/A ; 227.12 MHz ( period = 4.403 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ; clk_pin ; None ; None ; 4.217 ns ;
+; N/A ; 227.12 MHz ( period = 4.403 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_2 ; vga_driver:vga_driver_unit|column_counter_sig_8 ; clk_pin ; clk_pin ; None ; None ; 4.217 ns ;
+; N/A ; 227.17 MHz ( period = 4.402 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_1 ; vga_control:vga_control_unit|r ; clk_pin ; clk_pin ; None ; None ; 4.228 ns ;
+; N/A ; 227.38 MHz ( period = 4.398 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ; clk_pin ; None ; None ; 4.212 ns ;
+; N/A ; 227.38 MHz ( period = 4.398 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ; clk_pin ; None ; None ; 4.212 ns ;
+; N/A ; 227.38 MHz ( period = 4.398 ns ) ; vga_driver:vga_driver_unit|hsync_counter_6 ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ; clk_pin ; None ; None ; 4.212 ns ;
+; N/A ; 227.43 MHz ( period = 4.397 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_1 ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ; clk_pin ; None ; None ; 4.219 ns ;
+; N/A ; 227.48 MHz ( period = 4.396 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_1 ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ; clk_pin ; None ; None ; 4.218 ns ;
+; N/A ; 227.53 MHz ( period = 4.395 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_4 ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ; clk_pin ; None ; None ; 4.217 ns ;
+; N/A ; 227.58 MHz ( period = 4.394 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_4 ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ; clk_pin ; None ; None ; 4.216 ns ;
+; N/A ; 227.63 MHz ( period = 4.393 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_1 ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ; clk_pin ; None ; None ; 4.215 ns ;
+; N/A ; 227.74 MHz ( period = 4.391 ns ) ; vga_driver:vga_driver_unit|column_counter_sig_4 ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ; clk_pin ; None ; None ; 4.213 ns ;
+; N/A ; 227.95 MHz ( period = 4.387 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ; clk_pin ; None ; None ; 4.118 ns ;
+; N/A ; 227.95 MHz ( period = 4.387 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ; clk_pin ; None ; None ; 4.118 ns ;
+; N/A ; 228.10 MHz ( period = 4.384 ns ) ; vga_driver:vga_driver_unit|line_counter_sig_8 ; vga_control:vga_control_unit|b ; clk_pin ; clk_pin ; None ; None ; 4.152 ns ;
+; N/A ; 228.21 MHz ( period = 4.382 ns ) ; vga_driver:vga_driver_unit|line_counter_sig_8 ; vga_control:vga_control_unit|r ; clk_pin ; clk_pin ; None ; None ; 4.150 ns ;
+; N/A ; 228.47 MHz ( period = 4.377 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ; clk_pin ; None ; None ; 4.108 ns ;
+; N/A ; 228.47 MHz ( period = 4.377 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ; clk_pin ; None ; None ; 4.108 ns ;
+; N/A ; 228.47 MHz ( period = 4.377 ns ) ; vga_driver:vga_driver_unit|hsync_state_1 ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ; clk_pin ; None ; None ; 4.108 ns ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------+-------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; tsu ;
++-------+--------------+------------+-----------+-------------------------------------------------+----------+
+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
++-------+--------------+------------+-----------+-------------------------------------------------+----------+
+; N/A ; None ; 6.543 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ;
+; N/A ; None ; 6.543 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ;
+; N/A ; None ; 6.217 ns ; reset_pin ; vga_driver:vga_driver_unit|v_enable_sig ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ;
+; N/A ; None ; 6.164 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ;
+; N/A ; None ; 6.039 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ;
+; N/A ; None ; 6.039 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ;
+; N/A ; None ; 6.039 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ;
+; N/A ; None ; 5.943 ns ; reset_pin ; vga_driver:vga_driver_unit|h_enable_sig ; clk_pin ;
+; N/A ; None ; 5.831 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ;
+; N/A ; None ; 5.641 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_1 ; clk_pin ;
+; N/A ; None ; 5.614 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ;
+; N/A ; None ; 5.614 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ;
+; N/A ; None ; 5.614 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ;
+; N/A ; None ; 5.418 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_0 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_1 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_2 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_3 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_4 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_5 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_6 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_7 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_8 ; clk_pin ;
+; N/A ; None ; 5.351 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_9 ; clk_pin ;
+; N/A ; None ; 5.338 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ;
+; N/A ; None ; 5.338 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ;
+; N/A ; None ; 5.328 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ;
+; N/A ; None ; 5.328 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ;
+; N/A ; None ; 5.328 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ;
+; N/A ; None ; 5.328 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ;
+; N/A ; None ; 5.306 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ;
+; N/A ; None ; 5.306 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ;
+; N/A ; None ; 5.262 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ;
+; N/A ; None ; 5.232 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_0 ; clk_pin ;
+; N/A ; None ; 5.232 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_1 ; clk_pin ;
+; N/A ; None ; 5.232 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_2 ; clk_pin ;
+; N/A ; None ; 5.232 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_3 ; clk_pin ;
+; N/A ; None ; 5.158 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_8 ; clk_pin ;
+; N/A ; None ; 5.012 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ;
+; N/A ; None ; 4.939 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_8 ; clk_pin ;
+; N/A ; None ; 4.939 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_7 ; clk_pin ;
+; N/A ; None ; 4.939 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_4 ; clk_pin ;
+; N/A ; None ; 4.939 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_6 ; clk_pin ;
+; N/A ; None ; 4.387 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_6 ; clk_pin ;
+; N/A ; None ; 4.173 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_5 ; clk_pin ;
+; N/A ; None ; 3.151 ns ; reset_pin ; dly_counter[0] ; clk_pin ;
+; N/A ; None ; 2.920 ns ; reset_pin ; vga_driver:vga_driver_unit|h_sync ; clk_pin ;
+; N/A ; None ; 2.903 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_6 ; clk_pin ;
+; N/A ; None ; 2.900 ns ; reset_pin ; vga_driver:vga_driver_unit|v_sync ; clk_pin ;
+; N/A ; None ; 2.897 ns ; reset_pin ; dly_counter[1] ; clk_pin ;
++-------+--------------+------------+-----------+-------------------------------------------------+----------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; tco ;
++-------+--------------+------------+----------------------------------------------------+----------------------+------------+
+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
++-------+--------------+------------+----------------------------------------------------+----------------------+------------+
+; N/A ; None ; 10.494 ns ; vga_driver:vga_driver_unit|vsync_state_0 ; d_set_vsync_counter ; clk_pin ;
+; N/A ; None ; 10.365 ns ; dly_counter[0] ; seven_seg_pin[9] ; clk_pin ;
+; N/A ; None ; 10.365 ns ; dly_counter[0] ; seven_seg_pin[7] ; clk_pin ;
+; N/A ; None ; 10.365 ns ; dly_counter[0] ; seven_seg_pin[1] ; clk_pin ;
+; N/A ; None ; 10.362 ns ; dly_counter[0] ; seven_seg_pin[12] ; clk_pin ;
+; N/A ; None ; 10.329 ns ; dly_counter[0] ; seven_seg_pin[10] ; clk_pin ;
+; N/A ; None ; 10.288 ns ; vga_driver:vga_driver_unit|vsync_state_6 ; d_set_vsync_counter ; clk_pin ;
+; N/A ; None ; 10.192 ns ; dly_counter[0] ; seven_seg_pin[11] ; clk_pin ;
+; N/A ; None ; 10.045 ns ; dly_counter[0] ; seven_seg_pin[8] ; clk_pin ;
+; N/A ; None ; 10.045 ns ; dly_counter[0] ; seven_seg_pin[2] ; clk_pin ;
+; N/A ; None ; 9.951 ns ; vga_driver:vga_driver_unit|hsync_counter_1 ; d_hsync_counter[1] ; clk_pin ;
+; N/A ; None ; 9.949 ns ; dly_counter[1] ; seven_seg_pin[9] ; clk_pin ;
+; N/A ; None ; 9.949 ns ; dly_counter[1] ; seven_seg_pin[7] ; clk_pin ;
+; N/A ; None ; 9.949 ns ; dly_counter[1] ; seven_seg_pin[1] ; clk_pin ;
+; N/A ; None ; 9.946 ns ; dly_counter[1] ; seven_seg_pin[12] ; clk_pin ;
+; N/A ; None ; 9.913 ns ; dly_counter[1] ; seven_seg_pin[10] ; clk_pin ;
+; N/A ; None ; 9.776 ns ; dly_counter[1] ; seven_seg_pin[11] ; clk_pin ;
+; N/A ; None ; 9.629 ns ; dly_counter[1] ; seven_seg_pin[8] ; clk_pin ;
+; N/A ; None ; 9.629 ns ; dly_counter[1] ; seven_seg_pin[2] ; clk_pin ;
+; N/A ; None ; 9.578 ns ; vga_driver:vga_driver_unit|hsync_state_0 ; d_set_hsync_counter ; clk_pin ;
+; N/A ; None ; 9.535 ns ; vga_control:vga_control_unit|toggle_counter_sig_11 ; d_toggle_counter[11] ; clk_pin ;
+; N/A ; None ; 9.515 ns ; vga_driver:vga_driver_unit|vsync_state_4 ; d_vsync_state[4] ; clk_pin ;
+; N/A ; None ; 9.461 ns ; vga_control:vga_control_unit|b ; d_b ; clk_pin ;
+; N/A ; None ; 9.461 ns ; vga_control:vga_control_unit|b ; b0_pin ; clk_pin ;
+; N/A ; None ; 9.396 ns ; vga_control:vga_control_unit|b ; b1_pin ; clk_pin ;
+; N/A ; None ; 9.374 ns ; vga_driver:vga_driver_unit|hsync_counter_9 ; d_hsync_counter[9] ; clk_pin ;
+; N/A ; None ; 9.225 ns ; vga_driver:vga_driver_unit|hsync_counter_6 ; d_hsync_counter[6] ; clk_pin ;
+; N/A ; None ; 9.176 ns ; vga_driver:vga_driver_unit|hsync_state_1 ; d_hsync_state[1] ; clk_pin ;
+; N/A ; None ; 9.176 ns ; vga_driver:vga_driver_unit|hsync_state_1 ; d_set_column_counter ; clk_pin ;
+; N/A ; None ; 9.091 ns ; vga_driver:vga_driver_unit|h_enable_sig ; d_h_enable ; clk_pin ;
+; N/A ; None ; 9.032 ns ; vga_driver:vga_driver_unit|vsync_state_1 ; d_vsync_state[1] ; clk_pin ;
+; N/A ; None ; 9.032 ns ; vga_driver:vga_driver_unit|vsync_state_1 ; d_set_line_counter ; clk_pin ;
+; N/A ; None ; 9.007 ns ; vga_driver:vga_driver_unit|hsync_counter_4 ; d_hsync_counter[4] ; clk_pin ;
+; N/A ; None ; 9.006 ns ; vga_driver:vga_driver_unit|vsync_state_2 ; d_vsync_state[2] ; clk_pin ;
+; N/A ; None ; 8.974 ns ; vga_control:vga_control_unit|toggle_counter_sig_3 ; d_toggle_counter[3] ; clk_pin ;
+; N/A ; None ; 8.942 ns ; vga_driver:vga_driver_unit|hsync_counter_8 ; d_hsync_counter[8] ; clk_pin ;
+; N/A ; None ; 8.882 ns ; vga_driver:vga_driver_unit|column_counter_sig_5 ; d_column_counter[5] ; clk_pin ;
+; N/A ; None ; 8.863 ns ; vga_driver:vga_driver_unit|vsync_state_0 ; d_vsync_state[0] ; clk_pin ;
+; N/A ; None ; 8.846 ns ; vga_control:vga_control_unit|toggle_sig ; d_toggle ; clk_pin ;
+; N/A ; None ; 8.845 ns ; vga_driver:vga_driver_unit|hsync_state_6 ; d_hsync_state[6] ; clk_pin ;
+; N/A ; None ; 8.841 ns ; vga_driver:vga_driver_unit|vsync_counter_5 ; d_vsync_counter[5] ; clk_pin ;
+; N/A ; None ; 8.820 ns ; vga_driver:vga_driver_unit|vsync_state_3 ; d_vsync_state[3] ; clk_pin ;
+; N/A ; None ; 8.805 ns ; vga_driver:vga_driver_unit|vsync_counter_8 ; d_vsync_counter[8] ; clk_pin ;
+; N/A ; None ; 8.795 ns ; vga_driver:vga_driver_unit|hsync_state_4 ; d_hsync_state[4] ; clk_pin ;
+; N/A ; None ; 8.788 ns ; vga_driver:vga_driver_unit|hsync_counter_3 ; d_hsync_counter[3] ; clk_pin ;
+; N/A ; None ; 8.757 ns ; vga_control:vga_control_unit|r ; d_r ; clk_pin ;
+; N/A ; None ; 8.757 ns ; vga_control:vga_control_unit|r ; r1_pin ; clk_pin ;
+; N/A ; None ; 8.701 ns ; vga_driver:vga_driver_unit|column_counter_sig_8 ; d_column_counter[8] ; clk_pin ;
+; N/A ; None ; 8.690 ns ; vga_driver:vga_driver_unit|v_sync ; d_vsync ; clk_pin ;
+; N/A ; None ; 8.690 ns ; vga_driver:vga_driver_unit|v_sync ; vsync_pin ; clk_pin ;
+; N/A ; None ; 8.667 ns ; vga_control:vga_control_unit|toggle_counter_sig_13 ; d_toggle_counter[13] ; clk_pin ;
+; N/A ; None ; 8.624 ns ; vga_driver:vga_driver_unit|vsync_state_5 ; d_vsync_state[5] ; clk_pin ;
+; N/A ; None ; 8.614 ns ; vga_driver:vga_driver_unit|hsync_state_6 ; d_set_hsync_counter ; clk_pin ;
+; N/A ; None ; 8.586 ns ; vga_driver:vga_driver_unit|hsync_state_5 ; d_hsync_state[5] ; clk_pin ;
+; N/A ; None ; 8.585 ns ; vga_driver:vga_driver_unit|vsync_state_6 ; d_vsync_state[6] ; clk_pin ;
+; N/A ; None ; 8.521 ns ; vga_control:vga_control_unit|toggle_counter_sig_19 ; d_toggle_counter[19] ; clk_pin ;
+; N/A ; None ; 8.520 ns ; vga_driver:vga_driver_unit|line_counter_sig_5 ; d_line_counter[5] ; clk_pin ;
+; N/A ; None ; 8.506 ns ; vga_driver:vga_driver_unit|vsync_counter_4 ; d_vsync_counter[4] ; clk_pin ;
+; N/A ; None ; 8.481 ns ; vga_driver:vga_driver_unit|line_counter_sig_2 ; d_line_counter[2] ; clk_pin ;
+; N/A ; None ; 8.452 ns ; vga_driver:vga_driver_unit|hsync_state_3 ; d_hsync_state[3] ; clk_pin ;
+; N/A ; None ; 8.449 ns ; vga_control:vga_control_unit|r ; r2_pin ; clk_pin ;
+; N/A ; None ; 8.449 ns ; vga_control:vga_control_unit|r ; r0_pin ; clk_pin ;
+; N/A ; None ; 8.445 ns ; vga_driver:vga_driver_unit|vsync_counter_2 ; d_vsync_counter[2] ; clk_pin ;
+; N/A ; None ; 8.432 ns ; vga_driver:vga_driver_unit|column_counter_sig_6 ; d_column_counter[6] ; clk_pin ;
+; N/A ; None ; 8.412 ns ; vga_driver:vga_driver_unit|v_enable_sig ; d_v_enable ; clk_pin ;
+; N/A ; None ; 8.391 ns ; vga_driver:vga_driver_unit|vsync_counter_7 ; d_vsync_counter[7] ; clk_pin ;
+; N/A ; None ; 8.388 ns ; vga_control:vga_control_unit|toggle_counter_sig_17 ; d_toggle_counter[17] ; clk_pin ;
+; N/A ; None ; 8.387 ns ; vga_control:vga_control_unit|toggle_counter_sig_20 ; d_toggle_counter[20] ; clk_pin ;
+; N/A ; None ; 8.361 ns ; vga_driver:vga_driver_unit|vsync_counter_6 ; d_vsync_counter[6] ; clk_pin ;
+; N/A ; None ; 8.361 ns ; vga_driver:vga_driver_unit|line_counter_sig_8 ; d_line_counter[8] ; clk_pin ;
+; N/A ; None ; 8.338 ns ; vga_driver:vga_driver_unit|vsync_counter_1 ; d_vsync_counter[1] ; clk_pin ;
+; N/A ; None ; 8.326 ns ; vga_driver:vga_driver_unit|hsync_counter_0 ; d_hsync_counter[0] ; clk_pin ;
+; N/A ; None ; 8.296 ns ; vga_driver:vga_driver_unit|column_counter_sig_0 ; d_column_counter[0] ; clk_pin ;
+; N/A ; None ; 8.285 ns ; vga_driver:vga_driver_unit|column_counter_sig_1 ; d_column_counter[1] ; clk_pin ;
+; N/A ; None ; 8.281 ns ; vga_control:vga_control_unit|toggle_counter_sig_9 ; d_toggle_counter[9] ; clk_pin ;
+; N/A ; None ; 8.281 ns ; vga_driver:vga_driver_unit|line_counter_sig_4 ; d_line_counter[4] ; clk_pin ;
+; N/A ; None ; 8.257 ns ; vga_control:vga_control_unit|toggle_counter_sig_8 ; d_toggle_counter[8] ; clk_pin ;
+; N/A ; None ; 8.252 ns ; vga_driver:vga_driver_unit|hsync_counter_7 ; d_hsync_counter[7] ; clk_pin ;
+; N/A ; None ; 8.237 ns ; vga_driver:vga_driver_unit|column_counter_sig_3 ; d_column_counter[3] ; clk_pin ;
+; N/A ; None ; 8.228 ns ; vga_control:vga_control_unit|toggle_counter_sig_7 ; d_toggle_counter[7] ; clk_pin ;
+; N/A ; None ; 8.215 ns ; vga_driver:vga_driver_unit|line_counter_sig_6 ; d_line_counter[6] ; clk_pin ;
+; N/A ; None ; 8.206 ns ; vga_control:vga_control_unit|toggle_counter_sig_1 ; d_toggle_counter[1] ; clk_pin ;
+; N/A ; None ; 8.151 ns ; vga_driver:vga_driver_unit|line_counter_sig_7 ; d_line_counter[7] ; clk_pin ;
+; N/A ; None ; 8.125 ns ; vga_driver:vga_driver_unit|h_sync ; d_hsync ; clk_pin ;
+; N/A ; None ; 8.125 ns ; vga_driver:vga_driver_unit|h_sync ; hsync_pin ; clk_pin ;
+; N/A ; None ; 8.115 ns ; vga_driver:vga_driver_unit|hsync_counter_5 ; d_hsync_counter[5] ; clk_pin ;
+; N/A ; None ; 8.106 ns ; vga_driver:vga_driver_unit|hsync_state_2 ; d_hsync_state[2] ; clk_pin ;
+; N/A ; None ; 8.073 ns ; vga_control:vga_control_unit|toggle_counter_sig_18 ; d_toggle_counter[18] ; clk_pin ;
+; N/A ; None ; 8.046 ns ; vga_control:vga_control_unit|toggle_counter_sig_16 ; d_toggle_counter[16] ; clk_pin ;
+; N/A ; None ; 8.042 ns ; vga_control:vga_control_unit|toggle_counter_sig_14 ; d_toggle_counter[14] ; clk_pin ;
+; N/A ; None ; 8.009 ns ; vga_control:vga_control_unit|toggle_counter_sig_12 ; d_toggle_counter[12] ; clk_pin ;
+; N/A ; None ; 8.008 ns ; vga_control:vga_control_unit|toggle_counter_sig_6 ; d_toggle_counter[6] ; clk_pin ;
+; N/A ; None ; 8.002 ns ; vga_control:vga_control_unit|toggle_counter_sig_4 ; d_toggle_counter[4] ; clk_pin ;
+; N/A ; None ; 7.992 ns ; vga_driver:vga_driver_unit|vsync_counter_3 ; d_vsync_counter[3] ; clk_pin ;
+; N/A ; None ; 7.988 ns ; vga_control:vga_control_unit|toggle_counter_sig_5 ; d_toggle_counter[5] ; clk_pin ;
+; N/A ; None ; 7.986 ns ; vga_driver:vga_driver_unit|column_counter_sig_2 ; d_column_counter[2] ; clk_pin ;
+; N/A ; None ; 7.985 ns ; vga_driver:vga_driver_unit|column_counter_sig_7 ; d_column_counter[7] ; clk_pin ;
+; N/A ; None ; 7.982 ns ; vga_control:vga_control_unit|toggle_counter_sig_10 ; d_toggle_counter[10] ; clk_pin ;
+; N/A ; None ; 7.982 ns ; vga_driver:vga_driver_unit|column_counter_sig_4 ; d_column_counter[4] ; clk_pin ;
+; N/A ; None ; 7.971 ns ; vga_driver:vga_driver_unit|column_counter_sig_9 ; d_column_counter[9] ; clk_pin ;
+; N/A ; None ; 7.942 ns ; vga_control:vga_control_unit|toggle_counter_sig_2 ; d_toggle_counter[2] ; clk_pin ;
+; N/A ; None ; 7.927 ns ; vga_driver:vga_driver_unit|hsync_counter_2 ; d_hsync_counter[2] ; clk_pin ;
+; N/A ; None ; 7.904 ns ; vga_driver:vga_driver_unit|vsync_counter_0 ; d_vsync_counter[0] ; clk_pin ;
+; N/A ; None ; 7.870 ns ; vga_driver:vga_driver_unit|hsync_state_0 ; d_hsync_state[0] ; clk_pin ;
+; N/A ; None ; 7.869 ns ; vga_driver:vga_driver_unit|vsync_counter_9 ; d_vsync_counter[9] ; clk_pin ;
+; N/A ; None ; 7.858 ns ; vga_driver:vga_driver_unit|line_counter_sig_1 ; d_line_counter[1] ; clk_pin ;
+; N/A ; None ; 7.854 ns ; vga_driver:vga_driver_unit|line_counter_sig_3 ; d_line_counter[3] ; clk_pin ;
+; N/A ; None ; 7.816 ns ; vga_control:vga_control_unit|toggle_counter_sig_0 ; d_toggle_counter[0] ; clk_pin ;
+; N/A ; None ; 7.805 ns ; vga_driver:vga_driver_unit|line_counter_sig_0 ; d_line_counter[0] ; clk_pin ;
+; N/A ; None ; 7.548 ns ; vga_control:vga_control_unit|toggle_counter_sig_15 ; d_toggle_counter[15] ; clk_pin ;
++-------+--------------+------------+----------------------------------------------------+----------------------+------------+
+
+
++-----------------------------------------------------------------------------+
+; tpd ;
++-------+-------------------+-----------------+-----------+-------------------+
+; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
++-------+-------------------+-----------------+-----------+-------------------+
+; N/A ; None ; 11.756 ns ; reset_pin ; seven_seg_pin[9] ;
+; N/A ; None ; 11.756 ns ; reset_pin ; seven_seg_pin[7] ;
+; N/A ; None ; 11.756 ns ; reset_pin ; seven_seg_pin[1] ;
+; N/A ; None ; 11.753 ns ; reset_pin ; seven_seg_pin[12] ;
+; N/A ; None ; 11.720 ns ; reset_pin ; seven_seg_pin[10] ;
+; N/A ; None ; 11.583 ns ; reset_pin ; seven_seg_pin[11] ;
+; N/A ; None ; 11.436 ns ; reset_pin ; seven_seg_pin[8] ;
+; N/A ; None ; 11.436 ns ; reset_pin ; seven_seg_pin[2] ;
+; N/A ; None ; 5.998 ns ; clk_pin ; d_state_clk ;
++-------+-------------------+-----------------+-----------+-------------------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; th ;
++---------------+-------------+-----------+-----------+-------------------------------------------------+----------+
+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
++---------------+-------------+-----------+-----------+-------------------------------------------------+----------+
+; N/A ; None ; -2.787 ns ; reset_pin ; dly_counter[1] ; clk_pin ;
+; N/A ; None ; -2.790 ns ; reset_pin ; vga_driver:vga_driver_unit|v_sync ; clk_pin ;
+; N/A ; None ; -2.793 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_6 ; clk_pin ;
+; N/A ; None ; -2.810 ns ; reset_pin ; vga_driver:vga_driver_unit|h_sync ; clk_pin ;
+; N/A ; None ; -3.041 ns ; reset_pin ; dly_counter[0] ; clk_pin ;
+; N/A ; None ; -3.591 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_0 ; clk_pin ;
+; N/A ; None ; -3.672 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_0 ; clk_pin ;
+; N/A ; None ; -3.676 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_1 ; clk_pin ;
+; N/A ; None ; -3.679 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_2 ; clk_pin ;
+; N/A ; None ; -3.682 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_3 ; clk_pin ;
+; N/A ; None ; -3.684 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_4 ; clk_pin ;
+; N/A ; None ; -3.686 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_9 ; clk_pin ;
+; N/A ; None ; -3.688 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_7 ; clk_pin ;
+; N/A ; None ; -3.688 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_8 ; clk_pin ;
+; N/A ; None ; -3.689 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_5 ; clk_pin ;
+; N/A ; None ; -3.689 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_counter_6 ; clk_pin ;
+; N/A ; None ; -3.795 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_4 ; clk_pin ;
+; N/A ; None ; -3.795 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_5 ; clk_pin ;
+; N/A ; None ; -3.795 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_2 ; clk_pin ;
+; N/A ; None ; -4.063 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_5 ; clk_pin ;
+; N/A ; None ; -4.277 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_6 ; clk_pin ;
+; N/A ; None ; -4.527 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_3 ; clk_pin ;
+; N/A ; None ; -4.699 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_2 ; clk_pin ;
+; N/A ; None ; -4.701 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_1 ; clk_pin ;
+; N/A ; None ; -4.702 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_0 ; clk_pin ;
+; N/A ; None ; -4.702 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_3 ; clk_pin ;
+; N/A ; None ; -4.705 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_4 ; clk_pin ;
+; N/A ; None ; -4.708 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_9 ; clk_pin ;
+; N/A ; None ; -4.709 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_7 ; clk_pin ;
+; N/A ; None ; -4.709 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_8 ; clk_pin ;
+; N/A ; None ; -4.710 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_6 ; clk_pin ;
+; N/A ; None ; -4.712 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_counter_5 ; clk_pin ;
+; N/A ; None ; -4.829 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_8 ; clk_pin ;
+; N/A ; None ; -4.829 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_7 ; clk_pin ;
+; N/A ; None ; -4.829 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_4 ; clk_pin ;
+; N/A ; None ; -4.829 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_6 ; clk_pin ;
+; N/A ; None ; -4.902 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_7 ; clk_pin ;
+; N/A ; None ; -4.933 ns ; reset_pin ; vga_driver:vga_driver_unit|v_enable_sig ; clk_pin ;
+; N/A ; None ; -4.935 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_3 ; clk_pin ;
+; N/A ; None ; -5.048 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_8 ; clk_pin ;
+; N/A ; None ; -5.122 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_0 ; clk_pin ;
+; N/A ; None ; -5.122 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_1 ; clk_pin ;
+; N/A ; None ; -5.122 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_2 ; clk_pin ;
+; N/A ; None ; -5.122 ns ; reset_pin ; vga_driver:vga_driver_unit|line_counter_sig_3 ; clk_pin ;
+; N/A ; None ; -5.189 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_5 ; clk_pin ;
+; N/A ; None ; -5.189 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_0 ; clk_pin ;
+; N/A ; None ; -5.196 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_5 ; clk_pin ;
+; N/A ; None ; -5.196 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_9 ; clk_pin ;
+; N/A ; None ; -5.197 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_1 ; clk_pin ;
+; N/A ; None ; -5.197 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_4 ; clk_pin ;
+; N/A ; None ; -5.197 ns ; reset_pin ; vga_driver:vga_driver_unit|hsync_state_2 ; clk_pin ;
+; N/A ; None ; -5.218 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_6 ; clk_pin ;
+; N/A ; None ; -5.218 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_2 ; clk_pin ;
+; N/A ; None ; -5.218 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_3 ; clk_pin ;
+; N/A ; None ; -5.218 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_4 ; clk_pin ;
+; N/A ; None ; -5.228 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_0 ; clk_pin ;
+; N/A ; None ; -5.228 ns ; reset_pin ; vga_driver:vga_driver_unit|column_counter_sig_1 ; clk_pin ;
+; N/A ; None ; -5.445 ns ; reset_pin ; vga_driver:vga_driver_unit|h_enable_sig ; clk_pin ;
+; N/A ; None ; -5.531 ns ; reset_pin ; vga_driver:vga_driver_unit|vsync_state_1 ; clk_pin ;
++---------------+-------------+-----------+-----------+-------------------------------------------------+----------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Wed Oct 28 14:19:50 2009
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only
+Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
+Warning: Found pins functioning as undefined clocks and/or memory enables
+ Info: Assuming node "clk_pin" is an undefined clock
+Info: Clock "clk_pin" has Internal fmax of 191.9 MHz between source register "vga_driver:vga_driver_unit|hsync_counter_8" and destination register "vga_driver:vga_driver_unit|hsync_state_5" (period= 5.211 ns)
+ Info: + Longest register to register delay is 5.018 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y28_N8; Fanout = 8; REG Node = 'vga_driver:vga_driver_unit|hsync_counter_8'
+ Info: 2: + IC(0.990 ns) + CELL(0.332 ns) = 1.322 ns; Loc. = LC_X41_Y28_N3; Fanout = 4; COMB Node = 'vga_driver:vga_driver_unit|un10_hsync_counter_1'
+ Info: 3: + IC(1.038 ns) + CELL(0.087 ns) = 2.447 ns; Loc. = LC_X36_Y28_N3; Fanout = 1; COMB Node = 'vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1'
+ Info: 4: + IC(0.562 ns) + CELL(0.213 ns) = 3.222 ns; Loc. = LC_X37_Y28_N4; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0'
+ Info: 5: + IC(1.070 ns) + CELL(0.726 ns) = 5.018 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit|hsync_state_5'
+ Info: Total cell delay = 1.358 ns ( 27.06 % )
+ Info: Total interconnect delay = 3.660 ns ( 72.94 % )
+ Info: - Smallest clock skew is -0.007 ns
+ Info: + Shortest clock path from clock "clk_pin" to destination register is 3.255 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'
+ Info: 2: + IC(1.827 ns) + CELL(0.560 ns) = 3.255 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit|hsync_state_5'
+ Info: Total cell delay = 1.428 ns ( 43.87 % )
+ Info: Total interconnect delay = 1.827 ns ( 56.13 % )
+ Info: - Longest clock path from clock "clk_pin" to source register is 3.262 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'
+ Info: 2: + IC(1.834 ns) + CELL(0.560 ns) = 3.262 ns; Loc. = LC_X38_Y28_N8; Fanout = 8; REG Node = 'vga_driver:vga_driver_unit|hsync_counter_8'
+ Info: Total cell delay = 1.428 ns ( 43.78 % )
+ Info: Total interconnect delay = 1.834 ns ( 56.22 % )
+ Info: + Micro clock to output delay of source is 0.176 ns
+ Info: + Micro setup delay of destination is 0.010 ns
+Info: tsu for register "vga_driver:vga_driver_unit|hsync_state_5" (data pin = "reset_pin", clock pin = "clk_pin") is 6.543 ns
+ Info: + Longest pin to register delay is 9.788 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N2; Fanout = 10; PIN Node = 'reset_pin'
+ Info: 2: + IC(5.016 ns) + CELL(0.213 ns) = 5.989 ns; Loc. = LC_X38_Y30_N2; Fanout = 53; COMB Node = 'vga_driver:vga_driver_unit|un6_dly_counter_0_x'
+ Info: 3: + IC(1.544 ns) + CELL(0.459 ns) = 7.992 ns; Loc. = LC_X37_Y28_N4; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0'
+ Info: 4: + IC(1.070 ns) + CELL(0.726 ns) = 9.788 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit|hsync_state_5'
+ Info: Total cell delay = 2.158 ns ( 22.05 % )
+ Info: Total interconnect delay = 7.630 ns ( 77.95 % )
+ Info: + Micro setup delay of destination is 0.010 ns
+ Info: - Shortest clock path from clock "clk_pin" to destination register is 3.255 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'
+ Info: 2: + IC(1.827 ns) + CELL(0.560 ns) = 3.255 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit|hsync_state_5'
+ Info: Total cell delay = 1.428 ns ( 43.87 % )
+ Info: Total interconnect delay = 1.827 ns ( 56.13 % )
+Info: tco from clock "clk_pin" to destination pin "d_set_vsync_counter" through register "vga_driver:vga_driver_unit|vsync_state_0" is 10.494 ns
+ Info: + Longest clock path from clock "clk_pin" to source register is 3.247 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'
+ Info: 2: + IC(1.819 ns) + CELL(0.560 ns) = 3.247 ns; Loc. = LC_X38_Y30_N9; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|vsync_state_0'
+ Info: Total cell delay = 1.428 ns ( 43.98 % )
+ Info: Total interconnect delay = 1.819 ns ( 56.02 % )
+ Info: + Micro clock to output delay of source is 0.176 ns
+ Info: + Longest register to pin delay is 7.071 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y30_N9; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit|vsync_state_0'
+ Info: 2: + IC(0.944 ns) + CELL(0.332 ns) = 1.276 ns; Loc. = LC_X35_Y30_N4; Fanout = 2; COMB Node = 'vga_driver:vga_driver_unit|d_set_vsync_counter'
+ Info: 3: + IC(3.291 ns) + CELL(2.504 ns) = 7.071 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'd_set_vsync_counter'
+ Info: Total cell delay = 2.836 ns ( 40.11 % )
+ Info: Total interconnect delay = 4.235 ns ( 59.89 % )
+Info: Longest tpd from source pin "reset_pin" to destination pin "seven_seg_pin[9]" is 11.756 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N2; Fanout = 10; PIN Node = 'reset_pin'
+ Info: 2: + IC(5.016 ns) + CELL(0.213 ns) = 5.989 ns; Loc. = LC_X38_Y30_N2; Fanout = 53; COMB Node = 'vga_driver:vga_driver_unit|un6_dly_counter_0_x'
+ Info: 3: + IC(3.263 ns) + CELL(2.504 ns) = 11.756 ns; Loc. = PIN_A7; Fanout = 0; PIN Node = 'seven_seg_pin[9]'
+ Info: Total cell delay = 3.477 ns ( 29.58 % )
+ Info: Total interconnect delay = 8.279 ns ( 70.42 % )
+Info: th for register "dly_counter[1]" (data pin = "reset_pin", clock pin = "clk_pin") is -2.787 ns
+ Info: + Longest clock path from clock "clk_pin" to destination register is 3.247 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'
+ Info: 2: + IC(1.819 ns) + CELL(0.560 ns) = 3.247 ns; Loc. = LC_X38_Y30_N6; Fanout = 10; REG Node = 'dly_counter[1]'
+ Info: Total cell delay = 1.428 ns ( 43.98 % )
+ Info: Total interconnect delay = 1.819 ns ( 56.02 % )
+ Info: + Micro hold delay of destination is 0.100 ns
+ Info: - Shortest pin to register delay is 6.134 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N2; Fanout = 10; PIN Node = 'reset_pin'
+ Info: 2: + IC(5.010 ns) + CELL(0.364 ns) = 6.134 ns; Loc. = LC_X38_Y30_N6; Fanout = 10; REG Node = 'dly_counter[1]'
+ Info: Total cell delay = 1.124 ns ( 18.32 % )
+ Info: Total interconnect delay = 5.010 ns ( 81.68 % )
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 141 megabytes
+ Info: Processing ended: Wed Oct 28 14:19:50 2009
+ Info: Elapsed time: 00:00:00
+ Info: Total CPU time (on all processors): 00:00:01
+
+
--- /dev/null
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type : Worst-case tsu
+Slack : N/A
+Required Time : None
+Actual Time : 6.543 ns
+From : reset_pin
+To : vga_driver:vga_driver_unit|hsync_state_0
+From Clock : --
+To Clock : clk_pin
+Failed Paths : 0
+
+Type : Worst-case tco
+Slack : N/A
+Required Time : None
+Actual Time : 10.494 ns
+From : vga_driver:vga_driver_unit|vsync_state_0
+To : d_set_vsync_counter
+From Clock : clk_pin
+To Clock : --
+Failed Paths : 0
+
+Type : Worst-case tpd
+Slack : N/A
+Required Time : None
+Actual Time : 11.756 ns
+From : reset_pin
+To : seven_seg_pin[1]
+From Clock : --
+To Clock : --
+Failed Paths : 0
+
+Type : Worst-case th
+Slack : N/A
+Required Time : None
+Actual Time : -2.787 ns
+From : reset_pin
+To : dly_counter[1]
+From Clock : --
+To Clock : clk_pin
+Failed Paths : 0
+
+Type : Clock Setup: 'clk_pin'
+Slack : N/A
+Required Time : None
+Actual Time : 191.90 MHz ( period = 5.211 ns )
+From : vga_driver:vga_driver_unit|hsync_counter_8
+To : vga_driver:vga_driver_unit|hsync_state_0
+From Clock : clk_pin
+To Clock : clk_pin
+Failed Paths : 0
+
+Type : Total number of failed paths
+Slack :
+Required Time :
+Actual Time :
+From :
+To :
+From Clock :
+To Clock :
+Failed Paths : 0
+
+--------------------------------------------------------------------------------------
+
--- /dev/null
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R7
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--- /dev/null
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement default branches.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/report/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect ;
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL/Verilog immediate assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use MessageFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+; level), use MessageFormatBreak;
+; - otherwise, use MessageFormat.
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name: # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable System Verilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be indexed during
+; simulation. If set to 0, the WLF file will not be indexed.
+; The default is 1, indexed the WLF file.
+; WLFIndex = 0
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: these ini variables can be overriden by the vsim command
+; line switch "-onfinish <ask|stop|exit>".
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result at the end of simulation before shutdown.
+; If this is enabled, the simstats result will be printed out before shutdown.
+; The default is off.
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA concurrent assertion pass enable.
+; For SVA, Default is on when the assertion has a pass action block, or
+; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
+; For PSL, Default is on only when vsim switch "-assertdebug" is used
+; and the vopt "+acc=a" flag is active.
+; AssertionPassEnable = 0
+
+; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL/SVA concurrent assertion pass limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = 1
+
+; Set PSL/SVA concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
+; are included for toggle coverage. This leads to a longer simulation time with bigger
+; arrays covered with toggle coverage. Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable is 1
+; SVCovergroup63Compatibility = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
+; Sv_Seed = 0
+
+; Maximum size of dynamic arrays that are resized during randomize().
+; The default is 1000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 1000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; The default is 0 (no error).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures (SystemVerilog).
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; When SolveFailDebug is enabled, this value specifies the algorithm used to
+; discover conflicts between constraints for randomize() failures.
+; The default is "many".
+;
+; Valid schemes are:
+; "many" = best for determining conflicts due to many related constraints
+; "few" = best for determining conflicts due to few related constraints
+;
+; SolveFailDebugScheme = many
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum number of constraint subsets that will be tested for
+; conflicts.
+; The default is 0 (no limit).
+; SolveFailDebugLimit = 0
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum size of constraint subsets that will be tested for
+; conflicts.
+; The default value is 0 (no limit).
+; SolveFailDebugMaxSet = 0
+
+; Maximum size of the solution graph that may be generated during randomize().
+; This value can be used to force randomize() to abort if the memory
+; requirements of the constraint scenario exceeds the specified limit. This
+; value is specified in 1000s of nodes.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Maximum number of evaluations that may be performed on the solution graph
+; generated during randomize(). This value can be used to force randomize() to
+; abort if the complexity of the constraint scenario (in time) exceeds the
+; specified limit. This value is specified in 10000s of evaluations.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of
+; the constraint solver for others.
+; The default value is "" (no options).
+;
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints
+; n = disable bit interleaving for all constraints
+; r = reverse bit interleaving
+;
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; Note: To achieve the same random sequences, solver optimizations and/or
+; bug fixes introduced since the specified release may be disabled -
+; yielding the performance / behavior of the prior release.
+; Default value set to "" (random compatibility not required).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
--- /dev/null
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--- /dev/null
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--- /dev/null
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement default branches.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/report/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect ;
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL/Verilog immediate assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use MessageFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+; level), use MessageFormatBreak;
+; - otherwise, use MessageFormat.
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name: # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable System Verilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be indexed during
+; simulation. If set to 0, the WLF file will not be indexed.
+; The default is 1, indexed the WLF file.
+; WLFIndex = 0
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: these ini variables can be overriden by the vsim command
+; line switch "-onfinish <ask|stop|exit>".
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result at the end of simulation before shutdown.
+; If this is enabled, the simstats result will be printed out before shutdown.
+; The default is off.
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA concurrent assertion pass enable.
+; For SVA, Default is on when the assertion has a pass action block, or
+; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
+; For PSL, Default is on only when vsim switch "-assertdebug" is used
+; and the vopt "+acc=a" flag is active.
+; AssertionPassEnable = 0
+
+; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL/SVA concurrent assertion pass limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = 1
+
+; Set PSL/SVA concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
+; are included for toggle coverage. This leads to a longer simulation time with bigger
+; arrays covered with toggle coverage. Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable is 1
+; SVCovergroup63Compatibility = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
+; Sv_Seed = 0
+
+; Maximum size of dynamic arrays that are resized during randomize().
+; The default is 1000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 1000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; The default is 0 (no error).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures (SystemVerilog).
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; When SolveFailDebug is enabled, this value specifies the algorithm used to
+; discover conflicts between constraints for randomize() failures.
+; The default is "many".
+;
+; Valid schemes are:
+; "many" = best for determining conflicts due to many related constraints
+; "few" = best for determining conflicts due to few related constraints
+;
+; SolveFailDebugScheme = many
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum number of constraint subsets that will be tested for
+; conflicts.
+; The default is 0 (no limit).
+; SolveFailDebugLimit = 0
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum size of constraint subsets that will be tested for
+; conflicts.
+; The default value is 0 (no limit).
+; SolveFailDebugMaxSet = 0
+
+; Maximum size of the solution graph that may be generated during randomize().
+; This value can be used to force randomize() to abort if the memory
+; requirements of the constraint scenario exceeds the specified limit. This
+; value is specified in 1000s of nodes.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Maximum number of evaluations that may be performed on the solution graph
+; generated during randomize(). This value can be used to force randomize() to
+; abort if the complexity of the constraint scenario (in time) exceeds the
+; specified limit. This value is specified in 10000s of evaluations.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of
+; the constraint solver for others.
+; The default value is "" (no options).
+;
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints
+; n = disable bit interleaving for all constraints
+; r = reverse bit interleaving
+;
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; Note: To achieve the same random sequences, solver optimizations and/or
+; bug fixes introduced since the specified release may be disabled -
+; yielding the performance / behavior of the prior release.
+; Default value set to "" (random compatibility not required).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
--- /dev/null
+m255
+K3
+cModel Technology Builtin Library
+13
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+Z3 w1242971927
+Z4 d$MODEL_TECH/..
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--- /dev/null
+m255
+K3
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+cModel Technology
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--- /dev/null
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--- /dev/null
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projects / dide_16.git / commitdiff
