X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp4%2FDesignflow%2Fsrc%2Fvga_beh_tb.vhd;fp=bsp4%2FDesignflow%2Fsrc%2Fvga_beh_tb.vhd;h=cbeaa509ed756265fced87701eda14b3c770dd6e;hp=0000000000000000000000000000000000000000;hb=8c5b21b5de3f142d7210146a850cf7689e05c543;hpb=9388b7667104acb1a8ca81816d94d5ae71cffcc0 diff --git a/bsp4/Designflow/src/vga_beh_tb.vhd b/bsp4/Designflow/src/vga_beh_tb.vhd new file mode 100644 index 0000000..cbeaa50 --- /dev/null +++ b/bsp4/Designflow/src/vga_beh_tb.vhd @@ -0,0 +1,196 @@ +------------------------------------------------------------------------------- +-- Title : vga testbench +-- Project : +------------------------------------------------------------------------------- +-- File : vga_tb.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-04-07 +-- Last update: 2007-09-13 +-- Platform : +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-04-07 1.0 handl Created +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- +entity vga_tb is + +end vga_tb; + + +------------------------------------------------------------------------------- +-- ARCHITECTURE +------------------------------------------------------------------------------- +architecture behaviour of vga_tb is + + constant cc : time := 39.7 ns; -- test clock period + component vga + port ( + clk_pin : in std_logic; + reset_pin : in std_logic; + r0_pin, r1_pin, r2_pin : out std_logic; + g0_pin, g1_pin, g2_pin : out std_logic; + b0_pin, b1_pin : out std_logic; + hsync_pin : out std_logic; + vsync_pin : out std_logic; + seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0); + d_hsync, d_vsync : out std_logic; + d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0); + d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + d_set_column_counter, d_set_line_counter : out std_logic; + d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + d_set_hsync_counter, d_set_vsync_counter : out std_logic; + d_h_enable : out std_logic; + d_v_enable : out std_logic; + d_r, d_g, d_b : out std_logic; + d_hsync_state : out hsync_state_type; + d_vsync_state : out vsync_state_type; + d_state_clk : out std_logic; + d_toggle : out std_logic; + d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)); + end component; + + signal clk_pin : std_logic; + signal reset_pin : std_logic; + signal r0_pin, r1_pin, r2_pin : std_logic; + signal g0_pin, g1_pin, g2_pin : std_logic; + signal b0_pin, b1_pin : std_logic; + signal hsync_pin : std_logic; + signal vsync_pin : std_logic; + signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0); + signal d_hsync, d_vsync : std_logic; + signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0); + signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + signal d_set_column_counter, d_set_line_counter : std_logic; + signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0); + signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0); + signal d_set_hsync_counter, d_set_vsync_counter : std_logic; + signal d_h_enable : std_logic; + signal d_v_enable : std_logic; + signal d_r, d_g, d_b : std_logic; + signal d_hsync_state : hsync_state_type; + signal d_vsync_state : vsync_state_type; + signal d_state_clk : std_logic; + signal d_toggle : std_logic; + signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + + +begin + + vga_unit: vga + port map ( + clk_pin => clk_pin, + reset_pin => reset_pin, + r0_pin => r0_pin, + r1_pin => r1_pin, + r2_pin => r2_pin, + g0_pin => g0_pin, + g1_pin => g1_pin, + g2_pin => g2_pin, + b0_pin => b0_pin, + b1_pin => b1_pin, + hsync_pin => hsync_pin, + vsync_pin => vsync_pin, + seven_seg_pin => seven_seg_pin, + d_hsync => d_hsync, + d_vsync => d_vsync, + d_column_counter => d_column_counter, + d_line_counter => d_line_counter, + d_set_column_counter => d_set_column_counter, + d_set_line_counter => d_set_line_counter, + d_hsync_counter => d_hsync_counter, + d_vsync_counter => d_vsync_counter, + d_set_hsync_counter => d_set_hsync_counter, + d_set_vsync_counter => d_set_vsync_counter, + d_h_enable => d_h_enable, + d_v_enable => d_v_enable, + d_r => d_r, + d_g => d_g, + d_b => d_b, + d_hsync_state => d_hsync_state, + d_vsync_state => d_vsync_state, + d_state_clk => d_state_clk, + d_toggle => d_toggle, + d_toggle_counter => d_toggle_counter); + + +------------------------------------------------------------------------------- +-- generate simulation clock +------------------------------------------------------------------------------- + CLKGEN : process + begin + clk_pin <= '1'; + wait for cc/2; + clk_pin <= '0'; + wait for cc/2; + end process CLKGEN; + +------------------------------------------------------------------------------- +-- test the design +------------------------------------------------------------------------------- + TEST_IT : process + + -- wait for n clock cycles + procedure icwait(cycles : natural) is + begin + for i in 1 to cycles loop + wait until clk_pin = '1' and clk_pin'event; + end loop; + end; + + begin + ----------------------------------------------------------------------------- + -- initial reset + ----------------------------------------------------------------------------- + reset_pin <= '0'; + icwait(10); + + -- set reset_pin high! + reset_pin <= '1'; + icwait(10000000); + + --------------------------------------------------------------------------- + -- exit testbench + --------------------------------------------------------------------------- + assert false + report "Test finished" + severity error; + + end process test_it; + +end behaviour; + + +------------------------------------------------------------------------------- +-- configuration +------------------------------------------------------------------------------- +configuration vga_conf_beh of vga_tb is + for behaviour + for vga_unit : vga use entity work.vga(behav); + end for; + end for; +end vga_conf_beh; + +