X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp4%2FDesignflow%2Fppr%2Fsim%2Fvga.map.summary;fp=bsp4%2FDesignflow%2Fppr%2Fsim%2Fvga.map.summary;h=309a2db677cb1b4d6d4a744294a8b1e40f2a4069;hp=0000000000000000000000000000000000000000;hb=8c5b21b5de3f142d7210146a850cf7689e05c543;hpb=9388b7667104acb1a8ca81816d94d5ae71cffcc0

diff --git a/bsp4/Designflow/ppr/sim/vga.map.summary b/bsp4/Designflow/ppr/sim/vga.map.summary
new file mode 100644
index 0000000..309a2db
--- /dev/null
+++ b/bsp4/Designflow/ppr/sim/vga.map.summary
@@ -0,0 +1,12 @@
+Analysis & Synthesis Status : Successful - Tue Nov  3 17:30:34 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga
+Top-level Entity Name : vga
+Family : Stratix
+Total logic elements : 175
+Total pins : 117
+Total virtual pins : 0
+Total memory bits : 0
+DSP block 9-bit elements : 0
+Total PLLs : 0
+Total DLLs : 0