X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp4%2FDesignflow%2Fppr%2Fsim%2Fvga.fit.summary;fp=bsp4%2FDesignflow%2Fppr%2Fsim%2Fvga.fit.summary;h=e9f2365473ad9931550d2f9f7a039338ba78531f;hp=0000000000000000000000000000000000000000;hb=8c5b21b5de3f142d7210146a850cf7689e05c543;hpb=9388b7667104acb1a8ca81816d94d5ae71cffcc0

diff --git a/bsp4/Designflow/ppr/sim/vga.fit.summary b/bsp4/Designflow/ppr/sim/vga.fit.summary
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+Fitter Status : Successful - Tue Nov  3 17:31:09 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga
+Top-level Entity Name : vga
+Family : Stratix
+Device : EP1S25F672C6
+Timing Models : Final
+Total logic elements : 173 / 25,660 ( < 1 % )
+Total pins : 117 / 474 ( 25 % )
+Total virtual pins : 0
+Total memory bits : 0 / 1,944,576 ( 0 % )
+DSP block 9-bit elements : 0 / 80 ( 0 % )
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 2 ( 0 % )