X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp4%2FDesignflow%2Fppr%2Fsim%2Fvga.fit.smsg;fp=bsp4%2FDesignflow%2Fppr%2Fsim%2Fvga.fit.smsg;h=38de4e410159e27b3e1be0f2d0fceb50082e78b1;hp=0000000000000000000000000000000000000000;hb=8c5b21b5de3f142d7210146a850cf7689e05c543;hpb=9388b7667104acb1a8ca81816d94d5ae71cffcc0

diff --git a/bsp4/Designflow/ppr/sim/vga.fit.smsg b/bsp4/Designflow/ppr/sim/vga.fit.smsg
new file mode 100644
index 0000000..38de4e4
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+++ b/bsp4/Designflow/ppr/sim/vga.fit.smsg
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+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Start inferring scan chains for DSP blocks
+Extra Info: Inferring scan chains for DSP blocks is complete
+Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density
+Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks