X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp4%2FDesignflow%2Fppr%2Fdownload%2Fvga_pll.tcl;fp=bsp4%2FDesignflow%2Fppr%2Fdownload%2Fvga_pll.tcl;h=c2604349330083bdf8fbb7e7c5dff7f6adf24a66;hp=0000000000000000000000000000000000000000;hb=8c5b21b5de3f142d7210146a850cf7689e05c543;hpb=9388b7667104acb1a8ca81816d94d5ae71cffcc0 diff --git a/bsp4/Designflow/ppr/download/vga_pll.tcl b/bsp4/Designflow/ppr/download/vga_pll.tcl new file mode 100755 index 0000000..c260434 --- /dev/null +++ b/bsp4/Designflow/ppr/download/vga_pll.tcl @@ -0,0 +1,184 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: vga_pll.tcl +# Generated on: Fri Sep 29 09:31:24 2006 + +# Load Quartus II Tcl Project package +package require ::quartus::project +package require ::quartus::flow + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "vga_pll"]} { + puts "Project vga_pll is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists vga_pll]} { + project_open -cmp vga_pll vga_pll + } else { + project_new -cmp vga_pll vga_pll + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + catch { set_global_assignment -name FAMILY Stratix } result + catch { set_global_assignment -name DEVICE EP1S25F672C6 } result + catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result + catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result + catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result + catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result + catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result + catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result + catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result + catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result + catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result + catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result + catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result + catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result + catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result + catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result + + set_location_assignment PIN_E24 -to b0_pin + set_location_assignment PIN_T6 -to b1_pin + set_location_assignment PIN_N3 -to board_clk + set_location_assignment PIN_E23 -to g0_pin + set_location_assignment PIN_T5 -to g1_pin + set_location_assignment PIN_T24 -to g2_pin + set_location_assignment PIN_F1 -to hsync_pin + set_location_assignment PIN_E22 -to r0_pin + set_location_assignment PIN_T4 -to r1_pin + set_location_assignment PIN_T7 -to r2_pin + set_location_assignment PIN_A5 -to reset + set_location_assignment PIN_F2 -to vsync_pin + set_location_assignment PIN_Y5 -to d_hsync_state[0] + set_location_assignment PIN_F19 -to d_hsync_state[1] + set_location_assignment PIN_F17 -to d_hsync_state[2] + set_location_assignment PIN_Y2 -to d_hsync_state[3] + set_location_assignment PIN_F10 -to d_hsync_state[4] + set_location_assignment PIN_F9 -to d_hsync_state[5] + set_location_assignment PIN_F6 -to d_hsync_state[6] + set_location_assignment PIN_H4 -to d_hsync_counter[0] + set_location_assignment PIN_G25 -to d_hsync_counter[7] + set_location_assignment PIN_G22 -to d_hsync_counter[8] + set_location_assignment PIN_G18 -to d_hsync_counter[9] + set_location_assignment PIN_F5 -to d_vsync_state[0] + set_location_assignment PIN_F4 -to d_vsync_state[1] + set_location_assignment PIN_F3 -to d_vsync_state[2] + set_location_assignment PIN_M19 -to d_vsync_state[3] + set_location_assignment PIN_M18 -to d_vsync_state[4] + set_location_assignment PIN_M7 -to d_vsync_state[5] + set_location_assignment PIN_M4 -to d_vsync_state[6] + set_location_assignment PIN_G9 -to d_vsync_counter[0] + set_location_assignment PIN_G6 -to d_vsync_counter[7] + set_location_assignment PIN_G4 -to d_vsync_counter[8] + set_location_assignment PIN_G2 -to d_vsync_counter[9] + set_location_assignment PIN_K6 -to d_line_counter[0] + set_location_assignment PIN_K4 -to d_line_counter[1] + set_location_assignment PIN_J22 -to d_line_counter[2] + set_location_assignment PIN_M9 -to d_line_counter[3] + set_location_assignment PIN_M8 -to d_line_counter[4] + set_location_assignment PIN_M6 -to d_line_counter[5] + set_location_assignment PIN_M5 -to d_line_counter[6] + set_location_assignment PIN_L24 -to d_line_counter[7] + set_location_assignment PIN_L25 -to d_line_counter[8] + set_location_assignment PIN_L23 -to d_column_counter[0] + set_location_assignment PIN_L22 -to d_column_counter[1] + set_location_assignment PIN_L21 -to d_column_counter[2] + set_location_assignment PIN_L20 -to d_column_counter[3] + set_location_assignment PIN_L6 -to d_column_counter[4] + set_location_assignment PIN_L4 -to d_column_counter[5] + set_location_assignment PIN_L2 -to d_column_counter[6] + set_location_assignment PIN_K23 -to d_column_counter[7] + set_location_assignment PIN_K19 -to d_column_counter[8] + set_location_assignment PIN_K5 -to d_column_counter[9] + set_location_assignment PIN_L7 -to d_hsync + set_location_assignment PIN_L5 -to d_vsync + set_location_assignment PIN_F26 -to d_set_hsync_counter + set_location_assignment PIN_F24 -to d_set_vsync_counter + set_location_assignment PIN_F21 -to d_set_line_counter + set_location_assignment PIN_Y23 -to d_set_column_counter + set_location_assignment PIN_L3 -to d_r + set_location_assignment PIN_K24 -to d_g + set_location_assignment PIN_K20 -to d_b + set_location_assignment PIN_H18 -to d_v_enable + set_location_assignment PIN_J21 -to d_h_enable + set_location_assignment PIN_R8 -to seven_seg_pin[0] + set_location_assignment PIN_R9 -to seven_seg_pin[1] + set_location_assignment PIN_R19 -to seven_seg_pin[2] + set_location_assignment PIN_R20 -to seven_seg_pin[3] + set_location_assignment PIN_R21 -to seven_seg_pin[4] + set_location_assignment PIN_R22 -to seven_seg_pin[5] + set_location_assignment PIN_R23 -to seven_seg_pin[6] + set_location_assignment PIN_Y11 -to seven_seg_pin[7] + set_location_assignment PIN_N7 -to seven_seg_pin[8] + set_location_assignment PIN_N8 -to seven_seg_pin[9] + set_location_assignment PIN_R4 -to seven_seg_pin[10] + set_location_assignment PIN_R6 -to seven_seg_pin[11] + set_location_assignment PIN_AA11 -to seven_seg_pin[12] + set_location_assignment PIN_T2 -to seven_seg_pin[13] + set_location_assignment PIN_K3 -to d_state_clk + set_location_assignment PIN_H3 -to d_toggle + set_location_assignment PIN_H26 -to d_toggle_counter[0] + set_location_assignment PIN_G24 -to d_toggle_counter[15] + set_location_assignment PIN_G23 -to d_toggle_counter[16] + set_location_assignment PIN_G21 -to d_toggle_counter[17] + set_location_assignment PIN_G20 -to d_toggle_counter[18] + set_location_assignment PIN_G5 -to d_toggle_counter[19] + set_location_assignment PIN_G3 -to d_toggle_counter[20] + set_location_assignment PIN_G1 -to d_toggle_counter[21] + set_location_assignment PIN_F25 -to d_toggle_counter[22] + set_location_assignment PIN_F23 -to d_toggle_counter[23] + set_location_assignment PIN_T19 -to d_toggle_counter[24] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6] + set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state + set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin + + + # Commit assignments + export_assignments + +execute_flow -compile + + # Close project + if {$need_to_close_project} { + project_close + } +}