X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp4%2FDesignflow%2Fppr%2Fdownload%2Fsimulation%2Fmodelsim%2Fvga_pll.sft;fp=bsp4%2FDesignflow%2Fppr%2Fdownload%2Fsimulation%2Fmodelsim%2Fvga_pll.sft;h=5aed62ecf6090e1f889bf2b74a3447bf230cce04;hp=0000000000000000000000000000000000000000;hb=8c5b21b5de3f142d7210146a850cf7689e05c543;hpb=9388b7667104acb1a8ca81816d94d5ae71cffcc0

diff --git a/bsp4/Designflow/ppr/download/simulation/modelsim/vga_pll.sft b/bsp4/Designflow/ppr/download/simulation/modelsim/vga_pll.sft
new file mode 100644
index 0000000..5aed62e
--- /dev/null
+++ b/bsp4/Designflow/ppr/download/simulation/modelsim/vga_pll.sft
@@ -0,0 +1,4 @@
+set tool_name "ModelSim-Altera (Verilog)"
+set corner_file_list {
+	{{"Slow Model"} {vga_pll.vo vga_pll_v.sdo}}
+}