X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fsim%2Fpre%2Fwork%2F_info;fp=bsp3%2FDesignflow%2Fsim%2Fpre%2Fwork%2F_info;h=cea90b84db59cc075606f60d67dcc11911b0c7f6;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99 diff --git a/bsp3/Designflow/sim/pre/work/_info b/bsp3/Designflow/sim/pre/work/_info new file mode 100644 index 0000000..cea90b8 --- /dev/null +++ b/bsp3/Designflow/sim/pre/work/_info @@ -0,0 +1,230 @@ +m255 +K3 +13 +cModel Technology +Z0 d/homes/burban/didelu/dide_16/bsp3/Designflow/sim/pre +T_opt +V2U0:J6hC1Tnnbgd;S6@lJ3 +04 12 0 work vga_conf_pre 1 +Z1 =1-0015609ed0a8-4ae9ba91-bb307-1314 +Z2 o-quiet -auto_acc_if_foreign -work work +Z3 n@_opt +Z4 OE;O;6.5b;42 +Evga +Z5 w1256831373 +Z6 DPx4 ieee 16 vital_primitives 0 22 E9g6AWKAc2T]enMfl94If3 +Z7 DPx7 stratix 17 stratix_atom_pack 0 22 4LU4R]0>3N6GcAdgd1O1R2 +Z8 DPx4 ieee 12 vital_timing 0 22 OBWK>;kUYmkGg4kgG0 +Evga_control +R5 +R6 +R7 +R8 +R9 +R10 +R11 +R12 +R13 +R14 +l0 +L21 +Z46 ViM8Slb>8F]WOeH5T3 +R16 +32 +R17 +R18 +Z47 !s100 cARWILLA2jkIezceCfQhO0 +Abeh +R6 +R7 +R8 +R9 +R10 +R11 +R12 +Z48 DEx4 work 11 vga_control 0 22 iM8Slb>8F]WOeH5T3 +l55 +L42 +Z49 VbU;JfUJ`PFDC^3Eh2 +R16 +32 +R17 +R18 +Z52 !s100 H`[B7Qa3Tzi2R<9UOVVF`2 +Abeh +R6 +R7 +R8 +R9 +R10 +R11 +R12 +Z53 DEx4 work 10 vga_driver 0 22 2[f_E^`FDC^3Eh2 +l487 +L358 +Z54 VQ6GQEDImWUnHG8g>LY9A]1 +R16 +32 +R22 +R23 +R24 +R25 +R26 +R27 +R28 +R17 +R18 +Z55 !s100 I:B2OkcJZiMG=N]jWY;Ri1 +Pvga_pak +R34 +R35 +R12 +Z56 w1256830367 +Z57 8/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd +Z58 F/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd +l0 +L35 +Z59 VHGKInm?j6h_E?hCL1=3Rf2 +R16 +32 +Z60 Mx3 4 ieee 14 std_logic_1164 +Z61 Mx2 4 ieee 18 std_logic_unsigned +Z62 Mx1 4 ieee 15 std_logic_arith +R17 +R18 +Z63 !s100 cALhF4me