X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fppr%2Fsim%2Fvga.map.summary;fp=bsp3%2FDesignflow%2Fppr%2Fsim%2Fvga.map.summary;h=b6cb501df95eb97cb7f7139dc5442858f93ddc49;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99

diff --git a/bsp3/Designflow/ppr/sim/vga.map.summary b/bsp3/Designflow/ppr/sim/vga.map.summary
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+Analysis & Synthesis Status : Successful - Thu Oct 29 16:59:53 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga
+Top-level Entity Name : vga
+Family : Stratix
+Total logic elements : 143
+Total pins : 91
+Total virtual pins : 0
+Total memory bits : 0
+DSP block 9-bit elements : 0
+Total PLLs : 0
+Total DLLs : 0