X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fppr%2Fsim%2Fvga.fit.summary;fp=bsp3%2FDesignflow%2Fppr%2Fsim%2Fvga.fit.summary;h=327f27c0937fe5ebe7ec14e1179461fc55db6f39;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99

diff --git a/bsp3/Designflow/ppr/sim/vga.fit.summary b/bsp3/Designflow/ppr/sim/vga.fit.summary
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+Fitter Status : Successful - Thu Oct 29 17:00:26 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga
+Top-level Entity Name : vga
+Family : Stratix
+Device : EP1S25F672C6
+Timing Models : Final
+Total logic elements : 141 / 25,660 ( < 1 % )
+Total pins : 91 / 474 ( 19 % )
+Total virtual pins : 0
+Total memory bits : 0 / 1,944,576 ( 0 % )
+DSP block 9-bit elements : 0 / 80 ( 0 % )
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 2 ( 0 % )