X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fppr%2Fsim%2Fvga.eda.rpt;fp=bsp3%2FDesignflow%2Fppr%2Fsim%2Fvga.eda.rpt;h=cb19c18f98afe120f27bab2050c599e691f0bd18;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99

diff --git a/bsp3/Designflow/ppr/sim/vga.eda.rpt b/bsp3/Designflow/ppr/sim/vga.eda.rpt
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+EDA Netlist Writer report for vga
+Thu Oct 29 17:00:56 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Thu Oct 29 17:00:56 2009 ;
+; Revision Name             ; vga                                   ;
+; Top-level Entity Name     ; vga                                   ;
+; Family                    ; Stratix                               ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++--------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                           ;
++--------------------------------------------------------------------------------------+
+; Generated Files                                                                      ;
++--------------------------------------------------------------------------------------+
+; /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho     ;
+; /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo ;
++--------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II EDA Netlist Writer
+    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+    Info: Processing started: Thu Oct 29 17:00:55 2009
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vga -c vga
+Info: Generated files "vga.vho" and "vga_vhd.sdo" in directory "/homes/burban/didelu/dide_16/bsp3/Designflow/ppr/sim/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 163 megabytes
+    Info: Processing ended: Thu Oct 29 17:00:56 2009
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+