X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fppr%2Fsim%2Fsimulation%2Fmodelsim%2Fvga.vho;fp=bsp3%2FDesignflow%2Fppr%2Fsim%2Fsimulation%2Fmodelsim%2Fvga.vho;h=2421f7cbd540f54c9e1e361363c62ce650eeea17;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99 diff --git a/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho new file mode 100644 index 0000000..2421f7c --- /dev/null +++ b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho @@ -0,0 +1,6160 @@ +-- Copyright (C) 1991-2009 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II" +-- VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version" + +-- DATE "10/29/2009 17:00:56" + +-- +-- Device: Altera EP1S25F672C6 Package FBGA672 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY IEEE, stratix; +USE IEEE.std_logic_1164.all; +USE stratix.stratix_components.all; + +ENTITY vga IS + PORT ( + clk_pin : IN std_logic; + reset_pin : IN std_logic; + r0_pin : OUT std_logic; + r1_pin : OUT std_logic; + r2_pin : OUT std_logic; + g0_pin : OUT std_logic; + g1_pin : OUT std_logic; + g2_pin : OUT std_logic; + b0_pin : OUT std_logic; + b1_pin : OUT std_logic; + hsync_pin : OUT std_logic; + vsync_pin : OUT std_logic; + seven_seg_pin : OUT std_logic_vector(13 DOWNTO 0); + d_hsync : OUT std_logic; + d_vsync : OUT std_logic; + d_column_counter : OUT std_logic_vector(9 DOWNTO 0); + d_line_counter : OUT std_logic_vector(8 DOWNTO 0); + d_set_column_counter : OUT std_logic; + d_set_line_counter : OUT std_logic; + d_hsync_counter : OUT std_logic_vector(9 DOWNTO 0); + d_vsync_counter : OUT std_logic_vector(9 DOWNTO 0); + d_set_hsync_counter : OUT std_logic; + d_set_vsync_counter : OUT std_logic; + d_h_enable : OUT std_logic; + d_v_enable : OUT std_logic; + d_r : OUT std_logic; + d_g : OUT std_logic; + d_b : OUT std_logic; + d_hsync_state : OUT std_logic_vector(0 TO 6); + d_vsync_state : OUT std_logic_vector(0 TO 6); + d_state_clk : OUT std_logic + ); +END vga; + +ARCHITECTURE structure OF vga IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_clk_pin : std_logic; +SIGNAL ww_reset_pin : std_logic; +SIGNAL ww_r0_pin : std_logic; +SIGNAL ww_r1_pin : std_logic; +SIGNAL ww_r2_pin : std_logic; +SIGNAL ww_g0_pin : std_logic; +SIGNAL ww_g1_pin : std_logic; +SIGNAL ww_g2_pin : std_logic; +SIGNAL ww_b0_pin : std_logic; +SIGNAL ww_b1_pin : std_logic; +SIGNAL ww_hsync_pin : std_logic; +SIGNAL ww_vsync_pin : std_logic; +SIGNAL ww_seven_seg_pin : std_logic_vector(13 DOWNTO 0); +SIGNAL ww_d_hsync : std_logic; +SIGNAL ww_d_vsync : std_logic; +SIGNAL ww_d_column_counter : std_logic_vector(9 DOWNTO 0); +SIGNAL ww_d_line_counter : std_logic_vector(8 DOWNTO 0); +SIGNAL ww_d_set_column_counter : std_logic; +SIGNAL ww_d_set_line_counter : std_logic; +SIGNAL ww_d_hsync_counter : std_logic_vector(9 DOWNTO 0); +SIGNAL ww_d_vsync_counter : std_logic_vector(9 DOWNTO 0); +SIGNAL ww_d_set_hsync_counter : std_logic; +SIGNAL ww_d_set_vsync_counter : std_logic; +SIGNAL ww_d_h_enable : std_logic; +SIGNAL ww_d_v_enable : std_logic; +SIGNAL ww_d_r : std_logic; +SIGNAL ww_d_g : std_logic; +SIGNAL ww_d_b : std_logic; +SIGNAL ww_d_hsync_state : std_logic_vector(0 TO 6); +SIGNAL ww_d_vsync_state : std_logic_vector(0 TO 6); +SIGNAL ww_d_state_clk : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\ : std_logic; +SIGNAL \clk_pin~combout\ : std_logic; +SIGNAL \reset_pin~combout\ : std_logic; +SIGNAL \vga_driver_unit|un6_dly_counter_0_x\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_6\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_0\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_1\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_5\ : std_logic; +SIGNAL \vga_driver_unit|un13_hsync_counter_7\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_6\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_8\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_9\ : std_logic; +SIGNAL \vga_driver_unit|un9_hsync_counterlt9_3\ : std_logic; +SIGNAL \vga_driver_unit|un9_hsync_counterlt9\ : std_logic; +SIGNAL \vga_driver_unit|G_2_i\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_7\ : std_logic; +SIGNAL \vga_driver_unit|un13_hsync_counter_2\ : std_logic; +SIGNAL \vga_driver_unit|un13_hsync_counter\ : std_logic; +SIGNAL \vga_driver_unit|un12_hsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|un12_hsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|un12_hsync_counter\ : std_logic; +SIGNAL \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ : std_logic; +SIGNAL \vga_driver_unit|un10_hsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_5\ : std_logic; +SIGNAL \vga_driver_unit|un10_hsync_counter_1\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ : std_logic; +SIGNAL \vga_driver_unit|un11_hsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|un11_hsync_counter_2\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_3\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_2\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_0\ : std_logic; +SIGNAL \vga_driver_unit|d_set_hsync_counter\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_next_1_sqmuxa\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_2\ : std_logic; +SIGNAL \vga_driver_unit|un10_hsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_4\ : std_logic; +SIGNAL \vga_driver_unit|hsync_state_1\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_0\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_1\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_3\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_2\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_4\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_5\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_7\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_8\ : std_logic; +SIGNAL \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_9\ : std_logic; +SIGNAL \vga_driver_unit|un10_column_counter_siglt6_1\ : std_logic; +SIGNAL \vga_driver_unit|un10_column_counter_siglt6\ : std_logic; +SIGNAL \vga_driver_unit|un10_column_counter_siglto9\ : std_logic; +SIGNAL \vga_driver_unit|column_counter_sig_6\ : std_logic; +SIGNAL \vga_driver_unit|un10_column_counter_siglt6_3\ : std_logic; +SIGNAL \vga_control_unit|b_next_i_o3_0\ : std_logic; +SIGNAL \vga_control_unit|g_next_i_o3\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_6\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_0\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_1\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_2\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_5\ : std_logic; +SIGNAL \vga_driver_unit|un9_vsync_counterlt9_6\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_6\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_8\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_9\ : std_logic; +SIGNAL \vga_driver_unit|un9_vsync_counterlt9_5\ : std_logic; +SIGNAL \vga_driver_unit|un9_vsync_counterlt9\ : std_logic; +SIGNAL \vga_driver_unit|G_16_i\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_7\ : std_logic; +SIGNAL \vga_driver_unit|un12_vsync_counter_6\ : std_logic; +SIGNAL \vga_driver_unit|un15_vsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|un15_vsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|un14_vsync_counter_8\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_5\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_4\ : std_logic; +SIGNAL \vga_driver_unit|un13_vsync_counter_3\ : std_logic; +SIGNAL \vga_driver_unit|un13_vsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ : std_logic; +SIGNAL \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_next_2_sqmuxa\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_3\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_2\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_0\ : std_logic; +SIGNAL \vga_driver_unit|d_set_vsync_counter\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_next_1_sqmuxa\ : std_logic; +SIGNAL \vga_driver_unit|vsync_counter_4\ : std_logic; +SIGNAL \vga_driver_unit|un12_vsync_counter_7\ : std_logic; +SIGNAL \vga_driver_unit|vsync_state_1\ : std_logic; +SIGNAL \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ : std_logic; +SIGNAL \vga_driver_unit|h_enable_sig\ : std_logic; +SIGNAL \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ : std_logic; +SIGNAL \vga_driver_unit|v_enable_sig\ : std_logic; +SIGNAL \vga_control_unit|r_next_i_o7\ : std_logic; +SIGNAL \vga_control_unit|N_4_i_0_g0_1\ : std_logic; +SIGNAL \vga_control_unit|r\ : std_logic; +SIGNAL \vga_control_unit|N_23_i_0_g0_a\ : std_logic; +SIGNAL \vga_control_unit|g\ : std_logic; +SIGNAL \vga_control_unit|b_next_i_a7_1\ : std_logic; +SIGNAL \vga_control_unit|N_6_i_0_g0_0\ : std_logic; +SIGNAL \vga_control_unit|b\ : std_logic; +SIGNAL \vga_driver_unit|un1_hsync_state_3_0\ : std_logic; +SIGNAL \vga_driver_unit|h_sync_1_0_0_0_g1\ : std_logic; +SIGNAL \vga_driver_unit|h_sync\ : std_logic; +SIGNAL \vga_driver_unit|un1_vsync_state_2_0\ : std_logic; +SIGNAL \vga_driver_unit|v_sync_1_0_0_0_g1\ : std_logic; +SIGNAL \vga_driver_unit|v_sync\ : std_logic; +SIGNAL \~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_1\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_2\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_3\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_4\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_5\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_6\ : std_logic; +SIGNAL \vga_driver_unit|un10_line_counter_siglt4_2\ : std_logic; +SIGNAL \vga_driver_unit|un10_line_counter_siglto5\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_7\ : std_logic; +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_8\ : std_logic; +SIGNAL \vga_driver_unit|un10_line_counter_siglto8\ : std_logic; +SIGNAL \vga_driver_unit|line_counter_sig_0\ : std_logic; +SIGNAL \vga_driver_unit|hsync_counter_cout\ : std_logic_vector(8 DOWNTO 0); +SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout\ : std_logic_vector(1 DOWNTO 1); +SIGNAL \vga_driver_unit|un1_line_counter_sig_combout\ : std_logic_vector(9 DOWNTO 1); +SIGNAL \vga_driver_unit|un1_line_counter_sig_cout\ : std_logic_vector(7 DOWNTO 1); +SIGNAL \vga_driver_unit|un2_column_counter_next_combout\ : std_logic_vector(9 DOWNTO 1); +SIGNAL \vga_driver_unit|un2_column_counter_next_cout\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \vga_driver_unit|vsync_counter_cout\ : std_logic_vector(8 DOWNTO 0); +SIGNAL dly_counter : std_logic_vector(1 DOWNTO 0); +SIGNAL \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_G_2_i\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_G_16_i\ : std_logic; +SIGNAL \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ : std_logic; +SIGNAL \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic; + +BEGIN + +ww_clk_pin <= clk_pin; +ww_reset_pin <= reset_pin; +r0_pin <= ww_r0_pin; +r1_pin <= ww_r1_pin; +r2_pin <= ww_r2_pin; +g0_pin <= ww_g0_pin; +g1_pin <= ww_g1_pin; +g2_pin <= ww_g2_pin; +b0_pin <= ww_b0_pin; +b1_pin <= ww_b1_pin; +hsync_pin <= ww_hsync_pin; +vsync_pin <= ww_vsync_pin; +seven_seg_pin <= ww_seven_seg_pin; +d_hsync <= ww_d_hsync; +d_vsync <= ww_d_vsync; +d_column_counter <= ww_d_column_counter; +d_line_counter <= ww_d_line_counter; +d_set_column_counter <= ww_d_set_column_counter; +d_set_line_counter <= ww_d_set_line_counter; +d_hsync_counter <= ww_d_hsync_counter; +d_vsync_counter <= ww_d_vsync_counter; +d_set_hsync_counter <= ww_d_set_hsync_counter; +d_set_vsync_counter <= ww_d_set_vsync_counter; +d_h_enable <= ww_d_h_enable; +d_v_enable <= ww_d_v_enable; +d_r <= ww_d_r; +d_g <= ww_d_g; +d_b <= ww_d_b; +d_hsync_state <= ww_d_hsync_state; +d_vsync_state <= ww_d_vsync_state; +d_state_clk <= ww_d_state_clk; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +\vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\; +\vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\; +\vga_driver_unit|ALT_INV_G_2_i\ <= NOT \vga_driver_unit|G_2_i\; +\vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ <= NOT \vga_driver_unit|un9_hsync_counterlt9\; +\vga_driver_unit|ALT_INV_G_16_i\ <= NOT \vga_driver_unit|G_16_i\; +\vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ <= NOT \vga_driver_unit|un9_vsync_counterlt9\; +\ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ <= NOT \~STRATIX_FITTER_CREATED_GND~I_combout\; + +clk_pin_in : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_clk_pin, + combout => \clk_pin~combout\); + +reset_pin_in : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_reset_pin, + combout => \reset_pin~combout\); + +\dly_counter_1_\ : stratix_lcell +-- Equation(s): +-- dly_counter(1) = DFFEAS(\reset_pin~combout\ & (dly_counter(0) # dly_counter(1)), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a8a8", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => dly_counter(1)); + +\dly_counter_0_\ : stratix_lcell +-- Equation(s): +-- dly_counter(0) = DFFEAS(\reset_pin~combout\ & (dly_counter(1) # !dly_counter(0)), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a2a2", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => dly_counter(0)); + +\vga_driver_unit|vsync_state_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un6_dly_counter_0_x\ = !dly_counter(1) # !dly_counter(0) # !\reset_pin~combout\ +-- \vga_driver_unit|vsync_state_6\ = DFFEAS(\vga_driver_unit|un6_dly_counter_0_x\, GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "7f7f", + operation_mode => "normal", + output_mode => "reg_and_comb", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un6_dly_counter_0_x\, + regout => \vga_driver_unit|vsync_state_6\); + +\vga_driver_unit|hsync_state_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|d_set_hsync_counter\ = C1_hsync_state_6 # \vga_driver_unit|hsync_state_0\ +-- \vga_driver_unit|hsync_state_6\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|un6_dly_counter_0_x\, , , VCC) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fff0", + operation_mode => "normal", + output_mode => "reg_and_comb", + register_cascade_mode => "off", + sum_lutc_input => "qfbk", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un6_dly_counter_0_x\, + datad => \vga_driver_unit|hsync_state_0\, + aclr => GND, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|d_set_hsync_counter\, + regout => \vga_driver_unit|hsync_state_6\); + +\vga_driver_unit|hsync_counter_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_0\ = DFFEAS(!\vga_driver_unit|hsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(0) = CARRY(\vga_driver_unit|hsync_counter_0\) +-- \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|hsync_counter_0\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "33cc", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_counter_0\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_0\, + cout0 => \vga_driver_unit|hsync_counter_cout\(0), + cout1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\); + +\vga_driver_unit|hsync_counter_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_1\ = DFFEAS(\vga_driver_unit|hsync_counter_1\ $ \vga_driver_unit|hsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(1) = CARRY(!\vga_driver_unit|hsync_counter_cout\(0) # !\vga_driver_unit|hsync_counter_1\) +-- \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|hsync_counter_1\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "3c3f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_counter_1\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin0 => \vga_driver_unit|hsync_counter_cout\(0), + cin1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_1\, + cout0 => \vga_driver_unit|hsync_counter_cout\(1), + cout1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\); + +\vga_driver_unit|hsync_counter_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_2\ = DFFEAS(\vga_driver_unit|hsync_counter_2\ $ (!\vga_driver_unit|hsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(2) = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout\(1))) +-- \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout[1]~COUT1_12\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_2\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin0 => \vga_driver_unit|hsync_counter_cout\(1), + cin1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_2\, + cout0 => \vga_driver_unit|hsync_counter_cout\(2), + cout1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\); + +\vga_driver_unit|hsync_counter_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_3\ = DFFEAS(\vga_driver_unit|hsync_counter_3\ $ (\vga_driver_unit|hsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(3) = CARRY(!\vga_driver_unit|hsync_counter_cout\(2) # !\vga_driver_unit|hsync_counter_3\) +-- \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|hsync_counter_3\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "5a5f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_3\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin0 => \vga_driver_unit|hsync_counter_cout\(2), + cin1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_3\, + cout0 => \vga_driver_unit|hsync_counter_cout\(3), + cout1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\); + +\vga_driver_unit|hsync_counter_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_4\ = DFFEAS(\vga_driver_unit|hsync_counter_4\ $ (!\vga_driver_unit|hsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(4) = CARRY(\vga_driver_unit|hsync_counter_4\ & (!\vga_driver_unit|hsync_counter_cout[3]~COUT1_16\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_4\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin0 => \vga_driver_unit|hsync_counter_cout\(3), + cin1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_4\, + cout => \vga_driver_unit|hsync_counter_cout\(4)); + +\vga_driver_unit|hsync_counter_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_5\ = DFFEAS(\vga_driver_unit|hsync_counter_5\ $ \vga_driver_unit|hsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, +-- !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(5) = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\) +-- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\) + +-- pragma translate_off +GENERIC MAP ( + cin_used => "true", + lut_mask => "3c3f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_counter_5\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_5\, + cout0 => \vga_driver_unit|hsync_counter_cout\(5), + cout1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\); + +\vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_hsync_counter_7\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_2\ & \vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_1\, + datab => \vga_driver_unit|hsync_counter_2\, + datac => \vga_driver_unit|hsync_counter_3\, + datad => \vga_driver_unit|hsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_hsync_counter_7\); + +\vga_driver_unit|hsync_counter_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_6\ = DFFEAS(\vga_driver_unit|hsync_counter_6\ $ !(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(5)) # (\vga_driver_unit|hsync_counter_cout\(4) & +-- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(6) = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout\(5)) +-- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout[5]~COUT1_18\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "c30c", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_counter_6\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + cin0 => \vga_driver_unit|hsync_counter_cout\(5), + cin1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_6\, + cout0 => \vga_driver_unit|hsync_counter_cout\(6), + cout1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\); + +\vga_driver_unit|hsync_counter_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_7\ = DFFEAS(\vga_driver_unit|hsync_counter_7\ $ ((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(6)) # (\vga_driver_unit|hsync_counter_cout\(4) & +-- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(7) = CARRY(!\vga_driver_unit|hsync_counter_cout\(6) # !\vga_driver_unit|hsync_counter_7\) +-- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|hsync_counter_7\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "5a5f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_7\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + cin0 => \vga_driver_unit|hsync_counter_cout\(6), + cin1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_7\, + cout0 => \vga_driver_unit|hsync_counter_cout\(7), + cout1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\); + +\vga_driver_unit|hsync_counter_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_8\ = DFFEAS(\vga_driver_unit|hsync_counter_8\ $ (!(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(7)) # (\vga_driver_unit|hsync_counter_cout\(4) & +-- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) +-- \vga_driver_unit|hsync_counter_cout\(8) = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout\(7))) +-- \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout[7]~COUT1_22\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_counter_8\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + cin0 => \vga_driver_unit|hsync_counter_cout\(7), + cin1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_8\, + cout0 => \vga_driver_unit|hsync_counter_cout\(8), + cout1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\); + +\vga_driver_unit|hsync_counter_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_9\ = DFFEAS((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(8)) # (\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\) $ +-- \vga_driver_unit|hsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "0ff0", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\, + datad => \vga_driver_unit|hsync_counter_9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_2_i\, + sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\, + cin => \vga_driver_unit|hsync_counter_cout\(4), + cin0 => \vga_driver_unit|hsync_counter_cout\(8), + cin1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_counter_9\); + +\vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_hsync_counterlt9_3\ = !\vga_driver_unit|hsync_counter_6\ # !\vga_driver_unit|hsync_counter_8\ # !\vga_driver_unit|hsync_counter_9\ # !\vga_driver_unit|hsync_counter_7\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "7fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_7\, + datab => \vga_driver_unit|hsync_counter_9\, + datac => \vga_driver_unit|hsync_counter_8\, + datad => \vga_driver_unit|hsync_counter_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_hsync_counterlt9_3\); + +\vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_hsync_counterlt9\ = \vga_driver_unit|un9_hsync_counterlt9_3\ # !\vga_driver_unit|un13_hsync_counter_7\ # !\vga_driver_unit|hsync_counter_4\ # !\vga_driver_unit|hsync_counter_5\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff7f", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_5\, + datab => \vga_driver_unit|hsync_counter_4\, + datac => \vga_driver_unit|un13_hsync_counter_7\, + datad => \vga_driver_unit|un9_hsync_counterlt9_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_hsync_counterlt9\); + +\vga_driver_unit|G_2\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|G_2_i\ = !\vga_driver_unit|hsync_state_6\ & !\vga_driver_unit|hsync_state_0\ & !\vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un9_hsync_counterlt9\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "3337", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_state_6\, + datab => \vga_driver_unit|un9_hsync_counterlt9\, + datac => \vga_driver_unit|hsync_state_0\, + datad => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|G_2_i\); + +\vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_hsync_counter_2\ = !\vga_driver_unit|hsync_counter_5\ & \vga_driver_unit|hsync_counter_9\ & \vga_driver_unit|hsync_counter_8\ & \vga_driver_unit|hsync_counter_4\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "4000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_5\, + datab => \vga_driver_unit|hsync_counter_9\, + datac => \vga_driver_unit|hsync_counter_8\, + datad => \vga_driver_unit|hsync_counter_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_hsync_counter_2\); + +\vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_hsync_counter\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|un13_hsync_counter_7\ & \vga_driver_unit|un13_hsync_counter_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_7\, + datab => \vga_driver_unit|hsync_counter_6\, + datac => \vga_driver_unit|un13_hsync_counter_7\, + datad => \vga_driver_unit|un13_hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_hsync_counter\); + +\vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_hsync_counter_4\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_6\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_7\, + datab => \vga_driver_unit|hsync_counter_4\, + datac => \vga_driver_unit|hsync_counter_8\, + datad => \vga_driver_unit|hsync_counter_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_hsync_counter_4\); + +\vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_5\ & \vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0400", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_5\, + datab => \vga_driver_unit|hsync_counter_9\, + datac => \vga_driver_unit|hsync_counter_3\, + datad => \vga_driver_unit|hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_hsync_counter_3\); + +\vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_hsync_counter\ = \vga_driver_unit|hsync_counter_0\ & \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|un12_hsync_counter_4\ & \vga_driver_unit|un12_hsync_counter_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_0\, + datab => \vga_driver_unit|hsync_counter_1\, + datac => \vga_driver_unit|un12_hsync_counter_4\, + datad => \vga_driver_unit|un12_hsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_hsync_counter\); + +\vga_driver_unit|hsync_state_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|hsync_state_2\ & (C1_hsync_state_3 & !\vga_driver_unit|un12_hsync_counter\ # !\vga_driver_unit|un13_hsync_counter\) # !\vga_driver_unit|hsync_state_2\ & (C1_hsync_state_3 & +-- !\vga_driver_unit|un12_hsync_counter\) +-- \vga_driver_unit|hsync_state_3\ = DFFEAS(\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, \vga_driver_unit|hsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "22f2", + operation_mode => "normal", + output_mode => "reg_and_comb", + register_cascade_mode => "off", + sum_lutc_input => "qfbk", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_state_2\, + datab => \vga_driver_unit|un13_hsync_counter\, + datac => \vga_driver_unit|hsync_state_1\, + datad => \vga_driver_unit|un12_hsync_counter\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + sload => VCC, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, + regout => \vga_driver_unit|hsync_state_3\); + +\vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_hsync_counter_4\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_1\, + datab => \vga_driver_unit|hsync_counter_6\, + datac => \vga_driver_unit|hsync_counter_4\, + datad => \vga_driver_unit|hsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_hsync_counter_4\); + +\vga_driver_unit|hsync_state_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_5\ = DFFEAS(\vga_driver_unit|hsync_state_0\ # \vga_driver_unit|hsync_state_6\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fcfc", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_state_0\, + datac => \vga_driver_unit|hsync_state_6\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_5\); + +\vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_hsync_counter_1\ = !\vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_5\ & (!\vga_driver_unit|hsync_counter_8\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_9\, + datab => \vga_driver_unit|hsync_counter_5\, + datad => \vga_driver_unit|hsync_counter_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_hsync_counter_1\); + +\vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|hsync_state_5\ & (!\vga_driver_unit|un10_hsync_counter_1\ # !\vga_driver_unit|un10_hsync_counter_4\ # !\vga_driver_unit|un10_hsync_counter_3\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "70f0", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un10_hsync_counter_3\, + datab => \vga_driver_unit|un10_hsync_counter_4\, + datac => \vga_driver_unit|hsync_state_5\, + datad => \vga_driver_unit|un10_hsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\); + +\vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un11_hsync_counter_3\ = \vga_driver_unit|hsync_counter_1\ & !\vga_driver_unit|hsync_counter_4\ & !\vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0200", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_counter_1\, + datab => \vga_driver_unit|hsync_counter_4\, + datac => \vga_driver_unit|hsync_counter_3\, + datad => \vga_driver_unit|hsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un11_hsync_counter_3\); + +\vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un11_hsync_counter_2\ = !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_7\ & \vga_driver_unit|hsync_counter_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "3000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|hsync_counter_6\, + datac => \vga_driver_unit|hsync_counter_7\, + datad => \vga_driver_unit|hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un11_hsync_counter_2\); + +\vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|hsync_state_4\ & (!\vga_driver_unit|un11_hsync_counter_2\ # !\vga_driver_unit|un11_hsync_counter_3\ # !\vga_driver_unit|un10_hsync_counter_1\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "2aaa", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_state_4\, + datab => \vga_driver_unit|un10_hsync_counter_1\, + datac => \vga_driver_unit|un11_hsync_counter_3\, + datad => \vga_driver_unit|un11_hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\); + +\vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "aaab", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un6_dly_counter_0_x\, + datab => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, + datac => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\, + datad => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\); + +\vga_driver_unit|hsync_state_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_2\ = DFFEAS(\vga_driver_unit|hsync_state_3\ & (\vga_driver_unit|un12_hsync_counter\), GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "cc00", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_state_3\, + datad => \vga_driver_unit|un12_hsync_counter\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_2\); + +\vga_driver_unit|hsync_state_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_0\ = DFFEAS(\vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|un13_hsync_counter\), GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a0a0", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_state_2\, + datac => \vga_driver_unit|un13_hsync_counter\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_0\); + +\vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_counter_next_1_sqmuxa\ = \reset_pin~combout\ & dly_counter(0) & !\vga_driver_unit|d_set_hsync_counter\ & dly_counter(1) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0800", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => \vga_driver_unit|d_set_hsync_counter\, + datad => dly_counter(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|hsync_counter_next_1_sqmuxa\); + +\vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_2\ & !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0003", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|hsync_counter_2\, + datac => \vga_driver_unit|hsync_counter_7\, + datad => \vga_driver_unit|hsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_hsync_counter_3\); + +\vga_driver_unit|hsync_state_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_4\ = DFFEAS(\vga_driver_unit|un10_hsync_counter_3\ & \vga_driver_unit|un10_hsync_counter_4\ & \vga_driver_unit|hsync_state_5\ & \vga_driver_unit|un10_hsync_counter_1\, GLOBAL(\clk_pin~combout\), VCC, , +-- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un10_hsync_counter_3\, + datab => \vga_driver_unit|un10_hsync_counter_4\, + datac => \vga_driver_unit|hsync_state_5\, + datad => \vga_driver_unit|un10_hsync_counter_1\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_4\); + +\vga_driver_unit|hsync_state_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|hsync_state_1\ = DFFEAS(\vga_driver_unit|hsync_state_4\ & \vga_driver_unit|un10_hsync_counter_1\ & \vga_driver_unit|un11_hsync_counter_3\ & \vga_driver_unit|un11_hsync_counter_2\, GLOBAL(\clk_pin~combout\), VCC, , +-- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|hsync_state_4\, + datab => \vga_driver_unit|un10_hsync_counter_1\, + datac => \vga_driver_unit|un11_hsync_counter_3\, + datad => \vga_driver_unit|un11_hsync_counter_2\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|hsync_state_1\); + +\vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ = \reset_pin~combout\ & dly_counter(0) & dly_counter(1) & !\vga_driver_unit|hsync_state_1\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0080", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + datad => \vga_driver_unit|hsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\); + +\vga_driver_unit|column_counter_sig_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_0\ = DFFEAS(!\vga_driver_unit|un10_column_counter_siglto9\ # !\vga_driver_unit|column_counter_sig_0\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "3f3f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|column_counter_sig_0\, + datac => \vga_driver_unit|un10_column_counter_siglto9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_0\); + +\vga_driver_unit|un2_column_counter_next_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(1) = \vga_driver_unit|column_counter_sig_0\ $ \vga_driver_unit|column_counter_sig_1\ +-- \vga_driver_unit|un2_column_counter_next_cout\(1) = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\) +-- \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "6688", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_0\, + datab => \vga_driver_unit|column_counter_sig_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(1), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(1), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\); + +\vga_driver_unit|column_counter_sig_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_1\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(1) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "cfcf", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un2_column_counter_next_combout\(1), + datac => \vga_driver_unit|un10_column_counter_siglto9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_1\); + +\vga_driver_unit|un2_column_counter_next_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(3) = \vga_driver_unit|column_counter_sig_3\ $ (\vga_driver_unit|column_counter_sig_2\ & \vga_driver_unit|un2_column_counter_next_cout\(1)) +-- \vga_driver_unit|un2_column_counter_next_cout\(3) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(1) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\) +-- \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "6c7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_2\, + datab => \vga_driver_unit|column_counter_sig_3\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(1), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(3), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(3), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\); + +\vga_driver_unit|column_counter_sig_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_3\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(3) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_column_counter_siglto9\, + datad => \vga_driver_unit|un2_column_counter_next_combout\(3), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_3\); + +\vga_driver_unit|un2_column_counter_next_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_cout\(0) = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\) +-- \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff88", + operation_mode => "arithmetic", + output_mode => "none", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_0\, + datab => \vga_driver_unit|column_counter_sig_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\, + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(0), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\); + +\vga_driver_unit|un2_column_counter_next_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(2) = \vga_driver_unit|column_counter_sig_2\ $ (\vga_driver_unit|un2_column_counter_next_cout\(0)) +-- \vga_driver_unit|un2_column_counter_next_cout\(2) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(0) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\) +-- \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "5a7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_2\, + datab => \vga_driver_unit|column_counter_sig_3\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(0), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(2), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(2), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\); + +\vga_driver_unit|column_counter_sig_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_2\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(2) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f5f5", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un10_column_counter_siglto9\, + datac => \vga_driver_unit|un2_column_counter_next_combout\(2), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_2\); + +\vga_driver_unit|un2_column_counter_next_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(4) = \vga_driver_unit|column_counter_sig_4\ $ !\vga_driver_unit|un2_column_counter_next_cout\(2) +-- \vga_driver_unit|un2_column_counter_next_cout\(4) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(2)) +-- \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "c308", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_5\, + datab => \vga_driver_unit|column_counter_sig_4\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(2), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(4), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(4), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\); + +\vga_driver_unit|column_counter_sig_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_4\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(4) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f3f3", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_column_counter_siglto9\, + datac => \vga_driver_unit|un2_column_counter_next_combout\(4), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_4\); + +\vga_driver_unit|un2_column_counter_next_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(5) = \vga_driver_unit|column_counter_sig_5\ $ (\vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3)) +-- \vga_driver_unit|un2_column_counter_next_cout\(5) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3)) +-- \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a608", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_5\, + datab => \vga_driver_unit|column_counter_sig_4\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(3), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(5), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(5), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\); + +\vga_driver_unit|column_counter_sig_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_5\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(5) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "afaf", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un2_column_counter_next_combout\(5), + datac => \vga_driver_unit|un10_column_counter_siglto9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_5\); + +\vga_driver_unit|un2_column_counter_next_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(7) = \vga_driver_unit|column_counter_sig_7\ $ (\vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|un2_column_counter_next_cout\(5)) +-- \vga_driver_unit|un2_column_counter_next_cout\(7) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(5) # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\) +-- \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "6a7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_7\, + datab => \vga_driver_unit|column_counter_sig_6\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(5), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(7), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(7), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\); + +\vga_driver_unit|column_counter_sig_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_7\ = DFFEAS(\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ & (\vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|un2_column_counter_next_combout\(7)), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, + datac => \vga_driver_unit|un10_column_counter_siglto9\, + datad => \vga_driver_unit|un2_column_counter_next_combout\(7), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_7\); + +\vga_driver_unit|un2_column_counter_next_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(6) = \vga_driver_unit|column_counter_sig_6\ $ \vga_driver_unit|un2_column_counter_next_cout\(4) +-- \vga_driver_unit|un2_column_counter_next_cout\(6) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(4) # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\) +-- \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "3c7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_7\, + datab => \vga_driver_unit|column_counter_sig_6\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(4), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(6), + cout0 => \vga_driver_unit|un2_column_counter_next_cout\(6), + cout1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\); + +\vga_driver_unit|un2_column_counter_next_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(8) = \vga_driver_unit|un2_column_counter_next_cout\(6) $ !\vga_driver_unit|column_counter_sig_8\ + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "f00f", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datad => \vga_driver_unit|column_counter_sig_8\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(6), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(8)); + +\vga_driver_unit|column_counter_sig_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_8\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(8) & (\vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un2_column_counter_next_combout\(8), + datac => \vga_driver_unit|un10_column_counter_siglto9\, + datad => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_8\); + +\vga_driver_unit|un2_column_counter_next_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un2_column_counter_next_combout\(9) = \vga_driver_unit|column_counter_sig_9\ $ (\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|un2_column_counter_next_cout\(7)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "f30c", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|column_counter_sig_8\, + datad => \vga_driver_unit|column_counter_sig_9\, + cin0 => \vga_driver_unit|un2_column_counter_next_cout\(7), + cin1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un2_column_counter_next_combout\(9)); + +\vga_driver_unit|column_counter_sig_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_9\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(9) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_column_counter_siglto9\, + datad => \vga_driver_unit|un2_column_counter_next_combout\(9), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_9\); + +\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_column_counter_siglt6_1\ = !\vga_driver_unit|column_counter_sig_2\ # !\vga_driver_unit|column_counter_sig_1\ # !\vga_driver_unit|column_counter_sig_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "3fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|column_counter_sig_0\, + datac => \vga_driver_unit|column_counter_sig_1\, + datad => \vga_driver_unit|column_counter_sig_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_column_counter_siglt6_1\); + +\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_column_counter_siglt6\ = \vga_driver_unit|un10_column_counter_siglt6_3\ # \vga_driver_unit|un10_column_counter_siglt6_1\ # !\vga_driver_unit|column_counter_sig_4\ # !\vga_driver_unit|column_counter_sig_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fdff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_3\, + datab => \vga_driver_unit|un10_column_counter_siglt6_3\, + datac => \vga_driver_unit|un10_column_counter_siglt6_1\, + datad => \vga_driver_unit|column_counter_sig_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_column_counter_siglt6\); + +\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_column_counter_siglto9\ = !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\ & \vga_driver_unit|un10_column_counter_siglt6\ # !\vga_driver_unit|column_counter_sig_9\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1f0f", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_8\, + datab => \vga_driver_unit|column_counter_sig_7\, + datac => \vga_driver_unit|column_counter_sig_9\, + datad => \vga_driver_unit|un10_column_counter_siglt6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_column_counter_siglto9\); + +\vga_driver_unit|column_counter_sig_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|column_counter_sig_6\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(6) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f3f3", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_column_counter_siglto9\, + datac => \vga_driver_unit|un2_column_counter_next_combout\(6), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|column_counter_sig_6\); + +\vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_column_counter_siglt6_3\ = !\vga_driver_unit|column_counter_sig_5\ # !\vga_driver_unit|column_counter_sig_6\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datac => \vga_driver_unit|column_counter_sig_6\, + datad => \vga_driver_unit|column_counter_sig_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_column_counter_siglt6_3\); + +\vga_control_unit|b_next_i_o3_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|b_next_i_o3_0\ = \vga_driver_unit|column_counter_sig_7\ # \vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|column_counter_sig_4\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f8f0", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_5\, + datab => \vga_driver_unit|column_counter_sig_6\, + datac => \vga_driver_unit|column_counter_sig_7\, + datad => \vga_driver_unit|column_counter_sig_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|b_next_i_o3_0\); + +\vga_control_unit|g_next_i_o3_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|g_next_i_o3\ = \vga_driver_unit|column_counter_sig_4\ # \vga_driver_unit|column_counter_sig_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ffaa", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_4\, + datad => \vga_driver_unit|column_counter_sig_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|g_next_i_o3\); + +\vga_driver_unit|vsync_counter_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_0\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\ $ \vga_driver_unit|vsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(0) = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|vsync_counter_0\) +-- \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|vsync_counter_0\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "6688", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|d_set_hsync_counter\, + datab => \vga_driver_unit|vsync_counter_0\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_0\, + cout0 => \vga_driver_unit|vsync_counter_cout\(0), + cout1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\); + +\vga_driver_unit|vsync_counter_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_1\ = DFFEAS(\vga_driver_unit|vsync_counter_1\ $ \vga_driver_unit|vsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(1) = CARRY(!\vga_driver_unit|vsync_counter_cout\(0) # !\vga_driver_unit|vsync_counter_1\) +-- \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|vsync_counter_1\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "3c3f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|vsync_counter_1\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin0 => \vga_driver_unit|vsync_counter_cout\(0), + cin1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_1\, + cout0 => \vga_driver_unit|vsync_counter_cout\(1), + cout1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\); + +\vga_driver_unit|vsync_counter_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_2\ = DFFEAS(\vga_driver_unit|vsync_counter_2\ $ (!\vga_driver_unit|vsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(2) = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout\(1))) +-- \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout[1]~COUT1_12\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_2\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin0 => \vga_driver_unit|vsync_counter_cout\(1), + cin1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_2\, + cout0 => \vga_driver_unit|vsync_counter_cout\(2), + cout1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\); + +\vga_driver_unit|vsync_counter_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_3\ = DFFEAS(\vga_driver_unit|vsync_counter_3\ $ (\vga_driver_unit|vsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(3) = CARRY(!\vga_driver_unit|vsync_counter_cout\(2) # !\vga_driver_unit|vsync_counter_3\) +-- \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|vsync_counter_3\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "5a5f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_3\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin0 => \vga_driver_unit|vsync_counter_cout\(2), + cin1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_3\, + cout0 => \vga_driver_unit|vsync_counter_cout\(3), + cout1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\); + +\vga_driver_unit|vsync_counter_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_4\ = DFFEAS(\vga_driver_unit|vsync_counter_4\ $ (!\vga_driver_unit|vsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(4) = CARRY(\vga_driver_unit|vsync_counter_4\ & (!\vga_driver_unit|vsync_counter_cout[3]~COUT1_16\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_4\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin0 => \vga_driver_unit|vsync_counter_cout\(3), + cin1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_4\, + cout => \vga_driver_unit|vsync_counter_cout\(4)); + +\vga_driver_unit|vsync_counter_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_5\ = DFFEAS(\vga_driver_unit|vsync_counter_5\ $ \vga_driver_unit|vsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, +-- !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(5) = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\) +-- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\) + +-- pragma translate_off +GENERIC MAP ( + cin_used => "true", + lut_mask => "3c3f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|vsync_counter_5\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_5\, + cout0 => \vga_driver_unit|vsync_counter_cout\(5), + cout1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\); + +\vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_vsync_counterlt9_6\ = !\vga_driver_unit|vsync_counter_1\ # !\vga_driver_unit|vsync_counter_2\ # !\vga_driver_unit|vsync_counter_3\ # !\vga_driver_unit|vsync_counter_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "7fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_0\, + datab => \vga_driver_unit|vsync_counter_3\, + datac => \vga_driver_unit|vsync_counter_2\, + datad => \vga_driver_unit|vsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_vsync_counterlt9_6\); + +\vga_driver_unit|vsync_counter_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_6\ = DFFEAS(\vga_driver_unit|vsync_counter_6\ $ !(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(5)) # (\vga_driver_unit|vsync_counter_cout\(4) & +-- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(6) = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout\(5)) +-- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout[5]~COUT1_18\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "c30c", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|vsync_counter_6\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + cin0 => \vga_driver_unit|vsync_counter_cout\(5), + cin1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_6\, + cout0 => \vga_driver_unit|vsync_counter_cout\(6), + cout1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\); + +\vga_driver_unit|vsync_counter_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_7\ = DFFEAS(\vga_driver_unit|vsync_counter_7\ $ ((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(6)) # (\vga_driver_unit|vsync_counter_cout\(4) & +-- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(7) = CARRY(!\vga_driver_unit|vsync_counter_cout\(6) # !\vga_driver_unit|vsync_counter_7\) +-- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|vsync_counter_7\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "5a5f", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_7\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + cin0 => \vga_driver_unit|vsync_counter_cout\(6), + cin1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_7\, + cout0 => \vga_driver_unit|vsync_counter_cout\(7), + cout1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\); + +\vga_driver_unit|vsync_counter_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_8\ = DFFEAS(\vga_driver_unit|vsync_counter_8\ $ (!(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(7)) # (\vga_driver_unit|vsync_counter_cout\(4) & +-- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\) +-- \vga_driver_unit|vsync_counter_cout\(8) = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout\(7))) +-- \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout[7]~COUT1_22\)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "a50a", + operation_mode => "arithmetic", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_8\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + cin0 => \vga_driver_unit|vsync_counter_cout\(7), + cin1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_8\, + cout0 => \vga_driver_unit|vsync_counter_cout\(8), + cout1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\); + +\vga_driver_unit|vsync_counter_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_9\ = DFFEAS((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(8)) # (\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\) $ +-- \vga_driver_unit|vsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + cin_used => "true", + lut_mask => "0ff0", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\, + datad => \vga_driver_unit|vsync_counter_9\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_G_16_i\, + sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\, + cin => \vga_driver_unit|vsync_counter_cout\(4), + cin0 => \vga_driver_unit|vsync_counter_cout\(8), + cin1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_counter_9\); + +\vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_vsync_counterlt9_5\ = !\vga_driver_unit|vsync_counter_7\ # !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_6\ # !\vga_driver_unit|vsync_counter_8\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "7fff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_8\, + datab => \vga_driver_unit|vsync_counter_6\, + datac => \vga_driver_unit|vsync_counter_9\, + datad => \vga_driver_unit|vsync_counter_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_vsync_counterlt9_5\); + +\vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un9_vsync_counterlt9\ = \vga_driver_unit|un9_vsync_counterlt9_6\ # \vga_driver_unit|un9_vsync_counterlt9_5\ # !\vga_driver_unit|vsync_counter_4\ # !\vga_driver_unit|vsync_counter_5\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ffdf", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_5\, + datab => \vga_driver_unit|un9_vsync_counterlt9_6\, + datac => \vga_driver_unit|vsync_counter_4\, + datad => \vga_driver_unit|un9_vsync_counterlt9_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un9_vsync_counterlt9\); + +\vga_driver_unit|G_16\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|G_16_i\ = !\vga_driver_unit|un6_dly_counter_0_x\ & !\vga_driver_unit|vsync_state_6\ & !\vga_driver_unit|vsync_state_0\ # !\vga_driver_unit|un9_vsync_counterlt9\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "01ff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un6_dly_counter_0_x\, + datab => \vga_driver_unit|vsync_state_6\, + datac => \vga_driver_unit|vsync_state_0\, + datad => \vga_driver_unit|un9_vsync_counterlt9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|G_16_i\); + +\vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_vsync_counter_6\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_5\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_7\, + datab => \vga_driver_unit|vsync_counter_8\, + datac => \vga_driver_unit|vsync_counter_6\, + datad => \vga_driver_unit|vsync_counter_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_vsync_counter_6\); + +\vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un15_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|vsync_counter_3\ & \vga_driver_unit|vsync_counter_9\ & !\vga_driver_unit|vsync_counter_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0040", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_0\, + datab => \vga_driver_unit|vsync_counter_3\, + datac => \vga_driver_unit|vsync_counter_9\, + datad => \vga_driver_unit|vsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un15_vsync_counter_3\); + +\vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un15_vsync_counter_4\ = !\vga_driver_unit|vsync_counter_4\ & !\vga_driver_unit|vsync_counter_1\ & \vga_driver_unit|un15_vsync_counter_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0300", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|vsync_counter_4\, + datac => \vga_driver_unit|vsync_counter_1\, + datad => \vga_driver_unit|un15_vsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un15_vsync_counter_4\); + +\vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un14_vsync_counter_8\ = \vga_driver_unit|un12_vsync_counter_6\ & \vga_driver_unit|un12_vsync_counter_7\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datac => \vga_driver_unit|un12_vsync_counter_6\, + datad => \vga_driver_unit|un12_vsync_counter_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un14_vsync_counter_8\); + +\vga_driver_unit|vsync_state_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_5\ = DFFEAS(\vga_driver_unit|vsync_state_0\ # \vga_driver_unit|vsync_state_6\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fff0", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|vsync_state_0\, + datad => \vga_driver_unit|vsync_state_6\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_5\); + +\vga_driver_unit|vsync_state_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_4\ = DFFEAS(\vga_driver_unit|vsync_counter_0\ & !\vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|un14_vsync_counter_8\ & \vga_driver_unit|vsync_state_5\, GLOBAL(\clk_pin~combout\), VCC, , +-- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "2000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_0\, + datab => \vga_driver_unit|vsync_counter_9\, + datac => \vga_driver_unit|un14_vsync_counter_8\, + datad => \vga_driver_unit|vsync_state_5\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_4\); + +\vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_9\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_7\, + datab => \vga_driver_unit|vsync_counter_6\, + datac => \vga_driver_unit|vsync_counter_8\, + datad => \vga_driver_unit|vsync_counter_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_vsync_counter_3\); + +\vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un13_vsync_counter_4\ = \vga_driver_unit|vsync_counter_5\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un13_vsync_counter_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "c000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|vsync_counter_5\, + datac => \vga_driver_unit|vsync_counter_0\, + datad => \vga_driver_unit|un13_vsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un13_vsync_counter_4\); + +\vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|vsync_state_4\ & (!\vga_driver_unit|un13_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_7\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0ccc", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|vsync_state_4\, + datac => \vga_driver_unit|un12_vsync_counter_7\, + datad => \vga_driver_unit|un13_vsync_counter_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\); + +\vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ # \vga_driver_unit|vsync_state_2\ & (!\vga_driver_unit|un15_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_6\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff2a", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_state_2\, + datab => \vga_driver_unit|un12_vsync_counter_6\, + datac => \vga_driver_unit|un15_vsync_counter_4\, + datad => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\); + +\vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|vsync_state_5\ & (\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_0\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8ccc", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_9\, + datab => \vga_driver_unit|vsync_state_5\, + datac => \vga_driver_unit|vsync_counter_0\, + datad => \vga_driver_unit|un14_vsync_counter_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\); + +\vga_driver_unit|vsync_state_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ = C1_vsync_state_3 & (!\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_0\) +-- \vga_driver_unit|vsync_state_3\ = DFFEAS(\vga_driver_unit|vsync_state_next_1_sqmuxa_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, \vga_driver_unit|vsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "70f0", + operation_mode => "normal", + output_mode => "reg_and_comb", + register_cascade_mode => "off", + sum_lutc_input => "qfbk", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_counter_0\, + datab => \vga_driver_unit|vsync_counter_9\, + datac => \vga_driver_unit|vsync_state_1\, + datad => \vga_driver_unit|un14_vsync_counter_8\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + sload => VCC, + ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\, + regout => \vga_driver_unit|vsync_state_3\); + +\vga_driver_unit|vsync_state_next_2_sqmuxa_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_next_2_sqmuxa\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ & !\vga_driver_unit|vsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|vsync_state_next_1_sqmuxa_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "aaab", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un6_dly_counter_0_x\, + datab => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\, + datac => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\, + datad => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_next_2_sqmuxa\); + +\vga_driver_unit|vsync_state_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_2\ = DFFEAS(\vga_driver_unit|un14_vsync_counter_8\ & \vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|vsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , +-- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "8000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un14_vsync_counter_8\, + datab => \vga_driver_unit|vsync_counter_9\, + datac => \vga_driver_unit|vsync_counter_0\, + datad => \vga_driver_unit|vsync_state_3\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_2\); + +\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ = \vga_driver_unit|un12_vsync_counter_6\ & \vga_driver_unit|un15_vsync_counter_4\ & \vga_driver_unit|vsync_state_2\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "c000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|un12_vsync_counter_6\, + datac => \vga_driver_unit|un15_vsync_counter_4\, + datad => \vga_driver_unit|vsync_state_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\); + +\vga_driver_unit|vsync_state_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_0\ = DFFEAS(\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ & (\vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\ # !\vga_driver_unit|un6_dly_counter_0_x\) # +-- !\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ & (\vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "22f2", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\, + datab => \vga_driver_unit|un6_dly_counter_0_x\, + datac => \vga_driver_unit|vsync_state_0\, + datad => \vga_driver_unit|vsync_state_next_2_sqmuxa\, + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_0\); + +\vga_driver_unit|d_set_vsync_counter_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|d_set_vsync_counter\ = \vga_driver_unit|vsync_state_6\ # \vga_driver_unit|vsync_state_0\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ffcc", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|vsync_state_6\, + datad => \vga_driver_unit|vsync_state_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|d_set_vsync_counter\); + +\vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_counter_next_1_sqmuxa\ = dly_counter(1) & \reset_pin~combout\ & !\vga_driver_unit|d_set_vsync_counter\ & dly_counter(0) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0800", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => dly_counter(1), + datab => \reset_pin~combout\, + datac => \vga_driver_unit|d_set_vsync_counter\, + datad => dly_counter(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|vsync_counter_next_1_sqmuxa\); + +\vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un12_vsync_counter_7\ = !\vga_driver_unit|vsync_counter_4\ & !\vga_driver_unit|vsync_counter_2\ & !\vga_driver_unit|vsync_counter_3\ & !\vga_driver_unit|vsync_counter_1\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_counter_4\, + datab => \vga_driver_unit|vsync_counter_2\, + datac => \vga_driver_unit|vsync_counter_3\, + datad => \vga_driver_unit|vsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un12_vsync_counter_7\); + +\vga_driver_unit|vsync_state_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|vsync_state_1\ = DFFEAS(\vga_driver_unit|un12_vsync_counter_7\ & !\vga_driver_unit|un6_dly_counter_0_x\ & \vga_driver_unit|un13_vsync_counter_4\ & \vga_driver_unit|vsync_state_4\, GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "2000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un12_vsync_counter_7\, + datab => \vga_driver_unit|un6_dly_counter_0_x\, + datac => \vga_driver_unit|un13_vsync_counter_4\, + datad => \vga_driver_unit|vsync_state_4\, + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|vsync_state_1\); + +\vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|vsync_state_4\ & (!\vga_driver_unit|vsync_state_5\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ccdd", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|vsync_state_4\, + datab => \vga_driver_unit|un6_dly_counter_0_x\, + datad => \vga_driver_unit|vsync_state_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\); + +\vga_driver_unit|h_enable_sig_Z\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|h_enable_sig\ = DFFEAS(\vga_driver_unit|vsync_state_1\ # \vga_driver_unit|vsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ffcc", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|vsync_state_1\, + datad => \vga_driver_unit|vsync_state_3\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|h_enable_sig\); + +\vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|hsync_state_5\ & !\vga_driver_unit|hsync_state_4\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "aaaf", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|un6_dly_counter_0_x\, + datac => \vga_driver_unit|hsync_state_5\, + datad => \vga_driver_unit|hsync_state_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\); + +\vga_driver_unit|v_enable_sig_Z\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|v_enable_sig\ = DFFEAS(\vga_driver_unit|hsync_state_1\ # \vga_driver_unit|hsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fcfc", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|hsync_state_1\, + datac => \vga_driver_unit|hsync_state_3\, + aclr => GND, + sclr => \vga_driver_unit|un6_dly_counter_0_x\, + ena => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|v_enable_sig\); + +\vga_control_unit|r_next_i_o7_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|r_next_i_o7\ = \vga_driver_unit|column_counter_sig_9\ # !\vga_driver_unit|v_enable_sig\ # !\vga_driver_unit|h_enable_sig\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f3ff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|h_enable_sig\, + datac => \vga_driver_unit|column_counter_sig_9\, + datad => \vga_driver_unit|v_enable_sig\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|r_next_i_o7\); + +\vga_control_unit|N_4_i_0_g0_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|N_4_i_0_g0_1\ = !\vga_control_unit|r_next_i_o7\ & (\vga_driver_unit|column_counter_sig_8\ # \vga_control_unit|g_next_i_o3\ & \vga_driver_unit|column_counter_sig_7\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "00f8", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_control_unit|g_next_i_o3\, + datab => \vga_driver_unit|column_counter_sig_7\, + datac => \vga_driver_unit|column_counter_sig_8\, + datad => \vga_control_unit|r_next_i_o7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|N_4_i_0_g0_1\); + +\vga_control_unit|r_Z\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|r\ = DFFEAS(\vga_control_unit|N_4_i_0_g0_1\ & (\vga_driver_unit|column_counter_sig_8\ & (!\vga_control_unit|b_next_i_o3_0\) # !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|un10_column_counter_siglt6_3\), +-- GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1d00", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un10_column_counter_siglt6_3\, + datab => \vga_driver_unit|column_counter_sig_8\, + datac => \vga_control_unit|b_next_i_o3_0\, + datad => \vga_control_unit|N_4_i_0_g0_1\, + aclr => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_control_unit|r\); + +\vga_control_unit|N_23_i_0_g0_a_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|N_23_i_0_g0_a\ = \vga_driver_unit|column_counter_sig_5\ & (\vga_driver_unit|column_counter_sig_6\ & (!\vga_control_unit|g_next_i_o3\) # !\vga_driver_unit|column_counter_sig_6\ & (\vga_control_unit|g_next_i_o3\ # +-- !\vga_driver_unit|un10_column_counter_siglt6_1\)) # !\vga_driver_unit|column_counter_sig_5\ & (\vga_driver_unit|column_counter_sig_6\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "5af2", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_5\, + datab => \vga_driver_unit|un10_column_counter_siglt6_1\, + datac => \vga_driver_unit|column_counter_sig_6\, + datad => \vga_control_unit|g_next_i_o3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|N_23_i_0_g0_a\); + +\vga_control_unit|g_Z\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|g\ = DFFEAS(\vga_driver_unit|column_counter_sig_7\ & !\vga_driver_unit|column_counter_sig_8\ & \vga_control_unit|N_23_i_0_g0_a\ & !\vga_control_unit|r_next_i_o7\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), +-- , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0020", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|column_counter_sig_7\, + datab => \vga_driver_unit|column_counter_sig_8\, + datac => \vga_control_unit|N_23_i_0_g0_a\, + datad => \vga_control_unit|r_next_i_o7\, + aclr => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_control_unit|g\); + +\vga_control_unit|b_next_i_a7_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|b_next_i_a7_1\ = !\vga_driver_unit|column_counter_sig_2\ & !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\ & !\vga_control_unit|g_next_i_o3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_2\, + datab => \vga_driver_unit|column_counter_sig_8\, + datac => \vga_driver_unit|column_counter_sig_7\, + datad => \vga_control_unit|g_next_i_o3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|b_next_i_a7_1\); + +\vga_control_unit|N_6_i_0_g0_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|N_6_i_0_g0_0\ = !\vga_control_unit|r_next_i_o7\ & (\vga_driver_unit|column_counter_sig_7\ # \vga_driver_unit|column_counter_sig_8\ # !\vga_driver_unit|un10_column_counter_siglt6_3\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "00ef", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|column_counter_sig_7\, + datab => \vga_driver_unit|column_counter_sig_8\, + datac => \vga_driver_unit|un10_column_counter_siglt6_3\, + datad => \vga_control_unit|r_next_i_o7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_control_unit|N_6_i_0_g0_0\); + +\vga_control_unit|b_Z\ : stratix_lcell +-- Equation(s): +-- \vga_control_unit|b\ = DFFEAS(!\vga_control_unit|b_next_i_a7_1\ & \vga_control_unit|N_6_i_0_g0_0\ & (!\vga_driver_unit|column_counter_sig_8\ # !\vga_control_unit|b_next_i_o3_0\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , +-- , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1050", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_control_unit|b_next_i_a7_1\, + datab => \vga_control_unit|b_next_i_o3_0\, + datac => \vga_control_unit|N_6_i_0_g0_0\, + datad => \vga_driver_unit|column_counter_sig_8\, + aclr => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_control_unit|b\); + +\vga_driver_unit|un1_hsync_state_3_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_hsync_state_3_0\ = \vga_driver_unit|hsync_state_1\ # \vga_driver_unit|hsync_state_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fcfc", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|hsync_state_1\, + datac => \vga_driver_unit|hsync_state_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_hsync_state_3_0\); + +\vga_driver_unit|h_sync_1_0_0_0_g1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|h_sync_1_0_0_0_g1\ = \vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|hsync_state_2\ & +-- \vga_driver_unit|hsync_state_4\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fe02", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|hsync_state_4\, + datab => \vga_driver_unit|un1_hsync_state_3_0\, + datac => \vga_driver_unit|hsync_state_2\, + datad => \vga_driver_unit|h_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|h_sync_1_0_0_0_g1\); + +\vga_driver_unit|h_sync_Z\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|h_sync\ = DFFEAS(\vga_driver_unit|h_sync_1_0_0_0_g1\ # !dly_counter(0) # !dly_counter(1) # !\reset_pin~combout\, GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "bfff", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|h_sync_1_0_0_0_g1\, + datab => \reset_pin~combout\, + datac => dly_counter(1), + datad => dly_counter(0), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|h_sync\); + +\vga_driver_unit|un1_vsync_state_2_0_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_vsync_state_2_0\ = \vga_driver_unit|vsync_state_1\ # \vga_driver_unit|vsync_state_3\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "fff0", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datac => \vga_driver_unit|vsync_state_1\, + datad => \vga_driver_unit|vsync_state_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_vsync_state_2_0\); + +\vga_driver_unit|v_sync_1_0_0_0_g1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|v_sync_1_0_0_0_g1\ = \vga_driver_unit|vsync_state_2\ & \vga_driver_unit|v_sync\ # !\vga_driver_unit|vsync_state_2\ & (\vga_driver_unit|un1_vsync_state_2_0\ & \vga_driver_unit|v_sync\ # !\vga_driver_unit|un1_vsync_state_2_0\ & +-- (\vga_driver_unit|vsync_state_4\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "aba8", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|v_sync\, + datab => \vga_driver_unit|vsync_state_2\, + datac => \vga_driver_unit|un1_vsync_state_2_0\, + datad => \vga_driver_unit|vsync_state_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|v_sync_1_0_0_0_g1\); + +\vga_driver_unit|v_sync_Z\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|v_sync\ = DFFEAS(\vga_driver_unit|v_sync_1_0_0_0_g1\ # !dly_counter(1) # !dly_counter(0) # !\reset_pin~combout\, GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff7f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \reset_pin~combout\, + datab => dly_counter(0), + datac => dly_counter(1), + datad => \vga_driver_unit|v_sync_1_0_0_0_g1\, + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|v_sync\); + +\~STRATIX_FITTER_CREATED_GND~I\ : stratix_lcell +-- Equation(s): +-- \~STRATIX_FITTER_CREATED_GND~I_combout\ = GND + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \~STRATIX_FITTER_CREATED_GND~I_combout\); + +\vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ = \reset_pin~combout\ & !\vga_driver_unit|vsync_state_1\ & dly_counter(1) & dly_counter(0) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "2000", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \reset_pin~combout\, + datab => \vga_driver_unit|vsync_state_1\, + datac => dly_counter(1), + datad => dly_counter(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\); + +\vga_driver_unit|un1_line_counter_sig_a_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_a_cout\(1) = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\) +-- \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff88", + operation_mode => "arithmetic", + output_mode => "none", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_0\, + datab => \vga_driver_unit|d_set_hsync_counter\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\, + cout0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1), + cout1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\); + +\vga_driver_unit|un1_line_counter_sig_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(2) = \vga_driver_unit|line_counter_sig_1\ $ \vga_driver_unit|un1_line_counter_sig_a_cout\(1) +-- \vga_driver_unit|un1_line_counter_sig_cout\(2) = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout\(1) # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\) +-- \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "3c7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_2\, + datab => \vga_driver_unit|line_counter_sig_1\, + cin0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1), + cin1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(2), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(2), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\); + +\vga_driver_unit|line_counter_sig_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_1\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(2) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(2), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_1\); + +\vga_driver_unit|un1_line_counter_sig_1_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(1) = \vga_driver_unit|line_counter_sig_0\ $ \vga_driver_unit|d_set_hsync_counter\ +-- \vga_driver_unit|un1_line_counter_sig_cout\(1) = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\) +-- \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "6688", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_0\, + datab => \vga_driver_unit|d_set_hsync_counter\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(1), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(1), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\); + +\vga_driver_unit|un1_line_counter_sig_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(3) = \vga_driver_unit|line_counter_sig_2\ $ (\vga_driver_unit|line_counter_sig_1\ & \vga_driver_unit|un1_line_counter_sig_cout\(1)) +-- \vga_driver_unit|un1_line_counter_sig_cout\(3) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(1) # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\) +-- \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "6c7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_1\, + datab => \vga_driver_unit|line_counter_sig_2\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(1), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(3), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(3), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\); + +\vga_driver_unit|line_counter_sig_2_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_2\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(3) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(3), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_2\); + +\vga_driver_unit|un1_line_counter_sig_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(4) = \vga_driver_unit|line_counter_sig_3\ $ !\vga_driver_unit|un1_line_counter_sig_cout\(2) +-- \vga_driver_unit|un1_line_counter_sig_cout\(4) = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(2)) +-- \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "c308", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_4\, + datab => \vga_driver_unit|line_counter_sig_3\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(2), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(4), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(4), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\); + +\vga_driver_unit|line_counter_sig_3_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_3\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(4) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f3f3", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_line_counter_siglto8\, + datac => \vga_driver_unit|un1_line_counter_sig_combout\(4), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_3\); + +\vga_driver_unit|un1_line_counter_sig_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(5) = \vga_driver_unit|line_counter_sig_4\ $ (\vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3)) +-- \vga_driver_unit|un1_line_counter_sig_cout\(5) = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3)) +-- \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a608", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_4\, + datab => \vga_driver_unit|line_counter_sig_3\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(3), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(5), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(5), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\); + +\vga_driver_unit|line_counter_sig_4_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_4\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(5) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(5), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_4\); + +\vga_driver_unit|un1_line_counter_sig_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(6) = \vga_driver_unit|line_counter_sig_5\ $ (\vga_driver_unit|un1_line_counter_sig_cout\(4)) +-- \vga_driver_unit|un1_line_counter_sig_cout\(6) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(4) # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\) +-- \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "5a7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_5\, + datab => \vga_driver_unit|line_counter_sig_6\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(4), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(6), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(6), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\); + +\vga_driver_unit|line_counter_sig_5_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_5\ = DFFEAS(\vga_driver_unit|un10_line_counter_siglto8\ & (\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ & \vga_driver_unit|un1_line_counter_sig_combout\(6)), GLOBAL(\clk_pin~combout\), VCC, , , , , , ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "a000", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + dataa => \vga_driver_unit|un10_line_counter_siglto8\, + datac => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(6), + aclr => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_5\); + +\vga_driver_unit|un1_line_counter_sig_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(7) = \vga_driver_unit|line_counter_sig_6\ $ (\vga_driver_unit|line_counter_sig_5\ & \vga_driver_unit|un1_line_counter_sig_cout\(5)) +-- \vga_driver_unit|un1_line_counter_sig_cout\(7) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(5) # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\) +-- \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "6a7f", + operation_mode => "arithmetic", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_6\, + datab => \vga_driver_unit|line_counter_sig_5\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(5), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(7), + cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(7), + cout1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\); + +\vga_driver_unit|line_counter_sig_6_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_6\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(7) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "f0ff", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un1_line_counter_sig_combout\(7), + datad => \vga_driver_unit|un10_line_counter_siglto8\, + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_6\); + +\vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_line_counter_siglt4_2\ = !\vga_driver_unit|line_counter_sig_0\ # !\vga_driver_unit|line_counter_sig_3\ # !\vga_driver_unit|line_counter_sig_4\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "77ff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_4\, + datab => \vga_driver_unit|line_counter_sig_3\, + datad => \vga_driver_unit|line_counter_sig_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_line_counter_siglt4_2\); + +\vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_line_counter_siglto5\ = !\vga_driver_unit|line_counter_sig_5\ & (\vga_driver_unit|un10_line_counter_siglt4_2\ # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0f07", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_1\, + datab => \vga_driver_unit|line_counter_sig_2\, + datac => \vga_driver_unit|line_counter_sig_5\, + datad => \vga_driver_unit|un10_line_counter_siglt4_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_line_counter_siglto5\); + +\vga_driver_unit|un1_line_counter_sig_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(8) = \vga_driver_unit|line_counter_sig_7\ $ (!\vga_driver_unit|un1_line_counter_sig_cout\(6)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "a5a5", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_7\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(6), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(8)); + +\vga_driver_unit|line_counter_sig_7_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_7\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(8) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff0f", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datac => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(8), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_7\); + +\vga_driver_unit|un1_line_counter_sig_9_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un1_line_counter_sig_combout\(9) = \vga_driver_unit|line_counter_sig_8\ $ (\vga_driver_unit|line_counter_sig_7\ & !\vga_driver_unit|un1_line_counter_sig_cout\(7)) + +-- pragma translate_off +GENERIC MAP ( + cin0_used => "true", + cin1_used => "true", + lut_mask => "f30c", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "cin", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + datab => \vga_driver_unit|line_counter_sig_7\, + datad => \vga_driver_unit|line_counter_sig_8\, + cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(7), + cin1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un1_line_counter_sig_combout\(9)); + +\vga_driver_unit|line_counter_sig_8_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_8\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(9) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff33", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(9), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_8\); + +\vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|un10_line_counter_siglto8\ = \vga_driver_unit|un10_line_counter_siglto5\ # !\vga_driver_unit|line_counter_sig_8\ # !\vga_driver_unit|line_counter_sig_7\ # !\vga_driver_unit|line_counter_sig_6\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "dfff", + operation_mode => "normal", + output_mode => "comb_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "off") +-- pragma translate_on +PORT MAP ( + dataa => \vga_driver_unit|line_counter_sig_6\, + datab => \vga_driver_unit|un10_line_counter_siglto5\, + datac => \vga_driver_unit|line_counter_sig_7\, + datad => \vga_driver_unit|line_counter_sig_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + combout => \vga_driver_unit|un10_line_counter_siglto8\); + +\vga_driver_unit|line_counter_sig_0_\ : stratix_lcell +-- Equation(s): +-- \vga_driver_unit|line_counter_sig_0\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(1) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, ) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "ff33", + operation_mode => "normal", + output_mode => "reg_only", + register_cascade_mode => "off", + sum_lutc_input => "datac", + synch_mode => "on") +-- pragma translate_on +PORT MAP ( + clk => \clk_pin~combout\, + datab => \vga_driver_unit|un10_line_counter_siglto8\, + datad => \vga_driver_unit|un1_line_counter_sig_combout\(1), + aclr => GND, + sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \vga_driver_unit|line_counter_sig_0\); + +r0_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|r\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_r0_pin); + +r1_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|r\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_r1_pin); + +r2_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|r\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_r2_pin); + +g0_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|g\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_g0_pin); + +g1_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|g\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_g1_pin); + +g2_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|g\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_g2_pin); + +b0_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|b\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_b0_pin); + +b1_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|b\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_b1_pin); + +hsync_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|h_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_hsync_pin); + +vsync_pin_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|v_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_vsync_pin); + +\seven_seg_pin_tri_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(0)); + +\seven_seg_pin_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(1)); + +\seven_seg_pin_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(2)); + +\seven_seg_pin_tri_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(3)); + +\seven_seg_pin_tri_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(4)); + +\seven_seg_pin_tri_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(5)); + +\seven_seg_pin_tri_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(6)); + +\seven_seg_pin_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(7)); + +\seven_seg_pin_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(8)); + +\seven_seg_pin_out_9_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(9)); + +\seven_seg_pin_out_10_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(10)); + +\seven_seg_pin_out_11_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(11)); + +\seven_seg_pin_out_12_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|un6_dly_counter_0_x\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(12)); + +\seven_seg_pin_tri_13_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_seven_seg_pin(13)); + +d_hsync_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|h_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync); + +d_vsync_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|v_sync\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync); + +\d_column_counter_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(0)); + +\d_column_counter_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(1)); + +\d_column_counter_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(2)); + +\d_column_counter_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(3)); + +\d_column_counter_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(4)); + +\d_column_counter_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(5)); + +\d_column_counter_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(6)); + +\d_column_counter_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(7)); + +\d_column_counter_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(8)); + +\d_column_counter_out_9_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|column_counter_sig_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_column_counter(9)); + +\d_line_counter_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(0)); + +\d_line_counter_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(1)); + +\d_line_counter_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(2)); + +\d_line_counter_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(3)); + +\d_line_counter_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(4)); + +\d_line_counter_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(5)); + +\d_line_counter_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(6)); + +\d_line_counter_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(7)); + +\d_line_counter_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|line_counter_sig_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_line_counter(8)); + +d_set_column_counter_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_set_column_counter); + +d_set_line_counter_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_set_line_counter); + +\d_hsync_counter_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(0)); + +\d_hsync_counter_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(1)); + +\d_hsync_counter_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(2)); + +\d_hsync_counter_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(3)); + +\d_hsync_counter_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(4)); + +\d_hsync_counter_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(5)); + +\d_hsync_counter_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(6)); + +\d_hsync_counter_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(7)); + +\d_hsync_counter_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(8)); + +\d_hsync_counter_out_9_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_counter_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_counter(9)); + +\d_vsync_counter_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(0)); + +\d_vsync_counter_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(1)); + +\d_vsync_counter_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(2)); + +\d_vsync_counter_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(3)); + +\d_vsync_counter_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(4)); + +\d_vsync_counter_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(5)); + +\d_vsync_counter_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(6)); + +\d_vsync_counter_out_7_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_7\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(7)); + +\d_vsync_counter_out_8_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_8\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(8)); + +\d_vsync_counter_out_9_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_counter_9\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_counter(9)); + +d_set_hsync_counter_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|d_set_hsync_counter\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_set_hsync_counter); + +d_set_vsync_counter_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|d_set_vsync_counter\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_set_vsync_counter); + +d_h_enable_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|h_enable_sig\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_h_enable); + +d_v_enable_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|v_enable_sig\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_v_enable); + +d_r_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|r\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_r); + +d_g_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|g\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_g); + +d_b_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_control_unit|b\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_b); + +\d_hsync_state_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(6)); + +\d_hsync_state_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(5)); + +\d_hsync_state_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(4)); + +\d_hsync_state_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(3)); + +\d_hsync_state_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(2)); + +\d_hsync_state_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(1)); + +\d_hsync_state_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|hsync_state_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_hsync_state(0)); + +\d_vsync_state_out_6_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_6\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(6)); + +\d_vsync_state_out_5_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_5\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(5)); + +\d_vsync_state_out_4_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_4\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(4)); + +\d_vsync_state_out_3_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_3\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(3)); + +\d_vsync_state_out_2_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_2\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(2)); + +\d_vsync_state_out_1_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_1\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(1)); + +\d_vsync_state_out_0_\ : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \vga_driver_unit|vsync_state_0\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_vsync_state(0)); + +d_state_clk_out : stratix_io +-- pragma translate_off +GENERIC MAP ( + ddio_mode => "none", + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \clk_pin~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_d_state_clk); +END structure; + +