X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fppr%2Fdownload%2Fvga_pll.map.summary;fp=bsp3%2FDesignflow%2Fppr%2Fdownload%2Fvga_pll.map.summary;h=3ed37626af9d41b498a3cda6b39b48083677bb2a;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99

diff --git a/bsp3/Designflow/ppr/download/vga_pll.map.summary b/bsp3/Designflow/ppr/download/vga_pll.map.summary
new file mode 100644
index 0000000..3ed3762
--- /dev/null
+++ b/bsp3/Designflow/ppr/download/vga_pll.map.summary
@@ -0,0 +1,12 @@
+Analysis & Synthesis Status : Successful - Thu Oct 29 17:12:32 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga_pll
+Top-level Entity Name : vga_pll
+Family : Stratix
+Total logic elements : 143
+Total pins : 91
+Total virtual pins : 0
+Total memory bits : 0
+DSP block 9-bit elements : 0
+Total PLLs : 1
+Total DLLs : 0