X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fppr%2Fdownload%2Fvga_pll.fit.smsg;fp=bsp3%2FDesignflow%2Fppr%2Fdownload%2Fvga_pll.fit.smsg;h=38de4e410159e27b3e1be0f2d0fceb50082e78b1;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99

diff --git a/bsp3/Designflow/ppr/download/vga_pll.fit.smsg b/bsp3/Designflow/ppr/download/vga_pll.fit.smsg
new file mode 100644
index 0000000..38de4e4
--- /dev/null
+++ b/bsp3/Designflow/ppr/download/vga_pll.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Start inferring scan chains for DSP blocks
+Extra Info: Inferring scan chains for DSP blocks is complete
+Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density
+Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks