X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fppr%2Fdownload%2Fsimulation%2Fmodelsim%2Fvga_pll.vo;fp=bsp3%2FDesignflow%2Fppr%2Fdownload%2Fsimulation%2Fmodelsim%2Fvga_pll.vo;h=75e886a8268cbad06409a8da7effe51807a4d436;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99 diff --git a/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.vo b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.vo new file mode 100644 index 0000000..75e886a --- /dev/null +++ b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.vo @@ -0,0 +1,9013 @@ +// Copyright (C) 1991-2009 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II" +// VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version" + +// DATE "10/29/2009 17:13:31" + +// +// Device: Altera EP1S25F672C6 Package FBGA672 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_pll ( + d_hsync, + board_clk, + reset, + d_vsync, + d_set_column_counter, + d_set_line_counter, + d_set_hsync_counter, + d_set_vsync_counter, + d_r, + d_g, + d_b, + d_h_enable, + d_v_enable, + d_state_clk, + r0_pin, + r1_pin, + r2_pin, + g0_pin, + g1_pin, + g2_pin, + b0_pin, + b1_pin, + hsync_pin, + vsync_pin, + d_column_counter, + d_hsync_counter, + d_hsync_state, + d_line_counter, + d_vsync_counter, + d_vsync_state, + seven_seg_pin); +output d_hsync; +input board_clk; +input reset; +output d_vsync; +output d_set_column_counter; +output d_set_line_counter; +output d_set_hsync_counter; +output d_set_vsync_counter; +output d_r; +output d_g; +output d_b; +output d_h_enable; +output d_v_enable; +output d_state_clk; +output r0_pin; +output r1_pin; +output r2_pin; +output g0_pin; +output g1_pin; +output g2_pin; +output b0_pin; +output b1_pin; +output hsync_pin; +output vsync_pin; +output [9:0] d_column_counter; +output [9:0] d_hsync_counter; +output [0:6] d_hsync_state; +output [8:0] d_line_counter; +output [9:0] d_vsync_counter; +output [0:6] d_vsync_state; +output [13:0] seven_seg_pin; + +wire gnd = 1'b0; +wire vcc = 1'b1; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_pll_v.sdo"); +// synopsys translate_on + +wire \inst1|altpll_component|pll~CLK1 ; +wire \inst1|altpll_component|pll~CLK2 ; +wire \inst1|altpll_component|pll~CLK3 ; +wire \inst1|altpll_component|pll~CLK4 ; +wire \inst1|altpll_component|pll~CLK5 ; +wire \inst|vga_driver_unit|un2_column_counter_next_0_~COMBOUT ; +wire \inst|vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT ; +wire \board_clk~combout ; +wire \inst1|altpll_component|_clk0 ; +wire \reset~combout ; +wire \inst|vga_driver_unit|un6_dly_counter_0_x ; +wire \inst|vga_driver_unit|hsync_state_6 ; +wire \inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ; +wire \inst|vga_driver_unit|hsync_counter_1 ; +wire \inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ; +wire \inst|vga_driver_unit|hsync_counter_2 ; +wire \inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ; +wire \inst|vga_driver_unit|hsync_counter_3 ; +wire \inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ; +wire \inst|vga_driver_unit|hsync_counter_5 ; +wire \inst|vga_driver_unit|un13_hsync_counter_7 ; +wire \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ; +wire \inst|vga_driver_unit|hsync_counter_6 ; +wire \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ; +wire \inst|vga_driver_unit|hsync_counter_7 ; +wire \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ; +wire \inst|vga_driver_unit|hsync_counter_8 ; +wire \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ; +wire \inst|vga_driver_unit|hsync_counter_9 ; +wire \inst|vga_driver_unit|un9_hsync_counterlt9_3 ; +wire \inst|vga_driver_unit|un9_hsync_counterlt9 ; +wire \inst|vga_driver_unit|G_2_i ; +wire \inst|vga_driver_unit|hsync_counter_0 ; +wire \inst|vga_driver_unit|un12_hsync_counter_3 ; +wire \inst|vga_driver_unit|un12_hsync_counter_4 ; +wire \inst|vga_driver_unit|un12_hsync_counter ; +wire \inst|vga_driver_unit|un10_hsync_counter_1 ; +wire \inst|vga_driver_unit|un11_hsync_counter_3 ; +wire \inst|vga_driver_unit|un11_hsync_counter_2 ; +wire \inst|vga_driver_unit|un10_hsync_counter_4 ; +wire \inst|vga_driver_unit|un10_hsync_counter_3 ; +wire \inst|vga_driver_unit|hsync_state_5 ; +wire \inst|vga_driver_unit|hsync_state_4 ; +wire \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ; +wire \inst|vga_driver_unit|hsync_state_1 ; +wire \inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ; +wire \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ; +wire \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ; +wire \inst|vga_driver_unit|hsync_state_2 ; +wire \inst|vga_driver_unit|hsync_state_0 ; +wire \inst|vga_driver_unit|d_set_hsync_counter ; +wire \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ; +wire \inst|vga_driver_unit|hsync_counter_4 ; +wire \inst|vga_driver_unit|un13_hsync_counter_2 ; +wire \inst|vga_driver_unit|un13_hsync_counter ; +wire \inst|vga_driver_unit|hsync_state_3 ; +wire \inst|vga_driver_unit|un1_hsync_state_3_0 ; +wire \inst|vga_driver_unit|h_sync_1_0_0_0_g1 ; +wire \inst|vga_driver_unit|h_sync ; +wire \inst|vga_driver_unit|vsync_state_6 ; +wire \inst|vga_driver_unit|vsync_counter_0 ; +wire \inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ; +wire \inst|vga_driver_unit|vsync_counter_1 ; +wire \inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ; +wire \inst|vga_driver_unit|vsync_counter_2 ; +wire \inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ; +wire \inst|vga_driver_unit|vsync_counter_3 ; +wire \inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ; +wire \inst|vga_driver_unit|vsync_counter_4 ; +wire \inst|vga_driver_unit|vsync_counter_5 ; +wire \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ; +wire \inst|vga_driver_unit|vsync_counter_6 ; +wire \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ; +wire \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ; +wire \inst|vga_driver_unit|vsync_counter_8 ; +wire \inst|vga_driver_unit|un9_vsync_counterlt9_5 ; +wire \inst|vga_driver_unit|un9_vsync_counterlt9_6 ; +wire \inst|vga_driver_unit|un9_vsync_counterlt9 ; +wire \inst|vga_driver_unit|G_16_i ; +wire \inst|vga_driver_unit|vsync_counter_7 ; +wire \inst|vga_driver_unit|un12_vsync_counter_6 ; +wire \inst|vga_driver_unit|un12_vsync_counter_7 ; +wire \inst|vga_driver_unit|un14_vsync_counter_8 ; +wire \inst|vga_driver_unit|un13_vsync_counter_3 ; +wire \inst|vga_driver_unit|un13_vsync_counter_4 ; +wire \inst|vga_driver_unit|vsync_state_1 ; +wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ; +wire \inst|vga_driver_unit|un15_vsync_counter_3 ; +wire \inst|vga_driver_unit|un15_vsync_counter_4 ; +wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ; +wire \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ; +wire \inst|vga_driver_unit|vsync_state_5 ; +wire \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ; +wire \inst|vga_driver_unit|vsync_state_next_2_sqmuxa ; +wire \inst|vga_driver_unit|vsync_state_3 ; +wire \inst|vga_driver_unit|vsync_state_2 ; +wire \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ; +wire \inst|vga_driver_unit|vsync_state_0 ; +wire \inst|vga_driver_unit|d_set_vsync_counter ; +wire \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ; +wire \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ; +wire \inst|vga_driver_unit|vsync_counter_9 ; +wire \inst|vga_driver_unit|vsync_state_4 ; +wire \inst|vga_driver_unit|un1_vsync_state_2_0 ; +wire \inst|vga_driver_unit|v_sync_1_0_0_0_g1 ; +wire \inst|vga_driver_unit|v_sync ; +wire \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ; +wire \inst|vga_driver_unit|column_counter_sig_0 ; +wire \inst|vga_driver_unit|column_counter_sig_1 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ; +wire \inst|vga_driver_unit|column_counter_sig_3 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ; +wire \inst|vga_driver_unit|column_counter_sig_2 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ; +wire \inst|vga_driver_unit|column_counter_sig_4 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ; +wire \inst|vga_driver_unit|column_counter_sig_5 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ; +wire \inst|vga_driver_unit|column_counter_sig_8 ; +wire \inst|vga_driver_unit|un10_column_counter_siglt6_1 ; +wire \inst|vga_driver_unit|un10_column_counter_siglt6 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ; +wire \inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ; +wire \inst|vga_driver_unit|column_counter_sig_9 ; +wire \inst|vga_driver_unit|un10_column_counter_siglto9 ; +wire \inst|vga_driver_unit|column_counter_sig_7 ; +wire \inst|vga_driver_unit|column_counter_sig_6 ; +wire \inst|vga_driver_unit|un10_column_counter_siglt6_3 ; +wire \inst|vga_control_unit|b_next_i_o3_0 ; +wire \inst|vga_control_unit|g_next_i_o3 ; +wire \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ; +wire \inst|vga_driver_unit|v_enable_sig ; +wire \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ; +wire \inst|vga_driver_unit|h_enable_sig ; +wire \inst|vga_control_unit|r_next_i_o7 ; +wire \inst|vga_control_unit|N_4_i_0_g0_1 ; +wire \inst|vga_control_unit|r ; +wire \inst|vga_control_unit|N_23_i_0_g0_a ; +wire \inst|vga_control_unit|g ; +wire \inst|vga_control_unit|N_6_i_0_g0_0 ; +wire \inst|vga_control_unit|b_next_i_a7_1 ; +wire \inst|vga_control_unit|b ; +wire \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ; +wire \inst|vga_driver_unit|line_counter_sig_0 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ; +wire \inst|vga_driver_unit|line_counter_sig_2 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ; +wire \inst|vga_driver_unit|line_counter_sig_1 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ; +wire \inst|vga_driver_unit|line_counter_sig_3 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ; +wire \inst|vga_driver_unit|line_counter_sig_4 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ; +wire \inst|vga_driver_unit|line_counter_sig_5 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ; +wire \inst|vga_driver_unit|line_counter_sig_6 ; +wire \inst|vga_driver_unit|un10_line_counter_siglt4_2 ; +wire \inst|vga_driver_unit|un10_line_counter_siglto5 ; +wire \inst|vga_driver_unit|un10_line_counter_siglto8 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ; +wire \inst|vga_driver_unit|line_counter_sig_7 ; +wire \inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ; +wire \inst|vga_driver_unit|line_counter_sig_8 ; +wire \~STRATIX_FITTER_CREATED_GND~I_combout ; +wire [8:0] \inst|vga_driver_unit|hsync_counter_cout ; +wire [1:1] \inst|vga_driver_unit|un1_line_counter_sig_a_cout ; +wire [9:1] \inst|vga_driver_unit|un1_line_counter_sig_combout ; +wire [7:1] \inst|vga_driver_unit|un1_line_counter_sig_cout ; +wire [9:1] \inst|vga_driver_unit|un2_column_counter_next_combout ; +wire [7:0] \inst|vga_driver_unit|un2_column_counter_next_cout ; +wire [8:0] \inst|vga_driver_unit|vsync_counter_cout ; +wire [1:0] \inst|dly_counter ; + +wire [5:0] \inst1|altpll_component|pll_CLK_bus ; + +assign \inst1|altpll_component|_clk0 = \inst1|altpll_component|pll_CLK_bus [0]; +assign \inst1|altpll_component|pll~CLK1 = \inst1|altpll_component|pll_CLK_bus [1]; +assign \inst1|altpll_component|pll~CLK2 = \inst1|altpll_component|pll_CLK_bus [2]; +assign \inst1|altpll_component|pll~CLK3 = \inst1|altpll_component|pll_CLK_bus [3]; +assign \inst1|altpll_component|pll~CLK4 = \inst1|altpll_component|pll_CLK_bus [4]; +assign \inst1|altpll_component|pll~CLK5 = \inst1|altpll_component|pll_CLK_bus [5]; + +// atom is at PIN_N3 +stratix_io \board_clk~I ( + .datain(gnd), + .ddiodatain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\board_clk~combout ), + .regout(), + .ddioregout(), + .padio(board_clk), + .dqsundelayedout()); +// synopsys translate_off +defparam \board_clk~I .ddio_mode = "none"; +defparam \board_clk~I .input_async_reset = "none"; +defparam \board_clk~I .input_power_up = "low"; +defparam \board_clk~I .input_register_mode = "none"; +defparam \board_clk~I .input_sync_reset = "none"; +defparam \board_clk~I .oe_async_reset = "none"; +defparam \board_clk~I .oe_power_up = "low"; +defparam \board_clk~I .oe_register_mode = "none"; +defparam \board_clk~I .oe_sync_reset = "none"; +defparam \board_clk~I .operation_mode = "input"; +defparam \board_clk~I .output_async_reset = "none"; +defparam \board_clk~I .output_power_up = "low"; +defparam \board_clk~I .output_register_mode = "none"; +defparam \board_clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PLL_1 +stratix_pll \inst1|altpll_component|pll ( + .fbin(vcc), + .ena(vcc), + .clkswitch(gnd), + .areset(gnd), + .pfdena(vcc), + .scanclk(gnd), + .scanaclr(gnd), + .scandata(gnd), + .comparator(gnd), + .inclk({gnd,\board_clk~combout }), + .clkena(6'b111111), + .extclkena(4'b1111), + .activeclock(), + .clkloss(), + .locked(), + .scandataout(), + .enable0(), + .enable1(), + .clk(\inst1|altpll_component|pll_CLK_bus ), + .extclk(), + .clkbad()); +// synopsys translate_off +defparam \inst1|altpll_component|pll .clk0_counter = "g0"; +defparam \inst1|altpll_component|pll .clk0_divide_by = 38; +defparam \inst1|altpll_component|pll .clk0_duty_cycle = 50; +defparam \inst1|altpll_component|pll .clk0_multiply_by = 31; +defparam \inst1|altpll_component|pll .clk0_phase_shift = "-725"; +defparam \inst1|altpll_component|pll .clk1_divide_by = 1; +defparam \inst1|altpll_component|pll .clk1_duty_cycle = 50; +defparam \inst1|altpll_component|pll .clk1_multiply_by = 1; +defparam \inst1|altpll_component|pll .clk1_phase_shift = "0"; +defparam \inst1|altpll_component|pll .clk2_divide_by = 1; +defparam \inst1|altpll_component|pll .clk2_duty_cycle = 50; +defparam \inst1|altpll_component|pll .clk2_multiply_by = 1; +defparam \inst1|altpll_component|pll .clk2_phase_shift = "0"; +defparam \inst1|altpll_component|pll .compensate_clock = "clk0"; +defparam \inst1|altpll_component|pll .enable_switch_over_counter = "off"; +defparam \inst1|altpll_component|pll .g0_high = 10; +defparam \inst1|altpll_component|pll .g0_initial = 1; +defparam \inst1|altpll_component|pll .g0_low = 9; +defparam \inst1|altpll_component|pll .g0_mode = "odd"; +defparam \inst1|altpll_component|pll .g0_ph = 0; +defparam \inst1|altpll_component|pll .gate_lock_counter = 0; +defparam \inst1|altpll_component|pll .gate_lock_signal = "no"; +defparam \inst1|altpll_component|pll .inclk0_input_frequency = 30003; +defparam \inst1|altpll_component|pll .inclk1_input_frequency = 30003; +defparam \inst1|altpll_component|pll .invalid_lock_multiplier = 5; +defparam \inst1|altpll_component|pll .l0_high = 13; +defparam \inst1|altpll_component|pll .l0_initial = 1; +defparam \inst1|altpll_component|pll .l0_low = 13; +defparam \inst1|altpll_component|pll .l0_mode = "even"; +defparam \inst1|altpll_component|pll .l0_ph = 0; +defparam \inst1|altpll_component|pll .l1_mode = "bypass"; +defparam \inst1|altpll_component|pll .l1_ph = 0; +defparam \inst1|altpll_component|pll .m = 31; +defparam \inst1|altpll_component|pll .m_initial = 1; +defparam \inst1|altpll_component|pll .m_ph = 3; +defparam \inst1|altpll_component|pll .n = 2; +defparam \inst1|altpll_component|pll .operation_mode = "normal"; +defparam \inst1|altpll_component|pll .pfd_max = 100000; +defparam \inst1|altpll_component|pll .pfd_min = 2000; +defparam \inst1|altpll_component|pll .pll_compensation_delay = 1713; +defparam \inst1|altpll_component|pll .pll_type = "fast"; +defparam \inst1|altpll_component|pll .primary_clock = "inclk0"; +defparam \inst1|altpll_component|pll .qualify_conf_done = "off"; +defparam \inst1|altpll_component|pll .simulation_type = "timing"; +defparam \inst1|altpll_component|pll .skip_vco = "off"; +defparam \inst1|altpll_component|pll .switch_over_counter = 1; +defparam \inst1|altpll_component|pll .switch_over_on_gated_lock = "off"; +defparam \inst1|altpll_component|pll .switch_over_on_lossclk = "off"; +defparam \inst1|altpll_component|pll .valid_lock_multiplier = 1; +defparam \inst1|altpll_component|pll .vco_center = 1250; +defparam \inst1|altpll_component|pll .vco_max = 3334; +defparam \inst1|altpll_component|pll .vco_min = 1000; +// synopsys translate_on + +// atom is at PIN_A5 +stratix_io \inst|reset_pin_in~I ( + .datain(gnd), + .ddiodatain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\reset~combout ), + .regout(), + .ddioregout(), + .padio(reset), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|reset_pin_in~I .ddio_mode = "none"; +defparam \inst|reset_pin_in~I .input_async_reset = "none"; +defparam \inst|reset_pin_in~I .input_power_up = "low"; +defparam \inst|reset_pin_in~I .input_register_mode = "none"; +defparam \inst|reset_pin_in~I .input_sync_reset = "none"; +defparam \inst|reset_pin_in~I .oe_async_reset = "none"; +defparam \inst|reset_pin_in~I .oe_power_up = "low"; +defparam \inst|reset_pin_in~I .oe_register_mode = "none"; +defparam \inst|reset_pin_in~I .oe_sync_reset = "none"; +defparam \inst|reset_pin_in~I .operation_mode = "input"; +defparam \inst|reset_pin_in~I .output_async_reset = "none"; +defparam \inst|reset_pin_in~I .output_power_up = "low"; +defparam \inst|reset_pin_in~I .output_register_mode = "none"; +defparam \inst|reset_pin_in~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N3 +stratix_lcell \inst|dly_counter_0_ ( +// Equation(s): +// \inst|dly_counter [0] = DFFEAS(\reset~combout & (\inst|dly_counter [1] # !\inst|dly_counter [0]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\reset~combout ), + .datab(vcc), + .datac(\inst|dly_counter [0]), + .datad(\inst|dly_counter [1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|dly_counter [0]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|dly_counter_0_ .lut_mask = "aa0a"; +defparam \inst|dly_counter_0_ .operation_mode = "normal"; +defparam \inst|dly_counter_0_ .output_mode = "reg_only"; +defparam \inst|dly_counter_0_ .register_cascade_mode = "off"; +defparam \inst|dly_counter_0_ .sum_lutc_input = "datac"; +defparam \inst|dly_counter_0_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N9 +stratix_lcell \inst|dly_counter_1_ ( +// Equation(s): +// \inst|dly_counter [1] = DFFEAS(\reset~combout & (\inst|dly_counter [0] # \inst|dly_counter [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\reset~combout ), + .datab(vcc), + .datac(\inst|dly_counter [0]), + .datad(\inst|dly_counter [1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|dly_counter [1]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|dly_counter_1_ .lut_mask = "aaa0"; +defparam \inst|dly_counter_1_ .operation_mode = "normal"; +defparam \inst|dly_counter_1_ .output_mode = "reg_only"; +defparam \inst|dly_counter_1_ .register_cascade_mode = "off"; +defparam \inst|dly_counter_1_ .sum_lutc_input = "datac"; +defparam \inst|dly_counter_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N7 +stratix_lcell \inst|vga_driver_unit|vsync_state_6_ ( +// Equation(s): +// \inst|vga_driver_unit|un6_dly_counter_0_x = !\inst|dly_counter [1] # !\inst|dly_counter [0] # !\reset~combout +// \inst|vga_driver_unit|vsync_state_6 = DFFEAS(\inst|vga_driver_unit|un6_dly_counter_0_x , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\reset~combout ), + .datab(vcc), + .datac(\inst|dly_counter [0]), + .datad(\inst|dly_counter [1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .regout(\inst|vga_driver_unit|vsync_state_6 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_6_ .lut_mask = "5fff"; +defparam \inst|vga_driver_unit|vsync_state_6_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_6_ .output_mode = "reg_and_comb"; +defparam \inst|vga_driver_unit|vsync_state_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_6_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_6_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N2 +stratix_lcell \inst|vga_driver_unit|hsync_state_6_ ( +// Equation(s): +// \inst|vga_driver_unit|d_set_hsync_counter = E1_hsync_state_6 # \inst|vga_driver_unit|hsync_state_0 +// \inst|vga_driver_unit|hsync_state_6 = DFFEAS(\inst|vga_driver_unit|d_set_hsync_counter , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|un6_dly_counter_0_x , , , VCC) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|hsync_state_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|d_set_hsync_counter ), + .regout(\inst|vga_driver_unit|hsync_state_6 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_6_ .lut_mask = "fff0"; +defparam \inst|vga_driver_unit|hsync_state_6_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_6_ .output_mode = "reg_and_comb"; +defparam \inst|vga_driver_unit|hsync_state_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_6_ .sum_lutc_input = "qfbk"; +defparam \inst|vga_driver_unit|hsync_state_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N0 +stratix_lcell \inst|vga_driver_unit|hsync_counter_0_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_0 = DFFEAS(!\inst|vga_driver_unit|hsync_counter_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , +// !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [0] = CARRY(\inst|vga_driver_unit|hsync_counter_0 ) +// \inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 = CARRY(\inst|vga_driver_unit|hsync_counter_0 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_0 ), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_0 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [0]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_0_ .lut_mask = "33cc"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_counter_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N1 +stratix_lcell \inst|vga_driver_unit|hsync_counter_1_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_1 = DFFEAS(\inst|vga_driver_unit|hsync_counter_1 $ \inst|vga_driver_unit|hsync_counter_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [1] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [0] # !\inst|vga_driver_unit|hsync_counter_1 ) +// \inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 # !\inst|vga_driver_unit|hsync_counter_1 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_1 ), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [0]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[0]~COUT1_10 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_1 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [1]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_1_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .lut_mask = "3c3f"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N2 +stratix_lcell \inst|vga_driver_unit|hsync_counter_2_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_2 = DFFEAS(\inst|vga_driver_unit|hsync_counter_2 $ (!\inst|vga_driver_unit|hsync_counter_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [2] = CARRY(\inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_cout [1])) +// \inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 = CARRY(\inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_2 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [1]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[1]~COUT1_12 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_2 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [2]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_2_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N3 +stratix_lcell \inst|vga_driver_unit|hsync_counter_3_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_3 = DFFEAS(\inst|vga_driver_unit|hsync_counter_3 $ (\inst|vga_driver_unit|hsync_counter_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [3] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [2] # !\inst|vga_driver_unit|hsync_counter_3 ) +// \inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 # !\inst|vga_driver_unit|hsync_counter_3 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_3 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [2]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[2]~COUT1_14 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_3 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [3]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_3_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .lut_mask = "5a5f"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N4 +stratix_lcell \inst|vga_driver_unit|hsync_counter_4_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_4 = DFFEAS(\inst|vga_driver_unit|hsync_counter_4 $ (!\inst|vga_driver_unit|hsync_counter_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [4] = CARRY(\inst|vga_driver_unit|hsync_counter_4 & (!\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_4 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [3]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[3]~COUT1_16 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_4 ), + .cout(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_4_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N5 +stratix_lcell \inst|vga_driver_unit|hsync_counter_5_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_5 = DFFEAS(\inst|vga_driver_unit|hsync_counter_5 $ \inst|vga_driver_unit|hsync_counter_cout [4], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [5] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [4] # !\inst|vga_driver_unit|hsync_counter_5 ) +// \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [4] # !\inst|vga_driver_unit|hsync_counter_5 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_5 ), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_5 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [5]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_5_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .lut_mask = "3c3f"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N1 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 ( +// Equation(s): +// \inst|vga_driver_unit|un13_hsync_counter_7 = \inst|vga_driver_unit|hsync_counter_2 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_0 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_2 ), + .datab(\inst|vga_driver_unit|hsync_counter_1 ), + .datac(\inst|vga_driver_unit|hsync_counter_3 ), + .datad(\inst|vga_driver_unit|hsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_hsync_counter_7 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .lut_mask = "8000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N6 +stratix_lcell \inst|vga_driver_unit|hsync_counter_6_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_6 = DFFEAS(\inst|vga_driver_unit|hsync_counter_6 $ !(!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [5]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & +// \inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [6] = CARRY(\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_cout [5]) +// \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 = CARRY(\inst|vga_driver_unit|hsync_counter_6 & !\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_6 ), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [5]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[5]~COUT1_18 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_6 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [6]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_6_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .lut_mask = "c30c"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N7 +stratix_lcell \inst|vga_driver_unit|hsync_counter_7_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_7 = DFFEAS(\inst|vga_driver_unit|hsync_counter_7 $ ((!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [6]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & +// \inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [7] = CARRY(!\inst|vga_driver_unit|hsync_counter_cout [6] # !\inst|vga_driver_unit|hsync_counter_7 ) +// \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 = CARRY(!\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 # !\inst|vga_driver_unit|hsync_counter_7 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_7 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [6]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[6]~COUT1_20 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_7 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [7]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_7_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .lut_mask = "5a5f"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_7_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N8 +stratix_lcell \inst|vga_driver_unit|hsync_counter_8_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_8 = DFFEAS(\inst|vga_driver_unit|hsync_counter_8 $ (!(!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [7]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & +// \inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) +// \inst|vga_driver_unit|hsync_counter_cout [8] = CARRY(\inst|vga_driver_unit|hsync_counter_8 & (!\inst|vga_driver_unit|hsync_counter_cout [7])) +// \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 = CARRY(\inst|vga_driver_unit|hsync_counter_8 & (!\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_counter_8 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [7]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[7]~COUT1_22 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_8 ), + .cout(), + .cout0(\inst|vga_driver_unit|hsync_counter_cout [8]), + .cout1(\inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_8_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_8_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y43_N9 +stratix_lcell \inst|vga_driver_unit|hsync_counter_9_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_9 = DFFEAS((!\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout [8]) # (\inst|vga_driver_unit|hsync_counter_cout [4] & \inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ) $ +// \inst|vga_driver_unit|hsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_2_i , !\inst|vga_driver_unit|un9_hsync_counterlt9 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .datad(\inst|vga_driver_unit|hsync_counter_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_2_i ), + .sload(!\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|hsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|hsync_counter_cout [8]), + .cin1(\inst|vga_driver_unit|hsync_counter_cout[8]~COUT1_24 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_counter_9 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_9_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .cin_used = "true"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .lut_mask = "0ff0"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|hsync_counter_9_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N2 +stratix_lcell \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 ( +// Equation(s): +// \inst|vga_driver_unit|un9_hsync_counterlt9_3 = !\inst|vga_driver_unit|hsync_counter_6 # !\inst|vga_driver_unit|hsync_counter_8 # !\inst|vga_driver_unit|hsync_counter_9 # !\inst|vga_driver_unit|hsync_counter_7 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_7 ), + .datab(\inst|vga_driver_unit|hsync_counter_9 ), + .datac(\inst|vga_driver_unit|hsync_counter_8 ), + .datad(\inst|vga_driver_unit|hsync_counter_6 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_hsync_counterlt9_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .lut_mask = "7fff"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N4 +stratix_lcell \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 ( +// Equation(s): +// \inst|vga_driver_unit|un9_hsync_counterlt9 = \inst|vga_driver_unit|un9_hsync_counterlt9_3 # !\inst|vga_driver_unit|un13_hsync_counter_7 # !\inst|vga_driver_unit|hsync_counter_4 # !\inst|vga_driver_unit|hsync_counter_5 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_5 ), + .datab(\inst|vga_driver_unit|hsync_counter_4 ), + .datac(\inst|vga_driver_unit|un13_hsync_counter_7 ), + .datad(\inst|vga_driver_unit|un9_hsync_counterlt9_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .lut_mask = "ff7f"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N5 +stratix_lcell \inst|vga_driver_unit|G_2 ( +// Equation(s): +// \inst|vga_driver_unit|G_2_i = !\inst|vga_driver_unit|hsync_state_6 & !\inst|vga_driver_unit|hsync_state_0 & !\inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|un9_hsync_counterlt9 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_state_6 ), + .datab(\inst|vga_driver_unit|hsync_state_0 ), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|un9_hsync_counterlt9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|G_2_i ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|G_2 .lut_mask = "01ff"; +defparam \inst|vga_driver_unit|G_2 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|G_2 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|G_2 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|G_2 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|G_2 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N5 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un12_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_9 & \inst|vga_driver_unit|hsync_counter_2 & !\inst|vga_driver_unit|hsync_counter_5 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_3 ), + .datab(\inst|vga_driver_unit|hsync_counter_9 ), + .datac(\inst|vga_driver_unit|hsync_counter_2 ), + .datad(\inst|vga_driver_unit|hsync_counter_5 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_hsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .lut_mask = "0040"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N6 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 ( +// Equation(s): +// \inst|vga_driver_unit|un12_hsync_counter_4 = !\inst|vga_driver_unit|hsync_counter_4 & !\inst|vga_driver_unit|hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|hsync_counter_8 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_4 ), + .datab(\inst|vga_driver_unit|hsync_counter_7 ), + .datac(\inst|vga_driver_unit|hsync_counter_6 ), + .datad(\inst|vga_driver_unit|hsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_hsync_counter_4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .lut_mask = "0100"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N8 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter ( +// Equation(s): +// \inst|vga_driver_unit|un12_hsync_counter = \inst|vga_driver_unit|hsync_counter_0 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|un12_hsync_counter_3 & \inst|vga_driver_unit|un12_hsync_counter_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_0 ), + .datab(\inst|vga_driver_unit|hsync_counter_1 ), + .datac(\inst|vga_driver_unit|un12_hsync_counter_3 ), + .datad(\inst|vga_driver_unit|un12_hsync_counter_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_hsync_counter ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .lut_mask = "8000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N8 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 ( +// Equation(s): +// \inst|vga_driver_unit|un10_hsync_counter_1 = !\inst|vga_driver_unit|hsync_counter_5 & !\inst|vga_driver_unit|hsync_counter_9 & !\inst|vga_driver_unit|hsync_counter_8 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_5 ), + .datac(\inst|vga_driver_unit|hsync_counter_9 ), + .datad(\inst|vga_driver_unit|hsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .lut_mask = "0003"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N3 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un11_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_3 & !\inst|vga_driver_unit|hsync_counter_4 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|hsync_counter_0 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_3 ), + .datab(\inst|vga_driver_unit|hsync_counter_4 ), + .datac(\inst|vga_driver_unit|hsync_counter_1 ), + .datad(\inst|vga_driver_unit|hsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un11_hsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .lut_mask = "1000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N1 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 ( +// Equation(s): +// \inst|vga_driver_unit|un11_hsync_counter_2 = \inst|vga_driver_unit|hsync_counter_2 & (!\inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|hsync_counter_7 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_2 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_counter_6 ), + .datad(\inst|vga_driver_unit|hsync_counter_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un11_hsync_counter_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .lut_mask = "0a00"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N7 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 ( +// Equation(s): +// \inst|vga_driver_unit|un10_hsync_counter_4 = \inst|vga_driver_unit|hsync_counter_3 & \inst|vga_driver_unit|hsync_counter_1 & \inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|hsync_counter_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_3 ), + .datab(\inst|vga_driver_unit|hsync_counter_1 ), + .datac(\inst|vga_driver_unit|hsync_counter_6 ), + .datad(\inst|vga_driver_unit|hsync_counter_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_hsync_counter_4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .lut_mask = "8000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N9 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un10_hsync_counter_3 = !\inst|vga_driver_unit|hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_2 & !\inst|vga_driver_unit|hsync_counter_0 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_counter_7 ), + .datac(\inst|vga_driver_unit|hsync_counter_2 ), + .datad(\inst|vga_driver_unit|hsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_hsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .lut_mask = "0003"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N8 +stratix_lcell \inst|vga_driver_unit|hsync_state_5_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_5 = DFFEAS(\inst|vga_driver_unit|hsync_state_6 # \inst|vga_driver_unit|hsync_state_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|hsync_state_6 ), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|hsync_state_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_5 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_5_ .lut_mask = "ffaa"; +defparam \inst|vga_driver_unit|hsync_state_5_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_5_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N6 +stratix_lcell \inst|vga_driver_unit|hsync_state_4_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_4 = DFFEAS(\inst|vga_driver_unit|un10_hsync_counter_4 & \inst|vga_driver_unit|un10_hsync_counter_3 & \inst|vga_driver_unit|hsync_state_5 & \inst|vga_driver_unit|un10_hsync_counter_1 , +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_hsync_counter_4 ), + .datab(\inst|vga_driver_unit|un10_hsync_counter_3 ), + .datac(\inst|vga_driver_unit|hsync_state_5 ), + .datad(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_4 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_4_ .lut_mask = "8000"; +defparam \inst|vga_driver_unit|hsync_state_4_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_4_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N4 +stratix_lcell \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 = \inst|vga_driver_unit|hsync_state_4 & (!\inst|vga_driver_unit|un11_hsync_counter_2 # !\inst|vga_driver_unit|un11_hsync_counter_3 # !\inst|vga_driver_unit|un10_hsync_counter_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .datab(\inst|vga_driver_unit|un11_hsync_counter_3 ), + .datac(\inst|vga_driver_unit|un11_hsync_counter_2 ), + .datad(\inst|vga_driver_unit|hsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .lut_mask = "7f00"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N4 +stratix_lcell \inst|vga_driver_unit|hsync_state_1_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_1 = DFFEAS(\inst|vga_driver_unit|un10_hsync_counter_1 & \inst|vga_driver_unit|un11_hsync_counter_2 & \inst|vga_driver_unit|un11_hsync_counter_3 & \inst|vga_driver_unit|hsync_state_4 , +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .datab(\inst|vga_driver_unit|un11_hsync_counter_2 ), + .datac(\inst|vga_driver_unit|un11_hsync_counter_3 ), + .datad(\inst|vga_driver_unit|hsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_1 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_1_ .lut_mask = "8000"; +defparam \inst|vga_driver_unit|hsync_state_1_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N9 +stratix_lcell \inst|vga_driver_unit|hsync_state_3_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 = \inst|vga_driver_unit|un13_hsync_counter & (E1_hsync_state_3 & !\inst|vga_driver_unit|un12_hsync_counter ) # !\inst|vga_driver_unit|un13_hsync_counter & (\inst|vga_driver_unit|hsync_state_2 # +// E1_hsync_state_3 & !\inst|vga_driver_unit|un12_hsync_counter ) +// \inst|vga_driver_unit|hsync_state_3 = DFFEAS(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , \inst|vga_driver_unit|hsync_state_1 , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , VCC) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un13_hsync_counter ), + .datab(\inst|vga_driver_unit|hsync_state_2 ), + .datac(\inst|vga_driver_unit|hsync_state_1 ), + .datad(\inst|vga_driver_unit|un12_hsync_counter ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(vcc), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ), + .regout(\inst|vga_driver_unit|hsync_state_3 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_3_ .lut_mask = "44f4"; +defparam \inst|vga_driver_unit|hsync_state_3_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_3_ .output_mode = "reg_and_comb"; +defparam \inst|vga_driver_unit|hsync_state_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_3_ .sum_lutc_input = "qfbk"; +defparam \inst|vga_driver_unit|hsync_state_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N0 +stratix_lcell \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 = \inst|vga_driver_unit|hsync_state_5 & (!\inst|vga_driver_unit|un10_hsync_counter_1 # !\inst|vga_driver_unit|un10_hsync_counter_4 # !\inst|vga_driver_unit|un10_hsync_counter_3 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un10_hsync_counter_3 ), + .datab(\inst|vga_driver_unit|hsync_state_5 ), + .datac(\inst|vga_driver_unit|un10_hsync_counter_4 ), + .datad(\inst|vga_driver_unit|un10_hsync_counter_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .lut_mask = "4ccc"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N7 +stratix_lcell \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 & !\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 & +// !\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_2 ), + .datab(\inst|vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0 ), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|hsync_state_next_1_sqmuxa_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .lut_mask = "f0f1"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N6 +stratix_lcell \inst|vga_driver_unit|hsync_state_2_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_2 = DFFEAS(\inst|vga_driver_unit|un12_hsync_counter & \inst|vga_driver_unit|hsync_state_3 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un12_hsync_counter ), + .datad(\inst|vga_driver_unit|hsync_state_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_2 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_2_ .lut_mask = "f000"; +defparam \inst|vga_driver_unit|hsync_state_2_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_2_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X55_Y44_N9 +stratix_lcell \inst|vga_driver_unit|hsync_state_0_ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_state_0 = DFFEAS(\inst|vga_driver_unit|hsync_state_2 & (\inst|vga_driver_unit|un13_hsync_counter ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_state_2 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|un13_hsync_counter ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|hsync_state_3_0_0_0__g0_0 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|hsync_state_0 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_state_0_ .lut_mask = "cc00"; +defparam \inst|vga_driver_unit|hsync_state_0_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_state_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|hsync_state_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_state_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_state_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N1 +stratix_lcell \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ ( +// Equation(s): +// \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa = \reset~combout & \inst|dly_counter [1] & \inst|dly_counter [0] & !\inst|vga_driver_unit|d_set_hsync_counter + + .clk(gnd), + .dataa(\reset~combout ), + .datab(\inst|dly_counter [1]), + .datac(\inst|dly_counter [0]), + .datad(\inst|vga_driver_unit|d_set_hsync_counter ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|hsync_counter_next_1_sqmuxa ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .lut_mask = "0080"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N2 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 ( +// Equation(s): +// \inst|vga_driver_unit|un13_hsync_counter_2 = \inst|vga_driver_unit|hsync_counter_4 & !\inst|vga_driver_unit|hsync_counter_5 & \inst|vga_driver_unit|hsync_counter_9 & \inst|vga_driver_unit|hsync_counter_8 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|hsync_counter_4 ), + .datab(\inst|vga_driver_unit|hsync_counter_5 ), + .datac(\inst|vga_driver_unit|hsync_counter_9 ), + .datad(\inst|vga_driver_unit|hsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_hsync_counter_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .lut_mask = "2000"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y44_N3 +stratix_lcell \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter ( +// Equation(s): +// \inst|vga_driver_unit|un13_hsync_counter = \inst|vga_driver_unit|un13_hsync_counter_2 & !\inst|vga_driver_unit|hsync_counter_7 & !\inst|vga_driver_unit|hsync_counter_6 & \inst|vga_driver_unit|un13_hsync_counter_7 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un13_hsync_counter_2 ), + .datab(\inst|vga_driver_unit|hsync_counter_7 ), + .datac(\inst|vga_driver_unit|hsync_counter_6 ), + .datad(\inst|vga_driver_unit|un13_hsync_counter_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_hsync_counter ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .lut_mask = "0200"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .operation_mode = "normal"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N3 +stratix_lcell \inst|vga_driver_unit|un1_hsync_state_3_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|un1_hsync_state_3_0 = \inst|vga_driver_unit|hsync_state_3 # \inst|vga_driver_unit|hsync_state_1 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_state_3 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|hsync_state_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_hsync_state_3_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .lut_mask = "ffcc"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_hsync_state_3_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N2 +stratix_lcell \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|h_sync_1_0_0_0_g1 = \inst|vga_driver_unit|un1_hsync_state_3_0 & \inst|vga_driver_unit|h_sync # !\inst|vga_driver_unit|un1_hsync_state_3_0 & (\inst|vga_driver_unit|hsync_state_2 & \inst|vga_driver_unit|h_sync # +// !\inst|vga_driver_unit|hsync_state_2 & (\inst|vga_driver_unit|hsync_state_4 )) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un1_hsync_state_3_0 ), + .datab(\inst|vga_driver_unit|h_sync ), + .datac(\inst|vga_driver_unit|hsync_state_2 ), + .datad(\inst|vga_driver_unit|hsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .lut_mask = "cdc8"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|h_sync_1_0_0_0_g1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N9 +stratix_lcell \inst|vga_driver_unit|h_sync_Z ( +// Equation(s): +// \inst|vga_driver_unit|h_sync = DFFEAS(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 # !\inst|dly_counter [0] # !\reset~combout # !\inst|dly_counter [1], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|dly_counter [1]), + .datab(\reset~combout ), + .datac(\inst|dly_counter [0]), + .datad(\inst|vga_driver_unit|h_sync_1_0_0_0_g1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|h_sync ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|h_sync_Z .lut_mask = "ff7f"; +defparam \inst|vga_driver_unit|h_sync_Z .operation_mode = "normal"; +defparam \inst|vga_driver_unit|h_sync_Z .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|h_sync_Z .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|h_sync_Z .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|h_sync_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N0 +stratix_lcell \inst|vga_driver_unit|vsync_counter_0_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_0 = DFFEAS(\inst|vga_driver_unit|vsync_counter_0 $ \inst|vga_driver_unit|d_set_hsync_counter , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [0] = CARRY(\inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|d_set_hsync_counter ) +// \inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 = CARRY(\inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|d_set_hsync_counter ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_0 ), + .datab(\inst|vga_driver_unit|d_set_hsync_counter ), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_0 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [0]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_0_ .lut_mask = "6688"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_counter_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N1 +stratix_lcell \inst|vga_driver_unit|vsync_counter_1_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_1 = DFFEAS(\inst|vga_driver_unit|vsync_counter_1 $ \inst|vga_driver_unit|vsync_counter_cout [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [1] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [0] # !\inst|vga_driver_unit|vsync_counter_1 ) +// \inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 # !\inst|vga_driver_unit|vsync_counter_1 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|vsync_counter_1 ), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [0]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[0]~COUT1_10 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_1 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [1]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_1_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .lut_mask = "3c3f"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N2 +stratix_lcell \inst|vga_driver_unit|vsync_counter_2_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_2 = DFFEAS(\inst|vga_driver_unit|vsync_counter_2 $ (!\inst|vga_driver_unit|vsync_counter_cout [1]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [2] = CARRY(\inst|vga_driver_unit|vsync_counter_2 & (!\inst|vga_driver_unit|vsync_counter_cout [1])) +// \inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 = CARRY(\inst|vga_driver_unit|vsync_counter_2 & (!\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_2 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [1]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[1]~COUT1_12 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_2 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [2]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_2_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N3 +stratix_lcell \inst|vga_driver_unit|vsync_counter_3_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_3 = DFFEAS(\inst|vga_driver_unit|vsync_counter_3 $ (\inst|vga_driver_unit|vsync_counter_cout [2]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [3] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [2] # !\inst|vga_driver_unit|vsync_counter_3 ) +// \inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 # !\inst|vga_driver_unit|vsync_counter_3 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_3 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [2]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[2]~COUT1_14 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_3 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [3]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_3_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .lut_mask = "5a5f"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N4 +stratix_lcell \inst|vga_driver_unit|vsync_counter_4_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_4 = DFFEAS(\inst|vga_driver_unit|vsync_counter_4 $ (!\inst|vga_driver_unit|vsync_counter_cout [3]), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [4] = CARRY(\inst|vga_driver_unit|vsync_counter_4 & (!\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_4 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [3]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[3]~COUT1_16 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_4 ), + .cout(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_4_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N5 +stratix_lcell \inst|vga_driver_unit|vsync_counter_5_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_5 = DFFEAS(\inst|vga_driver_unit|vsync_counter_5 $ \inst|vga_driver_unit|vsync_counter_cout [4], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , +// !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [5] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [4] # !\inst|vga_driver_unit|vsync_counter_5 ) +// \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [4] # !\inst|vga_driver_unit|vsync_counter_5 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|vsync_counter_5 ), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_5 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [5]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_5_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .lut_mask = "3c3f"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N6 +stratix_lcell \inst|vga_driver_unit|vsync_counter_6_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_6 = DFFEAS(\inst|vga_driver_unit|vsync_counter_6 $ !(!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [5]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & +// \inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [6] = CARRY(\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_cout [5]) +// \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 = CARRY(\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [5]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[5]~COUT1_18 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_6 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [6]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_6_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .lut_mask = "c30c"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N7 +stratix_lcell \inst|vga_driver_unit|vsync_counter_7_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_7 = DFFEAS(\inst|vga_driver_unit|vsync_counter_7 $ ((!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [6]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & +// \inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [7] = CARRY(!\inst|vga_driver_unit|vsync_counter_cout [6] # !\inst|vga_driver_unit|vsync_counter_7 ) +// \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 = CARRY(!\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 # !\inst|vga_driver_unit|vsync_counter_7 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_7 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [6]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[6]~COUT1_20 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_7 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [7]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_7_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .lut_mask = "5a5f"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_7_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N8 +stratix_lcell \inst|vga_driver_unit|vsync_counter_8_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_8 = DFFEAS(\inst|vga_driver_unit|vsync_counter_8 $ (!(!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [7]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & +// \inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 )), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) +// \inst|vga_driver_unit|vsync_counter_cout [8] = CARRY(\inst|vga_driver_unit|vsync_counter_8 & (!\inst|vga_driver_unit|vsync_counter_cout [7])) +// \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 = CARRY(\inst|vga_driver_unit|vsync_counter_8 & (!\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 )) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_8 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [7]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[7]~COUT1_22 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_8 ), + .cout(), + .cout0(\inst|vga_driver_unit|vsync_counter_cout [8]), + .cout1(\inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_8_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .lut_mask = "a50a"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_8_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N9 +stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 ( +// Equation(s): +// \inst|vga_driver_unit|un9_vsync_counterlt9_5 = !\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|vsync_counter_8 # !\inst|vga_driver_unit|vsync_counter_7 # !\inst|vga_driver_unit|vsync_counter_6 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_6 ), + .datab(\inst|vga_driver_unit|vsync_counter_7 ), + .datac(\inst|vga_driver_unit|vsync_counter_8 ), + .datad(\inst|vga_driver_unit|vsync_counter_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_vsync_counterlt9_5 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .lut_mask = "7fff"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N2 +stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 ( +// Equation(s): +// \inst|vga_driver_unit|un9_vsync_counterlt9_6 = !\inst|vga_driver_unit|vsync_counter_2 # !\inst|vga_driver_unit|vsync_counter_0 # !\inst|vga_driver_unit|vsync_counter_3 # !\inst|vga_driver_unit|vsync_counter_1 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_1 ), + .datab(\inst|vga_driver_unit|vsync_counter_3 ), + .datac(\inst|vga_driver_unit|vsync_counter_0 ), + .datad(\inst|vga_driver_unit|vsync_counter_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_vsync_counterlt9_6 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .lut_mask = "7fff"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N5 +stratix_lcell \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 ( +// Equation(s): +// \inst|vga_driver_unit|un9_vsync_counterlt9 = \inst|vga_driver_unit|un9_vsync_counterlt9_5 # \inst|vga_driver_unit|un9_vsync_counterlt9_6 # !\inst|vga_driver_unit|vsync_counter_5 # !\inst|vga_driver_unit|vsync_counter_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_4 ), + .datab(\inst|vga_driver_unit|un9_vsync_counterlt9_5 ), + .datac(\inst|vga_driver_unit|vsync_counter_5 ), + .datad(\inst|vga_driver_unit|un9_vsync_counterlt9_6 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .lut_mask = "ffdf"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N4 +stratix_lcell \inst|vga_driver_unit|G_16 ( +// Equation(s): +// \inst|vga_driver_unit|G_16_i = !\inst|vga_driver_unit|vsync_state_6 & !\inst|vga_driver_unit|vsync_state_0 & !\inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|un9_vsync_counterlt9 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_state_6 ), + .datab(\inst|vga_driver_unit|vsync_state_0 ), + .datac(\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .datad(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|G_16_i ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|G_16 .lut_mask = "0f1f"; +defparam \inst|vga_driver_unit|G_16 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|G_16 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|G_16 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|G_16 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|G_16 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N6 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 ( +// Equation(s): +// \inst|vga_driver_unit|un12_vsync_counter_6 = !\inst|vga_driver_unit|vsync_counter_7 & !\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_5 & !\inst|vga_driver_unit|vsync_counter_8 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_7 ), + .datab(\inst|vga_driver_unit|vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_counter_5 ), + .datad(\inst|vga_driver_unit|vsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_vsync_counter_6 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .lut_mask = "0001"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N9 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 ( +// Equation(s): +// \inst|vga_driver_unit|un12_vsync_counter_7 = !\inst|vga_driver_unit|vsync_counter_1 & !\inst|vga_driver_unit|vsync_counter_4 & !\inst|vga_driver_unit|vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_2 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_1 ), + .datab(\inst|vga_driver_unit|vsync_counter_4 ), + .datac(\inst|vga_driver_unit|vsync_counter_3 ), + .datad(\inst|vga_driver_unit|vsync_counter_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un12_vsync_counter_7 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .lut_mask = "0001"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N4 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 ( +// Equation(s): +// \inst|vga_driver_unit|un14_vsync_counter_8 = \inst|vga_driver_unit|un12_vsync_counter_7 & (\inst|vga_driver_unit|un12_vsync_counter_6 ) + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un12_vsync_counter_7 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|un12_vsync_counter_6 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .lut_mask = "cc00"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N5 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un13_vsync_counter_3 = !\inst|vga_driver_unit|vsync_counter_7 & !\inst|vga_driver_unit|vsync_counter_6 & !\inst|vga_driver_unit|vsync_counter_9 & !\inst|vga_driver_unit|vsync_counter_8 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_7 ), + .datab(\inst|vga_driver_unit|vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_counter_9 ), + .datad(\inst|vga_driver_unit|vsync_counter_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_vsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .lut_mask = "0001"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N0 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 ( +// Equation(s): +// \inst|vga_driver_unit|un13_vsync_counter_4 = \inst|vga_driver_unit|vsync_counter_5 & (\inst|vga_driver_unit|un13_vsync_counter_3 & \inst|vga_driver_unit|vsync_counter_0 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_5 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|un13_vsync_counter_3 ), + .datad(\inst|vga_driver_unit|vsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un13_vsync_counter_4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .lut_mask = "a000"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N4 +stratix_lcell \inst|vga_driver_unit|vsync_state_1_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_1 = DFFEAS(\inst|vga_driver_unit|un12_vsync_counter_7 & \inst|vga_driver_unit|un13_vsync_counter_4 & !\inst|vga_driver_unit|un6_dly_counter_0_x & \inst|vga_driver_unit|vsync_state_4 , +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un12_vsync_counter_7 ), + .datab(\inst|vga_driver_unit|un13_vsync_counter_4 ), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|vsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_1 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_1_ .lut_mask = "0800"; +defparam \inst|vga_driver_unit|vsync_state_1_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N0 +stratix_lcell \inst|vga_driver_unit|vsync_state_3_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 = E1_vsync_state_3 & (!\inst|vga_driver_unit|vsync_counter_0 # !\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|un14_vsync_counter_8 ) +// \inst|vga_driver_unit|vsync_state_3 = DFFEAS(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , \inst|vga_driver_unit|vsync_state_1 , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , VCC) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .datab(\inst|vga_driver_unit|vsync_counter_9 ), + .datac(\inst|vga_driver_unit|vsync_state_1 ), + .datad(\inst|vga_driver_unit|vsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(vcc), + .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ), + .regout(\inst|vga_driver_unit|vsync_state_3 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_3_ .lut_mask = "70f0"; +defparam \inst|vga_driver_unit|vsync_state_3_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_3_ .output_mode = "reg_and_comb"; +defparam \inst|vga_driver_unit|vsync_state_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_3_ .sum_lutc_input = "qfbk"; +defparam \inst|vga_driver_unit|vsync_state_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N3 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 ( +// Equation(s): +// \inst|vga_driver_unit|un15_vsync_counter_3 = \inst|vga_driver_unit|vsync_counter_9 & \inst|vga_driver_unit|vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_0 & !\inst|vga_driver_unit|vsync_counter_2 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_9 ), + .datab(\inst|vga_driver_unit|vsync_counter_3 ), + .datac(\inst|vga_driver_unit|vsync_counter_0 ), + .datad(\inst|vga_driver_unit|vsync_counter_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un15_vsync_counter_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .lut_mask = "0008"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N8 +stratix_lcell \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 ( +// Equation(s): +// \inst|vga_driver_unit|un15_vsync_counter_4 = !\inst|vga_driver_unit|vsync_counter_4 & (\inst|vga_driver_unit|un15_vsync_counter_3 & !\inst|vga_driver_unit|vsync_counter_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_4 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|un15_vsync_counter_3 ), + .datad(\inst|vga_driver_unit|vsync_counter_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un15_vsync_counter_4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .lut_mask = "0050"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N1 +stratix_lcell \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 = \inst|vga_driver_unit|vsync_state_4 & (!\inst|vga_driver_unit|un13_vsync_counter_4 # !\inst|vga_driver_unit|un12_vsync_counter_7 ) + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un12_vsync_counter_7 ), + .datac(\inst|vga_driver_unit|vsync_state_4 ), + .datad(\inst|vga_driver_unit|un13_vsync_counter_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .lut_mask = "30f0"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N5 +stratix_lcell \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 = \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 # \inst|vga_driver_unit|vsync_state_2 & (!\inst|vga_driver_unit|un12_vsync_counter_6 # !\inst|vga_driver_unit|un15_vsync_counter_4 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un15_vsync_counter_4 ), + .datab(\inst|vga_driver_unit|un12_vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_2 ), + .datad(\inst|vga_driver_unit|vsync_state_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .lut_mask = "f7f0"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N3 +stratix_lcell \inst|vga_driver_unit|vsync_state_5_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_5 = DFFEAS(\inst|vga_driver_unit|vsync_state_0 # \inst|vga_driver_unit|vsync_state_6 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|vsync_state_0 ), + .datac(\inst|vga_driver_unit|vsync_state_6 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_5 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_5_ .lut_mask = "fcfc"; +defparam \inst|vga_driver_unit|vsync_state_5_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_5_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N0 +stratix_lcell \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 = \inst|vga_driver_unit|vsync_state_5 & (\inst|vga_driver_unit|vsync_counter_9 # !\inst|vga_driver_unit|vsync_counter_0 # !\inst|vga_driver_unit|un14_vsync_counter_8 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_counter_9 ), + .datab(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .datac(\inst|vga_driver_unit|vsync_state_5 ), + .datad(\inst|vga_driver_unit|vsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .lut_mask = "b0f0"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N2 +stratix_lcell \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_next_2_sqmuxa = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 & !\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 & +// !\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_3 ), + .datab(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datac(\inst|vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0 ), + .datad(\inst|vga_driver_unit|vsync_state_next_1_sqmuxa_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .lut_mask = "cccd"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_next_2_sqmuxa_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N8 +stratix_lcell \inst|vga_driver_unit|vsync_state_2_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_2 = DFFEAS(\inst|vga_driver_unit|vsync_counter_0 & \inst|vga_driver_unit|un14_vsync_counter_8 & \inst|vga_driver_unit|vsync_state_3 & \inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), +// VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_0 ), + .datab(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .datac(\inst|vga_driver_unit|vsync_state_3 ), + .datad(\inst|vga_driver_unit|vsync_counter_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_2 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_2_ .lut_mask = "8000"; +defparam \inst|vga_driver_unit|vsync_state_2_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_2_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N7 +stratix_lcell \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 = \inst|vga_driver_unit|un12_vsync_counter_6 & \inst|vga_driver_unit|vsync_state_2 & \inst|vga_driver_unit|un15_vsync_counter_4 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un12_vsync_counter_6 ), + .datac(\inst|vga_driver_unit|vsync_state_2 ), + .datad(\inst|vga_driver_unit|un15_vsync_counter_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .lut_mask = "c000"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y34_N6 +stratix_lcell \inst|vga_driver_unit|vsync_state_0_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_0 = DFFEAS(\inst|vga_driver_unit|un6_dly_counter_0_x & \inst|vga_driver_unit|vsync_state_0 & (!\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ) # !\inst|vga_driver_unit|un6_dly_counter_0_x & +// (\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 # \inst|vga_driver_unit|vsync_state_0 & !\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datab(\inst|vga_driver_unit|vsync_state_0 ), + .datac(\inst|vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0 ), + .datad(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_0 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_0_ .lut_mask = "50dc"; +defparam \inst|vga_driver_unit|vsync_state_0_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_0_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N1 +stratix_lcell \inst|vga_driver_unit|d_set_vsync_counter_cZ ( +// Equation(s): +// \inst|vga_driver_unit|d_set_vsync_counter = \inst|vga_driver_unit|vsync_state_0 # \inst|vga_driver_unit|vsync_state_6 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|vsync_state_0 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_state_6 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|d_set_vsync_counter ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .lut_mask = "fafa"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|d_set_vsync_counter_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N4 +stratix_lcell \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa = \inst|dly_counter [0] & \reset~combout & \inst|dly_counter [1] & !\inst|vga_driver_unit|d_set_vsync_counter + + .clk(gnd), + .dataa(\inst|dly_counter [0]), + .datab(\reset~combout ), + .datac(\inst|dly_counter [1]), + .datad(\inst|vga_driver_unit|d_set_vsync_counter ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .lut_mask = "0080"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X35_Y33_N9 +stratix_lcell \inst|vga_driver_unit|vsync_counter_9_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_counter_9 = DFFEAS((!\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout [8]) # (\inst|vga_driver_unit|vsync_counter_cout [4] & \inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ) $ +// \inst|vga_driver_unit|vsync_counter_9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , \inst|vga_driver_unit|vsync_counter_next_1_sqmuxa , , !\inst|vga_driver_unit|G_16_i , !\inst|vga_driver_unit|un9_vsync_counterlt9 ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_counter_next_1_sqmuxa ), + .datad(\inst|vga_driver_unit|vsync_counter_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|G_16_i ), + .sload(!\inst|vga_driver_unit|un9_vsync_counterlt9 ), + .ena(vcc), + .cin(\inst|vga_driver_unit|vsync_counter_cout [4]), + .cin0(\inst|vga_driver_unit|vsync_counter_cout [8]), + .cin1(\inst|vga_driver_unit|vsync_counter_cout[8]~COUT1_24 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_counter_9 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_counter_9_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .cin_used = "true"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .lut_mask = "0ff0"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|vsync_counter_9_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X36_Y34_N7 +stratix_lcell \inst|vga_driver_unit|vsync_state_4_ ( +// Equation(s): +// \inst|vga_driver_unit|vsync_state_4 = DFFEAS(!\inst|vga_driver_unit|vsync_counter_9 & \inst|vga_driver_unit|un14_vsync_counter_8 & \inst|vga_driver_unit|vsync_state_5 & \inst|vga_driver_unit|vsync_counter_0 , GLOBAL(\inst1|altpll_component|_clk0 ), +// VCC, , \inst|vga_driver_unit|vsync_state_next_2_sqmuxa , , , \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|vsync_counter_9 ), + .datab(\inst|vga_driver_unit|un14_vsync_counter_8 ), + .datac(\inst|vga_driver_unit|vsync_state_5 ), + .datad(\inst|vga_driver_unit|vsync_counter_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|vsync_state_next_2_sqmuxa ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|vsync_state_4 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|vsync_state_4_ .lut_mask = "4000"; +defparam \inst|vga_driver_unit|vsync_state_4_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|vsync_state_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|vsync_state_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|vsync_state_4_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|vsync_state_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N8 +stratix_lcell \inst|vga_driver_unit|un1_vsync_state_2_0_cZ ( +// Equation(s): +// \inst|vga_driver_unit|un1_vsync_state_2_0 = \inst|vga_driver_unit|vsync_state_1 # \inst|vga_driver_unit|vsync_state_3 + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_state_1 ), + .datad(\inst|vga_driver_unit|vsync_state_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_vsync_state_2_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .lut_mask = "fff0"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_vsync_state_2_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N5 +stratix_lcell \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|v_sync_1_0_0_0_g1 = \inst|vga_driver_unit|vsync_state_2 & \inst|vga_driver_unit|v_sync # !\inst|vga_driver_unit|vsync_state_2 & (\inst|vga_driver_unit|un1_vsync_state_2_0 & \inst|vga_driver_unit|v_sync # +// !\inst|vga_driver_unit|un1_vsync_state_2_0 & (\inst|vga_driver_unit|vsync_state_4 )) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|v_sync ), + .datab(\inst|vga_driver_unit|vsync_state_4 ), + .datac(\inst|vga_driver_unit|vsync_state_2 ), + .datad(\inst|vga_driver_unit|un1_vsync_state_2_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .lut_mask = "aaac"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|v_sync_1_0_0_0_g1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N7 +stratix_lcell \inst|vga_driver_unit|v_sync_Z ( +// Equation(s): +// \inst|vga_driver_unit|v_sync = DFFEAS(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 # !\inst|dly_counter [1] # !\reset~combout # !\inst|dly_counter [0], GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|dly_counter [0]), + .datab(\reset~combout ), + .datac(\inst|dly_counter [1]), + .datad(\inst|vga_driver_unit|v_sync_1_0_0_0_g1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|v_sync ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|v_sync_Z .lut_mask = "ff7f"; +defparam \inst|vga_driver_unit|v_sync_Z .operation_mode = "normal"; +defparam \inst|vga_driver_unit|v_sync_Z .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|v_sync_Z .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|v_sync_Z .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|v_sync_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N8 +stratix_lcell \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 = \reset~combout & \inst|dly_counter [1] & \inst|dly_counter [0] & !\inst|vga_driver_unit|hsync_state_1 + + .clk(gnd), + .dataa(\reset~combout ), + .datab(\inst|dly_counter [1]), + .datac(\inst|dly_counter [0]), + .datad(\inst|vga_driver_unit|hsync_state_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .lut_mask = "0080"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N5 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_0_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_0 = DFFEAS(!\inst|vga_driver_unit|column_counter_sig_0 # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(\inst|vga_driver_unit|column_counter_sig_0 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_0 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_0_ .lut_mask = "0fff"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N5 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_1_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [1] = \inst|vga_driver_unit|column_counter_sig_0 $ \inst|vga_driver_unit|column_counter_sig_1 +// \inst|vga_driver_unit|un2_column_counter_next_cout [1] = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_0 ), + .datab(\inst|vga_driver_unit|column_counter_sig_1 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [1]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [1]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .lut_mask = "6688"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un2_column_counter_next_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N2 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_1_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_1 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [1] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un2_column_counter_next_combout [1]), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_1 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_1_ .lut_mask = "afaf"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N6 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_3_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [3] = \inst|vga_driver_unit|column_counter_sig_3 $ (\inst|vga_driver_unit|column_counter_sig_2 & \inst|vga_driver_unit|un2_column_counter_next_cout [1]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [3] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [1] # !\inst|vga_driver_unit|column_counter_sig_2 # !\inst|vga_driver_unit|column_counter_sig_3 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 # !\inst|vga_driver_unit|column_counter_sig_2 # !\inst|vga_driver_unit|column_counter_sig_3 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_3 ), + .datab(\inst|vga_driver_unit|column_counter_sig_2 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [1]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [3]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [3]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .lut_mask = "6a7f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_3_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N2 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_3_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_3 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [3] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [3]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_3 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_3_ .lut_mask = "ff55"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N5 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_0_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_cout [0] = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 = CARRY(\inst|vga_driver_unit|column_counter_sig_0 & \inst|vga_driver_unit|column_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_0 ), + .datab(\inst|vga_driver_unit|column_counter_sig_1 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_0_~COMBOUT ), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [0]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .lut_mask = "ff88"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .output_mode = "none"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un2_column_counter_next_0_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N6 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_2_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [2] = \inst|vga_driver_unit|column_counter_sig_2 $ (\inst|vga_driver_unit|un2_column_counter_next_cout [0]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [2] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [0] # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_2 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_2 ), + .datab(\inst|vga_driver_unit|column_counter_sig_3 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [0]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [2]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [2]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .lut_mask = "5a7f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_2_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N4 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_2_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_2 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [2] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [2]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_2 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_2_ .lut_mask = "ff0f"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N7 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_4_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [4] = \inst|vga_driver_unit|column_counter_sig_4 $ !\inst|vga_driver_unit|un2_column_counter_next_cout [2] +// \inst|vga_driver_unit|un2_column_counter_next_cout [4] = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [2]) +// \inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_5 ), + .datab(\inst|vga_driver_unit|column_counter_sig_4 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [2]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [4]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [4]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .lut_mask = "c308"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_4_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N8 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_4_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_4 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [4] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [4]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_4 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_4_ .lut_mask = "ff0f"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N7 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_5_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [5] = \inst|vga_driver_unit|column_counter_sig_5 $ (\inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [3]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [5] = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout [3]) +// \inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 = CARRY(\inst|vga_driver_unit|column_counter_sig_5 & \inst|vga_driver_unit|column_counter_sig_4 & !\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_5 ), + .datab(\inst|vga_driver_unit|column_counter_sig_4 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [3]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [5]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [5]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .lut_mask = "a608"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_5_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N9 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_5_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_5 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [5] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datac(\inst|vga_driver_unit|un2_column_counter_next_combout [5]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_5 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_5_ .lut_mask = "f3f3"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_5_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N8 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_6_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [6] = \inst|vga_driver_unit|column_counter_sig_6 $ (\inst|vga_driver_unit|un2_column_counter_next_cout [4]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [6] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [4] # !\inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|column_counter_sig_6 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 # !\inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|column_counter_sig_6 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_6 ), + .datab(\inst|vga_driver_unit|column_counter_sig_7 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [4]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [6]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [6]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .lut_mask = "5a7f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_6_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N9 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_8_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [8] = \inst|vga_driver_unit|un2_column_counter_next_cout [6] $ !\inst|vga_driver_unit|column_counter_sig_8 + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|column_counter_sig_8 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [6]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [8]), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .lut_mask = "f00f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_8_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N2 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_8_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_8 = DFFEAS(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 & \inst|vga_driver_unit|un10_column_counter_siglto9 & \inst|vga_driver_unit|un2_column_counter_next_combout [8], +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [8]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_8 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_8_ .lut_mask = "c000"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_8_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N7 +stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 ( +// Equation(s): +// \inst|vga_driver_unit|un10_column_counter_siglt6_1 = !\inst|vga_driver_unit|column_counter_sig_1 # !\inst|vga_driver_unit|column_counter_sig_2 # !\inst|vga_driver_unit|column_counter_sig_0 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_0 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|column_counter_sig_2 ), + .datad(\inst|vga_driver_unit|column_counter_sig_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_column_counter_siglt6_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .lut_mask = "5fff"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N3 +stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 ( +// Equation(s): +// \inst|vga_driver_unit|un10_column_counter_siglt6 = \inst|vga_driver_unit|un10_column_counter_siglt6_3 # \inst|vga_driver_unit|un10_column_counter_siglt6_1 # !\inst|vga_driver_unit|column_counter_sig_3 # !\inst|vga_driver_unit|column_counter_sig_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_4 ), + .datab(\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), + .datac(\inst|vga_driver_unit|un10_column_counter_siglt6_1 ), + .datad(\inst|vga_driver_unit|column_counter_sig_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_column_counter_siglt6 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .lut_mask = "fdff"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N8 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_7_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [7] = \inst|vga_driver_unit|column_counter_sig_7 $ (\inst|vga_driver_unit|column_counter_sig_6 & \inst|vga_driver_unit|un2_column_counter_next_cout [5]) +// \inst|vga_driver_unit|un2_column_counter_next_cout [7] = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout [5] # !\inst|vga_driver_unit|column_counter_sig_6 # !\inst|vga_driver_unit|column_counter_sig_7 ) +// \inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 = CARRY(!\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 # !\inst|vga_driver_unit|column_counter_sig_6 # !\inst|vga_driver_unit|column_counter_sig_7 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_7 ), + .datab(\inst|vga_driver_unit|column_counter_sig_6 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [5]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [7]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un2_column_counter_next_cout [7]), + .cout1(\inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .lut_mask = "6a7f"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_7_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N9 +stratix_lcell \inst|vga_driver_unit|un2_column_counter_next_9_ ( +// Equation(s): +// \inst|vga_driver_unit|un2_column_counter_next_combout [9] = \inst|vga_driver_unit|column_counter_sig_9 $ (\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_driver_unit|un2_column_counter_next_cout [7]) + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|column_counter_sig_8 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|column_counter_sig_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un2_column_counter_next_cout [7]), + .cin1(\inst|vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un2_column_counter_next_combout [9]), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .lut_mask = "f30c"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un2_column_counter_next_9_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N0 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_9_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_9 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [9] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [9]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_9 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_9_ .lut_mask = "ff55"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_9_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N1 +stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 ( +// Equation(s): +// \inst|vga_driver_unit|un10_column_counter_siglto9 = !\inst|vga_driver_unit|column_counter_sig_7 & !\inst|vga_driver_unit|column_counter_sig_8 & \inst|vga_driver_unit|un10_column_counter_siglt6 # !\inst|vga_driver_unit|column_counter_sig_9 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_7 ), + .datab(\inst|vga_driver_unit|column_counter_sig_8 ), + .datac(\inst|vga_driver_unit|un10_column_counter_siglt6 ), + .datad(\inst|vga_driver_unit|column_counter_sig_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .lut_mask = "10ff"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N4 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_7_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_7 = DFFEAS(\inst|vga_driver_unit|un10_column_counter_siglto9 & (\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 & \inst|vga_driver_unit|un2_column_counter_next_combout [7]), +// GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datab(vcc), + .datac(\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .datad(\inst|vga_driver_unit|un2_column_counter_next_combout [7]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_7 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_7_ .lut_mask = "a000"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_7_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N6 +stratix_lcell \inst|vga_driver_unit|column_counter_sig_6_ ( +// Equation(s): +// \inst|vga_driver_unit|column_counter_sig_6 = DFFEAS(\inst|vga_driver_unit|un2_column_counter_next_combout [6] # !\inst|vga_driver_unit|un10_column_counter_siglto9 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un2_column_counter_next_combout [6]), + .datac(\inst|vga_driver_unit|un10_column_counter_siglto9 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|column_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|column_counter_sig_6 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|column_counter_sig_6_ .lut_mask = "cfcf"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|column_counter_sig_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X77_Y33_N0 +stratix_lcell \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 ( +// Equation(s): +// \inst|vga_driver_unit|un10_column_counter_siglt6_3 = !\inst|vga_driver_unit|column_counter_sig_5 # !\inst|vga_driver_unit|column_counter_sig_6 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|column_counter_sig_6 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|column_counter_sig_5 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .lut_mask = "33ff"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N1 +stratix_lcell \inst|vga_control_unit|b_next_i_o3_0_cZ ( +// Equation(s): +// \inst|vga_control_unit|b_next_i_o3_0 = \inst|vga_driver_unit|column_counter_sig_7 # \inst|vga_driver_unit|column_counter_sig_6 & \inst|vga_driver_unit|column_counter_sig_4 & \inst|vga_driver_unit|column_counter_sig_5 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_6 ), + .datab(\inst|vga_driver_unit|column_counter_sig_7 ), + .datac(\inst|vga_driver_unit|column_counter_sig_4 ), + .datad(\inst|vga_driver_unit|column_counter_sig_5 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|b_next_i_o3_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .lut_mask = "eccc"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|b_next_i_o3_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N3 +stratix_lcell \inst|vga_control_unit|g_next_i_o3_cZ ( +// Equation(s): +// \inst|vga_control_unit|g_next_i_o3 = \inst|vga_driver_unit|column_counter_sig_4 # \inst|vga_driver_unit|column_counter_sig_3 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|column_counter_sig_4 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|column_counter_sig_3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|g_next_i_o3 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|g_next_i_o3_cZ .lut_mask = "ffcc"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|g_next_i_o3_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N2 +stratix_lcell \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ ( +// Equation(s): +// \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|hsync_state_5 & !\inst|vga_driver_unit|hsync_state_4 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|hsync_state_5 ), + .datac(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datad(\inst|vga_driver_unit|hsync_state_4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .lut_mask = "f0f3"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N0 +stratix_lcell \inst|vga_driver_unit|v_enable_sig_Z ( +// Equation(s): +// \inst|vga_driver_unit|v_enable_sig = DFFEAS(\inst|vga_driver_unit|hsync_state_3 # \inst|vga_driver_unit|hsync_state_1 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|hsync_state_3 ), + .datad(\inst|vga_driver_unit|hsync_state_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|v_enable_sig ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|v_enable_sig_Z .lut_mask = "fff0"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .operation_mode = "normal"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|v_enable_sig_Z .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X34_Y34_N6 +stratix_lcell \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ ( +// Equation(s): +// \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 = \inst|vga_driver_unit|un6_dly_counter_0_x # !\inst|vga_driver_unit|vsync_state_4 & !\inst|vga_driver_unit|vsync_state_5 + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .datac(\inst|vga_driver_unit|vsync_state_4 ), + .datad(\inst|vga_driver_unit|vsync_state_5 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .lut_mask = "cccf"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X52_Y35_N2 +stratix_lcell \inst|vga_driver_unit|h_enable_sig_Z ( +// Equation(s): +// \inst|vga_driver_unit|h_enable_sig = DFFEAS(\inst|vga_driver_unit|vsync_state_3 # \inst|vga_driver_unit|vsync_state_1 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , \inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 , , , +// \inst|vga_driver_unit|un6_dly_counter_0_x , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|vsync_state_3 ), + .datad(\inst|vga_driver_unit|vsync_state_1 ), + .aclr(gnd), + .aload(gnd), + .sclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .sload(gnd), + .ena(\inst|vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|h_enable_sig ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|h_enable_sig_Z .lut_mask = "fff0"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .operation_mode = "normal"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|h_enable_sig_Z .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X56_Y45_N5 +stratix_lcell \inst|vga_control_unit|r_next_i_o7_cZ ( +// Equation(s): +// \inst|vga_control_unit|r_next_i_o7 = \inst|vga_driver_unit|column_counter_sig_9 # !\inst|vga_driver_unit|h_enable_sig # !\inst|vga_driver_unit|v_enable_sig + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|v_enable_sig ), + .datac(\inst|vga_driver_unit|h_enable_sig ), + .datad(\inst|vga_driver_unit|column_counter_sig_9 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|r_next_i_o7 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|r_next_i_o7_cZ .lut_mask = "ff3f"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|r_next_i_o7_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N3 +stratix_lcell \inst|vga_control_unit|N_4_i_0_g0_1_cZ ( +// Equation(s): +// \inst|vga_control_unit|N_4_i_0_g0_1 = !\inst|vga_control_unit|r_next_i_o7 & (\inst|vga_driver_unit|column_counter_sig_8 # \inst|vga_control_unit|g_next_i_o3 & \inst|vga_driver_unit|column_counter_sig_7 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_8 ), + .datab(\inst|vga_control_unit|g_next_i_o3 ), + .datac(\inst|vga_control_unit|r_next_i_o7 ), + .datad(\inst|vga_driver_unit|column_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|N_4_i_0_g0_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .lut_mask = "0e0a"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|N_4_i_0_g0_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N0 +stratix_lcell \inst|vga_control_unit|r_Z ( +// Equation(s): +// \inst|vga_control_unit|r = DFFEAS(\inst|vga_control_unit|N_4_i_0_g0_1 & (\inst|vga_driver_unit|column_counter_sig_8 & (!\inst|vga_control_unit|b_next_i_o3_0 ) # !\inst|vga_driver_unit|column_counter_sig_8 & +// !\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), GLOBAL(\inst1|altpll_component|_clk0 ), !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), + .datab(\inst|vga_control_unit|b_next_i_o3_0 ), + .datac(\inst|vga_control_unit|N_4_i_0_g0_1 ), + .datad(\inst|vga_driver_unit|column_counter_sig_8 ), + .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_control_unit|r ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|r_Z .lut_mask = "3050"; +defparam \inst|vga_control_unit|r_Z .operation_mode = "normal"; +defparam \inst|vga_control_unit|r_Z .output_mode = "reg_only"; +defparam \inst|vga_control_unit|r_Z .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|r_Z .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|r_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X76_Y33_N5 +stratix_lcell \inst|vga_control_unit|N_23_i_0_g0_a_cZ ( +// Equation(s): +// \inst|vga_control_unit|N_23_i_0_g0_a = \inst|vga_driver_unit|column_counter_sig_5 & (\inst|vga_driver_unit|column_counter_sig_6 & (!\inst|vga_control_unit|g_next_i_o3 ) # !\inst|vga_driver_unit|column_counter_sig_6 & +// (\inst|vga_control_unit|g_next_i_o3 # !\inst|vga_driver_unit|un10_column_counter_siglt6_1 )) # !\inst|vga_driver_unit|column_counter_sig_5 & (\inst|vga_driver_unit|column_counter_sig_6 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|un10_column_counter_siglt6_1 ), + .datab(\inst|vga_driver_unit|column_counter_sig_5 ), + .datac(\inst|vga_driver_unit|column_counter_sig_6 ), + .datad(\inst|vga_control_unit|g_next_i_o3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|N_23_i_0_g0_a ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .lut_mask = "3cf4"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|N_23_i_0_g0_a_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X76_Y33_N2 +stratix_lcell \inst|vga_control_unit|g_Z ( +// Equation(s): +// \inst|vga_control_unit|g = DFFEAS(!\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_control_unit|r_next_i_o7 & \inst|vga_control_unit|N_23_i_0_g0_a & \inst|vga_driver_unit|column_counter_sig_7 , GLOBAL(\inst1|altpll_component|_clk0 ), +// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|column_counter_sig_8 ), + .datab(\inst|vga_control_unit|r_next_i_o7 ), + .datac(\inst|vga_control_unit|N_23_i_0_g0_a ), + .datad(\inst|vga_driver_unit|column_counter_sig_7 ), + .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_control_unit|g ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|g_Z .lut_mask = "1000"; +defparam \inst|vga_control_unit|g_Z .operation_mode = "normal"; +defparam \inst|vga_control_unit|g_Z .output_mode = "reg_only"; +defparam \inst|vga_control_unit|g_Z .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|g_Z .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|g_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X76_Y33_N4 +stratix_lcell \inst|vga_control_unit|N_6_i_0_g0_0_cZ ( +// Equation(s): +// \inst|vga_control_unit|N_6_i_0_g0_0 = !\inst|vga_control_unit|r_next_i_o7 & (\inst|vga_driver_unit|column_counter_sig_8 # \inst|vga_driver_unit|column_counter_sig_7 # !\inst|vga_driver_unit|un10_column_counter_siglt6_3 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|column_counter_sig_8 ), + .datab(\inst|vga_control_unit|r_next_i_o7 ), + .datac(\inst|vga_driver_unit|un10_column_counter_siglt6_3 ), + .datad(\inst|vga_driver_unit|column_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|N_6_i_0_g0_0 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .lut_mask = "3323"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|N_6_i_0_g0_0_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y33_N1 +stratix_lcell \inst|vga_control_unit|b_next_i_a7_1_cZ ( +// Equation(s): +// \inst|vga_control_unit|b_next_i_a7_1 = !\inst|vga_control_unit|g_next_i_o3 & !\inst|vga_driver_unit|column_counter_sig_2 & !\inst|vga_driver_unit|column_counter_sig_8 & !\inst|vga_driver_unit|column_counter_sig_7 + + .clk(gnd), + .dataa(\inst|vga_control_unit|g_next_i_o3 ), + .datab(\inst|vga_driver_unit|column_counter_sig_2 ), + .datac(\inst|vga_driver_unit|column_counter_sig_8 ), + .datad(\inst|vga_driver_unit|column_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_control_unit|b_next_i_a7_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .lut_mask = "0001"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .operation_mode = "normal"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|b_next_i_a7_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X78_Y32_N4 +stratix_lcell \inst|vga_control_unit|b_Z ( +// Equation(s): +// \inst|vga_control_unit|b = DFFEAS(\inst|vga_control_unit|N_6_i_0_g0_0 & !\inst|vga_control_unit|b_next_i_a7_1 & (!\inst|vga_control_unit|b_next_i_o3_0 # !\inst|vga_driver_unit|column_counter_sig_8 ), GLOBAL(\inst1|altpll_component|_clk0 ), +// !GLOBAL(\inst|vga_driver_unit|un6_dly_counter_0_x ), , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|column_counter_sig_8 ), + .datab(\inst|vga_control_unit|b_next_i_o3_0 ), + .datac(\inst|vga_control_unit|N_6_i_0_g0_0 ), + .datad(\inst|vga_control_unit|b_next_i_a7_1 ), + .aclr(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_control_unit|b ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_control_unit|b_Z .lut_mask = "0070"; +defparam \inst|vga_control_unit|b_Z .operation_mode = "normal"; +defparam \inst|vga_control_unit|b_Z .output_mode = "reg_only"; +defparam \inst|vga_control_unit|b_Z .register_cascade_mode = "off"; +defparam \inst|vga_control_unit|b_Z .sum_lutc_input = "datac"; +defparam \inst|vga_control_unit|b_Z .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N5 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_1_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [1] = \inst|vga_driver_unit|d_set_hsync_counter $ \inst|vga_driver_unit|line_counter_sig_0 +// \inst|vga_driver_unit|un1_line_counter_sig_cout [1] = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|d_set_hsync_counter ), + .datab(\inst|vga_driver_unit|line_counter_sig_0 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [1]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [1]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .lut_mask = "6688"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X36_Y33_N6 +stratix_lcell \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 = \reset~combout & !\inst|vga_driver_unit|vsync_state_1 & \inst|dly_counter [0] & \inst|dly_counter [1] + + .clk(gnd), + .dataa(\reset~combout ), + .datab(\inst|vga_driver_unit|vsync_state_1 ), + .datac(\inst|dly_counter [0]), + .datad(\inst|dly_counter [1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .lut_mask = "2000"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N6 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_0_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_0 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [1] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un1_line_counter_sig_combout [1]), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_0 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_0_ .lut_mask = "afaf"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_0_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N6 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_3_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [3] = \inst|vga_driver_unit|line_counter_sig_2 $ (\inst|vga_driver_unit|line_counter_sig_1 & \inst|vga_driver_unit|un1_line_counter_sig_cout [1]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [3] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [1] # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_1 ), + .datab(\inst|vga_driver_unit|line_counter_sig_2 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [1]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [3]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [3]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .lut_mask = "6c7f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_3_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y31_N2 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_2_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_2 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [3] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un1_line_counter_sig_combout [3]), + .datac(vcc), + .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_2 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_2_ .lut_mask = "ccff"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_2_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N0 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_a_1_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_a_cout [1] = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 ) +// \inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 = CARRY(\inst|vga_driver_unit|d_set_hsync_counter & \inst|vga_driver_unit|line_counter_sig_0 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|d_set_hsync_counter ), + .datab(\inst|vga_driver_unit|line_counter_sig_0 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT ), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .lut_mask = "ff88"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .output_mode = "none"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_a_1_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N1 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_2_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [2] = \inst|vga_driver_unit|line_counter_sig_1 $ (\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [2] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1] # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_1 ), + .datab(\inst|vga_driver_unit|line_counter_sig_2 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_a_cout [1]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [2]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [2]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .lut_mask = "5a7f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_2_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N7 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_1_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_1 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [2] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un1_line_counter_sig_combout [2]), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_1 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_1_ .lut_mask = "cfcf"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_1_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N2 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_4_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [4] = \inst|vga_driver_unit|line_counter_sig_3 $ !\inst|vga_driver_unit|un1_line_counter_sig_cout [2] +// \inst|vga_driver_unit|un1_line_counter_sig_cout [4] = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [2]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_4 ), + .datab(\inst|vga_driver_unit|line_counter_sig_3 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [2]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [4]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [4]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .lut_mask = "c308"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_4_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N5 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_3_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_3 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [4] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [4]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_3 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_3_ .lut_mask = "ff0f"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_3_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N7 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_5_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [5] = \inst|vga_driver_unit|line_counter_sig_4 $ (\inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [3]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [5] = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout [3]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 = CARRY(\inst|vga_driver_unit|line_counter_sig_4 & \inst|vga_driver_unit|line_counter_sig_3 & !\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_4 ), + .datab(\inst|vga_driver_unit|line_counter_sig_3 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [3]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [5]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [5]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .lut_mask = "a608"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_5_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N4 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_4_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_4 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [5] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un1_line_counter_sig_combout [5]), + .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_4 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_4_ .lut_mask = "f0ff"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_4_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N3 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_6_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [6] = \inst|vga_driver_unit|line_counter_sig_5 $ (\inst|vga_driver_unit|un1_line_counter_sig_cout [4]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [6] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [4] # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_5 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 # !\inst|vga_driver_unit|line_counter_sig_6 # !\inst|vga_driver_unit|line_counter_sig_5 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_5 ), + .datab(\inst|vga_driver_unit|line_counter_sig_6 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [4]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [6]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [6]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .lut_mask = "5a7f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_6_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N8 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_5_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_5 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [6] & \inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 & \inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), +// VCC, , , , , , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(\inst|vga_driver_unit|un1_line_counter_sig_combout [6]), + .datab(\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_5 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_5_ .lut_mask = "8080"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_5_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N8 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_7_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [7] = \inst|vga_driver_unit|line_counter_sig_6 $ (\inst|vga_driver_unit|line_counter_sig_5 & \inst|vga_driver_unit|un1_line_counter_sig_cout [5]) +// \inst|vga_driver_unit|un1_line_counter_sig_cout [7] = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout [5] # !\inst|vga_driver_unit|line_counter_sig_5 # !\inst|vga_driver_unit|line_counter_sig_6 ) +// \inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 = CARRY(!\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 # !\inst|vga_driver_unit|line_counter_sig_5 # !\inst|vga_driver_unit|line_counter_sig_6 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_6 ), + .datab(\inst|vga_driver_unit|line_counter_sig_5 ), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [5]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [7]), + .regout(), + .cout(), + .cout0(\inst|vga_driver_unit|un1_line_counter_sig_cout [7]), + .cout1(\inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 )); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .lut_mask = "6a7f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .operation_mode = "arithmetic"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_7_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X55_Y31_N4 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_6_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_6 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [7] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un1_line_counter_sig_combout [7]), + .datac(vcc), + .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_6 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_6_ .lut_mask = "ccff"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_6_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N1 +stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 ( +// Equation(s): +// \inst|vga_driver_unit|un10_line_counter_siglt4_2 = !\inst|vga_driver_unit|line_counter_sig_3 # !\inst|vga_driver_unit|line_counter_sig_0 # !\inst|vga_driver_unit|line_counter_sig_4 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_4 ), + .datab(\inst|vga_driver_unit|line_counter_sig_0 ), + .datac(\inst|vga_driver_unit|line_counter_sig_3 ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_line_counter_siglt4_2 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .lut_mask = "7f7f"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N3 +stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 ( +// Equation(s): +// \inst|vga_driver_unit|un10_line_counter_siglto5 = !\inst|vga_driver_unit|line_counter_sig_5 & (\inst|vga_driver_unit|un10_line_counter_siglt4_2 # !\inst|vga_driver_unit|line_counter_sig_2 # !\inst|vga_driver_unit|line_counter_sig_1 ) + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_1 ), + .datab(\inst|vga_driver_unit|un10_line_counter_siglt4_2 ), + .datac(\inst|vga_driver_unit|line_counter_sig_5 ), + .datad(\inst|vga_driver_unit|line_counter_sig_2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_line_counter_siglto5 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .lut_mask = "0d0f"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N2 +stratix_lcell \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 ( +// Equation(s): +// \inst|vga_driver_unit|un10_line_counter_siglto8 = \inst|vga_driver_unit|un10_line_counter_siglto5 # !\inst|vga_driver_unit|line_counter_sig_7 # !\inst|vga_driver_unit|line_counter_sig_8 # !\inst|vga_driver_unit|line_counter_sig_6 + + .clk(gnd), + .dataa(\inst|vga_driver_unit|line_counter_sig_6 ), + .datab(\inst|vga_driver_unit|line_counter_sig_8 ), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto5 ), + .datad(\inst|vga_driver_unit|line_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .lut_mask = "f7ff"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .operation_mode = "normal"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8 .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N4 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_8_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [8] = \inst|vga_driver_unit|un1_line_counter_sig_cout [6] $ !\inst|vga_driver_unit|line_counter_sig_7 + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\inst|vga_driver_unit|line_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [6]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [8]), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .lut_mask = "f00f"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_8_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y32_N9 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_7_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_7 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [8] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(vcc), + .datac(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .datad(\inst|vga_driver_unit|un1_line_counter_sig_combout [8]), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_7 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_7_ .lut_mask = "ff0f"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_7_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N9 +stratix_lcell \inst|vga_driver_unit|un1_line_counter_sig_9_ ( +// Equation(s): +// \inst|vga_driver_unit|un1_line_counter_sig_combout [9] = \inst|vga_driver_unit|line_counter_sig_8 $ (!\inst|vga_driver_unit|un1_line_counter_sig_cout [7] & \inst|vga_driver_unit|line_counter_sig_7 ) + + .clk(gnd), + .dataa(vcc), + .datab(\inst|vga_driver_unit|line_counter_sig_8 ), + .datac(vcc), + .datad(\inst|vga_driver_unit|line_counter_sig_7 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(\inst|vga_driver_unit|un1_line_counter_sig_cout [7]), + .cin1(\inst|vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\inst|vga_driver_unit|un1_line_counter_sig_combout [9]), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .cin0_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .cin1_used = "true"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .lut_mask = "c3cc"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .output_mode = "comb_only"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .sum_lutc_input = "cin"; +defparam \inst|vga_driver_unit|un1_line_counter_sig_9_ .synch_mode = "off"; +// synopsys translate_on + +// atom is at LC_X54_Y31_N0 +stratix_lcell \inst|vga_driver_unit|line_counter_sig_8_ ( +// Equation(s): +// \inst|vga_driver_unit|line_counter_sig_8 = DFFEAS(\inst|vga_driver_unit|un1_line_counter_sig_combout [9] # !\inst|vga_driver_unit|un10_line_counter_siglto8 , GLOBAL(\inst1|altpll_component|_clk0 ), VCC, , , , , +// !\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 , ) + + .clk(\inst1|altpll_component|_clk0 ), + .dataa(vcc), + .datab(\inst|vga_driver_unit|un1_line_counter_sig_combout [9]), + .datac(vcc), + .datad(\inst|vga_driver_unit|un10_line_counter_siglto8 ), + .aclr(gnd), + .aload(gnd), + .sclr(!\inst|vga_driver_unit|line_counter_next_0_sqmuxa_1_1 ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\inst|vga_driver_unit|line_counter_sig_8 ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \inst|vga_driver_unit|line_counter_sig_8_ .lut_mask = "ccff"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .operation_mode = "normal"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .output_mode = "reg_only"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .register_cascade_mode = "off"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .sum_lutc_input = "datac"; +defparam \inst|vga_driver_unit|line_counter_sig_8_ .synch_mode = "on"; +// synopsys translate_on + +// atom is at LC_X41_Y19_N2 +stratix_lcell \~STRATIX_FITTER_CREATED_GND~I ( +// Equation(s): +// \~STRATIX_FITTER_CREATED_GND~I_combout = GND + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\~STRATIX_FITTER_CREATED_GND~I_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \~STRATIX_FITTER_CREATED_GND~I .lut_mask = "0000"; +defparam \~STRATIX_FITTER_CREATED_GND~I .operation_mode = "normal"; +defparam \~STRATIX_FITTER_CREATED_GND~I .output_mode = "comb_only"; +defparam \~STRATIX_FITTER_CREATED_GND~I .register_cascade_mode = "off"; +defparam \~STRATIX_FITTER_CREATED_GND~I .sum_lutc_input = "datac"; +defparam \~STRATIX_FITTER_CREATED_GND~I .synch_mode = "off"; +// synopsys translate_on + +// atom is at PIN_L7 +stratix_io \inst|d_hsync_out~I ( + .datain(\inst|vga_driver_unit|h_sync ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_out~I .ddio_mode = "none"; +defparam \inst|d_hsync_out~I .input_async_reset = "none"; +defparam \inst|d_hsync_out~I .input_power_up = "low"; +defparam \inst|d_hsync_out~I .input_register_mode = "none"; +defparam \inst|d_hsync_out~I .input_sync_reset = "none"; +defparam \inst|d_hsync_out~I .oe_async_reset = "none"; +defparam \inst|d_hsync_out~I .oe_power_up = "low"; +defparam \inst|d_hsync_out~I .oe_register_mode = "none"; +defparam \inst|d_hsync_out~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_out~I .operation_mode = "output"; +defparam \inst|d_hsync_out~I .output_async_reset = "none"; +defparam \inst|d_hsync_out~I .output_power_up = "low"; +defparam \inst|d_hsync_out~I .output_register_mode = "none"; +defparam \inst|d_hsync_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L5 +stratix_io \inst|d_vsync_out~I ( + .datain(\inst|vga_driver_unit|v_sync ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_out~I .ddio_mode = "none"; +defparam \inst|d_vsync_out~I .input_async_reset = "none"; +defparam \inst|d_vsync_out~I .input_power_up = "low"; +defparam \inst|d_vsync_out~I .input_register_mode = "none"; +defparam \inst|d_vsync_out~I .input_sync_reset = "none"; +defparam \inst|d_vsync_out~I .oe_async_reset = "none"; +defparam \inst|d_vsync_out~I .oe_power_up = "low"; +defparam \inst|d_vsync_out~I .oe_register_mode = "none"; +defparam \inst|d_vsync_out~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_out~I .operation_mode = "output"; +defparam \inst|d_vsync_out~I .output_async_reset = "none"; +defparam \inst|d_vsync_out~I .output_power_up = "low"; +defparam \inst|d_vsync_out~I .output_register_mode = "none"; +defparam \inst|d_vsync_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_Y23 +stratix_io \inst|d_set_column_counter_out~I ( + .datain(\inst|vga_driver_unit|hsync_state_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_set_column_counter), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_set_column_counter_out~I .ddio_mode = "none"; +defparam \inst|d_set_column_counter_out~I .input_async_reset = "none"; +defparam \inst|d_set_column_counter_out~I .input_power_up = "low"; +defparam \inst|d_set_column_counter_out~I .input_register_mode = "none"; +defparam \inst|d_set_column_counter_out~I .input_sync_reset = "none"; +defparam \inst|d_set_column_counter_out~I .oe_async_reset = "none"; +defparam \inst|d_set_column_counter_out~I .oe_power_up = "low"; +defparam \inst|d_set_column_counter_out~I .oe_register_mode = "none"; +defparam \inst|d_set_column_counter_out~I .oe_sync_reset = "none"; +defparam \inst|d_set_column_counter_out~I .operation_mode = "output"; +defparam \inst|d_set_column_counter_out~I .output_async_reset = "none"; +defparam \inst|d_set_column_counter_out~I .output_power_up = "low"; +defparam \inst|d_set_column_counter_out~I .output_register_mode = "none"; +defparam \inst|d_set_column_counter_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F21 +stratix_io \inst|d_set_line_counter_out~I ( + .datain(\inst|vga_driver_unit|vsync_state_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_set_line_counter), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_set_line_counter_out~I .ddio_mode = "none"; +defparam \inst|d_set_line_counter_out~I .input_async_reset = "none"; +defparam \inst|d_set_line_counter_out~I .input_power_up = "low"; +defparam \inst|d_set_line_counter_out~I .input_register_mode = "none"; +defparam \inst|d_set_line_counter_out~I .input_sync_reset = "none"; +defparam \inst|d_set_line_counter_out~I .oe_async_reset = "none"; +defparam \inst|d_set_line_counter_out~I .oe_power_up = "low"; +defparam \inst|d_set_line_counter_out~I .oe_register_mode = "none"; +defparam \inst|d_set_line_counter_out~I .oe_sync_reset = "none"; +defparam \inst|d_set_line_counter_out~I .operation_mode = "output"; +defparam \inst|d_set_line_counter_out~I .output_async_reset = "none"; +defparam \inst|d_set_line_counter_out~I .output_power_up = "low"; +defparam \inst|d_set_line_counter_out~I .output_register_mode = "none"; +defparam \inst|d_set_line_counter_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F26 +stratix_io \inst|d_set_hsync_counter_out~I ( + .datain(\inst|vga_driver_unit|d_set_hsync_counter ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_set_hsync_counter), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_set_hsync_counter_out~I .ddio_mode = "none"; +defparam \inst|d_set_hsync_counter_out~I .input_async_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .input_power_up = "low"; +defparam \inst|d_set_hsync_counter_out~I .input_register_mode = "none"; +defparam \inst|d_set_hsync_counter_out~I .input_sync_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .oe_async_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .oe_power_up = "low"; +defparam \inst|d_set_hsync_counter_out~I .oe_register_mode = "none"; +defparam \inst|d_set_hsync_counter_out~I .oe_sync_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .operation_mode = "output"; +defparam \inst|d_set_hsync_counter_out~I .output_async_reset = "none"; +defparam \inst|d_set_hsync_counter_out~I .output_power_up = "low"; +defparam \inst|d_set_hsync_counter_out~I .output_register_mode = "none"; +defparam \inst|d_set_hsync_counter_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F24 +stratix_io \inst|d_set_vsync_counter_out~I ( + .datain(\inst|vga_driver_unit|d_set_vsync_counter ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_set_vsync_counter), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_set_vsync_counter_out~I .ddio_mode = "none"; +defparam \inst|d_set_vsync_counter_out~I .input_async_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .input_power_up = "low"; +defparam \inst|d_set_vsync_counter_out~I .input_register_mode = "none"; +defparam \inst|d_set_vsync_counter_out~I .input_sync_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .oe_async_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .oe_power_up = "low"; +defparam \inst|d_set_vsync_counter_out~I .oe_register_mode = "none"; +defparam \inst|d_set_vsync_counter_out~I .oe_sync_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .operation_mode = "output"; +defparam \inst|d_set_vsync_counter_out~I .output_async_reset = "none"; +defparam \inst|d_set_vsync_counter_out~I .output_power_up = "low"; +defparam \inst|d_set_vsync_counter_out~I .output_register_mode = "none"; +defparam \inst|d_set_vsync_counter_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L3 +stratix_io \inst|d_r_out~I ( + .datain(\inst|vga_control_unit|r ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_r), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_r_out~I .ddio_mode = "none"; +defparam \inst|d_r_out~I .input_async_reset = "none"; +defparam \inst|d_r_out~I .input_power_up = "low"; +defparam \inst|d_r_out~I .input_register_mode = "none"; +defparam \inst|d_r_out~I .input_sync_reset = "none"; +defparam \inst|d_r_out~I .oe_async_reset = "none"; +defparam \inst|d_r_out~I .oe_power_up = "low"; +defparam \inst|d_r_out~I .oe_register_mode = "none"; +defparam \inst|d_r_out~I .oe_sync_reset = "none"; +defparam \inst|d_r_out~I .operation_mode = "output"; +defparam \inst|d_r_out~I .output_async_reset = "none"; +defparam \inst|d_r_out~I .output_power_up = "low"; +defparam \inst|d_r_out~I .output_register_mode = "none"; +defparam \inst|d_r_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K24 +stratix_io \inst|d_g_out~I ( + .datain(\inst|vga_control_unit|g ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_g), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_g_out~I .ddio_mode = "none"; +defparam \inst|d_g_out~I .input_async_reset = "none"; +defparam \inst|d_g_out~I .input_power_up = "low"; +defparam \inst|d_g_out~I .input_register_mode = "none"; +defparam \inst|d_g_out~I .input_sync_reset = "none"; +defparam \inst|d_g_out~I .oe_async_reset = "none"; +defparam \inst|d_g_out~I .oe_power_up = "low"; +defparam \inst|d_g_out~I .oe_register_mode = "none"; +defparam \inst|d_g_out~I .oe_sync_reset = "none"; +defparam \inst|d_g_out~I .operation_mode = "output"; +defparam \inst|d_g_out~I .output_async_reset = "none"; +defparam \inst|d_g_out~I .output_power_up = "low"; +defparam \inst|d_g_out~I .output_register_mode = "none"; +defparam \inst|d_g_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K20 +stratix_io \inst|d_b_out~I ( + .datain(\inst|vga_control_unit|b ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_b), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_b_out~I .ddio_mode = "none"; +defparam \inst|d_b_out~I .input_async_reset = "none"; +defparam \inst|d_b_out~I .input_power_up = "low"; +defparam \inst|d_b_out~I .input_register_mode = "none"; +defparam \inst|d_b_out~I .input_sync_reset = "none"; +defparam \inst|d_b_out~I .oe_async_reset = "none"; +defparam \inst|d_b_out~I .oe_power_up = "low"; +defparam \inst|d_b_out~I .oe_register_mode = "none"; +defparam \inst|d_b_out~I .oe_sync_reset = "none"; +defparam \inst|d_b_out~I .operation_mode = "output"; +defparam \inst|d_b_out~I .output_async_reset = "none"; +defparam \inst|d_b_out~I .output_power_up = "low"; +defparam \inst|d_b_out~I .output_register_mode = "none"; +defparam \inst|d_b_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_J21 +stratix_io \inst|d_h_enable_out~I ( + .datain(\inst|vga_driver_unit|h_enable_sig ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_h_enable), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_h_enable_out~I .ddio_mode = "none"; +defparam \inst|d_h_enable_out~I .input_async_reset = "none"; +defparam \inst|d_h_enable_out~I .input_power_up = "low"; +defparam \inst|d_h_enable_out~I .input_register_mode = "none"; +defparam \inst|d_h_enable_out~I .input_sync_reset = "none"; +defparam \inst|d_h_enable_out~I .oe_async_reset = "none"; +defparam \inst|d_h_enable_out~I .oe_power_up = "low"; +defparam \inst|d_h_enable_out~I .oe_register_mode = "none"; +defparam \inst|d_h_enable_out~I .oe_sync_reset = "none"; +defparam \inst|d_h_enable_out~I .operation_mode = "output"; +defparam \inst|d_h_enable_out~I .output_async_reset = "none"; +defparam \inst|d_h_enable_out~I .output_power_up = "low"; +defparam \inst|d_h_enable_out~I .output_register_mode = "none"; +defparam \inst|d_h_enable_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_H18 +stratix_io \inst|d_v_enable_out~I ( + .datain(\inst|vga_driver_unit|v_enable_sig ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_v_enable), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_v_enable_out~I .ddio_mode = "none"; +defparam \inst|d_v_enable_out~I .input_async_reset = "none"; +defparam \inst|d_v_enable_out~I .input_power_up = "low"; +defparam \inst|d_v_enable_out~I .input_register_mode = "none"; +defparam \inst|d_v_enable_out~I .input_sync_reset = "none"; +defparam \inst|d_v_enable_out~I .oe_async_reset = "none"; +defparam \inst|d_v_enable_out~I .oe_power_up = "low"; +defparam \inst|d_v_enable_out~I .oe_register_mode = "none"; +defparam \inst|d_v_enable_out~I .oe_sync_reset = "none"; +defparam \inst|d_v_enable_out~I .operation_mode = "output"; +defparam \inst|d_v_enable_out~I .output_async_reset = "none"; +defparam \inst|d_v_enable_out~I .output_power_up = "low"; +defparam \inst|d_v_enable_out~I .output_register_mode = "none"; +defparam \inst|d_v_enable_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K3 +stratix_io \inst|d_state_clk_out~I ( + .datain(\inst1|altpll_component|_clk0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_state_clk), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_state_clk_out~I .ddio_mode = "none"; +defparam \inst|d_state_clk_out~I .input_async_reset = "none"; +defparam \inst|d_state_clk_out~I .input_power_up = "low"; +defparam \inst|d_state_clk_out~I .input_register_mode = "none"; +defparam \inst|d_state_clk_out~I .input_sync_reset = "none"; +defparam \inst|d_state_clk_out~I .oe_async_reset = "none"; +defparam \inst|d_state_clk_out~I .oe_power_up = "low"; +defparam \inst|d_state_clk_out~I .oe_register_mode = "none"; +defparam \inst|d_state_clk_out~I .oe_sync_reset = "none"; +defparam \inst|d_state_clk_out~I .operation_mode = "output"; +defparam \inst|d_state_clk_out~I .output_async_reset = "none"; +defparam \inst|d_state_clk_out~I .output_power_up = "low"; +defparam \inst|d_state_clk_out~I .output_register_mode = "none"; +defparam \inst|d_state_clk_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_E22 +stratix_io \inst|r0_pin_out~I ( + .datain(\inst|vga_control_unit|r ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(r0_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|r0_pin_out~I .ddio_mode = "none"; +defparam \inst|r0_pin_out~I .input_async_reset = "none"; +defparam \inst|r0_pin_out~I .input_power_up = "low"; +defparam \inst|r0_pin_out~I .input_register_mode = "none"; +defparam \inst|r0_pin_out~I .input_sync_reset = "none"; +defparam \inst|r0_pin_out~I .oe_async_reset = "none"; +defparam \inst|r0_pin_out~I .oe_power_up = "low"; +defparam \inst|r0_pin_out~I .oe_register_mode = "none"; +defparam \inst|r0_pin_out~I .oe_sync_reset = "none"; +defparam \inst|r0_pin_out~I .operation_mode = "output"; +defparam \inst|r0_pin_out~I .output_async_reset = "none"; +defparam \inst|r0_pin_out~I .output_power_up = "low"; +defparam \inst|r0_pin_out~I .output_register_mode = "none"; +defparam \inst|r0_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T4 +stratix_io \inst|r1_pin_out~I ( + .datain(\inst|vga_control_unit|r ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(r1_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|r1_pin_out~I .ddio_mode = "none"; +defparam \inst|r1_pin_out~I .input_async_reset = "none"; +defparam \inst|r1_pin_out~I .input_power_up = "low"; +defparam \inst|r1_pin_out~I .input_register_mode = "none"; +defparam \inst|r1_pin_out~I .input_sync_reset = "none"; +defparam \inst|r1_pin_out~I .oe_async_reset = "none"; +defparam \inst|r1_pin_out~I .oe_power_up = "low"; +defparam \inst|r1_pin_out~I .oe_register_mode = "none"; +defparam \inst|r1_pin_out~I .oe_sync_reset = "none"; +defparam \inst|r1_pin_out~I .operation_mode = "output"; +defparam \inst|r1_pin_out~I .output_async_reset = "none"; +defparam \inst|r1_pin_out~I .output_power_up = "low"; +defparam \inst|r1_pin_out~I .output_register_mode = "none"; +defparam \inst|r1_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T7 +stratix_io \inst|r2_pin_out~I ( + .datain(\inst|vga_control_unit|r ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(r2_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|r2_pin_out~I .ddio_mode = "none"; +defparam \inst|r2_pin_out~I .input_async_reset = "none"; +defparam \inst|r2_pin_out~I .input_power_up = "low"; +defparam \inst|r2_pin_out~I .input_register_mode = "none"; +defparam \inst|r2_pin_out~I .input_sync_reset = "none"; +defparam \inst|r2_pin_out~I .oe_async_reset = "none"; +defparam \inst|r2_pin_out~I .oe_power_up = "low"; +defparam \inst|r2_pin_out~I .oe_register_mode = "none"; +defparam \inst|r2_pin_out~I .oe_sync_reset = "none"; +defparam \inst|r2_pin_out~I .operation_mode = "output"; +defparam \inst|r2_pin_out~I .output_async_reset = "none"; +defparam \inst|r2_pin_out~I .output_power_up = "low"; +defparam \inst|r2_pin_out~I .output_register_mode = "none"; +defparam \inst|r2_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_E23 +stratix_io \inst|g0_pin_out~I ( + .datain(\inst|vga_control_unit|g ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(g0_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|g0_pin_out~I .ddio_mode = "none"; +defparam \inst|g0_pin_out~I .input_async_reset = "none"; +defparam \inst|g0_pin_out~I .input_power_up = "low"; +defparam \inst|g0_pin_out~I .input_register_mode = "none"; +defparam \inst|g0_pin_out~I .input_sync_reset = "none"; +defparam \inst|g0_pin_out~I .oe_async_reset = "none"; +defparam \inst|g0_pin_out~I .oe_power_up = "low"; +defparam \inst|g0_pin_out~I .oe_register_mode = "none"; +defparam \inst|g0_pin_out~I .oe_sync_reset = "none"; +defparam \inst|g0_pin_out~I .operation_mode = "output"; +defparam \inst|g0_pin_out~I .output_async_reset = "none"; +defparam \inst|g0_pin_out~I .output_power_up = "low"; +defparam \inst|g0_pin_out~I .output_register_mode = "none"; +defparam \inst|g0_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T5 +stratix_io \inst|g1_pin_out~I ( + .datain(\inst|vga_control_unit|g ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(g1_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|g1_pin_out~I .ddio_mode = "none"; +defparam \inst|g1_pin_out~I .input_async_reset = "none"; +defparam \inst|g1_pin_out~I .input_power_up = "low"; +defparam \inst|g1_pin_out~I .input_register_mode = "none"; +defparam \inst|g1_pin_out~I .input_sync_reset = "none"; +defparam \inst|g1_pin_out~I .oe_async_reset = "none"; +defparam \inst|g1_pin_out~I .oe_power_up = "low"; +defparam \inst|g1_pin_out~I .oe_register_mode = "none"; +defparam \inst|g1_pin_out~I .oe_sync_reset = "none"; +defparam \inst|g1_pin_out~I .operation_mode = "output"; +defparam \inst|g1_pin_out~I .output_async_reset = "none"; +defparam \inst|g1_pin_out~I .output_power_up = "low"; +defparam \inst|g1_pin_out~I .output_register_mode = "none"; +defparam \inst|g1_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T24 +stratix_io \inst|g2_pin_out~I ( + .datain(\inst|vga_control_unit|g ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(g2_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|g2_pin_out~I .ddio_mode = "none"; +defparam \inst|g2_pin_out~I .input_async_reset = "none"; +defparam \inst|g2_pin_out~I .input_power_up = "low"; +defparam \inst|g2_pin_out~I .input_register_mode = "none"; +defparam \inst|g2_pin_out~I .input_sync_reset = "none"; +defparam \inst|g2_pin_out~I .oe_async_reset = "none"; +defparam \inst|g2_pin_out~I .oe_power_up = "low"; +defparam \inst|g2_pin_out~I .oe_register_mode = "none"; +defparam \inst|g2_pin_out~I .oe_sync_reset = "none"; +defparam \inst|g2_pin_out~I .operation_mode = "output"; +defparam \inst|g2_pin_out~I .output_async_reset = "none"; +defparam \inst|g2_pin_out~I .output_power_up = "low"; +defparam \inst|g2_pin_out~I .output_register_mode = "none"; +defparam \inst|g2_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_E24 +stratix_io \inst|b0_pin_out~I ( + .datain(\inst|vga_control_unit|b ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(b0_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|b0_pin_out~I .ddio_mode = "none"; +defparam \inst|b0_pin_out~I .input_async_reset = "none"; +defparam \inst|b0_pin_out~I .input_power_up = "low"; +defparam \inst|b0_pin_out~I .input_register_mode = "none"; +defparam \inst|b0_pin_out~I .input_sync_reset = "none"; +defparam \inst|b0_pin_out~I .oe_async_reset = "none"; +defparam \inst|b0_pin_out~I .oe_power_up = "low"; +defparam \inst|b0_pin_out~I .oe_register_mode = "none"; +defparam \inst|b0_pin_out~I .oe_sync_reset = "none"; +defparam \inst|b0_pin_out~I .operation_mode = "output"; +defparam \inst|b0_pin_out~I .output_async_reset = "none"; +defparam \inst|b0_pin_out~I .output_power_up = "low"; +defparam \inst|b0_pin_out~I .output_register_mode = "none"; +defparam \inst|b0_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T6 +stratix_io \inst|b1_pin_out~I ( + .datain(\inst|vga_control_unit|b ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(b1_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|b1_pin_out~I .ddio_mode = "none"; +defparam \inst|b1_pin_out~I .input_async_reset = "none"; +defparam \inst|b1_pin_out~I .input_power_up = "low"; +defparam \inst|b1_pin_out~I .input_register_mode = "none"; +defparam \inst|b1_pin_out~I .input_sync_reset = "none"; +defparam \inst|b1_pin_out~I .oe_async_reset = "none"; +defparam \inst|b1_pin_out~I .oe_power_up = "low"; +defparam \inst|b1_pin_out~I .oe_register_mode = "none"; +defparam \inst|b1_pin_out~I .oe_sync_reset = "none"; +defparam \inst|b1_pin_out~I .operation_mode = "output"; +defparam \inst|b1_pin_out~I .output_async_reset = "none"; +defparam \inst|b1_pin_out~I .output_power_up = "low"; +defparam \inst|b1_pin_out~I .output_register_mode = "none"; +defparam \inst|b1_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F1 +stratix_io \inst|hsync_pin_out~I ( + .datain(\inst|vga_driver_unit|h_sync ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(hsync_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|hsync_pin_out~I .ddio_mode = "none"; +defparam \inst|hsync_pin_out~I .input_async_reset = "none"; +defparam \inst|hsync_pin_out~I .input_power_up = "low"; +defparam \inst|hsync_pin_out~I .input_register_mode = "none"; +defparam \inst|hsync_pin_out~I .input_sync_reset = "none"; +defparam \inst|hsync_pin_out~I .oe_async_reset = "none"; +defparam \inst|hsync_pin_out~I .oe_power_up = "low"; +defparam \inst|hsync_pin_out~I .oe_register_mode = "none"; +defparam \inst|hsync_pin_out~I .oe_sync_reset = "none"; +defparam \inst|hsync_pin_out~I .operation_mode = "output"; +defparam \inst|hsync_pin_out~I .output_async_reset = "none"; +defparam \inst|hsync_pin_out~I .output_power_up = "low"; +defparam \inst|hsync_pin_out~I .output_register_mode = "none"; +defparam \inst|hsync_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F2 +stratix_io \inst|vsync_pin_out~I ( + .datain(\inst|vga_driver_unit|v_sync ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(vsync_pin), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|vsync_pin_out~I .ddio_mode = "none"; +defparam \inst|vsync_pin_out~I .input_async_reset = "none"; +defparam \inst|vsync_pin_out~I .input_power_up = "low"; +defparam \inst|vsync_pin_out~I .input_register_mode = "none"; +defparam \inst|vsync_pin_out~I .input_sync_reset = "none"; +defparam \inst|vsync_pin_out~I .oe_async_reset = "none"; +defparam \inst|vsync_pin_out~I .oe_power_up = "low"; +defparam \inst|vsync_pin_out~I .oe_register_mode = "none"; +defparam \inst|vsync_pin_out~I .oe_sync_reset = "none"; +defparam \inst|vsync_pin_out~I .operation_mode = "output"; +defparam \inst|vsync_pin_out~I .output_async_reset = "none"; +defparam \inst|vsync_pin_out~I .output_power_up = "low"; +defparam \inst|vsync_pin_out~I .output_register_mode = "none"; +defparam \inst|vsync_pin_out~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K5 +stratix_io \inst|d_column_counter_out_9_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_9 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[9]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_9_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_9_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_9_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_9_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_9_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_9_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_9_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_9_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_9_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_9_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K19 +stratix_io \inst|d_column_counter_out_8_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_8 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_8_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_8_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_8_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_8_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_8_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_8_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_8_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_8_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_8_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K23 +stratix_io \inst|d_column_counter_out_7_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_7 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_7_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_7_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_7_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_7_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_7_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_7_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_7_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_7_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_7_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L2 +stratix_io \inst|d_column_counter_out_6_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_6_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_6_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_6_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_6_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_6_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_6_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L4 +stratix_io \inst|d_column_counter_out_5_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_5_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_5_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_5_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_5_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_5_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_5_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L6 +stratix_io \inst|d_column_counter_out_4_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_4_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_4_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_4_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_4_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_4_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_4_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L20 +stratix_io \inst|d_column_counter_out_3_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_3_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_3_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_3_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_3_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_3_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_3_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L21 +stratix_io \inst|d_column_counter_out_2_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_2_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_2_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_2_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_2_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_2_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_2_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L22 +stratix_io \inst|d_column_counter_out_1_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_1_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_1_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_1_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_1_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_1_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_1_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L23 +stratix_io \inst|d_column_counter_out_0_~I ( + .datain(\inst|vga_driver_unit|column_counter_sig_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_column_counter[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_column_counter_out_0_~I .ddio_mode = "none"; +defparam \inst|d_column_counter_out_0_~I .input_async_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .input_power_up = "low"; +defparam \inst|d_column_counter_out_0_~I .input_register_mode = "none"; +defparam \inst|d_column_counter_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .oe_power_up = "low"; +defparam \inst|d_column_counter_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_column_counter_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .operation_mode = "output"; +defparam \inst|d_column_counter_out_0_~I .output_async_reset = "none"; +defparam \inst|d_column_counter_out_0_~I .output_power_up = "low"; +defparam \inst|d_column_counter_out_0_~I .output_register_mode = "none"; +defparam \inst|d_column_counter_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G18 +stratix_io \inst|d_hsync_counter_out_9_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_9 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[9]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_9_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_9_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_9_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_9_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_9_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_9_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_9_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_9_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_9_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_9_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G22 +stratix_io \inst|d_hsync_counter_out_8_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_8 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_8_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_8_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_8_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_8_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_8_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_8_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_8_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_8_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_8_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G25 +stratix_io \inst|d_hsync_counter_out_7_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_7 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_7_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_7_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_7_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_7_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_7_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_7_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_7_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_7_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_7_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_A17 +stratix_io \inst|d_hsync_counter_out_6_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_6_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_6_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_6_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_6_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_6_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_6_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F25 +stratix_io \inst|d_hsync_counter_out_5_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_5_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_5_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_5_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_5_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_5_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_5_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_D17 +stratix_io \inst|d_hsync_counter_out_4_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_4_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_4_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_4_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_4_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_4_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_4_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AE16 +stratix_io \inst|d_hsync_counter_out_3_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_3_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_3_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_3_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_3_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_3_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_3_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G17 +stratix_io \inst|d_hsync_counter_out_2_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_2_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_2_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_2_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_2_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_2_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_2_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AA17 +stratix_io \inst|d_hsync_counter_out_1_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_1_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_1_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_1_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_1_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_1_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_1_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_H4 +stratix_io \inst|d_hsync_counter_out_0_~I ( + .datain(\inst|vga_driver_unit|hsync_counter_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_counter[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_counter_out_0_~I .ddio_mode = "none"; +defparam \inst|d_hsync_counter_out_0_~I .input_async_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .input_power_up = "low"; +defparam \inst|d_hsync_counter_out_0_~I .input_register_mode = "none"; +defparam \inst|d_hsync_counter_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .oe_power_up = "low"; +defparam \inst|d_hsync_counter_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_counter_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .operation_mode = "output"; +defparam \inst|d_hsync_counter_out_0_~I .output_async_reset = "none"; +defparam \inst|d_hsync_counter_out_0_~I .output_power_up = "low"; +defparam \inst|d_hsync_counter_out_0_~I .output_register_mode = "none"; +defparam \inst|d_hsync_counter_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_Y5 +stratix_io \inst|d_hsync_state_out_0_~I ( + .datain(\inst|vga_driver_unit|hsync_state_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_0_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_0_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_0_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_0_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_0_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_0_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F19 +stratix_io \inst|d_hsync_state_out_1_~I ( + .datain(\inst|vga_driver_unit|hsync_state_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_1_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_1_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_1_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_1_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_1_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_1_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F17 +stratix_io \inst|d_hsync_state_out_2_~I ( + .datain(\inst|vga_driver_unit|hsync_state_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_2_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_2_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_2_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_2_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_2_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_2_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_Y2 +stratix_io \inst|d_hsync_state_out_3_~I ( + .datain(\inst|vga_driver_unit|hsync_state_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_3_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_3_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_3_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_3_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_3_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_3_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F10 +stratix_io \inst|d_hsync_state_out_4_~I ( + .datain(\inst|vga_driver_unit|hsync_state_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_4_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_4_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_4_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_4_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_4_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_4_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F9 +stratix_io \inst|d_hsync_state_out_5_~I ( + .datain(\inst|vga_driver_unit|hsync_state_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_5_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_5_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_5_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_5_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_5_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_5_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F6 +stratix_io \inst|d_hsync_state_out_6_~I ( + .datain(\inst|vga_driver_unit|hsync_state_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_hsync_state[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_hsync_state_out_6_~I .ddio_mode = "none"; +defparam \inst|d_hsync_state_out_6_~I .input_async_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .input_power_up = "low"; +defparam \inst|d_hsync_state_out_6_~I .input_register_mode = "none"; +defparam \inst|d_hsync_state_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .oe_power_up = "low"; +defparam \inst|d_hsync_state_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_hsync_state_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .operation_mode = "output"; +defparam \inst|d_hsync_state_out_6_~I .output_async_reset = "none"; +defparam \inst|d_hsync_state_out_6_~I .output_power_up = "low"; +defparam \inst|d_hsync_state_out_6_~I .output_register_mode = "none"; +defparam \inst|d_hsync_state_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L25 +stratix_io \inst|d_line_counter_out_8_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_8 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_8_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_8_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_8_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_8_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_8_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_8_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_8_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_8_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_8_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_L24 +stratix_io \inst|d_line_counter_out_7_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_7 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_7_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_7_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_7_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_7_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_7_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_7_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_7_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_7_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_7_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M5 +stratix_io \inst|d_line_counter_out_6_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_6_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_6_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_6_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_6_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_6_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_6_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M6 +stratix_io \inst|d_line_counter_out_5_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_5_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_5_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_5_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_5_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_5_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_5_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M8 +stratix_io \inst|d_line_counter_out_4_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_4_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_4_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_4_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_4_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_4_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_4_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M9 +stratix_io \inst|d_line_counter_out_3_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_3_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_3_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_3_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_3_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_3_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_3_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_J22 +stratix_io \inst|d_line_counter_out_2_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_2_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_2_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_2_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_2_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_2_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_2_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K4 +stratix_io \inst|d_line_counter_out_1_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_1_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_1_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_1_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_1_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_1_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_1_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K6 +stratix_io \inst|d_line_counter_out_0_~I ( + .datain(\inst|vga_driver_unit|line_counter_sig_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_line_counter[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_line_counter_out_0_~I .ddio_mode = "none"; +defparam \inst|d_line_counter_out_0_~I .input_async_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .input_power_up = "low"; +defparam \inst|d_line_counter_out_0_~I .input_register_mode = "none"; +defparam \inst|d_line_counter_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .oe_power_up = "low"; +defparam \inst|d_line_counter_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_line_counter_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .operation_mode = "output"; +defparam \inst|d_line_counter_out_0_~I .output_async_reset = "none"; +defparam \inst|d_line_counter_out_0_~I .output_power_up = "low"; +defparam \inst|d_line_counter_out_0_~I .output_register_mode = "none"; +defparam \inst|d_line_counter_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G2 +stratix_io \inst|d_vsync_counter_out_9_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_9 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[9]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_9_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_9_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_9_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_9_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_9_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_9_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_9_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_9_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_9_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_9_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G4 +stratix_io \inst|d_vsync_counter_out_8_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_8 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_8_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_8_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_8_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_8_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_8_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_8_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_8_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_8_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_8_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G6 +stratix_io \inst|d_vsync_counter_out_7_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_7 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_7_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_7_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_7_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_7_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_7_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_7_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_7_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_7_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_7_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K21 +stratix_io \inst|d_vsync_counter_out_6_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_6_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_6_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_6_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_6_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_6_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_6_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AA14 +stratix_io \inst|d_vsync_counter_out_5_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_5_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_5_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_5_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_5_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_5_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_5_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AB12 +stratix_io \inst|d_vsync_counter_out_4_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_4_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_4_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_4_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_4_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_4_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_4_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_K7 +stratix_io \inst|d_vsync_counter_out_3_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_3_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_3_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_3_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_3_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_3_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_3_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_E12 +stratix_io \inst|d_vsync_counter_out_2_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_2_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_2_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_2_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_2_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_2_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_2_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F14 +stratix_io \inst|d_vsync_counter_out_1_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_1_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_1_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_1_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_1_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_1_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_1_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_G9 +stratix_io \inst|d_vsync_counter_out_0_~I ( + .datain(\inst|vga_driver_unit|vsync_counter_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_counter[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_counter_out_0_~I .ddio_mode = "none"; +defparam \inst|d_vsync_counter_out_0_~I .input_async_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .input_power_up = "low"; +defparam \inst|d_vsync_counter_out_0_~I .input_register_mode = "none"; +defparam \inst|d_vsync_counter_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .oe_power_up = "low"; +defparam \inst|d_vsync_counter_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_counter_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .operation_mode = "output"; +defparam \inst|d_vsync_counter_out_0_~I .output_async_reset = "none"; +defparam \inst|d_vsync_counter_out_0_~I .output_power_up = "low"; +defparam \inst|d_vsync_counter_out_0_~I .output_register_mode = "none"; +defparam \inst|d_vsync_counter_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F5 +stratix_io \inst|d_vsync_state_out_0_~I ( + .datain(\inst|vga_driver_unit|vsync_state_0 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_0_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_0_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_0_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_0_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_0_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_0_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_0_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_0_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_0_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F4 +stratix_io \inst|d_vsync_state_out_1_~I ( + .datain(\inst|vga_driver_unit|vsync_state_1 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_1_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_1_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_1_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_1_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_1_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_1_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_1_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_1_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_1_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_F3 +stratix_io \inst|d_vsync_state_out_2_~I ( + .datain(\inst|vga_driver_unit|vsync_state_2 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_2_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_2_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_2_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_2_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_2_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_2_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_2_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_2_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_2_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M19 +stratix_io \inst|d_vsync_state_out_3_~I ( + .datain(\inst|vga_driver_unit|vsync_state_3 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_3_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_3_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_3_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_3_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_3_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_3_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_3_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_3_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_3_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M18 +stratix_io \inst|d_vsync_state_out_4_~I ( + .datain(\inst|vga_driver_unit|vsync_state_4 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_4_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_4_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_4_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_4_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_4_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_4_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_4_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_4_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_4_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M7 +stratix_io \inst|d_vsync_state_out_5_~I ( + .datain(\inst|vga_driver_unit|vsync_state_5 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_5_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_5_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_5_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_5_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_5_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_5_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_5_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_5_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_5_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_M4 +stratix_io \inst|d_vsync_state_out_6_~I ( + .datain(\inst|vga_driver_unit|vsync_state_6 ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(d_vsync_state[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|d_vsync_state_out_6_~I .ddio_mode = "none"; +defparam \inst|d_vsync_state_out_6_~I .input_async_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .input_power_up = "low"; +defparam \inst|d_vsync_state_out_6_~I .input_register_mode = "none"; +defparam \inst|d_vsync_state_out_6_~I .input_sync_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .oe_async_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .oe_power_up = "low"; +defparam \inst|d_vsync_state_out_6_~I .oe_register_mode = "none"; +defparam \inst|d_vsync_state_out_6_~I .oe_sync_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .operation_mode = "output"; +defparam \inst|d_vsync_state_out_6_~I .output_async_reset = "none"; +defparam \inst|d_vsync_state_out_6_~I .output_power_up = "low"; +defparam \inst|d_vsync_state_out_6_~I .output_register_mode = "none"; +defparam \inst|d_vsync_state_out_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_T2 +stratix_io \inst|seven_seg_pin_tri_13_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[13]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_13_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_13_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_13_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_13_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_13_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_13_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_AA11 +stratix_io \inst|seven_seg_pin_out_12_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[12]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_12_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_12_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_12_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_12_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_12_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_12_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_12_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_12_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_12_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_12_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R6 +stratix_io \inst|seven_seg_pin_out_11_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[11]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_11_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_11_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_11_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_11_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_11_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_11_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_11_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_11_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_11_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_11_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R4 +stratix_io \inst|seven_seg_pin_out_10_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[10]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_10_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_10_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_10_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_10_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_10_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_10_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_10_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_10_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_10_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_10_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_N8 +stratix_io \inst|seven_seg_pin_out_9_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[9]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_9_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_9_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_9_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_9_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_9_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_9_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_9_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_9_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_9_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_9_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_N7 +stratix_io \inst|seven_seg_pin_out_8_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[8]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_8_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_8_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_8_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_8_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_8_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_8_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_8_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_8_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_8_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_8_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_Y11 +stratix_io \inst|seven_seg_pin_out_7_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[7]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_7_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_7_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_7_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_7_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_7_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_7_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_7_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_7_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_7_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_7_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R23 +stratix_io \inst|seven_seg_pin_tri_6_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[6]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_6_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_6_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_6_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_6_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_6_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_6_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R22 +stratix_io \inst|seven_seg_pin_tri_5_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[5]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_5_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_5_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_5_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_5_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_5_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_5_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R21 +stratix_io \inst|seven_seg_pin_tri_4_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[4]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_4_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_4_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_4_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_4_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_4_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_4_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R20 +stratix_io \inst|seven_seg_pin_tri_3_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[3]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_3_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_3_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_3_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_3_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_3_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_3_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R19 +stratix_io \inst|seven_seg_pin_out_2_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[2]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_2_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_2_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_2_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_2_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_2_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_2_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_2_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_2_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_2_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_2_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R9 +stratix_io \inst|seven_seg_pin_out_1_~I ( + .datain(\inst|vga_driver_unit|un6_dly_counter_0_x ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[1]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_out_1_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_out_1_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_out_1_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_out_1_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_out_1_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_out_1_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_out_1_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_out_1_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_out_1_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_out_1_~I .output_sync_reset = "none"; +// synopsys translate_on + +// atom is at PIN_R8 +stratix_io \inst|seven_seg_pin_tri_0_~I ( + .datain(!\~STRATIX_FITTER_CREATED_GND~I_combout ), + .ddiodatain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .delayctrlin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .ddioregout(), + .padio(seven_seg_pin[0]), + .dqsundelayedout()); +// synopsys translate_off +defparam \inst|seven_seg_pin_tri_0_~I .ddio_mode = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .input_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .input_power_up = "low"; +defparam \inst|seven_seg_pin_tri_0_~I .input_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .input_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .oe_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .oe_power_up = "low"; +defparam \inst|seven_seg_pin_tri_0_~I .oe_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .oe_sync_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .operation_mode = "output"; +defparam \inst|seven_seg_pin_tri_0_~I .output_async_reset = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .output_power_up = "low"; +defparam \inst|seven_seg_pin_tri_0_~I .output_register_mode = "none"; +defparam \inst|seven_seg_pin_tri_0_~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule