X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fppr%2Fdownload%2Fdb%2Fvga_pll.hier_info;fp=bsp3%2FDesignflow%2Fppr%2Fdownload%2Fdb%2Fvga_pll.hier_info;h=71b8994dc1b7eb45d6abfd83239020adae8f72dc;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99 diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.hier_info b/bsp3/Designflow/ppr/download/db/vga_pll.hier_info new file mode 100644 index 0000000..71b8994 --- /dev/null +++ b/bsp3/Designflow/ppr/download/db/vga_pll.hier_info @@ -0,0 +1,432 @@ +|vga_pll +d_hsync <= vga:inst.d_hsync +board_clk => vpll:inst1.inclk0 +reset => vga:inst.reset_pin +d_vsync <= vga:inst.d_vsync +d_set_column_counter <= vga:inst.d_set_column_counter +d_set_line_counter <= vga:inst.d_set_line_counter +d_set_hsync_counter <= vga:inst.d_set_hsync_counter +d_set_vsync_counter <= vga:inst.d_set_vsync_counter +d_r <= vga:inst.d_r +d_g <= vga:inst.d_g +d_b <= vga:inst.d_b +d_h_enable <= vga:inst.d_h_enable +d_v_enable <= vga:inst.d_v_enable +d_state_clk <= vga:inst.d_state_clk +r0_pin <= vga:inst.r0_pin +r1_pin <= vga:inst.r1_pin +r2_pin <= vga:inst.r2_pin +g0_pin <= vga:inst.g0_pin +g1_pin <= vga:inst.g1_pin +g2_pin <= vga:inst.g2_pin +b0_pin <= vga:inst.b0_pin +b1_pin <= vga:inst.b1_pin +hsync_pin <= vga:inst.hsync_pin +vsync_pin <= vga:inst.vsync_pin +d_column_counter[0] <= vga:inst.d_column_counter[0] +d_column_counter[1] <= vga:inst.d_column_counter[1] +d_column_counter[2] <= vga:inst.d_column_counter[2] +d_column_counter[3] <= vga:inst.d_column_counter[3] +d_column_counter[4] <= vga:inst.d_column_counter[4] +d_column_counter[5] <= vga:inst.d_column_counter[5] +d_column_counter[6] <= vga:inst.d_column_counter[6] +d_column_counter[7] <= vga:inst.d_column_counter[7] +d_column_counter[8] <= vga:inst.d_column_counter[8] +d_column_counter[9] <= vga:inst.d_column_counter[9] +d_hsync_counter[0] <= vga:inst.d_hsync_counter[0] +d_hsync_counter[1] <= vga:inst.d_hsync_counter[1] +d_hsync_counter[2] <= vga:inst.d_hsync_counter[2] +d_hsync_counter[3] <= vga:inst.d_hsync_counter[3] +d_hsync_counter[4] <= vga:inst.d_hsync_counter[4] +d_hsync_counter[5] <= vga:inst.d_hsync_counter[5] +d_hsync_counter[6] <= vga:inst.d_hsync_counter[6] +d_hsync_counter[7] <= vga:inst.d_hsync_counter[7] +d_hsync_counter[8] <= vga:inst.d_hsync_counter[8] +d_hsync_counter[9] <= vga:inst.d_hsync_counter[9] +d_hsync_state[6] <= vga:inst.d_hsync_state[6] +d_hsync_state[5] <= vga:inst.d_hsync_state[5] +d_hsync_state[4] <= vga:inst.d_hsync_state[4] +d_hsync_state[3] <= vga:inst.d_hsync_state[3] +d_hsync_state[2] <= vga:inst.d_hsync_state[2] +d_hsync_state[1] <= vga:inst.d_hsync_state[1] +d_hsync_state[0] <= vga:inst.d_hsync_state[0] +d_line_counter[0] <= vga:inst.d_line_counter[0] +d_line_counter[1] <= vga:inst.d_line_counter[1] +d_line_counter[2] <= vga:inst.d_line_counter[2] +d_line_counter[3] <= vga:inst.d_line_counter[3] +d_line_counter[4] <= vga:inst.d_line_counter[4] +d_line_counter[5] <= vga:inst.d_line_counter[5] +d_line_counter[6] <= vga:inst.d_line_counter[6] +d_line_counter[7] <= vga:inst.d_line_counter[7] +d_line_counter[8] <= vga:inst.d_line_counter[8] +d_vsync_counter[0] <= vga:inst.d_vsync_counter[0] +d_vsync_counter[1] <= vga:inst.d_vsync_counter[1] +d_vsync_counter[2] <= vga:inst.d_vsync_counter[2] +d_vsync_counter[3] <= vga:inst.d_vsync_counter[3] +d_vsync_counter[4] <= vga:inst.d_vsync_counter[4] +d_vsync_counter[5] <= vga:inst.d_vsync_counter[5] +d_vsync_counter[6] <= vga:inst.d_vsync_counter[6] +d_vsync_counter[7] <= vga:inst.d_vsync_counter[7] +d_vsync_counter[8] <= vga:inst.d_vsync_counter[8] +d_vsync_counter[9] <= vga:inst.d_vsync_counter[9] +d_vsync_state[6] <= vga:inst.d_vsync_state[6] +d_vsync_state[5] <= vga:inst.d_vsync_state[5] +d_vsync_state[4] <= vga:inst.d_vsync_state[4] +d_vsync_state[3] <= vga:inst.d_vsync_state[3] +d_vsync_state[2] <= vga:inst.d_vsync_state[2] +d_vsync_state[1] <= vga:inst.d_vsync_state[1] +d_vsync_state[0] <= vga:inst.d_vsync_state[0] +seven_seg_pin[0] <= vga:inst.seven_seg_pin[0] +seven_seg_pin[1] <= vga:inst.seven_seg_pin[1] +seven_seg_pin[2] <= vga:inst.seven_seg_pin[2] +seven_seg_pin[3] <= vga:inst.seven_seg_pin[3] +seven_seg_pin[4] <= vga:inst.seven_seg_pin[4] +seven_seg_pin[5] <= vga:inst.seven_seg_pin[5] +seven_seg_pin[6] <= vga:inst.seven_seg_pin[6] +seven_seg_pin[7] <= vga:inst.seven_seg_pin[7] +seven_seg_pin[8] <= vga:inst.seven_seg_pin[8] +seven_seg_pin[9] <= vga:inst.seven_seg_pin[9] +seven_seg_pin[10] <= vga:inst.seven_seg_pin[10] +seven_seg_pin[11] <= vga:inst.seven_seg_pin[11] +seven_seg_pin[12] <= vga:inst.seven_seg_pin[12] +seven_seg_pin[13] <= vga:inst.seven_seg_pin[13] + + +|vga_pll|vga:inst +clk_pin => clk_pin_in.PADIO +reset_pin => reset_pin_in.PADIO +r0_pin <= r0_pin_out.PADIO +r1_pin <= r1_pin_out.PADIO +r2_pin <= r2_pin_out.PADIO +g0_pin <= g0_pin_out.PADIO +g1_pin <= g1_pin_out.PADIO +g2_pin <= g2_pin_out.PADIO +b0_pin <= b0_pin_out.PADIO +b1_pin <= b1_pin_out.PADIO +hsync_pin <= hsync_pin_out.PADIO +vsync_pin <= vsync_pin_out.PADIO +seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO +seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO +seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO +seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO +seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO +seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO +seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO +seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO +seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO +seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO +seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO +seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO +seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO +seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO +d_hsync <= d_hsync_out.PADIO +d_vsync <= d_vsync_out.PADIO +d_column_counter[0] <= d_column_counter_out_0_.PADIO +d_column_counter[1] <= d_column_counter_out_1_.PADIO +d_column_counter[2] <= d_column_counter_out_2_.PADIO +d_column_counter[3] <= d_column_counter_out_3_.PADIO +d_column_counter[4] <= d_column_counter_out_4_.PADIO +d_column_counter[5] <= d_column_counter_out_5_.PADIO +d_column_counter[6] <= d_column_counter_out_6_.PADIO +d_column_counter[7] <= d_column_counter_out_7_.PADIO +d_column_counter[8] <= d_column_counter_out_8_.PADIO +d_column_counter[9] <= d_column_counter_out_9_.PADIO +d_line_counter[0] <= d_line_counter_out_0_.PADIO +d_line_counter[1] <= d_line_counter_out_1_.PADIO +d_line_counter[2] <= d_line_counter_out_2_.PADIO +d_line_counter[3] <= d_line_counter_out_3_.PADIO +d_line_counter[4] <= d_line_counter_out_4_.PADIO +d_line_counter[5] <= d_line_counter_out_5_.PADIO +d_line_counter[6] <= d_line_counter_out_6_.PADIO +d_line_counter[7] <= d_line_counter_out_7_.PADIO +d_line_counter[8] <= d_line_counter_out_8_.PADIO +d_set_column_counter <= d_set_column_counter_out.PADIO +d_set_line_counter <= d_set_line_counter_out.PADIO +d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO +d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO +d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO +d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO +d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO +d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO +d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO +d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO +d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO +d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO +d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO +d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO +d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO +d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO +d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO +d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO +d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO +d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO +d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO +d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO +d_set_hsync_counter <= d_set_hsync_counter_out.PADIO +d_set_vsync_counter <= d_set_vsync_counter_out.PADIO +d_h_enable <= d_h_enable_out.PADIO +d_v_enable <= d_v_enable_out.PADIO +d_r <= d_r_out.PADIO +d_g <= d_g_out.PADIO +d_b <= d_b_out.PADIO +d_hsync_state[6] <= d_hsync_state_out_6_.PADIO +d_hsync_state[5] <= d_hsync_state_out_5_.PADIO +d_hsync_state[4] <= d_hsync_state_out_4_.PADIO +d_hsync_state[3] <= d_hsync_state_out_3_.PADIO +d_hsync_state[2] <= d_hsync_state_out_2_.PADIO +d_hsync_state[1] <= d_hsync_state_out_1_.PADIO +d_hsync_state[0] <= d_hsync_state_out_0_.PADIO +d_vsync_state[6] <= d_vsync_state_out_6_.PADIO +d_vsync_state[5] <= d_vsync_state_out_5_.PADIO +d_vsync_state[4] <= d_vsync_state_out_4_.PADIO +d_vsync_state[3] <= d_vsync_state_out_3_.PADIO +d_vsync_state[2] <= d_vsync_state_out_2_.PADIO +d_vsync_state[1] <= d_vsync_state_out_1_.PADIO +d_vsync_state[0] <= d_vsync_state_out_0_.PADIO +d_state_clk <= d_state_clk_out.PADIO + + +|vga_pll|vga:inst|vga_driver:vga_driver_unit +line_counter_sig_0 <= line_counter_sig_0_.REGOUT +line_counter_sig_1 <= line_counter_sig_1_.REGOUT +line_counter_sig_2 <= line_counter_sig_2_.REGOUT +line_counter_sig_3 <= line_counter_sig_3_.REGOUT +line_counter_sig_4 <= line_counter_sig_4_.REGOUT +line_counter_sig_5 <= line_counter_sig_5_.REGOUT +line_counter_sig_6 <= line_counter_sig_6_.REGOUT +line_counter_sig_7 <= line_counter_sig_7_.REGOUT +line_counter_sig_8 <= line_counter_sig_8_.REGOUT +dly_counter_1 => vsync_state_6_.DATAC +dly_counter_1 => h_sync_Z.DATAC +dly_counter_1 => v_sync_Z.DATAC +dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC +dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC +dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC +dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC +dly_counter_0 => vsync_state_6_.DATAB +dly_counter_0 => h_sync_Z.DATAB +dly_counter_0 => v_sync_Z.DATAB +dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB +dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB +dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB +dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB +vsync_state_2 <= vsync_state_2_.REGOUT +vsync_state_5 <= vsync_state_5_.REGOUT +vsync_state_3 <= vsync_state_3_.REGOUT +vsync_state_6 <= vsync_state_6_.REGOUT +vsync_state_4 <= vsync_state_4_.REGOUT +vsync_state_1 <= vsync_state_1_.REGOUT +vsync_state_0 <= vsync_state_0_.REGOUT +hsync_state_2 <= hsync_state_2_.REGOUT +hsync_state_4 <= hsync_state_4_.REGOUT +hsync_state_0 <= hsync_state_0_.REGOUT +hsync_state_5 <= hsync_state_5_.REGOUT +hsync_state_1 <= hsync_state_1_.REGOUT +hsync_state_3 <= hsync_state_3_.REGOUT +hsync_state_6 <= hsync_state_6_.REGOUT +column_counter_sig_0 <= column_counter_sig_0_.REGOUT +column_counter_sig_1 <= column_counter_sig_1_.REGOUT +column_counter_sig_2 <= column_counter_sig_2_.REGOUT +column_counter_sig_3 <= column_counter_sig_3_.REGOUT +column_counter_sig_4 <= column_counter_sig_4_.REGOUT +column_counter_sig_5 <= column_counter_sig_5_.REGOUT +column_counter_sig_6 <= column_counter_sig_6_.REGOUT +column_counter_sig_7 <= column_counter_sig_7_.REGOUT +column_counter_sig_8 <= column_counter_sig_8_.REGOUT +column_counter_sig_9 <= column_counter_sig_9_.REGOUT +vsync_counter_9 <= vsync_counter_9_.REGOUT +vsync_counter_8 <= vsync_counter_8_.REGOUT +vsync_counter_7 <= vsync_counter_7_.REGOUT +vsync_counter_6 <= vsync_counter_6_.REGOUT +vsync_counter_5 <= vsync_counter_5_.REGOUT +vsync_counter_4 <= vsync_counter_4_.REGOUT +vsync_counter_3 <= vsync_counter_3_.REGOUT +vsync_counter_2 <= vsync_counter_2_.REGOUT +vsync_counter_1 <= vsync_counter_1_.REGOUT +vsync_counter_0 <= vsync_counter_0_.REGOUT +hsync_counter_9 <= hsync_counter_9_.REGOUT +hsync_counter_8 <= hsync_counter_8_.REGOUT +hsync_counter_7 <= hsync_counter_7_.REGOUT +hsync_counter_6 <= hsync_counter_6_.REGOUT +hsync_counter_5 <= hsync_counter_5_.REGOUT +hsync_counter_4 <= hsync_counter_4_.REGOUT +hsync_counter_3 <= hsync_counter_3_.REGOUT +hsync_counter_2 <= hsync_counter_2_.REGOUT +hsync_counter_1 <= hsync_counter_1_.REGOUT +hsync_counter_0 <= hsync_counter_0_.REGOUT +d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT +un10_column_counter_siglt6_1 <= COLUMN_COUNT_next_un10_column_counter_siglt6_1.COMBOUT +un10_column_counter_siglt6_3 <= COLUMN_COUNT_next_un10_column_counter_siglt6_3.COMBOUT +v_sync <= v_sync_Z.REGOUT +h_sync <= h_sync_Z.REGOUT +h_enable_sig <= h_enable_sig_Z.REGOUT +v_enable_sig <= v_enable_sig_Z.REGOUT +reset_pin_c => vsync_state_6_.DATAA +reset_pin_c => h_sync_Z.DATAA +reset_pin_c => v_sync_Z.DATAA +reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA +reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA +reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA +reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA +un6_dly_counter_0_x <= vsync_state_6_.COMBOUT +d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT +clk_pin_c => hsync_counter_0_.CLK +clk_pin_c => hsync_counter_1_.CLK +clk_pin_c => hsync_counter_2_.CLK +clk_pin_c => hsync_counter_3_.CLK +clk_pin_c => hsync_counter_4_.CLK +clk_pin_c => hsync_counter_5_.CLK +clk_pin_c => hsync_counter_6_.CLK +clk_pin_c => hsync_counter_7_.CLK +clk_pin_c => hsync_counter_8_.CLK +clk_pin_c => hsync_counter_9_.CLK +clk_pin_c => vsync_counter_0_.CLK +clk_pin_c => vsync_counter_1_.CLK +clk_pin_c => vsync_counter_2_.CLK +clk_pin_c => vsync_counter_3_.CLK +clk_pin_c => vsync_counter_4_.CLK +clk_pin_c => vsync_counter_5_.CLK +clk_pin_c => vsync_counter_6_.CLK +clk_pin_c => vsync_counter_7_.CLK +clk_pin_c => vsync_counter_8_.CLK +clk_pin_c => vsync_counter_9_.CLK +clk_pin_c => column_counter_sig_9_.CLK +clk_pin_c => column_counter_sig_8_.CLK +clk_pin_c => column_counter_sig_7_.CLK +clk_pin_c => column_counter_sig_6_.CLK +clk_pin_c => column_counter_sig_5_.CLK +clk_pin_c => column_counter_sig_4_.CLK +clk_pin_c => column_counter_sig_3_.CLK +clk_pin_c => column_counter_sig_2_.CLK +clk_pin_c => column_counter_sig_1_.CLK +clk_pin_c => column_counter_sig_0_.CLK +clk_pin_c => hsync_state_6_.CLK +clk_pin_c => vsync_state_0_.CLK +clk_pin_c => vsync_state_1_.CLK +clk_pin_c => vsync_state_6_.CLK +clk_pin_c => line_counter_sig_8_.CLK +clk_pin_c => line_counter_sig_7_.CLK +clk_pin_c => line_counter_sig_6_.CLK +clk_pin_c => line_counter_sig_5_.CLK +clk_pin_c => line_counter_sig_4_.CLK +clk_pin_c => line_counter_sig_3_.CLK +clk_pin_c => line_counter_sig_2_.CLK +clk_pin_c => line_counter_sig_1_.CLK +clk_pin_c => line_counter_sig_0_.CLK +clk_pin_c => v_enable_sig_Z.CLK +clk_pin_c => h_enable_sig_Z.CLK +clk_pin_c => h_sync_Z.CLK +clk_pin_c => v_sync_Z.CLK +clk_pin_c => vsync_state_5_.CLK +clk_pin_c => vsync_state_4_.CLK +clk_pin_c => vsync_state_3_.CLK +clk_pin_c => vsync_state_2_.CLK +clk_pin_c => hsync_state_5_.CLK +clk_pin_c => hsync_state_4_.CLK +clk_pin_c => hsync_state_3_.CLK +clk_pin_c => hsync_state_2_.CLK +clk_pin_c => hsync_state_1_.CLK +clk_pin_c => hsync_state_0_.CLK + + +|vga_pll|vga:inst|vga_control:vga_control_unit +column_counter_sig_1 => g_next_i_o3_cZ.DATAB +column_counter_sig_7 => r_next_i_o7_cZ.DATAA +column_counter_sig_2 => b_next_i_o3_0_cZ.DATAC +column_counter_sig_2 => g_next_i_o3_cZ.DATAA +column_counter_sig_0 => b_next_i_a7_1_cZ.DATAC +column_counter_sig_4 => N_23_i_0_g0_a_cZ.DATAB +column_counter_sig_4 => b_next_i_o3_0_cZ.DATAB +column_counter_sig_3 => N_23_i_0_g0_a_cZ.DATAA +column_counter_sig_3 => b_next_i_o3_0_cZ.DATAA +column_counter_sig_5 => g_Z.DATAB +column_counter_sig_5 => N_4_i_0_g0_1_cZ.DATAA +column_counter_sig_5 => N_6_i_0_g0_0_cZ.DATAA +column_counter_sig_5 => b_next_i_a7_1_cZ.DATAA +column_counter_sig_5 => b_next_i_o3_0_cZ.DATAD +column_counter_sig_6 => b_Z.DATAA +column_counter_sig_6 => r_Z.DATAA +column_counter_sig_6 => g_Z.DATAA +column_counter_sig_6 => N_4_i_0_g0_1_cZ.DATAB +column_counter_sig_6 => N_6_i_0_g0_0_cZ.DATAB +column_counter_sig_6 => b_next_i_a7_1_cZ.DATAB +h_enable_sig => r_next_i_o7_cZ.DATAC +v_enable_sig => r_next_i_o7_cZ.DATAB +un10_column_counter_siglt6_1 => N_23_i_0_g0_a_cZ.DATAD +g <= g_Z.REGOUT +un10_column_counter_siglt6_3 => r_Z.DATAB +un10_column_counter_siglt6_3 => N_6_i_0_g0_0_cZ.DATAC +r <= r_Z.REGOUT +un6_dly_counter_0_x => b_Z.ACLR +un6_dly_counter_0_x => r_Z.ACLR +un6_dly_counter_0_x => g_Z.ACLR +clk_pin_c => b_Z.CLK +clk_pin_c => r_Z.CLK +clk_pin_c => g_Z.CLK +b <= b_Z.REGOUT + + +|vga_pll|vpll:inst1 +inclk0 => altpll:altpll_component.inclk[0] +c0 <= altpll:altpll_component.clk[0] + + +|vga_pll|vpll:inst1|altpll:altpll_component +inclk[0] => pll.CLK +inclk[1] => ~NO_FANOUT~ +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => ~NO_FANOUT~ +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => pll.ENA1 +clkena[2] => pll.ENA2 +clkena[3] => pll.ENA3 +clkena[4] => pll.ENA4 +clkena[5] => pll.ENA5 +extclkena[0] => pll.EXTCLKENA +extclkena[1] => pll.EXTCLKENA1 +extclkena[2] => pll.EXTCLKENA2 +extclkena[3] => pll.EXTCLKENA3 +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <= +clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= +clk[2] <= +clk[3] <= +clk[4] <= +clk[5] <= +extclk[0] <= +extclk[1] <= +extclk[2] <= +extclk[3] <= +clkbad[0] <= +clkbad[1] <= +enable1 <= +enable0 <= +activeclock <= +clkloss <= +locked <= +scandataout <= +scandone <= +sclkout0 <= +sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE +phasedone <= +vcooverrange <= +vcounderrange <= +fbout <= + +