X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp2%2FDesignflow%2Fsyn%2Frev_1%2Fbackup%2Fvga.srr;fp=bsp2%2FDesignflow%2Fsyn%2Frev_1%2Fbackup%2Fvga.srr;h=2a81acfec8aa5db1cea5edcc25bd66bf890326b2;hp=0000000000000000000000000000000000000000;hb=1d3e86fec5ba52f04aefbb676c4d03446264c2c8;hpb=cee156856f4a8d05e816dab384a819942d9ac31b

diff --git a/bsp2/Designflow/syn/rev_1/backup/vga.srr b/bsp2/Designflow/syn/rev_1/backup/vga.srr
new file mode 100644
index 0000000..2a81acf
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/backup/vga.srr
@@ -0,0 +1,33 @@
+#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
+#install: /opt/synplify/fpga_c200906
+#OS: Linux 
+#Hostname: ti12
+
+#Implementation: rev_1
+
+#Wed Oct 21 17:21:16 2009
+
+$ Start of Compile
+#Wed Oct 21 17:21:16 2009
+
+Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
+Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
+
+@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
+VHDL syntax check successful!
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav 
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav 
+@E: CD395 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd":50:73:50:95|Constant width 21 does not match context width 25
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav 
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav 
+1 errors during synthesis
+@END
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Oct 21 17:21:16 2009
+
+###########################################################]