X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp2%2FDesignflow%2Fsrc%2Fvga_control_ent.vhd;fp=bsp2%2FDesignflow%2Fsrc%2Fvga_control_ent.vhd;h=2ff5a0a2333b974b73b358568df6ab038ad0c011;hp=0000000000000000000000000000000000000000;hb=1d3e86fec5ba52f04aefbb676c4d03446264c2c8;hpb=cee156856f4a8d05e816dab384a819942d9ac31b diff --git a/bsp2/Designflow/src/vga_control_ent.vhd b/bsp2/Designflow/src/vga_control_ent.vhd new file mode 100644 index 0000000..2ff5a0a --- /dev/null +++ b/bsp2/Designflow/src/vga_control_ent.vhd @@ -0,0 +1,53 @@ +------------------------------------------------------------------------------- +-- Title : vga_control entity +-- Project : LU Digital Design +------------------------------------------------------------------------------- +-- File : vga_control_ent.vhd +-- Author : Thomas Handl +-- Company : TU Wien +-- Created : 2004-12-15 +-- Last update: 2006-02-24 +------------------------------------------------------------------------------- +-- Description: generation of colors (RGB) +------------------------------------------------------------------------------- +-- Copyright (c) 2004 TU Wien +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2004-12-15 1.0 handl Created +-- 2006-02-24 2.0 ST revised +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LIBRARIES +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +use work.vga_pak.all; + +------------------------------------------------------------------------------- +-- ENTITY +------------------------------------------------------------------------------- + + +entity vga_control is + port(clk : in std_logic; + reset : in std_logic; + column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0); + toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0); + toggle : out std_logic; + line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0); + v_enable : in std_logic; + h_enable : in std_logic; + r, g, b : out std_logic + ); + +end vga_control; + +------------------------------------------------------------------------------- +-- END ENTITY +-------------------------------------------------------------------------------