X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp2%2FDesignflow%2Fppr%2Fdownload%2Fsimulation%2Fmodelsim%2Fvga_pll_v.sdo;fp=bsp2%2FDesignflow%2Fppr%2Fdownload%2Fsimulation%2Fmodelsim%2Fvga_pll_v.sdo;h=f3f83150b56f92d4a76d896641be7c4451b7217a;hp=0000000000000000000000000000000000000000;hb=3696caab9416ac54ee349798f4735dd4e7bfe57d;hpb=ca832fa8fadb632cc02e0c14bf378dda2c9db74b

diff --git a/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo b/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo
new file mode 100644
index 0000000..f3f8315
--- /dev/null
+++ b/bsp2/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo
@@ -0,0 +1,5602 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP1S25F672C6 Package FBGA672
+// 
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "vga_pll")
+  (DATE "10/28/2009 14:55:41")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II")
+  (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE board_clk\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio combout (760:760:760) (760:760:760))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_pll")
+    (INSTANCE inst1\|altpll_component\|pll)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (649:649:649) (649:649:649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|reset_pin_in\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio combout (1141:1141:1141) (1141:1141:1141))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|dly_counter_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1191:1191:1191) (1191:1191:1191))
+        (PORT datac (5177:5177:5177) (5177:5177:5177))
+        (PORT datad (448:448:448) (448:448:448))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|dly_counter_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|dly_counter_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (441:441:441) (441:441:441))
+        (PORT datac (5628:5628:5628) (5628:5628:5628))
+        (PORT datad (1162:1162:1162) (1162:1162:1162))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|dly_counter_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (446:446:446) (446:446:446))
+        (PORT datac (5624:5624:5624) (5624:5624:5624))
+        (PORT datad (1164:1164:1164) (1164:1164:1164))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1379:1379:1379) (1379:1379:1379))
+        (PORT datac (1388:1388:1388) (1388:1388:1388))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH qfbkin combout (291:291:291) (291:291:291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1478:1478:1478) (1478:1478:1478))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+        (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (423:423:423) (423:423:423))
+        (PORT datac (1322:1322:1322) (1322:1322:1322))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1412:1412:1412) (1412:1412:1412))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (419:419:419) (419:419:419))
+        (PORT datac (1321:1321:1321) (1321:1321:1321))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1411:1411:1411) (1411:1411:1411))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (444:444:444))
+        (PORT datac (1320:1320:1320) (1320:1320:1320))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1410:1410:1410) (1410:1410:1410))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (437:437:437))
+        (PORT datac (1318:1318:1318) (1318:1318:1318))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1408:1408:1408) (1408:1408:1408))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (1317:1317:1317) (1317:1317:1317))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1407:1407:1407) (1407:1407:1407))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (420:420:420) (420:420:420))
+        (PORT datac (1304:1304:1304) (1304:1304:1304))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1394:1394:1394) (1394:1394:1394))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (422:422:422) (422:422:422))
+        (PORT datac (1307:1307:1307) (1307:1307:1307))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1397:1397:1397) (1397:1397:1397))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datac (1310:1310:1310) (1310:1310:1310))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1400:1400:1400) (1400:1400:1400))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (1313:1313:1313) (1313:1313:1313))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1403:1403:1403) (1403:1403:1403))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1316:1316:1316) (1316:1316:1316))
+        (PORT datad (432:432:432) (432:432:432))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1938:1938:1938) (1938:1938:1938))
+        (PORT datac (1406:1406:1406) (1406:1406:1406))
+        (PORT sclr (1841:1841:1841) (1841:1841:1841))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1127:1127:1127) (1127:1127:1127))
+        (PORT datab (1242:1242:1242) (1242:1242:1242))
+        (PORT datac (1186:1186:1186) (1186:1186:1186))
+        (PORT datad (1405:1405:1405) (1405:1405:1405))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1183:1183:1183) (1183:1183:1183))
+        (PORT datab (1157:1157:1157) (1157:1157:1157))
+        (PORT datac (1190:1190:1190) (1190:1190:1190))
+        (PORT datad (1419:1419:1419) (1419:1419:1419))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1430:1430:1430) (1430:1430:1430))
+        (PORT datab (1145:1145:1145) (1145:1145:1145))
+        (PORT datac (373:373:373) (373:373:373))
+        (PORT datad (359:359:359) (359:359:359))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|G_2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1983:1983:1983) (1983:1983:1983))
+        (PORT datab (2383:2383:2383) (2383:2383:2383))
+        (PORT datac (2111:2111:2111) (2111:2111:2111))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (774:774:774) (774:774:774))
+        (PORT datab (685:685:685) (685:685:685))
+        (PORT datac (650:650:650) (650:650:650))
+        (PORT datad (632:632:632) (632:632:632))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (666:666:666) (666:666:666))
+        (PORT datab (685:685:685) (685:685:685))
+        (PORT datac (1003:1003:1003) (1003:1003:1003))
+        (PORT datad (682:682:682) (682:682:682))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1179:1179:1179) (1179:1179:1179))
+        (PORT datab (1403:1403:1403) (1403:1403:1403))
+        (PORT datac (1075:1075:1075) (1075:1075:1075))
+        (PORT datad (1060:1060:1060) (1060:1060:1060))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (671:671:671) (671:671:671))
+        (PORT datac (655:655:655) (655:655:655))
+        (PORT datad (687:687:687) (687:687:687))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (776:776:776) (776:776:776))
+        (PORT datab (694:694:694) (694:694:694))
+        (PORT datad (635:635:635) (635:635:635))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (687:687:687) (687:687:687))
+        (PORT datab (681:681:681) (681:681:681))
+        (PORT datac (697:697:697) (697:697:697))
+        (PORT datad (642:642:642) (642:642:642))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (775:775:775) (775:775:775))
+        (PORT datab (694:694:694) (694:694:694))
+        (PORT datad (672:672:672) (672:672:672))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1745:1745:1745) (1745:1745:1745))
+        (PORT datad (419:419:419) (419:419:419))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3036:3036:3036) (3036:3036:3036))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (PORT ena (2335:2335:2335) (2335:2335:2335))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1066:1066:1066) (1066:1066:1066))
+        (PORT datab (1067:1067:1067) (1067:1067:1067))
+        (PORT datac (1736:1736:1736) (1736:1736:1736))
+        (PORT datad (1360:1360:1360) (1360:1360:1360))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1416:1416:1416) (1416:1416:1416))
+        (PORT datab (1406:1406:1406) (1406:1406:1406))
+        (PORT datac (1133:1133:1133) (1133:1133:1133))
+        (PORT datad (1151:1151:1151) (1151:1151:1151))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (351:351:351))
+        (PORT datab (353:353:353) (353:353:353))
+        (PORT datac (1188:1188:1188) (1188:1188:1188))
+        (PORT datad (1246:1246:1246) (1246:1246:1246))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1731:1731:1731) (1731:1731:1731))
+        (PORT datab (340:340:340) (340:340:340))
+        (PORT datac (1162:1162:1162) (1162:1162:1162))
+        (PORT datad (348:348:348) (348:348:348))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH qfbkin combout (291:291:291) (291:291:291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1252:1252:1252) (1252:1252:1252))
+        (PORT sclr (3171:3171:3171) (3171:3171:3171))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2092:2092:2092) (2092:2092:2092))
+        (PORT ena (1645:1645:1645) (1645:1645:1645))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+        (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (384:384:384) (384:384:384))
+        (PORT datab (346:346:346) (346:346:346))
+        (PORT datac (557:557:557) (557:557:557))
+        (PORT datad (449:449:449) (449:449:449))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (358:358:358) (358:358:358))
+        (PORT datab (347:347:347) (347:347:347))
+        (PORT datac (2397:2397:2397) (2397:2397:2397))
+        (PORT datad (1052:1052:1052) (1052:1052:1052))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (388:388:388) (388:388:388))
+        (PORT datab (347:347:347) (347:347:347))
+        (PORT datac (557:557:557) (557:557:557))
+        (PORT datad (448:448:448) (448:448:448))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3335:3335:3335) (3335:3335:3335))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (PORT ena (1806:1806:1806) (1806:1806:1806))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1613:1613:1613) (1613:1613:1613))
+        (PORT datad (1734:1734:1734) (1734:1734:1734))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3036:3036:3036) (3036:3036:3036))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (PORT ena (2335:2335:2335) (2335:2335:2335))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (454:454:454) (454:454:454))
+        (PORT datad (1621:1621:1621) (1621:1621:1621))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3036:3036:3036) (3036:3036:3036))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (PORT ena (2335:2335:2335) (2335:2335:2335))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2023:2023:2023) (2023:2023:2023))
+        (PORT datab (2145:2145:2145) (2145:2145:2145))
+        (PORT datac (5551:5551:5551) (5551:5551:5551))
+        (PORT datad (2002:2002:2002) (2002:2002:2002))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (656:656:656) (656:656:656))
+        (PORT datab (684:684:684) (684:684:684))
+        (PORT datac (701:701:701) (701:701:701))
+        (PORT datad (631:631:631) (631:631:631))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (352:352:352))
+        (PORT datab (1323:1323:1323) (1323:1323:1323))
+        (PORT datac (365:365:365) (365:365:365))
+        (PORT datad (376:376:376) (376:376:376))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3335:3335:3335) (3335:3335:3335))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (PORT ena (1806:1806:1806) (1806:1806:1806))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_hsync_state_3_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1588:1588:1588) (1588:1588:1588))
+        (PORT datad (1728:1728:1728) (1728:1728:1728))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|h_sync_1_0_0_0_g1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (604:604:604) (604:604:604))
+        (PORT datab (1266:1266:1266) (1266:1266:1266))
+        (PORT datac (455:455:455) (455:455:455))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (361:361:361) (361:361:361))
+        (PORT datab (2145:2145:2145) (2145:2145:2145))
+        (PORT datac (5552:5552:5552) (5552:5552:5552))
+        (PORT datad (2003:2003:2003) (2003:2003:2003))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1348:1348:1348) (1348:1348:1348))
+        (PORT datab (423:423:423) (423:423:423))
+        (PORT datac (689:689:689) (689:689:689))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (779:779:779) (779:779:779))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (419:419:419) (419:419:419))
+        (PORT datac (689:689:689) (689:689:689))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (779:779:779) (779:779:779))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (444:444:444))
+        (PORT datac (689:689:689) (689:689:689))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (779:779:779) (779:779:779))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (437:437:437))
+        (PORT datac (687:687:687) (687:687:687))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (777:777:777) (777:777:777))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (686:686:686) (686:686:686))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (776:776:776) (776:776:776))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (420:420:420) (420:420:420))
+        (PORT datac (672:672:672) (672:672:672))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (762:762:762) (762:762:762))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (683:683:683) (683:683:683))
+        (PORT datab (935:935:935) (935:935:935))
+        (PORT datac (623:623:623) (623:623:623))
+        (PORT datad (719:719:719) (719:719:719))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (422:422:422) (422:422:422))
+        (PORT datac (675:675:675) (675:675:675))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (765:765:765) (765:765:765))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datac (678:678:678) (678:678:678))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (768:768:768) (768:768:768))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (681:681:681) (681:681:681))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (771:771:771) (771:771:771))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (684:684:684) (684:684:684))
+        (PORT datad (432:432:432) (432:432:432))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1440:1440:1440) (1440:1440:1440))
+        (PORT datac (774:774:774) (774:774:774))
+        (PORT sclr (1317:1317:1317) (1317:1317:1317))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2034:2034:2034) (2034:2034:2034))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (688:688:688) (688:688:688))
+        (PORT datab (626:626:626) (626:626:626))
+        (PORT datac (688:688:688) (688:688:688))
+        (PORT datad (732:732:732) (732:732:732))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (938:938:938) (938:938:938))
+        (PORT datab (597:597:597) (597:597:597))
+        (PORT datac (371:371:371) (371:371:371))
+        (PORT datad (346:346:346) (346:346:346))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|G_16.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (698:698:698) (698:698:698))
+        (PORT datab (1398:1398:1398) (1398:1398:1398))
+        (PORT datac (360:360:360) (360:360:360))
+        (PORT datad (345:345:345) (345:345:345))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (681:681:681) (681:681:681))
+        (PORT datab (576:576:576) (576:576:576))
+        (PORT datac (651:651:651) (651:651:651))
+        (PORT datad (597:597:597) (597:597:597))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (337:337:337) (337:337:337))
+        (PORT datac (640:640:640) (640:640:640))
+        (PORT datad (647:647:647) (647:647:647))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (687:687:687) (687:687:687))
+        (PORT datab (626:626:626) (626:626:626))
+        (PORT datac (687:687:687) (687:687:687))
+        (PORT datad (731:731:731) (731:731:731))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1182:1182:1182) (1182:1182:1182))
+        (PORT datab (1299:1299:1299) (1299:1299:1299))
+        (PORT datad (1467:1467:1467) (1467:1467:1467))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1222:1222:1222) (1222:1222:1222))
+        (PORT datab (1117:1117:1117) (1117:1117:1117))
+        (PORT datac (1389:1389:1389) (1389:1389:1389))
+        (PORT datad (1160:1160:1160) (1160:1160:1160))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1416:1416:1416) (1416:1416:1416))
+        (PORT datab (846:846:846) (846:846:846))
+        (PORT datac (473:473:473) (473:473:473))
+        (PORT datad (833:833:833) (833:833:833))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (969:969:969) (969:969:969))
+        (PORT datad (1159:1159:1159) (1159:1159:1159))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2179:2179:2179) (2179:2179:2179))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (PORT ena (1573:1573:1573) (1573:1573:1573))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (383:383:383) (383:383:383))
+        (PORT datab (1168:1168:1168) (1168:1168:1168))
+        (PORT datac (924:924:924) (924:924:924))
+        (PORT datad (1466:1466:1466) (1466:1466:1466))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (382:382:382) (382:382:382))
+        (PORT datab (1457:1457:1457) (1457:1457:1457))
+        (PORT datac (990:990:990) (990:990:990))
+        (PORT datad (1178:1178:1178) (1178:1178:1178))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH qfbkin combout (291:291:291) (291:291:291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1080:1080:1080) (1080:1080:1080))
+        (PORT sclr (2188:2188:2188) (2188:2188:2188))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (PORT ena (1294:1294:1294) (1294:1294:1294))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+        (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (384:384:384) (384:384:384))
+        (PORT datac (366:366:366) (366:366:366))
+        (PORT datad (940:940:940) (940:940:940))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1060:1060:1060) (1060:1060:1060))
+        (PORT datab (349:349:349) (349:349:349))
+        (PORT datac (381:381:381) (381:381:381))
+        (PORT datad (937:937:937) (937:937:937))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (376:376:376) (376:376:376))
+        (PORT datab (335:335:335) (335:335:335))
+        (PORT datac (368:368:368) (368:368:368))
+        (PORT datad (1412:1412:1412) (1412:1412:1412))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (910:910:910) (910:910:910))
+        (PORT datab (947:947:947) (947:947:947))
+        (PORT datac (1155:1155:1155) (1155:1155:1155))
+        (PORT datad (1187:1187:1187) (1187:1187:1187))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2179:2179:2179) (2179:2179:2179))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (PORT ena (1573:1573:1573) (1573:1573:1573))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (354:354:354) (354:354:354))
+        (PORT datac (1614:1614:1614) (1614:1614:1614))
+        (PORT datad (1042:1042:1042) (1042:1042:1042))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (619:619:619) (619:619:619))
+        (PORT datab (1075:1075:1075) (1075:1075:1075))
+        (PORT datac (579:579:579) (579:579:579))
+        (PORT datad (1413:1413:1413) (1413:1413:1413))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|d_set_vsync_counter_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (696:696:696) (696:696:696))
+        (PORT datac (1410:1410:1410) (1410:1410:1410))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1180:1180:1180) (1180:1180:1180))
+        (PORT datab (343:343:343) (343:343:343))
+        (PORT datac (5619:5619:5619) (5619:5619:5619))
+        (PORT datad (453:453:453) (453:453:453))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1113:1113:1113) (1113:1113:1113))
+        (PORT datab (1378:1378:1378) (1378:1378:1378))
+        (PORT datac (1182:1182:1182) (1182:1182:1182))
+        (PORT datad (1202:1202:1202) (1202:1202:1202))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (379:379:379) (379:379:379))
+        (PORT datad (369:369:369) (369:369:369))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (916:916:916) (916:916:916))
+        (PORT datab (1143:1143:1143) (1143:1143:1143))
+        (PORT datac (469:469:469) (469:469:469))
+        (PORT datad (1181:1181:1181) (1181:1181:1181))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2179:2179:2179) (2179:2179:2179))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (PORT ena (1573:1573:1573) (1573:1573:1573))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_2_0_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (960:960:960) (960:960:960))
+        (PORT datad (437:437:437) (437:437:437))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|v_sync_1_0_0_0_g1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (461:461:461) (461:461:461))
+        (PORT datab (423:423:423) (423:423:423))
+        (PORT datac (445:445:445) (445:445:445))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1184:1184:1184) (1184:1184:1184))
+        (PORT datab (344:344:344) (344:344:344))
+        (PORT datac (5178:5178:5178) (5178:5178:5178))
+        (PORT datad (448:448:448) (448:448:448))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1176:1176:1176) (1176:1176:1176))
+        (PORT datab (444:444:444) (444:444:444))
+        (PORT datac (5625:5625:5625) (5625:5625:5625))
+        (PORT datad (1973:1973:1973) (1973:1973:1973))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (485:485:485) (485:485:485))
+        (PORT datad (442:442:442) (442:442:442))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2533:2533:2533) (2533:2533:2533))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (972:972:972) (972:972:972))
+        (PORT datab (944:944:944) (944:944:944))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (456:456:456) (456:456:456))
+        (PORT datad (843:843:843) (843:843:843))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2533:2533:2533) (2533:2533:2533))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (952:952:952) (952:952:952))
+        (PORT datab (973:973:973) (973:973:973))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (875:875:875) (875:875:875))
+        (PORT datad (437:437:437) (437:437:437))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2533:2533:2533) (2533:2533:2533))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (955:955:955) (955:955:955))
+        (PORT datab (919:919:919) (919:919:919))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (954:954:954) (954:954:954))
+        (PORT datab (945:945:945) (945:945:945))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (868:868:868) (868:868:868))
+        (PORT datad (445:445:445) (445:445:445))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2533:2533:2533) (2533:2533:2533))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1004:1004:1004) (1004:1004:1004))
+        (PORT datab (1004:1004:1004) (1004:1004:1004))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (457:457:457) (457:457:457))
+        (PORT datad (845:845:845) (845:845:845))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2533:2533:2533) (2533:2533:2533))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1034:1034:1034) (1034:1034:1034))
+        (PORT datab (1020:1020:1020) (1020:1020:1020))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (450:450:450) (450:450:450))
+        (PORT datad (851:851:851) (851:851:851))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2533:2533:2533) (2533:2533:2533))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1015:1015:1015) (1015:1015:1015))
+        (PORT datab (644:644:644) (644:644:644))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (636:636:636) (636:636:636))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1510:1510:1510) (1510:1510:1510))
+        (PORT datab (865:865:865) (865:865:865))
+        (PORT datad (536:536:536) (536:536:536))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (489:489:489) (489:489:489))
+        (PORT datab (418:418:418) (418:418:418))
+        (PORT datac (446:446:446) (446:446:446))
+        (PORT datad (470:470:470) (470:470:470))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (564:564:564) (564:564:564))
+        (PORT datab (420:420:420) (420:420:420))
+        (PORT datac (666:666:666) (666:666:666))
+        (PORT datad (958:958:958) (958:958:958))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (439:439:439) (439:439:439))
+        (PORT datab (962:962:962) (962:962:962))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (430:430:430) (430:430:430))
+        (PORT datab (416:416:416) (416:416:416))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (884:884:884) (884:884:884))
+        (PORT datad (341:341:341) (341:341:341))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2278:2278:2278) (2278:2278:2278))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (942:942:942) (942:942:942))
+        (PORT datab (945:945:945) (945:945:945))
+        (PORT datac (359:359:359) (359:359:359))
+        (PORT datad (940:940:940) (940:940:940))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1509:1509:1509) (1509:1509:1509))
+        (PORT datac (884:884:884) (884:884:884))
+        (PORT datad (348:348:348) (348:348:348))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (882:882:882) (882:882:882))
+        (PORT datad (442:442:442) (442:442:442))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2533:2533:2533) (2533:2533:2533))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelt2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (947:947:947) (947:947:947))
+        (PORT datac (963:963:963) (963:963:963))
+        (PORT datad (958:958:958) (958:958:958))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto5.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1057:1057:1057) (1057:1057:1057))
+        (PORT datab (1007:1007:1007) (1007:1007:1007))
+        (PORT datac (1086:1086:1086) (1086:1086:1086))
+        (PORT datad (881:881:881) (881:881:881))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto4.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1471:1471:1471) (1471:1471:1471))
+        (PORT datac (1089:1089:1089) (1089:1089:1089))
+        (PORT datad (1013:1013:1013) (1013:1013:1013))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1061:1061:1061) (1061:1061:1061))
+        (PORT datac (1054:1054:1054) (1054:1054:1054))
+        (PORT datad (253:253:253) (253:253:253))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1183:1183:1183) (1183:1183:1183))
+        (PORT datab (424:424:424) (424:424:424))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (460:460:460) (460:460:460))
+        (PORT datab (987:987:987) (987:987:987))
+        (PORT datac (5175:5175:5175) (5175:5175:5175))
+        (PORT datad (1181:1181:1181) (1181:1181:1181))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (635:635:635) (635:635:635))
+        (PORT datad (357:357:357) (357:357:357))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2226:2226:2226) (2226:2226:2226))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1028:1028:1028) (1028:1028:1028))
+        (PORT datab (425:425:425) (425:425:425))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (371:371:371) (371:371:371))
+        (PORT datad (641:641:641) (641:641:641))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2226:2226:2226) (2226:2226:2226))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_a_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1012:1012:1012) (1012:1012:1012))
+        (PORT datab (1225:1225:1225) (1225:1225:1225))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1041:1041:1041) (1041:1041:1041))
+        (PORT datab (620:620:620) (620:620:620))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (937:937:937) (937:937:937))
+        (PORT datac (905:905:905) (905:905:905))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2572:2572:2572) (2572:2572:2572))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2110:2110:2110) (2110:2110:2110))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (615:615:615) (615:615:615))
+        (PORT datab (616:616:616) (616:616:616))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (634:634:634) (634:634:634))
+        (PORT datad (351:351:351) (351:351:351))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2226:2226:2226) (2226:2226:2226))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (666:666:666) (666:666:666))
+        (PORT datab (427:427:427) (427:427:427))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (361:361:361) (361:361:361))
+        (PORT datad (362:362:362) (362:362:362))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2225:2225:2225) (2225:2225:2225))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1068:1068:1068) (1068:1068:1068))
+        (PORT datab (426:426:426) (426:426:426))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (360:360:360) (360:360:360))
+        (PORT datad (644:644:644) (644:644:644))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2226:2226:2226) (2226:2226:2226))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1062:1062:1062) (1062:1062:1062))
+        (PORT datab (656:656:656) (656:656:656))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (900:900:900) (900:900:900))
+        (PORT datab (932:932:932) (932:932:932))
+        (PORT datac (1799:1799:1799) (1799:1799:1799))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2110:2110:2110) (2110:2110:2110))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (440:440:440) (440:440:440))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (342:342:342))
+        (PORT datad (362:362:362) (362:362:362))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2225:2225:2225) (2225:2225:2225))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (671:671:671) (671:671:671))
+        (PORT datac (451:451:451) (451:451:451))
+        (PORT datad (1002:1002:1002) (1002:1002:1002))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1039:1039:1039) (1039:1039:1039))
+        (PORT datab (342:342:342) (342:342:342))
+        (PORT datac (1056:1056:1056) (1056:1056:1056))
+        (PORT datad (631:631:631) (631:631:631))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (453:453:453) (453:453:453))
+        (PORT datab (651:651:651) (651:651:651))
+        (PORT datac (672:672:672) (672:672:672))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (967:967:967) (967:967:967))
+        (PORT datad (428:428:428) (428:428:428))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (633:633:633) (633:633:633))
+        (PORT datad (350:350:350) (350:350:350))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2226:2226:2226) (2226:2226:2226))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2064:2064:2064) (2064:2064:2064))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (463:463:463) (463:463:463))
+        (PORT datac (466:466:466) (466:466:466))
+        (PORT datad (1406:1406:1406) (1406:1406:1406))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1200:1200:1200) (1200:1200:1200))
+        (PORT datad (1471:1471:1471) (1471:1471:1471))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2226:2226:2226) (2226:2226:2226))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (PORT ena (2067:2067:2067) (2067:2067:2067))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_2_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1006:1006:1006) (1006:1006:1006))
+        (PORT datab (977:977:977) (977:977:977))
+        (PORT datac (1591:1591:1591) (1591:1591:1591))
+        (PORT datad (433:433:433) (433:433:433))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_3_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1006:1006:1006) (1006:1006:1006))
+        (PORT datab (1002:1002:1002) (1002:1002:1002))
+        (PORT datac (363:363:363) (363:363:363))
+        (PORT datad (346:346:346) (346:346:346))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_5_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1064:1064:1064) (1064:1064:1064))
+        (PORT datab (1002:1002:1002) (1002:1002:1002))
+        (PORT datac (359:359:359) (359:359:359))
+        (PORT datad (352:352:352) (352:352:352))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto4_0.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1012:1012:1012) (1012:1012:1012))
+        (PORT datad (992:992:992) (992:992:992))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (433:433:433) (433:433:433))
+        (PORT datab (336:336:336) (336:336:336))
+        (PORT datac (1002:1002:1002) (1002:1002:1002))
+        (PORT datad (940:940:940) (940:940:940))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelto3.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (616:616:616) (616:616:616))
+        (PORT datab (984:984:984) (984:984:984))
+        (PORT datac (1041:1041:1041) (1041:1041:1041))
+        (PORT datad (991:991:991) (991:991:991))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_4_a_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2058:2058:2058) (2058:2058:2058))
+        (PORT datab (1540:1540:1540) (1540:1540:1540))
+        (PORT datac (1550:1550:1550) (1550:1550:1550))
+        (PORT datad (1887:1887:1887) (1887:1887:1887))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|b_next_0_sqmuxa_7_4_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1596:1596:1596) (1596:1596:1596))
+        (PORT datab (1768:1768:1768) (1768:1768:1768))
+        (PORT datac (2067:2067:2067) (2067:2067:2067))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (441:441:441) (441:441:441))
+        (PORT datac (1283:1283:1283) (1283:1283:1283))
+        (PORT datad (2257:2257:2257) (2257:2257:2257))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (953:953:953) (953:953:953))
+        (PORT datad (1367:1367:1367) (1367:1367:1367))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (3066:3066:3066) (3066:3066:3066))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2097:2097:2097) (2097:2097:2097))
+        (PORT ena (1631:1631:1631) (1631:1631:1631))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (443:443:443) (443:443:443))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_0_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_1_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (958:958:958) (958:958:958))
+        (PORT datab (423:423:423) (423:423:423))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_1_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_3_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (976:976:976) (976:976:976))
+        (PORT datab (419:419:419) (419:419:419))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_3_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|un2_toggle_counter_next_0_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (966:966:966) (966:966:966))
+        (PORT datab (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_2_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (971:971:971) (971:971:971))
+        (PORT datab (434:434:434) (434:434:434))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_2_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_5_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (444:444:444))
+        (PORT datab (942:942:942) (942:942:942))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_5_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_4_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datab (955:955:955) (955:955:955))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_4_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_6_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1000:1000:1000) (1000:1000:1000))
+        (PORT datab (609:609:609) (609:609:609))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_6_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_7_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (437:437:437))
+        (PORT datab (897:897:897) (897:897:897))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_7_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_8_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (942:942:942) (942:942:942))
+        (PORT datab (440:440:440) (440:440:440))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (644:644:644) (644:644:644))
+        (IOPATH datab cout (533:533:533) (533:533:533))
+        (IOPATH cin0 cout (219:219:219) (219:219:219))
+        (IOPATH cin1 cout (205:205:205) (205:205:205))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_8_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_9_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datab (945:945:945) (945:945:945))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH datab cout (460:460:460) (460:460:460))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_9_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_11_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1409:1409:1409) (1409:1409:1409))
+        (PORT datab (420:420:420) (420:420:420))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_11_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_10_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (596:596:596) (596:596:596))
+        (PORT datab (1407:1407:1407) (1407:1407:1407))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_10_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1150:1150:1150) (1150:1150:1150))
+        (PORT aclr (5475:5475:5475) (5475:5475:5475))
+        (PORT clk (2051:2051:2051) (2051:2051:2051))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_13_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1465:1465:1465) (1465:1465:1465))
+        (PORT datab (422:422:422) (422:422:422))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_13_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_12_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (996:996:996) (996:996:996))
+        (PORT datab (1423:1423:1423) (1423:1423:1423))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_12_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1150:1150:1150) (1150:1150:1150))
+        (PORT aclr (5475:5475:5475) (5475:5475:5475))
+        (PORT clk (2051:2051:2051) (2051:2051:2051))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_15_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datab (1362:1362:1362) (1362:1362:1362))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_15_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_14_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (458:458:458) (458:458:458))
+        (PORT datab (1387:1387:1387) (1387:1387:1387))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_14_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1150:1150:1150) (1150:1150:1150))
+        (PORT aclr (5475:5475:5475) (5475:5475:5475))
+        (PORT clk (2051:2051:2051) (2051:2051:2051))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglt6.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (443:443:443) (443:443:443))
+        (PORT datad (961:961:961) (961:961:961))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto9.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1002:1002:1002) (1002:1002:1002))
+        (PORT datab (440:440:440) (440:440:440))
+        (PORT datac (367:367:367) (367:367:367))
+        (PORT datad (932:932:932) (932:932:932))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto12.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1061:1061:1061) (1061:1061:1061))
+        (PORT datab (428:428:428) (428:428:428))
+        (PORT datac (457:457:457) (457:457:457))
+        (PORT datad (1408:1408:1408) (1408:1408:1408))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto15.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (461:461:461) (461:461:461))
+        (PORT datab (345:345:345) (345:345:345))
+        (PORT datac (1403:1403:1403) (1403:1403:1403))
+        (PORT datad (1429:1429:1429) (1429:1429:1429))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_16_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (447:447:447) (447:447:447))
+        (PORT datab (1377:1377:1377) (1377:1377:1377))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_16_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1150:1150:1150) (1150:1150:1150))
+        (PORT aclr (5475:5475:5475) (5475:5475:5475))
+        (PORT clk (2051:2051:2051) (2051:2051:2051))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_17_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datab (1366:1366:1366) (1366:1366:1366))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_17_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_19_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1379:1379:1379) (1379:1379:1379))
+        (PORT datad (432:432:432) (432:432:432))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_19_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2111:2111:2111) (2111:2111:2111))
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_18_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (461:461:461) (461:461:461))
+        (PORT datab (1385:1385:1385) (1385:1385:1385))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH datab cout (460:460:460) (460:460:460))
+        (IOPATH cin cout (110:110:110) (110:110:110))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_18_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1150:1150:1150) (1150:1150:1150))
+        (PORT aclr (5475:5475:5475) (5475:5475:5475))
+        (PORT clk (2051:2051:2051) (2051:2051:2051))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto18.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (364:364:364))
+        (PORT datab (1377:1377:1377) (1377:1377:1377))
+        (PORT datac (458:458:458) (458:458:458))
+        (PORT datad (449:449:449) (449:449:449))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_20_.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (427:427:427) (427:427:427))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_counter_sig_20_.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1150:1150:1150) (1150:1150:1150))
+        (PORT aclr (5475:5475:5475) (5475:5475:5475))
+        (PORT clk (2051:2051:2051) (2051:2051:2051))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_sig_0_0_0_g1_cZ.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (376:376:376) (376:376:376))
+        (PORT datac (460:460:460) (460:460:460))
+        (PORT datad (1393:1393:1393) (1393:1393:1393))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|toggle_sig_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1085:1085:1085) (1085:1085:1085))
+        (PORT datad (436:436:436) (436:436:436))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|toggle_sig_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|r_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3166:3166:3166) (3166:3166:3166))
+        (PORT datab (3139:3139:3139) (3139:3139:3139))
+        (PORT datac (2967:2967:2967) (2967:2967:2967))
+        (PORT datad (435:435:435) (435:435:435))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|r_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (5468:5468:5468) (5468:5468:5468))
+        (PORT clk (2043:2043:2043) (2043:2043:2043))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE inst\|vga_control_unit\|b_Z.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (359:359:359) (359:359:359))
+        (PORT datab (344:344:344) (344:344:344))
+        (PORT datac (3215:3215:3215) (3215:3215:3215))
+        (PORT datad (2167:2167:2167) (2167:2167:2167))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE inst\|vga_control_unit\|b_Z.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (5413:5413:5413) (5413:5413:5413))
+        (PORT clk (2025:2025:2025) (2025:2025:2025))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3422:3422:3422) (3422:3422:3422))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2656:2656:2656) (2656:2656:2656))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_set_column_counter_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3695:3695:3695) (3695:3695:3695))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_set_line_counter_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3004:3004:3004) (3004:3004:3004))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_set_hsync_counter_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3189:3189:3189) (3189:3189:3189))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_set_vsync_counter_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2937:2937:2937) (2937:2937:2937))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_r_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4042:4042:4042) (4042:4042:4042))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_g_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3227:3227:3227) (3227:3227:3227))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_b_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3536:3536:3536) (3536:3536:3536))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_h_enable_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3035:3035:3035) (3035:3035:3035))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_v_enable_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1665:1665:1665) (1665:1665:1665))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_state_clk_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2239:2239:2239) (2239:2239:2239))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4509:4509:4509) (4509:4509:4509))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|r0_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3637:3637:3637) (3637:3637:3637))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|r1_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3447:3447:3447) (3447:3447:3447))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|r2_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3473:3473:3473) (3473:3473:3473))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|g0_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3335:3335:3335) (3335:3335:3335))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|g1_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3519:3519:3519) (3519:3519:3519))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|g2_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3768:3768:3768) (3768:3768:3768))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|b0_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3020:3020:3020) (3020:3020:3020))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|b1_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2936:2936:2936) (2936:2936:2936))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|hsync_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2478:2478:2478) (2478:2478:2478))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|vsync_pin_out\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2475:2475:2475) (2475:2475:2475))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_9_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2563:2563:2563) (2563:2563:2563))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3085:3085:3085) (3085:3085:3085))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2835:2835:2835) (2835:2835:2835))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2328:2328:2328) (2328:2328:2328))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2320:2320:2320) (2320:2320:2320))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2102:2102:2102) (2102:2102:2102))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2887:2887:2887) (2887:2887:2887))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3106:3106:3106) (3106:3106:3106))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3351:3351:3351) (3351:3351:3351))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_column_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3224:3224:3224) (3224:3224:3224))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_9_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1656:1656:1656) (1656:1656:1656))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1887:1887:1887) (1887:1887:1887))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2401:2401:2401) (2401:2401:2401))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1823:1823:1823) (1823:1823:1823))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2330:2330:2330) (2330:2330:2330))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2339:2339:2339) (2339:2339:2339))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1904:1904:1904) (1904:1904:1904))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1362:1362:1362) (1362:1362:1362))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3075:3075:3075) (3075:3075:3075))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2143:2143:2143) (2143:2143:2143))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4065:4065:4065) (4065:4065:4065))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1982:1982:1982) (1982:1982:1982))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2393:2393:2393) (2393:2393:2393))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3954:3954:3954) (3954:3954:3954))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2620:2620:2620) (2620:2620:2620))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2319:2319:2319) (2319:2319:2319))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_hsync_state_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2823:2823:2823) (2823:2823:2823))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3582:3582:3582) (3582:3582:3582))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
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+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3259:3259:3259) (3259:3259:3259))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2575:2575:2575) (2575:2575:2575))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
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+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2529:2529:2529) (2529:2529:2529))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2798:2798:2798) (2798:2798:2798))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
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+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2409:2409:2409) (2409:2409:2409))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
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+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3183:3183:3183) (3183:3183:3183))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2508:2508:2508) (2508:2508:2508))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_line_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2341:2341:2341) (2341:2341:2341))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_24_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3622:3622:3622) (3622:3622:3622))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_23_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3328:3328:3328) (3328:3328:3328))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_22_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3328:3328:3328) (3328:3328:3328))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_21_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2472:2472:2472) (2472:2472:2472))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_20_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4383:4383:4383) (4383:4383:4383))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_19_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4446:4446:4446) (4446:4446:4446))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_18_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3470:3470:3470) (3470:3470:3470))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_17_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3051:3051:3051) (3051:3051:3051))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_16_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4056:4056:4056) (4056:4056:4056))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_15_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (2929:2929:2929) (2929:2929:2929))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_14_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (1354:1354:1354) (1354:1354:1354))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_13_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (3924:3924:3924) (3924:3924:3924))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_12_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (1359:1359:1359) (1359:1359:1359))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_11_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (1630:1630:1630) (1630:1630:1630))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_10_\~I.inst1)
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+      (ABSOLUTE
+        (PORT datain (1199:1199:1199) (1199:1199:1199))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
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+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_9_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1654:1654:1654) (1654:1654:1654))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1210:1210:1210) (1210:1210:1210))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1842:1842:1842) (1842:1842:1842))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4797:4797:4797) (4797:4797:4797))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2092:2092:2092) (2092:2092:2092))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1658:1658:1658) (1658:1658:1658))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3319:3319:3319) (3319:3319:3319))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3783:3783:3783) (3783:3783:3783))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1128:1128:1128) (1128:1128:1128))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_toggle_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3613:3613:3613) (3613:3613:3613))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_9_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2292:2292:2292) (2292:2292:2292))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2631:2631:2631) (2631:2631:2631))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2678:2678:2678) (2678:2678:2678))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2309:2309:2309) (2309:2309:2309))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2307:2307:2307) (2307:2307:2307))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2340:2340:2340) (2340:2340:2340))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1914:1914:1914) (1914:1914:1914))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1790:1790:1790) (1790:1790:1790))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2543:2543:2543) (2543:2543:2543))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_counter_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2087:2087:2087) (2087:2087:2087))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2661:2661:2661) (2661:2661:2661))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2763:2763:2763) (2763:2763:2763))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2969:2969:2969) (2969:2969:2969))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3068:3068:3068) (3068:3068:3068))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3360:3360:3360) (3360:3360:3360))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3036:3036:3036) (3036:3036:3036))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|d_vsync_state_out_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2653:2653:2653) (2653:2653:2653))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_13_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3481:3481:3481) (3481:3481:3481))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_12_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4857:4857:4857) (4857:4857:4857))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_11_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2937:2937:2937) (2937:2937:2937))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_10_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2929:2929:2929) (2929:2929:2929))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_9_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2778:2778:2778) (2778:2778:2778))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_8_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2763:2763:2763) (2763:2763:2763))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_7_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4867:4867:4867) (4867:4867:4867))
+        (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_6_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3621:3621:3621) (3621:3621:3621))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_5_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3621:3621:3621) (3621:3621:3621))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_4_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3615:3615:3615) (3615:3615:3615))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_3_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3615:3615:3615) (3615:3615:3615))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_2_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (4048:4048:4048) (4048:4048:4048))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_out_1_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2937:2937:2937) (2937:2937:2937))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE inst\|seven_seg_pin_tri_0_\~I.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3465:3465:3465) (3465:3465:3465))
+        (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+      )
+    )
+  )
+)