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after slot5
[dide_16.git]
/
bsp4
/
Designflow
/
syn
/
rev_1
/
vga_cons.tcl
diff --git a/bsp4/Designflow/syn/rev_1/vga_cons.tcl
b/bsp4/Designflow/syn/rev_1/vga_cons.tcl
new file mode 100644
(file)
index 0000000..
43fc06f
--- /dev/null
+++ b/
bsp4/Designflow/syn/rev_1/vga_cons.tcl
@@ -0,0
+1,6
@@
+source "/opt/synplify/fpga_c200906/lib/altera/quartus_cons.tcl"
+syn_create_and_open_prj vga
+source $::quartus(binpath)/prj_asd_import.tcl
+syn_create_and_open_csf vga
+syn_handle_cons vga
+syn_compile_quartus