m255
K3
13
cModel Technology
Z0 d/homes/burban/didelu/dide_16/bsp4/Designflow/sim/post
T_opt
VEaAWm1d_JS=VNkklOXhG;0
04 12 0 work vga_conf_pos 1
Z1 =1-0015609ed0a8-4af05b46-4068a-7b76
Z2 o-quiet -auto_acc_if_foreign -work work -sdftyp /vga_unit=/homes/burban/didelu/dide_16/bsp4/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo -suppress 1948
Z3 n@_opt
Z4 OE;O;6.5b;42
Evga
Z5 w1257265900
Z6 DPx4 ieee 16 vital_primitives 0 22 E9g6AWKAc2T]enMfl94If3
Z7 DPx7 stratix 17 stratix_atom_pack 0 22 4LU4R]0>3N6GcAdgd1O1R2
Z8 DPx4 ieee 12 vital_timing 0 22 OBWK>;kUYmkG<OChK2lhV1
Z9 DPx7 stratix 18 stratix_components 0 22 ETJi=`V@8?ceQEj0KODmn3
Z10 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
Z11 8/homes/burban/didelu/dide_16/bsp4/Designflow/ppr/sim/simulation/modelsim/vga.vho
Z12 F/homes/burban/didelu/dide_16/bsp4/Designflow/ppr/sim/simulation/modelsim/vga.vho
l0
L33
Z13 Va^A3`oj7W2X29O[KC68:E3
Z14 OE;C;6.5b;42
32
Z15 o-work work
Z16 tExplicit 1
Z17 !s100 JmIRf5hghCim]`W8beHGP0
Astructure
R6
R7
R8
R9
R10
Z18 DEx4 work 3 vga 0 22 a^A3`oj7W2X29O[KC68:E3
l339
L71
Z19 V]Wm516:I9;]lA9UPJ_ON=3
R14
32
Z20 Mx5 4 ieee 14 std_logic_1164
Z21 Mx4 7 stratix 18 stratix_components
Z22 Mx3 4 ieee 12 vital_timing
Z23 Mx2 7 stratix 17 stratix_atom_pack
Z24 Mx1 4 ieee 16 vital_primitives
R15
R16
Z25 !s100 @2=YGQ1l@859QgkB=LQ;73
Cvga_conf_pos
Z26 astructure
Z27 evga_pos_tb
R6
R7
R8
R9
R18
Z28 DAx4 work 10 vga_pos_tb 9 structure 22 2H0Zl8k[9mYf8bN=NCbeH0
Z29 DPx4 work 7 vga_pak 0 22 HkmzP=gd;mD@MOhh4AYKl3
Z30 DPx4 ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
Z31 DPx4 ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
R10
Z32 DEx4 work 10 vga_pos_tb 0 22 WYVDk8:IlXF:G=gkK18_k0
Z33 w1255952276
Z34 8/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pos_tb.vhd
Z35 F/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pos_tb.vhd
l0
L190
Z36 V0i2Wgcf;160Sh<_O1]Yd91
R14
32
Z37 Mx8 4 ieee 14 std_logic_1164
Z38 Mx7 4 ieee 18 std_logic_unsigned
Z39 Mx6 4 ieee 15 std_logic_arith
Z40 Mx5 4 work 7 vga_pak
R21
R22
R23
R24
R15
R16
Z41 !s100 5AFP2EDWmkBg2TkYkScac0
Pvga_pak
R30
R31
R10
Z42 w1257265128
Z43 8/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd
Z44 F/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd
l0
L35
Z45 VHkmzP=gd;mD@MOhh4AYKl3
R14
32
Z46 Mx3 4 ieee 14 std_logic_1164
Z47 Mx2 4 ieee 18 std_logic_unsigned
Z48 Mx1 4 ieee 15 std_logic_arith
R15
R16
Z49 !s100 VL:Z2?FJISz9N5>XaK:5k0
Evga_pos_tb
R33
R29
R30
R31
R10
R34
R35
l0
L37
Z50 VWYVDk8:IlXF:G=gkK18_k0
R14
32
R15
R16
Z51 !s100 ?:YH_R3N79K7J0L`IT49_0
Astructure
R29
R30
R31
R10
R32
l101
L45
Z52 V2H0Zl8k[9mYf8bN=NCbeH0
R14
32
Z53 Mx4 4 ieee 14 std_logic_1164
Z54 Mx3 4 ieee 18 std_logic_unsigned
Z55 Mx2 4 ieee 15 std_logic_arith
Z56 Mx1 4 work 7 vga_pak
R15
R16
Z57 !s100 T_8dcPYGCmK@^6g;3L5;b0