|vga clk_pin => clk_pin_in.PADIO reset_pin => reset_pin_in.PADIO r0_pin <= r0_pin_out.PADIO r1_pin <= r1_pin_out.PADIO r2_pin <= r2_pin_out.PADIO g0_pin <= g0_pin_out.PADIO g1_pin <= g1_pin_out.PADIO g2_pin <= g2_pin_out.PADIO b0_pin <= b0_pin_out.PADIO b1_pin <= b1_pin_out.PADIO hsync_pin <= hsync_pin_out.PADIO vsync_pin <= vsync_pin_out.PADIO seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO d_hsync <= d_hsync_out.PADIO d_vsync <= d_vsync_out.PADIO d_column_counter[0] <= d_column_counter_out_0_.PADIO d_column_counter[1] <= d_column_counter_out_1_.PADIO d_column_counter[2] <= d_column_counter_out_2_.PADIO d_column_counter[3] <= d_column_counter_out_3_.PADIO d_column_counter[4] <= d_column_counter_out_4_.PADIO d_column_counter[5] <= d_column_counter_out_5_.PADIO d_column_counter[6] <= d_column_counter_out_6_.PADIO d_column_counter[7] <= d_column_counter_out_7_.PADIO d_column_counter[8] <= d_column_counter_out_8_.PADIO d_column_counter[9] <= d_column_counter_out_9_.PADIO d_line_counter[0] <= d_line_counter_out_0_.PADIO d_line_counter[1] <= d_line_counter_out_1_.PADIO d_line_counter[2] <= d_line_counter_out_2_.PADIO d_line_counter[3] <= d_line_counter_out_3_.PADIO d_line_counter[4] <= d_line_counter_out_4_.PADIO d_line_counter[5] <= d_line_counter_out_5_.PADIO d_line_counter[6] <= d_line_counter_out_6_.PADIO d_line_counter[7] <= d_line_counter_out_7_.PADIO d_line_counter[8] <= d_line_counter_out_8_.PADIO d_set_column_counter <= d_set_column_counter_out.PADIO d_set_line_counter <= d_set_line_counter_out.PADIO d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO d_set_hsync_counter <= d_set_hsync_counter_out.PADIO d_set_vsync_counter <= d_set_vsync_counter_out.PADIO d_h_enable <= d_h_enable_out.PADIO d_v_enable <= d_v_enable_out.PADIO d_r <= d_r_out.PADIO d_g <= d_g_out.PADIO d_b <= d_b_out.PADIO d_hsync_state[6] <= d_hsync_state_out_6_.PADIO d_hsync_state[5] <= d_hsync_state_out_5_.PADIO d_hsync_state[4] <= d_hsync_state_out_4_.PADIO d_hsync_state[3] <= d_hsync_state_out_3_.PADIO d_hsync_state[2] <= d_hsync_state_out_2_.PADIO d_hsync_state[1] <= d_hsync_state_out_1_.PADIO d_hsync_state[0] <= d_hsync_state_out_0_.PADIO d_vsync_state[6] <= d_vsync_state_out_6_.PADIO d_vsync_state[5] <= d_vsync_state_out_5_.PADIO d_vsync_state[4] <= d_vsync_state_out_4_.PADIO d_vsync_state[3] <= d_vsync_state_out_3_.PADIO d_vsync_state[2] <= d_vsync_state_out_2_.PADIO d_vsync_state[1] <= d_vsync_state_out_1_.PADIO d_vsync_state[0] <= d_vsync_state_out_0_.PADIO d_state_clk <= d_state_clk_out.PADIO d_toggle <= d_toggle_out.PADIO d_toggle_counter[0] <= d_toggle_counter_out_0_.PADIO d_toggle_counter[1] <= d_toggle_counter_out_1_.PADIO d_toggle_counter[2] <= d_toggle_counter_out_2_.PADIO d_toggle_counter[3] <= d_toggle_counter_out_3_.PADIO d_toggle_counter[4] <= d_toggle_counter_out_4_.PADIO d_toggle_counter[5] <= d_toggle_counter_out_5_.PADIO d_toggle_counter[6] <= d_toggle_counter_out_6_.PADIO d_toggle_counter[7] <= d_toggle_counter_out_7_.PADIO d_toggle_counter[8] <= d_toggle_counter_out_8_.PADIO d_toggle_counter[9] <= d_toggle_counter_out_9_.PADIO d_toggle_counter[10] <= d_toggle_counter_out_10_.PADIO d_toggle_counter[11] <= d_toggle_counter_out_11_.PADIO d_toggle_counter[12] <= d_toggle_counter_out_12_.PADIO d_toggle_counter[13] <= d_toggle_counter_out_13_.PADIO d_toggle_counter[14] <= d_toggle_counter_out_14_.PADIO d_toggle_counter[15] <= d_toggle_counter_out_15_.PADIO d_toggle_counter[16] <= d_toggle_counter_out_16_.PADIO d_toggle_counter[17] <= d_toggle_counter_out_17_.PADIO d_toggle_counter[18] <= d_toggle_counter_out_18_.PADIO d_toggle_counter[19] <= d_toggle_counter_out_19_.PADIO d_toggle_counter[20] <= d_toggle_counter_out_20_.PADIO d_toggle_counter[21] <= d_toggle_counter_out_21_.PADIO d_toggle_counter[22] <= d_toggle_counter_out_22_.PADIO d_toggle_counter[23] <= d_toggle_counter_out_23_.PADIO d_toggle_counter[24] <= d_toggle_counter_out_24_.PADIO |vga|vga_driver:vga_driver_unit line_counter_sig_0 <= line_counter_sig_0_.REGOUT line_counter_sig_1 <= line_counter_sig_1_.REGOUT line_counter_sig_2 <= line_counter_sig_2_.REGOUT line_counter_sig_3 <= line_counter_sig_3_.REGOUT line_counter_sig_4 <= line_counter_sig_4_.REGOUT line_counter_sig_5 <= line_counter_sig_5_.REGOUT line_counter_sig_6 <= line_counter_sig_6_.REGOUT line_counter_sig_7 <= line_counter_sig_7_.REGOUT line_counter_sig_8 <= line_counter_sig_8_.REGOUT dly_counter_1 => vsync_state_6_.DATAC dly_counter_1 => h_sync_Z.DATAC dly_counter_1 => v_sync_Z.DATAC dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC dly_counter_0 => vsync_state_6_.DATAB dly_counter_0 => h_sync_Z.DATAB dly_counter_0 => v_sync_Z.DATAB dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB vsync_state_2 <= vsync_state_2_.REGOUT vsync_state_5 <= vsync_state_5_.REGOUT vsync_state_3 <= vsync_state_3_.REGOUT vsync_state_6 <= vsync_state_6_.REGOUT vsync_state_4 <= vsync_state_4_.REGOUT vsync_state_1 <= vsync_state_1_.REGOUT vsync_state_0 <= vsync_state_0_.REGOUT hsync_state_2 <= hsync_state_2_.REGOUT hsync_state_4 <= hsync_state_4_.REGOUT hsync_state_0 <= hsync_state_0_.REGOUT hsync_state_5 <= hsync_state_5_.REGOUT hsync_state_1 <= hsync_state_1_.REGOUT hsync_state_3 <= hsync_state_3_.REGOUT hsync_state_6 <= hsync_state_6_.REGOUT column_counter_sig_0 <= column_counter_sig_0_.REGOUT column_counter_sig_1 <= column_counter_sig_1_.REGOUT column_counter_sig_2 <= column_counter_sig_2_.REGOUT column_counter_sig_3 <= column_counter_sig_3_.REGOUT column_counter_sig_4 <= column_counter_sig_4_.REGOUT column_counter_sig_5 <= column_counter_sig_5_.REGOUT column_counter_sig_6 <= column_counter_sig_6_.REGOUT column_counter_sig_7 <= column_counter_sig_7_.REGOUT column_counter_sig_8 <= column_counter_sig_8_.REGOUT column_counter_sig_9 <= column_counter_sig_9_.REGOUT vsync_counter_9 <= vsync_counter_9_.REGOUT vsync_counter_8 <= vsync_counter_8_.REGOUT vsync_counter_7 <= vsync_counter_7_.REGOUT vsync_counter_6 <= vsync_counter_6_.REGOUT vsync_counter_5 <= vsync_counter_5_.REGOUT vsync_counter_4 <= vsync_counter_4_.REGOUT vsync_counter_3 <= vsync_counter_3_.REGOUT vsync_counter_2 <= vsync_counter_2_.REGOUT vsync_counter_1 <= vsync_counter_1_.REGOUT vsync_counter_0 <= vsync_counter_0_.REGOUT hsync_counter_9 <= hsync_counter_9_.REGOUT hsync_counter_8 <= hsync_counter_8_.REGOUT hsync_counter_7 <= hsync_counter_7_.REGOUT hsync_counter_6 <= hsync_counter_6_.REGOUT hsync_counter_5 <= hsync_counter_5_.REGOUT hsync_counter_4 <= hsync_counter_4_.REGOUT hsync_counter_3 <= hsync_counter_3_.REGOUT hsync_counter_2 <= hsync_counter_2_.REGOUT hsync_counter_1 <= hsync_counter_1_.REGOUT hsync_counter_0 <= hsync_counter_0_.REGOUT d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT un10_column_counter_siglt6_1 <= COLUMN_COUNT_next_un10_column_counter_siglt6_1.COMBOUT v_sync <= v_sync_Z.REGOUT h_sync <= h_sync_Z.REGOUT h_enable_sig <= h_enable_sig_Z.REGOUT v_enable_sig <= v_enable_sig_Z.REGOUT reset_pin_c => vsync_state_6_.DATAA reset_pin_c => h_sync_Z.DATAA reset_pin_c => v_sync_Z.DATAA reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA un6_dly_counter_0_x <= vsync_state_6_.COMBOUT d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT clk_pin_c => hsync_counter_0_.CLK clk_pin_c => hsync_counter_1_.CLK clk_pin_c => hsync_counter_2_.CLK clk_pin_c => hsync_counter_3_.CLK clk_pin_c => hsync_counter_4_.CLK clk_pin_c => hsync_counter_5_.CLK clk_pin_c => hsync_counter_6_.CLK clk_pin_c => hsync_counter_7_.CLK clk_pin_c => hsync_counter_8_.CLK clk_pin_c => hsync_counter_9_.CLK clk_pin_c => vsync_counter_0_.CLK clk_pin_c => vsync_counter_1_.CLK clk_pin_c => vsync_counter_2_.CLK clk_pin_c => vsync_counter_3_.CLK clk_pin_c => vsync_counter_4_.CLK clk_pin_c => vsync_counter_5_.CLK clk_pin_c => vsync_counter_6_.CLK clk_pin_c => vsync_counter_7_.CLK clk_pin_c => vsync_counter_8_.CLK clk_pin_c => vsync_counter_9_.CLK clk_pin_c => column_counter_sig_9_.CLK clk_pin_c => column_counter_sig_8_.CLK clk_pin_c => column_counter_sig_7_.CLK clk_pin_c => column_counter_sig_6_.CLK clk_pin_c => column_counter_sig_5_.CLK clk_pin_c => column_counter_sig_4_.CLK clk_pin_c => column_counter_sig_3_.CLK clk_pin_c => column_counter_sig_2_.CLK clk_pin_c => column_counter_sig_1_.CLK clk_pin_c => column_counter_sig_0_.CLK clk_pin_c => hsync_state_6_.CLK clk_pin_c => vsync_state_0_.CLK clk_pin_c => vsync_state_1_.CLK clk_pin_c => vsync_state_6_.CLK clk_pin_c => line_counter_sig_8_.CLK clk_pin_c => line_counter_sig_7_.CLK clk_pin_c => line_counter_sig_6_.CLK clk_pin_c => line_counter_sig_5_.CLK clk_pin_c => line_counter_sig_4_.CLK clk_pin_c => line_counter_sig_3_.CLK clk_pin_c => line_counter_sig_2_.CLK clk_pin_c => line_counter_sig_1_.CLK clk_pin_c => line_counter_sig_0_.CLK clk_pin_c => v_enable_sig_Z.CLK clk_pin_c => h_enable_sig_Z.CLK clk_pin_c => h_sync_Z.CLK clk_pin_c => v_sync_Z.CLK clk_pin_c => vsync_state_5_.CLK clk_pin_c => vsync_state_4_.CLK clk_pin_c => vsync_state_3_.CLK clk_pin_c => vsync_state_2_.CLK clk_pin_c => hsync_state_5_.CLK clk_pin_c => hsync_state_4_.CLK clk_pin_c => hsync_state_3_.CLK clk_pin_c => hsync_state_2_.CLK clk_pin_c => hsync_state_1_.CLK clk_pin_c => hsync_state_0_.CLK |vga|vga_control:vga_control_unit column_counter_sig_5 => DRAW_SQUARE_next_un5_v_enablelto5_0.DATAA column_counter_sig_0 => DRAW_SQUARE_next_un5_v_enablelto3.DATAC column_counter_sig_1 => DRAW_SQUARE_next_un5_v_enablelto3.DATAA column_counter_sig_3 => DRAW_SQUARE_next_un9_v_enablelto6.DATAC column_counter_sig_3 => DRAW_SQUARE_next_un5_v_enablelto3.DATAD column_counter_sig_4 => DRAW_SQUARE_next_un9_v_enablelto6.DATAB column_counter_sig_4 => DRAW_SQUARE_next_un5_v_enablelto5_0.DATAB column_counter_sig_2 => DRAW_SQUARE_next_un9_v_enablelto6.DATAA column_counter_sig_2 => DRAW_SQUARE_next_un5_v_enablelto3.DATAB column_counter_sig_9 => DRAW_SQUARE_next_un9_v_enablelto9.DATAC column_counter_sig_9 => b_next_0_g0_3_cZ.DATAD column_counter_sig_8 => DRAW_SQUARE_next_un9_v_enablelto9.DATAB column_counter_sig_8 => b_next_0_g0_3_cZ.DATAC column_counter_sig_7 => DRAW_SQUARE_next_un5_v_enablelto7.DATAB column_counter_sig_7 => DRAW_SQUARE_next_un9_v_enablelto9.DATAA column_counter_sig_6 => DRAW_SQUARE_next_un5_v_enablelto7.DATAA line_counter_sig_0 => DRAW_SQUARE_next_un17_v_enablelt2.DATAC line_counter_sig_1 => DRAW_SQUARE_next_un17_v_enablelt2.DATAA line_counter_sig_2 => DRAW_SQUARE_next_un13_v_enablelto8_a.DATAA line_counter_sig_2 => DRAW_SQUARE_next_un17_v_enablelt2.DATAB line_counter_sig_8 => DRAW_SQUARE_next_un13_v_enablelto8.DATAA line_counter_sig_8 => b_next_0_g0_3_cZ.DATAA line_counter_sig_3 => DRAW_SQUARE_next_un17_v_enablelto5.DATAC line_counter_sig_3 => DRAW_SQUARE_next_un13_v_enablelto8_a.DATAC line_counter_sig_5 => DRAW_SQUARE_next_un17_v_enablelto5.DATAB line_counter_sig_5 => DRAW_SQUARE_next_un13_v_enablelto8_a.DATAD line_counter_sig_4 => DRAW_SQUARE_next_un17_v_enablelto5.DATAA line_counter_sig_4 => DRAW_SQUARE_next_un13_v_enablelto8_a.DATAB line_counter_sig_7 => DRAW_SQUARE_next_un17_v_enablelto7.DATAB line_counter_sig_7 => DRAW_SQUARE_next_un13_v_enablelto8.DATAB line_counter_sig_6 => DRAW_SQUARE_next_un17_v_enablelto7.DATAA line_counter_sig_6 => DRAW_SQUARE_next_un13_v_enablelto8.DATAC toggle_counter_sig_0 <= toggle_counter_sig_0_.REGOUT toggle_counter_sig_1 <= toggle_counter_sig_1_.REGOUT toggle_counter_sig_2 <= toggle_counter_sig_2_.REGOUT toggle_counter_sig_3 <= toggle_counter_sig_3_.REGOUT toggle_counter_sig_4 <= toggle_counter_sig_4_.REGOUT toggle_counter_sig_5 <= toggle_counter_sig_5_.REGOUT toggle_counter_sig_6 <= toggle_counter_sig_6_.REGOUT toggle_counter_sig_7 <= toggle_counter_sig_7_.REGOUT toggle_counter_sig_8 <= toggle_counter_sig_8_.REGOUT toggle_counter_sig_9 <= toggle_counter_sig_9_.REGOUT toggle_counter_sig_10 <= toggle_counter_sig_10_.REGOUT toggle_counter_sig_11 <= toggle_counter_sig_11_.REGOUT toggle_counter_sig_12 <= toggle_counter_sig_12_.REGOUT toggle_counter_sig_13 <= toggle_counter_sig_13_.REGOUT toggle_counter_sig_14 <= toggle_counter_sig_14_.REGOUT toggle_counter_sig_15 <= toggle_counter_sig_15_.REGOUT toggle_counter_sig_16 <= toggle_counter_sig_16_.REGOUT toggle_counter_sig_17 <= toggle_counter_sig_17_.REGOUT toggle_counter_sig_18 <= toggle_counter_sig_18_.REGOUT toggle_counter_sig_19 <= toggle_counter_sig_19_.REGOUT toggle_counter_sig_20 <= toggle_counter_sig_20_.REGOUT toggle_counter_sig_21 <= toggle_counter_sig_21_.REGOUT toggle_counter_sig_22 <= toggle_counter_sig_22_.REGOUT toggle_counter_sig_23 <= toggle_counter_sig_23_.REGOUT toggle_counter_sig_24 <= toggle_counter_sig_24_.REGOUT v_enable_sig => b_next_0_g0_3_cZ.DATAB un10_column_counter_siglt6_1 => DRAW_SQUARE_next_un9_v_enablelto6.DATAD h_enable_sig => b_next_0_g0_5_cZ.DATAA g <= g_Z.REGOUT r <= r_Z.REGOUT b <= b_Z.REGOUT toggle_sig <= toggle_sig_Z.REGOUT un6_dly_counter_0_x => toggle_counter_sig_24_.ACLR un6_dly_counter_0_x => toggle_counter_sig_23_.ACLR un6_dly_counter_0_x => toggle_counter_sig_22_.ACLR un6_dly_counter_0_x => toggle_counter_sig_21_.ACLR un6_dly_counter_0_x => toggle_counter_sig_20_.ACLR un6_dly_counter_0_x => toggle_counter_sig_19_.ACLR un6_dly_counter_0_x => toggle_counter_sig_18_.ACLR un6_dly_counter_0_x => toggle_counter_sig_17_.ACLR un6_dly_counter_0_x => toggle_counter_sig_16_.ACLR un6_dly_counter_0_x => toggle_counter_sig_15_.ACLR un6_dly_counter_0_x => toggle_counter_sig_14_.ACLR un6_dly_counter_0_x => toggle_counter_sig_13_.ACLR un6_dly_counter_0_x => toggle_counter_sig_12_.ACLR un6_dly_counter_0_x => toggle_counter_sig_11_.ACLR un6_dly_counter_0_x => toggle_counter_sig_10_.ACLR un6_dly_counter_0_x => toggle_counter_sig_9_.ACLR un6_dly_counter_0_x => toggle_counter_sig_8_.ACLR un6_dly_counter_0_x => toggle_counter_sig_7_.ACLR un6_dly_counter_0_x => toggle_counter_sig_6_.ACLR un6_dly_counter_0_x => toggle_counter_sig_5_.ACLR un6_dly_counter_0_x => toggle_counter_sig_4_.ACLR un6_dly_counter_0_x => toggle_counter_sig_3_.ACLR un6_dly_counter_0_x => toggle_counter_sig_2_.ACLR un6_dly_counter_0_x => toggle_counter_sig_1_.ACLR un6_dly_counter_0_x => toggle_counter_sig_0_.ACLR un6_dly_counter_0_x => toggle_sig_Z.ACLR un6_dly_counter_0_x => b_Z.ACLR un6_dly_counter_0_x => r_Z.ACLR un6_dly_counter_0_x => g_Z.ACLR clk_pin_c => toggle_counter_sig_24_.CLK clk_pin_c => toggle_counter_sig_23_.CLK clk_pin_c => toggle_counter_sig_22_.CLK clk_pin_c => toggle_counter_sig_21_.CLK clk_pin_c => toggle_counter_sig_20_.CLK clk_pin_c => toggle_counter_sig_19_.CLK clk_pin_c => toggle_counter_sig_18_.CLK clk_pin_c => toggle_counter_sig_17_.CLK clk_pin_c => toggle_counter_sig_16_.CLK clk_pin_c => toggle_counter_sig_15_.CLK clk_pin_c => toggle_counter_sig_14_.CLK clk_pin_c => toggle_counter_sig_13_.CLK clk_pin_c => toggle_counter_sig_12_.CLK clk_pin_c => toggle_counter_sig_11_.CLK clk_pin_c => toggle_counter_sig_10_.CLK clk_pin_c => toggle_counter_sig_9_.CLK clk_pin_c => toggle_counter_sig_8_.CLK clk_pin_c => toggle_counter_sig_7_.CLK clk_pin_c => toggle_counter_sig_6_.CLK clk_pin_c => toggle_counter_sig_5_.CLK clk_pin_c => toggle_counter_sig_4_.CLK clk_pin_c => toggle_counter_sig_3_.CLK clk_pin_c => toggle_counter_sig_2_.CLK clk_pin_c => toggle_counter_sig_1_.CLK clk_pin_c => toggle_counter_sig_0_.CLK clk_pin_c => toggle_sig_Z.CLK clk_pin_c => b_Z.CLK clk_pin_c => r_Z.CLK clk_pin_c => g_Z.CLK